Bandgap reference circuit, bandgap reference generation method, and chip

Abstract

The application discloses a band gap reference circuit, a band gap reference generation method and a chip. The band gap reference circuit comprises a first resistor, a first PNP transistor and a second PNP transistor, a first current mirror unit, a first transistor, a second current mirror unit and a reference voltage generation unit. The first current mirror unit outputs a first current and a second current; the first transistor is used for generating a third current; the second current mirror unit proportionally copies the third current to generate a fourth current and a fifth current; and the reference voltage generation unit is used for generating a zero-temperature-coefficient reference voltage. According to the band gap reference circuit, the band gap reference generation method and the chip, NPN transistors are not used, so that a smaller number of masks and a smaller area are required, the application in a large-scale integrated circuit is more favorable, good temperature characteristics are simultaneously achieved, a stable reference voltage is maintained at high temperature, and the application in a high-temperature or high-power module in a system basic chip is suitable.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a bandgap reference circuit, a method for generating a bandgap reference, and a chip. Background Technology

[0002] A system base chip (SBC) is a multi-functional integrated chip that includes power management, communication interfaces, and other features. It operates in multiple modes and faces significant chip area constraints. During power-up, a low-cost reference generation circuit is typically needed to monitor the power supply and provide basic functionality in low-power modes.

[0003] Traditional reference voltage circuits mainly employ two schemes: one is a bandgap circuit without op-amp based on NPN bis-junction transistors, and the other is a bandgap circuit implemented by adding an operational amplifier (OPA).

[0004] The disadvantages of these two structures are that the former is limited by its structure and can only use NPN transistors with high current gain (β), while current integrated circuit technology usually uses N-well technology, which requires a large area and faces serious high-temperature leakage problems; the latter introduces an amplifier, which generates additional compensation requirements and consumes power and area.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a bandgap reference circuit, a bandgap reference generation method, and a chip, which can greatly optimize the power consumption and area consumption of the chip's reference voltage generation module.

[0007] To achieve the above objectives, embodiments of the present invention provide a bandgap reference circuit, comprising:

[0008] A first resistor, a first PNP transistor, and a second PNP transistor, wherein the base and collector of the first PNP transistor and the second PNP transistor are both connected to ground voltage, and the emitter of the second PNP transistor is connected to the first terminal of the first resistor.

[0009] The first current mirror unit is connected to the emitter of the first PNP transistor and the second terminal of the first resistor to output the first current and the second current.

[0010] The first transistor has its control terminal connected to the second terminal of the first resistor, and the second terminal of the first transistor is connected to the input terminal of the first current mirror unit. The first transistor generates a third current based on the voltage at the second terminal of the first resistor.

[0011] The second current mirror unit is connected to the first terminal of the first transistor and the input terminal of the first current mirror unit to proportionally replicate the third current to generate the fourth and fifth currents; and

[0012] The reference voltage generation unit is used to generate a reference voltage with zero temperature coefficient based on the fifth current.

[0013] In one or more embodiments of the present invention, the first current mirror unit includes a second transistor and a third transistor. The control terminal of the second transistor is connected to the control terminal of the third transistor. The first terminal and the control terminal of the second transistor are connected to the emitter of the first PNP transistor. The first terminal of the third transistor is connected to the second terminal of the first resistor and the control terminal of the first transistor. The second terminals of the second transistor and the second terminals of the third transistor are connected to the input terminal of the first current mirror unit and connected to the second current mirror unit to receive a fourth current.

[0014] In one or more embodiments of the present invention, the second current mirror unit includes a first current mirror and a second current mirror, the first current mirror being connected to a first terminal of a first transistor, and the second current mirror being connected to the first current mirror to generate a fourth current and a fifth current.

[0015] In one or more embodiments of the present invention, the first current mirror includes a fourth transistor and a fifth transistor, the control terminal of the fourth transistor is connected to the control terminal of the fifth transistor, the first terminal of the fourth transistor is connected to the control terminal of the fourth transistor and the first terminal of the first transistor, the first terminal of the fifth transistor is connected to the second current mirror, and the second terminals of the fourth transistor and the second terminals of the fifth transistor are connected to ground voltage.

[0016] In one or more embodiments of the present invention, the second current mirror includes a sixth transistor, a seventh transistor, and an eighth transistor. The control terminals of the sixth transistor, the seventh transistor, and the eighth transistor are connected. The second terminals of the sixth transistor, the seventh transistor, and the eighth transistor are connected to a power supply voltage. The first terminal of the sixth transistor is connected to the control terminal of the sixth transistor and the first current mirror. The first terminal of the seventh transistor is connected to the input terminal of the first current mirror unit and the second terminal of the first transistor. The first terminal of the eighth transistor is connected to a reference voltage generating unit.

[0017] In one or more embodiments of the present invention, the reference voltage generating unit includes a second resistor and a third PNP transistor. The first end of the second resistor is connected to a second current mirror unit to generate a reference voltage. The second end of the second resistor is connected to the emitter of the third PNP transistor. The base and collector of the third PNP transistor are connected to ground voltage.

[0018] In one or more embodiments of the present invention, the first current is equal to the second current and the third current, and the fourth current is equal to the sum of the first current, the second current and the third current.

[0019] In one or more embodiments of the present invention, the mirror ratio of the third current input to the first current mirror to the output current of the first current mirror is 1:M, and the mirror ratio of the current received by the second current mirror from the output of the first current mirror to the fourth and fifth currents output by the second current mirror is M:3:1.

[0020] The present invention also discloses a method for generating a bandgap reference, used in the bandgap reference circuit, the method comprising:

[0021] Equal first and second currents are generated by the first current mirror unit and delivered to the first resistor and the first PNP transistor, respectively.

[0022] A third current, equal to the first current, is generated by the first transistor;

[0023] The second current mirror unit generates a fourth current based on the third current, which is equal in magnitude to the sum of the first current, the second current, and the third current, to be supplied to the first current mirror unit and the first transistor, and generates a fifth current.

[0024] A reference voltage with zero temperature coefficient is generated based on the fifth current through the reference voltage generation unit.

[0025] The present invention also discloses a chip including the aforementioned bandgap reference circuit.

[0026] Compared with the prior art, the bandgap reference circuit, bandgap reference generation method and chip according to the embodiments of the present invention use PNP type transistors, which have the simplest structure in N-well technology, to generate the required reference voltage. Since NPN type transistors are not used, fewer masks and less area are required. At the same time, there is no need to introduce amplifiers, nor to introduce additional compensation requirements or increase power consumption and area consumption, which makes it more suitable for application in large-scale integrated circuits. It also has good temperature characteristics and maintains a stable reference voltage at high temperatures, making it suitable for application in high-temperature or high-power modules in system base chips. Attached Figure Description

[0027] Figure 1 This is a circuit schematic diagram of a bandgap reference circuit according to an embodiment of the present invention.

[0028] Figure 2 This is a flowchart of a method for generating a bandgap reference according to an embodiment of the present invention. Detailed Implementation

[0029] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0030] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0031] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0032] like Figure 1 As shown, a bandgap reference circuit includes: a first resistor R1, a first PNP transistor Q1, a second PNP transistor Q2, a first current mirror unit 10, a first transistor M1, a second current mirror unit, and a reference voltage generation unit 30. The area ratio of the first PNP transistor Q1 to the second PNP transistor Q2 is 1:N.

[0033] Specifically, the base and collector of the first PNP transistor Q1 and the second PNP transistor Q2 are both connected to the ground voltage GND. The emitter of the second PNP transistor Q2 is connected to the first end of the first resistor R1. The first current mirror unit 10 is connected to the emitter of the first PNP transistor Q1 and the second end of the first resistor R1 to output a first current I1 and a second current I2, where the first current I1 is equal to the second current I2.

[0034] The control terminal of the first transistor M1 is connected to the second terminal of the first resistor R1. The second terminal of the first transistor M1 is connected to the input terminal of the first current mirror unit 10. The first transistor M1 generates a third current I3 based on the voltage at the second terminal of the first resistor R1. The third current I3 is equal to the second current I2.

[0035] The second current mirror unit I2 is connected to the first terminal of the first transistor M1 and the input terminal of the first current mirror unit 10 to proportionally replicate the third current I3 to generate the fourth current I4 and the fifth current I5. In one embodiment, the fourth current I4 is equal to the sum of the first current I1, the second current I2 and the third current I3.

[0036] The reference voltage generation unit 30 is used to generate a reference voltage with zero temperature coefficient based on the fifth current I5.

[0037] like Figure 1 As shown, the first current mirror unit 10 includes a second transistor M2 and a third transistor M3. The control terminal of the second transistor M2 is connected to the control terminal of the third transistor M3. The first terminal and the control terminal of the second transistor M2 are connected to the emitter of the first PNP transistor Q1. The first terminal of the third transistor M3 is connected to the second terminal of the first resistor R1 and the control terminal of the first transistor M1. The second terminals of the second transistor M2 and the second terminals of the third transistor M3 are connected to the input terminal of the first current mirror unit 10 and are connected to the second current mirror unit to receive a fourth current I4. The first terminal of the second transistor M2 outputs a first current I1, and the first terminal of the third transistor M3 outputs a second current I2. The width-to-length ratio of the second transistor M2 and the third transistor M3 is 1:1, therefore the first current I1 and the second current I2 are equal.

[0038] In one embodiment, both the second transistor M2 and the third transistor M3 are P-channel MOSFETs. The first terminal of the second transistor M2 and the first terminal of the third transistor M3 are the drains, the second terminals of the second transistor M2 and the second terminals of the third transistor M3 are the sources, and the control terminals of the second transistor M2 and the third transistor M3 are the gates. In other embodiments, the second transistor M2 and the third transistor M3 can be configured as N-channel MOSFETs or transistors, as needed.

[0039] like Figure 1 As shown, the control terminal of the first transistor M1 is connected to the second terminal of the first resistor R1 and the first terminal of the third transistor M3. The second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2 and the first terminal of the third transistor M3 of the first current mirror unit 10. The first transistor M1 generates a third current I3 based on the voltage at the second terminal of the first resistor R1.

[0040] In one embodiment, the first transistor M1 is a P-channel MOS transistor. The first terminal of the first transistor M1 is the drain, the second terminal of the first transistor M1 is the source, and the control terminal of the first transistor M1 is the gate.

[0041] like Figure 1 As shown, the second current mirror unit includes a first current mirror 21 and a second current mirror 22. The first current mirror 21 is connected to the first terminal of the first transistor M1, and the second current mirror 22 is connected to the first current mirror 21 to generate a fourth current I4 and a fifth current I5. The mirror ratio of the third current I3 input to the first current mirror 21 to the output current of the first current mirror 21 is 1:M, and the mirror ratio of the current received by the second current mirror 22 from the output of the first current mirror to the fourth current I4 and the fifth current I5 output by the second current mirror 22 is M:3:1.

[0042] Specifically, the first current mirror 21 includes a fourth transistor M4 and a fifth transistor M5. The control terminal of the fourth transistor M4 is connected to the control terminal of the fifth transistor M5. The first terminal of the fourth transistor M4 is connected to both the control terminal of the fourth transistor M4 and the first terminal of the first transistor M1. The first terminal of the fifth transistor M5 is connected to the second current mirror 22. The second terminals of both the fourth transistor M4 and the fifth transistor M5 are connected to ground voltage GND. The fourth transistor M4 is used to acquire the third current I3, and the fifth transistor M5 is used to mirror the third current I3 to obtain a mirrored current. The width-to-length ratio of the fourth transistor M4 and the fifth transistor M5 is 1:M, where M is greater than or equal to 1. In one embodiment, M can be 1.

[0043] In one embodiment, both the fourth transistor M4 and the fifth transistor M5 are N-channel MOSFETs. The first terminal of the fourth transistor M4 and the first terminal of the fifth transistor M5 are the drains, the second terminals of the fourth transistor M4 and the fifth transistor M5 are the sources, and the control terminals of the fourth transistor M4 and the fifth transistor M5 are the gates. In other embodiments, the fourth transistor M4 and the fifth transistor M5 can be configured as P-channel MOSFETs or transistors, as needed.

[0044] Meanwhile, the second current mirror 22 includes a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The control terminals of the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are connected, and the second terminals of the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are connected to the power supply voltage. The width-to-length ratio of the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 is M:3:1, where M is greater than or equal to 1. In one embodiment, M can be 1.

[0045] The first terminal of the sixth transistor M6 is connected to the control terminal of the sixth transistor M6 and the first terminal of the fifth transistor M5 of the first current mirror 21 to collect the mirror current on the fifth transistor M5.

[0046] The first terminal of the seventh transistor M7 is connected to the second terminals of the second transistor M2 and the third transistor M3 of the first current mirror unit 10, as well as the second terminal of the first transistor M1, to output a fourth current I4. The fourth current I4 is equal to the sum of the first current I1, the second current I2, and the third current I3. In one embodiment, M equals 1, and the fourth current I4 is equal to 3 times the third current I3.

[0047] The first terminal of the eighth transistor M8 is connected to the reference voltage generation unit 30 to output the fifth current I5, which is equal to the third current I3.

[0048] In one embodiment, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all P-channel MOSFETs. The first terminals of the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are the drains; the second terminals of the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are the sources; and the control terminals of the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are the gates. In other embodiments, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can be configured as N-channel MOSFETs or transistors, depending on the requirements.

[0049] like Figure 1 As shown, the reference voltage generating unit 30 includes a second resistor R2 and a third PNP transistor Q3. The first end of the second resistor R2 is connected to the second current mirror unit to generate a reference voltage VREF, and the second end of the second resistor R2 is connected to the emitter of the third PNP transistor Q3. The base and collector of the third PNP transistor Q3 are connected to ground voltage GND.

[0050] like Figure 2 As shown, a method for generating a bandgap reference, used in the aforementioned bandgap reference circuit, includes the following steps:

[0051] The first current mirror unit 10 generates an equal first current I1 and a second current I2 to be delivered to the first resistor R1 and the first PNP transistor Q1, respectively.

[0052] A third current I3, equal to the first current I1, is generated by the first transistor M1.

[0053] The second current mirror unit generates a fourth current I4, which is equal to the sum of the first current I1, the second current I2 and the third current I3, based on the third current I3, and delivers it to the first current mirror unit 10 and the first transistor M1, and generates a fifth current I5.

[0054] A reference voltage with zero temperature coefficient is generated by the reference voltage generation unit 30 based on the fifth current I5.

[0055] To satisfy the current equation To obtain a positive temperature coefficient current, and then coordinate it with the base voltage of a transistor with a negative temperature coefficient, a temperature-independent reference voltage can be obtained. This requires that the two branches formed by the first PNP transistor Q1, the second PNP transistor Q2, and the first resistor R1 simultaneously satisfy: 1. The currents in the two branches are equal (i.e., the current on the first PNP transistor Q1 is equal to the current on the second PNP transistor Q2 and the first resistor R1); 2. The voltages at both ends are equal (i.e., the emitter voltage of the first PNP transistor Q1 is equal to the voltage at the second end of the first resistor R1).

[0056] In one embodiment, the first condition can be well satisfied by the current mirror structure composed of the second transistor M2 and the third transistor M3, that is, the first current I1 and the second current I2 generated by the second transistor M2 and the third transistor M3 are equal.

[0057] Compared to existing technologies, where the second condition for the first PNP transistor Q1 and the second PNP transistor Q2 typically requires a differential error amplifier to clamp the voltage between the emitter of the first PNP transistor Q1 and the second terminal of the first resistor R1, this invention provides a third branch formed by the first transistor M1. When the third current I3 on ​​the first transistor M1 is equal to the first current I1 and the second current I2, the control terminal voltage of the first transistor M1 is equal to the control terminal voltage of the third transistor M3. In other words, the control terminal voltages of the second transistor M2 and the third transistor M3 are equal, thus obtaining the desired positive temperature coefficient current.

[0058] By mirroring the third current I3 through the first current mirror 21 and the second current mirror 22, and forcibly constraining the output current of the seventh transistor M7 to be equal to three times the third current I3, we can obtain...

[0059] Therefore, the fourth current The fifth current I5 is generated by mirroring the eighth transistor M8, thereby obtaining the reference voltage through the second resistor R2 and the third PNP transistor Q3. Among them, V BEQ3The voltage between the emitter and base of the third PNP transistor Q3 is given by k, which is the Boltzmann constant, T is the temperature, and q is the electron charge. By appropriately adjusting the ratio coefficients of the second resistor R2 and the first resistor R1, the temperature coefficient can be eliminated, and an analog voltage of about 1.2V can be obtained.

[0060] The present invention also discloses a chip including the above-described bandgap reference circuit.

[0061] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings; the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments and various different choices and modifications of the invention without departing from the scope and spirit of the invention. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A bandgap reference circuit, characterized by, include: A first resistor, a first PNP transistor, and a second PNP transistor, wherein the base and collector of the first PNP transistor and the second PNP transistor are both connected to ground voltage, and the emitter of the second PNP transistor is connected to the first terminal of the first resistor. The first current mirror unit is connected to the emitter of the first PNP transistor and the second terminal of the first resistor to output the first current and the second current. The first transistor has its control terminal connected to the second terminal of the first resistor, and the second terminal of the first transistor is connected to the input terminal of the first current mirror unit. The first transistor generates a third current based on the voltage at the second terminal of the first resistor. The second current mirror unit is connected to the first terminal of the first transistor and the input terminal of the first current mirror unit to proportionally replicate the third current to generate a fourth current and a fifth current. The fourth current is equal to the sum of the first current, the second current and the third current, and the first current, the second current and the third current are equal. as well as The reference voltage generation unit is used to generate a reference voltage with zero temperature coefficient based on the fifth current.

2. The bandgap reference circuit as described in claim 1, characterized in that, The first current mirror unit includes a second transistor and a third transistor. The control terminal of the second transistor is connected to the control terminal of the third transistor. The first terminal and the control terminal of the second transistor are connected to the emitter of the first PNP transistor. The first terminal of the third transistor is connected to the second terminal of the first resistor and the control terminal of the first transistor. The second terminals of the second transistor and the second terminals of the third transistor are connected to the input terminal of the first current mirror unit and are connected to the second current mirror unit to receive a fourth current.

3. The bandgap reference circuit as described in claim 1, characterized in that, The second current mirror unit includes a first current mirror and a second current mirror. The first current mirror is connected to the first terminal of the first transistor, and the second current mirror is connected to the first current mirror to generate a fourth current and a fifth current.

4. The bandgap reference circuit as described in claim 3, characterized in that, The first current mirror includes a fourth transistor and a fifth transistor. The control terminal of the fourth transistor is connected to the control terminal of the fifth transistor. The first terminal of the fourth transistor is connected to the control terminal of the fourth transistor and the first terminal of the first transistor. The first terminal of the fifth transistor is connected to the second current mirror. The second terminals of the fourth transistor and the second terminals of the fifth transistor are connected to ground voltage.

5. The bandgap reference circuit as described in claim 3, characterized in that, The second current mirror includes a sixth transistor, a seventh transistor, and an eighth transistor. The control terminals of the sixth transistor, the seventh transistor, and the eighth transistor are connected. The second terminals of the sixth transistor, the seventh transistor, and the eighth transistor are connected to the power supply voltage. The first terminal of the sixth transistor is connected to the control terminal of the sixth transistor and the first current mirror. The first terminal of the seventh transistor is connected to the input terminal of the first current mirror unit and the second terminal of the first transistor. The first terminal of the eighth transistor is connected to the reference voltage generation unit.

6. The bandgap reference circuit as described in claim 1, characterized in that, The reference voltage generating unit includes a second resistor and a third PNP transistor. The first end of the second resistor is connected to the second current mirror unit to generate a reference voltage. The second end of the second resistor is connected to the emitter of the third PNP transistor. The base and collector of the third PNP transistor are connected to ground voltage.

7. The bandgap reference circuit as described in claim 1, characterized in that, The first current is equal to the second current and the third current, and the fourth current is equal to the sum of the first current, the second current and the third current.

8. The bandgap reference circuit as described in claim 3, characterized in that, The mirror ratio of the third current input to the first current mirror to the output current of the first current mirror is 1:M, and the mirror ratio of the current received by the second current mirror from the output of the first current mirror to the fourth and fifth currents output by the second current mirror is M:3:

1.

9. A method for generating a bandgap reference, characterized in that, The method for generating a bandgap reference circuit as described in any one of claims 1 to 8 includes: Equal first and second currents are generated by the first current mirror unit and delivered to the first resistor and the first PNP transistor, respectively. A third current, equal to the first current, is generated by the first transistor; The second current mirror unit generates a fourth current based on the third current, which is equal in magnitude to the sum of the first current, the second current, and the third current, to be supplied to the first current mirror unit and the first transistor, and generates a fifth current. A reference voltage with zero temperature coefficient is generated based on the fifth current through the reference voltage generation unit.

10. A chip, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1 to 8.

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