A jbs diode structure and a method of manufacturing the same

Abstract

This invention provides a JBS diode structure and its fabrication method. The JBS diode structure includes a substrate of a first conductivity type, an epitaxial layer of a first conductivity type, a well region of a second conductivity type, a first electrode, and a second electrode. The epitaxial layer is located on the upper surface of the substrate. Multiple well regions are spaced apart and located on the upper surface of the epitaxial layer. Each well region includes a first implantation region and a second implantation region. Multiple doped regions of the second conductivity type, stacked upwards sequentially, form the second implantation region. The lateral width of the doped region is greater than the lateral width of the first implantation region. The first electrode is located on the upper surface of the epitaxial layer and electrically connected to the epitaxial layer and the well regions. The second electrode is located on the lower surface of the substrate and electrically connected to the substrate. This invention adjusts the process for forming the well regions to create sharp, curved sidewalls, increasing the electric field strength at these sharp corners. This shifts the peak electric field strength of the device to the sharp corners of the well region sidewalls, reducing leakage current and increasing the reverse breakdown voltage of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a JBS diode structure and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, possesses characteristics such as high electron saturation velocity, high breakdown voltage, radiation resistance, and high temperature resistance, which compensate for the shortcomings of traditional silicon materials in high-power density, high-temperature, and high-frequency applications. This has made SiC-based power semiconductor devices, especially high-current-density SiC Schottky diodes, one of the hottest research topics in the SiC field. SiC JBS (silicon carbide junction barrier diode) structure devices, as a type of SiC Schottky diode, have become the mainstream design scheme in SiC Schottky diodes due to their high reverse breakdown voltage.

[0003] Since the forward current characteristics of SiC JBS diodes mainly depend on the area of ​​the active region, when the area of ​​the active region of the chip increases, the forward output characteristics of the device will increase proportionally. However, at the same time, the leakage current of the active region generated during reverse withstand voltage will also increase exponentially. Moreover, the leakage current of the active region is proportional to the square of the increase in area, far exceeding the impact of terminal leakage current.

[0004] like Figure 1 The diagram shows a cross-sectional structure of a SiC JBS diode, including a substrate 01, an epitaxial layer 02, a well region 021, a first electrode 03, and a second electrode 04. Due to the influence of the Schottky barrier, the leakage current of the JBS diode is greater than that of a traditional PN junction when it is in reverse breakdown voltage. As the product generation increases, the current density increases, and the surface electric field of the N-type region becomes higher, resulting in a larger leakage current. Currently, the leakage current of the device is usually reduced by adjusting the ion implantation dose. However, while this reduces the leakage current, the breakdown voltage (BV) of the device is also reduced to a certain extent. It is impossible to increase the breakdown voltage of the device while reducing the leakage current. There are also methods to reduce the leakage current and increase the breakdown voltage of the device by increasing the implantation depth through high-energy implantation or by using trench etching and high-energy ion implantation. However, these methods require additional equipment for the appropriate process.

[0005] Therefore, there is an urgent need to find a method for fabricating JBS diode structures that reduces leakage current while increasing breakdown voltage without requiring additional equipment. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a JBS diode structure and its fabrication method, which solves the problem that in the prior art, reducing the leakage current of JBS diodes while increasing the breakdown voltage of the device requires additional equipment.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a JBS diode structure, comprising the following steps:

[0008] A substrate of a first conductivity type is provided, and an epitaxial layer of the first conductivity type is formed on the upper surface of the substrate;

[0009] A patterned masking layer is formed on the upper surface of the epitaxial layer to obtain multiple spaced openings;

[0010] A first injection region of a second conductivity type with a predetermined depth is formed based on the opening in the upper surface layer of the epitaxial layer;

[0011] The edges of the opening in the shielding layer are etched multiple times to expand the edges of the opening. After each etching, a second conductivity type doped region with a lateral width greater than the first injection region is formed below the first injection region based on the expanded opening. Multiple doped regions are stacked upwards to form a second conductivity type second injection region. The bottom surface of the first injection region is in contact with the upper surface of the second injection region. The first injection region and the second injection region form a second conductivity type well region.

[0012] A first electrode electrically connected to the epitaxial layer and the well region is formed on the upper surface of the epitaxial layer, and a second electrode electrically connected to the substrate is formed on the lower surface of the substrate.

[0013] Optionally, the material of the shielding layer includes polycrystalline silicon.

[0014] Optionally, after the opening is formed, before each etching of the edge of the opening, the step of oxidizing the surface of the masking layer is further included.

[0015] Alternatively, the method for etching the edges of the opening includes wet etching.

[0016] Optionally, the method for forming the first implantation region includes ion implantation; the method for forming the doped region includes ion implantation.

[0017] Optionally, the implantation energy of ion implantation to form the first implantation region is less than the implantation energy of ion implantation to form the doped region.

[0018] Optionally, the ion implantation energy for forming the doped region is different each time, and the doping concentration of the doped region in the second implantation region is the same.

[0019] Optionally, the sidewall of the second injection region is formed with a pointed region.

[0020] The present invention also provides a JBS diode structure, comprising:

[0021] First conductivity type substrate;

[0022] A first conductivity type epitaxial layer is located on the upper surface of the substrate;

[0023] Multiple spaced second conductivity type well regions are located on the upper surface of the epitaxial layer. The second conductivity type well region includes a second conductivity type first implantation region and a second conductivity type second implantation region. The bottom surface of the first implantation region is in contact with the upper surface of the second implantation region. Multiple second conductivity type doped regions are stacked upwards in sequence to form the second implantation region. The lateral width of the doped region is greater than the lateral width of the first implantation region.

[0024] A first electrode and a second electrode, wherein the first electrode is located on the upper surface of the epitaxial layer and is electrically connected to the epitaxial layer and the well region, and the second electrode is located on the lower surface of the substrate and is electrically connected to the substrate.

[0025] Optionally, the sidewall of the second injection region is provided with a pointed region.

[0026] As described above, the JBS diode structure and its fabrication method of the present invention, by adjusting the formation process of the well region, first forms the opening in the shielding layer, and then forms the first implantation region based on the opening. The surface layer of the shielding layer is then oxidized multiple times, and after each oxidation, the oxide layer on the surface of the shielding layer is etched to enlarge the opening. A doped layer is then formed based on each enlarged opening, and multiple stacked doped layers form the second implantation region. By repeatedly oxidizing the surface layer of the shielding layer and then removing the oxide layer after each oxidation, the opening is enlarged in a gradually increasing manner, ensuring the consistency of the sidewall morphology of the enlarged opening and reducing the influence of lateral scattering of particles during ion implantation. The first implantation region is formed based on each enlarged opening. The doped region below, with multiple stacked doped regions forming the second implantation region, has its upper surface in contact with the lower surface of the first implantation region, thereby forming the well region composed of the first and second implantation regions. The sidewall of the second implantation region has a pointed region, so that the sidewall of the well region has a pointed region with a large curvature, which increases the electric field intensity of the pointed region of the sidewall of the well region. This causes the peak electric field intensity in the device to shift from the upper surface of the epitaxial layer to the pointed region of the sidewall of the well region, reducing the surface electric field intensity of the device and reducing the leakage current of the device. This improves the problem of excessive leakage current caused by image force, increases the reverse breakdown voltage of the device, and requires no additional equipment configuration or adjustment of ion implantation dosage. The process is simple and has high industrial application value. Attached Figure Description

[0027] Figure 1The diagram shown is a cross-sectional view of a JBS diode structure.

[0028] Figure 2 The diagram shows the process flow of the JBS diode structure fabrication method of the present invention.

[0029] Figure 3 The diagram shows a cross-sectional structure after the epitaxial layer is formed, which is a method for fabricating the JBS diode structure of the present invention.

[0030] Figure 4 The diagram shows a cross-sectional structure after the formation of the first injection region, which is a method for fabricating the JBS diode structure of the present invention.

[0031] Figure 5 The diagram shows a cross-sectional structure after forming a well region, which is a method for fabricating the JBS diode structure of the present invention.

[0032] Figure 6 The diagram shows a cross-sectional structure after forming another well region, which is a method for fabricating the JBS diode structure of the present invention.

[0033] Figure 7 The diagram shows a cross-sectional view of the JBS diode structure fabrication method of the present invention after removing the shielding layer.

[0034] Figure 8 The diagram shows a cross-sectional structure after the formation of the first and second electrodes in the fabrication method of the JBS diode structure of the present invention.

[0035] Figure 9 Displayed as Figure 1 The electric field strength of the JBS diode structure in the present invention varies with the depth of the epitaxial layer.

[0036] Figure 10 Displayed as Figure 1 The leakage current of the JBS diode structure in the present invention is shown as a function of reverse bias voltage.

[0037] Explanation of icon numbers

[0038] 01 Substrate

[0039] 02 Epitaxial Layer

[0040] 021 Tunnel Area

[0041] 03 First Electrode

[0042] 04 Second Electrode

[0043] 1 Substrate

[0044] 2 Epitaxial layer

[0045] 21 First Injection Zone

[0046] 22 Second Injection Zone

[0047] 23 Tunnel Area

[0048] 24 Doped Regions

[0049] 3. Shielding layer

[0050] 31 Opening

[0051] 4 First electrode

[0052] 5 Second electrode Detailed Implementation

[0053] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] Please see Figures 2 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0055] Example 1

[0056] This embodiment provides a method for fabricating a JBS diode structure, such as... Figure 2 The diagram shown is a process flow chart of the fabrication method of the JBS diode structure, including the following steps:

[0057] S1: A substrate of a first conductivity type is provided, and an epitaxial layer of the first conductivity type is formed on the upper surface of the substrate;

[0058] S2: A patterned masking layer is formed on the upper surface of the epitaxial layer to obtain multiple spaced openings;

[0059] S3: A first injection region of a second conductivity type with a preset depth is formed based on the opening in the upper surface layer of the epitaxial layer;

[0060] S4: The edge of the opening in the shielding layer is etched multiple times to expand the edge of the opening. After each etching, a second conductivity type doped region with a lateral width greater than the first injection region is formed below the first injection region based on the expanded opening. Multiple doped regions are stacked upwards to form a second conductivity type second injection region. The bottom surface of the first injection region is in contact with the upper surface of the second injection region. The first injection region and the second injection region form a second conductivity type well region.

[0061] S5: A first electrode electrically connected to the epitaxial layer and the well region is formed on the upper surface of the epitaxial layer, and a second electrode electrically connected to the substrate is formed on the lower surface of the substrate.

[0062] Please see Figures 3 to 6 The following steps are executed: Step S1, Step S2, Step 3, and Step S4: A first conductivity type substrate 1 is provided, and a first conductivity type epitaxial layer 2 is formed on the upper surface of the substrate 1; a patterned masking layer 3 is formed on the upper surface of the epitaxial layer 2 to obtain a plurality of spaced openings 31; a second conductivity type first implantation region 21 of a preset depth is formed on the upper surface of the epitaxial layer 2 based on the openings 31; the edges of the openings 31 in the masking layer 3 are etched multiple times to expand the edges of the openings 31, and after each etching, a second conductivity type doped region 24 with a lateral width greater than the first implantation region 21 is formed below the first implantation region 21 based on the expanded openings 31; a plurality of doped regions 24 are stacked upwards to form a second conductivity type second implantation region 22; the bottom surface of the first implantation region 21 is in contact with the upper surface of the second implantation region 22; the first implantation region 21 and the second implantation region 22 form a second conductivity type well region 23.

[0063] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0064] Specifically, the substrate 1 is made of silicon carbide or other suitable semiconductor materials.

[0065] Specifically, the material of the epitaxial layer 2 includes silicon carbide or other suitable semiconductor materials.

[0066] Specifically, such as Figure 3 The diagram shown is a cross-sectional view of the epitaxial layer 2 after its formation. The method for forming the epitaxial layer 2 includes chemical vapor deposition or other suitable methods.

[0067] Specifically, the method for forming the shielding layer 3 includes physical vapor deposition, chemical vapor deposition, or other suitable methods.

[0068] As an example, the material of the shielding layer 3 includes polycrystalline silicon or other suitable materials. In this embodiment, a single layer of polycrystalline silicon is used as the shielding layer 3 to facilitate the expansion of the opening 31 by means of oxidation and etching of the oxide layer, thereby forming an opening 31 with a gradually changing opening size, while ensuring the consistency of the sidewall morphology of the expanded opening 31 and reducing the influence of lateral scattering.

[0069] Specifically, patterning the masking layer 3 includes the following steps: forming a photoresist layer (not shown) on the upper surface of the masking layer 3, and forming a photoresist opening with a preset pattern in the photoresist layer; etching the masking layer based on the photoresist opening to obtain the opening 31.

[0070] Specifically, the method for forming the photoresist layer includes coating or other suitable methods.

[0071] Specifically, the method for etching the masking layer 3 includes dry etching, wet etching, or other suitable methods.

[0072] Specifically, in the etching process that forms the opening 31, the etching reagent has a high etching selectivity for the masking layer 3 and the epitaxial layer 2, so as to avoid damaging the epitaxial layer 2 during the formation of the opening 31.

[0073] Specifically, while ensuring device performance, the size of the opening 31 can be selected according to the actual situation, and is not limited here.

[0074] Specifically, such as Figure 4 The diagram shown is a cross-sectional view of the structure after the first implantation region 21 is formed. The method for forming the first implantation region 21 includes ion implantation or other suitable methods.

[0075] Specifically, while ensuring device performance, the doping concentration of the first implantation region 21 can be selected according to the actual situation, and is not limited here.

[0076] Specifically, while ensuring device performance, the thickness of the first implantation region 21 can be selected according to actual conditions and is not limited here; the bottom depth of the first implantation region 21 can also be selected according to actual conditions and is not limited here. Here, thickness refers to the distance between the bottom surface of the first implantation region 21 and its upper surface (the upper surface of the epitaxial layer 2), and depth refers to the distance between the bottom surface of the first implantation region 21 and its upper surface. In this embodiment, the first implantation region 21 is formed using ion implantation, with an ion implantation energy not exceeding 300 keV, so that the implantation depth of the first implantation region 21 is less than 0.4 μm, i.e., the thickness of the first implantation region 21 is less than 0.4 μm.

[0077] Specifically, the photoresist layer can be removed after the opening 31 is formed and before the first injection region 21 is formed, or the photoresist layer can be removed after the first injection region 21 is formed and before the opening 31 is expanded outward.

[0078] Specifically, since the method for removing the photoresist layer is a common process, it will not be described in detail here.

[0079] As an example, after the opening 31 is formed, before each etching of the edge of the opening 31, the surface of the masking layer 3 is oxidized.

[0080] As an example, the method of etching the edge of the opening 31 includes wet etching or other suitable etching methods.

[0081] Specifically, the masking layer 3 is oxidized to form an oxide layer of a predetermined thickness on its surface, facilitating etching with a high-selectivity etchant. This etchant only etches the oxide layer on the surface of the masking layer 3, thereby expanding the edge of the opening 31. By expanding the opening 31 multiple times, and oxidizing the surface of the masking layer 3 after each expansion, an opening 31 with a gradually changing size is obtained. This facilitates the formation of the well region 23 with a pointed sidewall, while ensuring the consistency of the sidewall morphology of the expanded opening 31 and reducing the influence of lateral scattering. In this embodiment, the opening 31 is expanded twice, i.e., the masking layer 3 is oxidized twice. The second implantation region 22 consists of two doped regions 24.

[0082] Specifically, during the expansion of the opening 31, the etching reagent has a high etching selectivity for the oxide layer on the surface of the shielding layer 3 and the epitaxial layer 2 and the shielding layer 3. While etching the oxide layer on the surface of the shielding layer 3, there is almost no damage to the epitaxial layer 2. Moreover, after each expansion of the opening 31, the remaining shielding layer 22 can still serve as a mask layer to shield the non-ion implantation region of the epitaxial layer 2 and prevent ions from entering the non-ion implantation region of the epitaxial layer 2.

[0083] As an example, the method for forming the doped region 24 includes ion implantation or other suitable methods. In this embodiment, the doped region 24 is formed by ion implantation, and the ion implantation energy is not less than 300 keV.

[0084] As an example, the ion implantation energy for forming the first implantation region 21 is less than the ion implantation energy for forming the second implantation region 22, so that the particles when forming the doped region 24 penetrate the epitaxial layer 2 to a greater depth, thereby placing the first implantation region 21 above the doped region 24.

[0085] As an example, the ion implantation energy for forming the doped region 24 is different each time, while the doping concentration of the doped region 24 in the second implantation region 22 is the same.

[0086] Specifically, the depth and thickness of the doped region 24 are controlled by controlling the ion implantation energy that forms the doped region 24, thereby controlling the morphology of the second implantation region 22.

[0087] As an example, the sidewall of the second injection region 22 is formed with a pointed region.

[0088] Specifically, since the sidewall of the second implantation region 22 has a sharp tip region with a large curvature, the peak value of the electric field intensity in the device is transferred from the upper surface of the epitaxial layer 2 to the sharp tip region of the second implantation region 22, which reduces the surface electric field of the device and reduces the leakage current of the device. This improves the problem of excessive leakage current caused by image force, increases the reverse breakdown voltage of the device, and requires no additional equipment configuration or adjustment of ion implantation dose, making the process simple.

[0089] Specifically, such as Figure 5 and Figure 6The figures show cross-sectional structural diagrams of one type of well region 23 and another type of well region 23. Under the condition of ensuring device performance, the position of the tip of the second injection region 22 can be at any position of the sidewall of the second injection region 22, that is, the sidewall of the second injection region 22 is convex, or it can be at the bottom of the second injection region 22, that is, the tip is composed of the sidewall of the second injection region 22 and the bottom surface of the second injection region 22.

[0090] Specifically, when the tip is located on the sidewall of the second implantation region 22, after each expansion of the opening 31, at least two ion implantations with different ion implantation energies can be performed to form the doped regions 24 with different depths.

[0091] Specifically, while ensuring device performance, the number of tips located on the sidewall of the second injection region 22 can be one or more. In this embodiment, the number of tips on the sidewall of the second injection region 22 is one.

[0092] Specifically, while ensuring device performance, the doping concentration of the doped region 24 can be selected according to actual conditions, and is not limited here. In this embodiment, the first implantation region 21 and the doped region 24 have the same doping concentration.

[0093] Specifically, while ensuring device performance, the thickness of the second injection region 22 can be selected according to the actual situation, and is not limited here. The thickness here refers to the distance between the upper surface of the second injection region 22 (the lower surface of the first injection region 21) and the lower surface of the second injection region 22.

[0094] Specifically, while ensuring device performance, the depth of the bottom surface of the second implantation region 22 can be selected according to actual conditions when forming the second implantation region 22, and is not limited here. The depth here refers to the distance between the bottom surface of the second implantation region 22 and the upper surface of the epitaxial layer 2. In this embodiment, the bottom surface depth of the second implantation region 22 is not less than 0.4 μm.

[0095] Specifically, after forming the well region 23, an annealing step is also included.

[0096] Specifically, after the well region 23 is formed, annealing is used to make the doped ions in the well region 23 uniformly distributed and to activate the ions, while reducing the lattice damage of the epitaxial layer 2 caused by ion implantation.

[0097] Specifically, such as Figure 7 The diagram shown is a cross-sectional view of the structure after the shielding layer 3 is removed. After the trap region 23 is formed, the step of removing the shielding layer 3 is also included.

[0098] Specifically, since the method for removing the masking layer 3 is a common method, it will not be described in detail here.

[0099] Please see again Figure 8 Step S5 is performed: a first electrode 4 electrically connected to the epitaxial layer 2 and the well region 23 is formed on the upper surface of the epitaxial layer 2, and a second electrode 5 electrically connected to the substrate 1 is formed on the lower surface of the substrate 1.

[0100] Specifically, the method for forming the first electrode 4 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0101] Specifically, the method for forming the second electrode 5 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0102] The JBS diode fabrication method of this embodiment adjusts the process for forming the well region 23. First, the opening 31 is formed in the shielding layer 3, and then the first implantation region 21 located on the upper surface of the epitaxial layer 2 is formed based on the opening 31. After forming the first implantation region 21, the opening 31 is expanded multiple times. After each expansion, the surface of the shielding layer 3 is oxidized, and the oxide layer on the surface of the shielding layer 3 is etched. The opening 31 is enlarged by oxidizing the surface of the shielding layer 3 and then removing the oxide layer to obtain… The opening 31 has a gradually changing size, while ensuring the consistency of the sidewall morphology of the opening 31 after expansion, reducing the influence of lateral scattering of particles during ion implantation; based on the opening 31 after each expansion, a doped region 24 is formed below the first implantation region 21, the lower surface of the first implantation region 21 is in contact with the upper surface of the second implantation region 22 composed of the doped region 24, and the sidewall of the second implantation region 22 is formed with a tip, so that the sidewall of the well region 23 forms a tip region with a large curvature, and the process is simple.

[0103] Example 2

[0104] This embodiment provides a JBS diode structure, such as Figure 8The diagram shows a cross-sectional view of the JBS diode structure, including a first conductivity type substrate 1, a first conductivity type epitaxial layer 2, a second conductivity type well region 23, a first electrode 4, and a second electrode 5. The epitaxial layer 2 is located on the upper surface of the substrate 1. Multiple well regions 23 are spaced apart and located on the upper surface of the epitaxial layer 2. Each well region 23 includes a second conductivity type first implantation region 21 and a second conductivity type second implantation region 22. The bottom surface of the first implantation region 21 contacts the upper surface of the second implantation region 22. Multiple second conductivity type doped regions 24 are stacked upwards to form the second implantation region 22. The lateral width of each doped region 24 is greater than the lateral width of the first implantation region 21. The first electrode 4 is located on the upper surface of the epitaxial layer 2 and electrically connected to the epitaxial layer 2 and the well region 23. The second electrode 5 is located on the lower surface of the substrate 1 and electrically connected to the substrate 1.

[0105] Specifically, while ensuring device performance, the thickness of the substrate 1 can be selected according to the actual situation, and is not limited here.

[0106] Specifically, while ensuring device performance and the formation of ohmic contact between the substrate 1 and the second electrode 5, the doping concentration of the substrate 1 can be selected according to actual conditions, and is not limited here.

[0107] Specifically, while ensuring device performance, the thickness of the epitaxial layer 2 can be selected according to the actual situation, and is not limited here; the doping concentration of the epitaxial layer 2 can be set according to the actual situation, and is not limited here.

[0108] As an example, the sidewall of the second injection region 22 is provided with a pointed area.

[0109] Specifically, since the sidewall of the second injection region 22 has a pointed area, the sidewall of the well region 23 has a region with a large curvature (at the pointed end), which in turn enhances the electric field intensity at the pointed end of the sidewall of the second injection region 22. This causes the peak electric field intensity of the device to shift from the upper surface of the epitaxial layer 2 to the pointed end of the sidewall of the well region 23, thereby reducing the surface electric field of the device and reducing the problem of excessive leakage current caused by image force.

[0110] Specifically, the material of the first electrode 4 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.

[0111] Specifically, the material of the second electrode 5 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.

[0112] Specifically, such as Figure 8and Figure 9 As shown, they are respectively Figure 1 The electric field strength of the JBS diode structure in the present invention and the electric field strength of the JBS diode structure of the present invention as a function of epitaxial layer depth are shown in the curves. Figure 1 The leakage current versus reverse voltage curves of the JBS diode structure in the present invention and the JBS diode structure of the present invention are shown. Here, depth refers to the vertical distance from the upper surface of the epitaxial layer 2 to the interior of the epitaxial layer 2. The doping concentration and size of the epitaxial layer 02 and substrate 01 of the JBS diode are the same as those of the epitaxial layer 2 and substrate 1 of the JBS diode of the present invention. The doping concentration and effective size of the well region 021 of the JBS diode are the same as those of the well region 23 of the JBS diode of the present invention. Here, effective size refers to the cross-sectional area of ​​the well region 021 being the same as that of the well region 23. Figure 8 As can be seen, the maximum electric field strength of the JBS diode is located on the surface of the epitaxial layer, while the maximum electric field strength of the JBS diode of the present invention is located inside the epitaxial layer, at a certain distance from the upper surface of the epitaxial layer, and the electric field strength on the surface of the epitaxial layer is lower; from Figure 9 As can be seen, the leakage current of the JBS diode of the present invention is significantly lower than that of the JBS diode, and the reverse breakdown voltage of the JBS diode of the present invention is also significantly higher than that of the JBS diode. Figure 9 The experimental data is about 150V higher. By adjusting the process of forming the well region 23, the leakage current of the device is reduced and the reverse breakdown voltage of the device is increased. No additional equipment configuration or adjustment of ion implantation dose (doping concentration) is required, and the process is simple.

[0113] The JBS diode structure in this embodiment features a pointed region on the sidewall of the well region 23, resulting in a sharper, more curved sidewall. This increases the electric field strength at the sharper sidewall of the well region 23, causing the peak electric field strength in the device to shift from the upper surface of the epitaxial layer 2 to the sharper sidewall of the well region 23. This reduces the surface electric field of the device, thereby reducing leakage current and mitigating the problem of excessive leakage current caused by image force. It also improves the reverse breakdown voltage of the device. Furthermore, it requires no additional equipment configuration or adjustment of the ion implantation dose, simplifying the manufacturing process.

[0114] In summary, the JBS diode structure and its fabrication method of the present invention, by adjusting the process of forming the well region, firstly patterning the masking layer to form an opening, and then forming a first implantation region on the upper surface of the epitaxial layer based on the opening, then repeatedly oxidizing the surface of the masking layer, and etching the oxide layer on the surface of the masking layer after each oxidation, in order to obtain an opening with a gradually expanding opening size, while ensuring the consistency of the sidewall morphology of the opening during the outward expansion process, reducing the influence of lateral scattering of particles during ion implantation, and forming a doped region below the first implantation region and in contact with the lower surface of the first implantation region based on the opening after each outward expansion, and then sequentially upwards... The stacked doped regions form a second implantation region with pointed sidewalls, which in turn creates a well region composed of the first and second implantation regions, also with pointed sidewalls. This results in pointed sidewalls with significant curvature, increasing the electric field intensity at these pointed sidewalls. Consequently, the peak electric field intensity in the device shifts from the upper surface of the epitaxial layer to the pointed sidewalls of the well region, reducing the surface electric field and leakage current. This addresses the problem of excessive leakage current caused by image forces, improves the reverse breakdown voltage, and eliminates the need for additional equipment or ion implantation dosage adjustments, simplifying the process. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a JBS diode structure, characterized in that, Includes the following steps: A substrate of a first conductivity type is provided, and an epitaxial layer of the first conductivity type is formed on the upper surface of the substrate; A patterned masking layer is formed on the upper surface of the epitaxial layer to obtain a plurality of spaced openings, wherein the material of the masking layer includes polycrystalline silicon; A first injection region of a second conductivity type with a predetermined depth is formed based on the opening in the upper surface layer of the epitaxial layer; The edges of the opening in the shielding layer are etched multiple times to expand the edges of the opening. After each etching, a second conductivity type doped region with a lateral width greater than the first implantation region is formed below the first implantation region based on the expanded opening. Multiple doped regions are stacked upwards to form a second conductivity type second implantation region. The bottom surface of the first implantation region is in contact with the upper surface of the second implantation region. The first implantation region and the second implantation region form a second conductivity type well region. After the opening is formed, before each etching of the edge of the opening, the surface layer of the shielding layer is oxidized. The method for etching the edge of the opening includes wet etching. A pointed region is formed on the sidewall of the second implantation region. A first electrode electrically connected to the epitaxial layer and the well region is formed on the upper surface of the epitaxial layer, and a second electrode electrically connected to the substrate is formed on the lower surface of the substrate.

2. The method for fabricating the JBS diode structure according to claim 1, characterized in that: The method for forming the first implantation region includes ion implantation; the method for forming the doped region includes ion implantation.

3. The method for fabricating the JBS diode structure according to claim 2, characterized in that: The implantation energy of ions implanted to form the first implantation region is less than the implantation energy of ions implanted to form the doped region.

4. The method for fabricating the JBS diode structure according to claim 2, characterized in that: Each time the doped region is formed, the ion implantation energy is different, and the doping concentration of the doped region in the second implantation region is the same.

5. A JBS diode structure, characterized in that, The JBS diode structure is fabricated using the method for fabricating a JBS diode structure as described in any one of claims 1 to 4, including: First conductivity type substrate; A first conductivity type epitaxial layer is located on the upper surface of the substrate; Multiple spaced second conductivity type well regions are located on the upper surface of the epitaxial layer. The second conductivity type well region includes a second conductivity type first implantation region and a second conductivity type second implantation region. The bottom surface of the first implantation region is in contact with the upper surface of the second implantation region. Multiple second conductivity type doped regions are stacked upwards in sequence to form the second implantation region. The lateral width of the doped region is greater than the lateral width of the first implantation region. The sidewall of the second implantation region is provided with a sharp region. A first electrode and a second electrode, wherein the first electrode is located on the upper surface of the epitaxial layer and is electrically connected to the epitaxial layer and the well region, and the second electrode is located on the lower surface of the substrate and is electrically connected to the substrate.

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