A rail-to-rail fully differential folded cascode operational amplifier

Abstract

The invention relates to the field of amplifiers, and in particular to a rail-to-rail fully differential folded cascode operational amplifier, comprising a bias unit, a constant-transconductance rail-to-rail folded cascode input unit and a Class-AB differential output unit; the output end of the constant-transconductance rail-to-rail folded cascode input unit is electrically connected to the input end of the Class-AB differential output unit; the constant-transconductance rail-to-rail folded cascode input unit simultaneously adopts NMOS and PMOS differential pair structures to realize rail-to-rail input, adopts a maximum current method to ensure input constant transconductance, adopts a cascode structure to improve input stage gain, and adopts a switched capacitor common-mode feedback, wherein the sampled common-mode voltage is isolated from the input common-mode voltage, and the stability is good; the Class-AB differential output unit adopts an AB class output stage with a transconductance linear ring structure, thereby improving the output swing of the operational amplifier, and effectively improving the problem that the input and output dynamic ranges of traditional operational amplifiers cannot be rail-to-rail.

Description

Technical Field

[0001] The present invention relates to the field of operational amplifiers, and in particular to a rail-to-rail fully differential folded common-source common-gate operational amplifier. Background Art

[0002] An operational amplifier (OPA) is a circuit unit with a very high amplification factor. Its output signal can be the result of mathematical operations such as addition, subtraction, differentiation, and integration of the input signal. This feature has led to the use of operational amplifiers in early analog computers to implement mathematical operations, hence the name. An operational amplifier usually includes a differential amplifier circuit as an input stage, which has high input resistance and the ability to suppress zero drift; the intermediate stage performs voltage amplification and has a high voltage amplification factor; the output stage is connected to the load, and has the characteristics of strong load capacity and low output resistance.

[0003] There are many types of op amps, which can be divided into many types according to different classification standards, such as general-purpose, high-resistance, low-temperature drift, high-speed, low-power, high-voltage and high-power, and programmable control types. Each type of op amp has its specific application scenarios and advantages. For example, general-purpose operational amplifiers are inexpensive, large in quantity, and suitable for general use; while low-temperature drift operational amplifiers have the characteristics of high precision and low temperature drift, and are suitable for occasions such as precision instruments and weak signal detection.

[0004] Fully differential op amps have good anti-noise and anti-distortion performance. Their input stage is usually composed of differential pairs (such as NMOS and PMOS tubes), which have specific threshold voltages (Vth) and saturation voltages (Vsat). When the input common-mode voltage is too high or too low, it may cause the differential pair tubes to enter the non-saturation region or cutoff region, and thus fail to work properly. This will affect the gain, linearity, and stability of the op amp. Therefore, the existence of the MOS tube threshold voltage (Vth) limits the input common-mode voltage and output swing of traditional fully differential op amps. Summary of the invention

[0005] The purpose of the present invention is to provide a rail-to-rail fully differential folded common-source common-gate operational amplifier, aiming to solve the problem that the differential input common mode and differential output voltage of a traditional fully differential operational amplifier cannot reach the full swing when the operational amplifier is used in circuits such as a fully differential switched capacitor integrator in specific scenarios.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A rail-to-rail fully differential folded cascode operational amplifier, comprising a bias unit, a constant-transduction rail-to-rail folded cascode input unit and a Class-AB differential output unit;

[0008] The same-direction input terminal and the inverting input terminal of the constant-span rail-to-rail folded common-source common-gate input unit are electrically connected to the front-end signal output unit, the output terminal of the constant-span rail-to-rail folded common-source common-gate input unit is electrically connected to the input terminal of the Class-AB differential output unit, and the same-direction output terminal and the inverting output terminal of the Class-AB differential output unit are electrically connected to the rear-end signal receiving unit;

[0009] The bias unit is electrically connected to an external bias module, and the external bias module outputs a bias current I bias1 To the bias unit, the bias unit outputs a first bias voltage V B1 , the fourth bias voltage V B4 , the sixth bias voltage V B6 and the eighth bias voltage V B8 To the Class-AB differential output unit; the bias unit outputs a second bias voltage V B2 , the third bias voltage V B3 , the fifth bias voltage V B5 and the sixth bias voltage V B6 To constant-span rail-to-rail folded cascode input cell.

[0010] Furthermore, it also includes a switched capacitor common-mode feedback unit, wherein the same-direction input terminal and the inverting input terminal of the switched capacitor common-mode feedback unit are electrically connected to the same-direction output terminal and the inverting output terminal of the Class-AB differential output unit, and the output terminal of the switched capacitor common-mode feedback unit is electrically connected to the constant-span rail-to-rail folded common-source common-gate input unit, providing a seventh bias voltage V for the constant-span rail-to-rail folded common-source common-gate input unit. B7 .

[0011] Further, the switch capacitor common mode feedback unit includes MOS transistor N32, MOS transistor P32, clock switch 9S1, clock switch 10S1, clock switch 11S1, clock switch 12S1, clock switch 13S1, clock switch 5S2, clock switch 6S2, clock switch 7S2, clock switch 8S2 and capacitor C1, capacitor C2, capacitor C3, capacitor C4;

[0012] One end of the clock switch 9S1, one end of the clock switch 12S1 and the source of the MOS transistor P32 are all electrically connected to the external power supply VDD1;

[0013] The other end of the clock switch 9S1 is electrically connected to one end of the capacitor C4 and one end of the clock switch 5S2, the other end of the clock switch 5S2 is electrically connected to one end of the clock switch 6S2 and the reverse output end of the Class-AB differential output unit, and the other end of the clock switch 6S2 is electrically connected to one end of the clock switch 11S1 and one end of the capacitor C1;

[0014] The other end of the clock switch 12S1 is electrically connected to one end of the capacitor C3 and one end of the clock switch 7S2, the other end of the clock switch 7S2 is electrically connected to one end of the clock switch 8S2 and the same-direction output end of the Class-AB differential output unit, and the other end of the clock switch 8S2 is electrically connected to one end of the clock switch 13S1 and one end of the capacitor C2;

[0015] The other end of the capacitor C4 is electrically connected to the other end of the capacitor C3, the other end of the capacitor C1, the other end of the capacitor C2, one end of the clock switch 10S1 and the gate of the MOS transistor N32, the drain of the MOS transistor N32 is electrically connected to the gate and drain of the MOS transistor P32, and outputs the seventh bias voltage V B7 To the constant cross rail-to-rail folded common source and common gate input unit; the bias unit outputs a sixth bias voltage V B6 To the other end of the clock switch 10S1;

[0016] The other end of the clock switch 11S1, the other end of the clock switch 13S1 and the source of the MOS transistor N32 are all grounded.

[0017] Furthermore, the capacitance values ​​of the capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4 are equal.

[0018] Further, the bias unit includes MOS transistor P10, MOS transistor P11, MOS transistor P12, MOS transistor P13, MOS transistor P14, MOS transistor P15, MOS transistor N11, MOS transistor N12, MOS transistor N13, MOS transistor N14, MOS transistor N15, MOS transistor N16, MOS transistor N17, MOS transistor N18 and MOS transistor N19;

[0019] The source of the MOS transistor P10, the source of the MOS transistor P11, the source of the MOS transistor P13 and the source of the MOS transistor P14 are all electrically connected to the external power supply VDD1;

[0020] The gate and drain of the MOS transistor P10 are electrically connected to the gate of the MOS transistor P11 and the drain of the MOS transistor N13, and outputs a second bias voltage V B2 To the constant-span rail-to-rail folded common-source common-gate input unit; the external bias module outputs the bias current I bias1 To the drain and gate of the MOS tube N11, the gate of the MOS tube N13, the gate of the MOS tube N16 and the gate of the MOS tube N18, and output the first bias voltage V B1To the Class-AB differential output unit; the source of the MOS tube N11 is electrically connected to the drain, gate, gate of the MOS tube N12, gate of the MOS tube N14, gate of the MOS tube N17 and gate of the MOS tube N19, and outputs a sixth bias voltage V B6 To the constant-cross-rail-to-rail folded common-source common-gate input unit; the source of the MOS tube N13 is electrically connected to the drain of the MOS tube N14;

[0021] The drain of the MOS transistor P11 is electrically connected to the source of the MOS transistor P12, the gate of the MOS transistor P12 is electrically connected to the gate and drain of the MOS transistor P13 and the drain of the MOS transistor N16, and outputs a fifth bias voltage V B5 To the constant cross rail-to-rail folded common source and common gate input unit, the source of the MOS tube N16 is electrically connected to the drain of the MOS tube N17; the drain of the MOS tube P12 is electrically connected to the gate and drain of the MOS tube N15, and outputs a third bias voltage V B3 To the constant-span rail-to-rail folded cascode input unit;

[0022] The gate and drain of the MOS transistor P14 are electrically connected to the source of the MOS transistor P15, and output a fourth bias voltage V B4 To the Class-AB differential output unit; the gate and drain of the MOS tube P15 are electrically connected to the drain of the MOS tube N18, and outputs the eighth bias voltage V B8 To the Class-AB differential output unit, the source of the MOS tube N18 is electrically connected to the drain of the MOS tube N19;

[0023] The source of the MOS transistor N12, the source of the MOS transistor N1, the source of the MOS transistor N15, the source of the MOS transistor N17 and the source of the MOS transistor N19 are all grounded.

[0024] Further, the constant-cross-rail-to-rail folded common-source common-gate input unit includes MOS transistor P16, MOS transistor P17, MOS transistor P18, MOS transistor P19, MOS transistor P20, MOS transistor P21, MOS transistor P22, MOS transistor P23, MOS transistor P24, MOS transistor P25, MOS transistor P26, MOS transistor P27, MOS transistor P28, MOS transistor P29, MOS transistor P30, MOS transistor P31, MOS transistor P39, MOS transistor P40, MOS transistor N20, MOS transistor N21, MOS transistor N22, MOS transistor N23, MOS transistor N24, MOS transistor N25, MOS transistor N26, MOS transistor N27, MOS transistor N28, MOS transistor N29, MOS transistor N30 and MOS transistor N31;

[0025] The source of the MOS transistor P16, the source of the MOS transistor P17, the source of the MOS transistor P18, the source of the MOS transistor P22, the source of the MOS transistor P23, the source of the MOS transistor P24, the source of the MOS transistor P25, the source of the MOS transistor P26, the source of the MOS transistor P27, the source of the MOS transistor P28, the source of the MOS transistor P29, the source of the MOS transistor P39 and the source of the MOS transistor P40 are all electrically connected to the external power supply VDD1;

[0026] The gate of the MOS transistor P16 is electrically connected to the gate and drain of the MOS transistor P17, the drain of the MOS transistor N20, and the gate of the MOS transistor P40; the drain of the MOS transistor P16 is electrically connected to the gate and drain of the MOS transistor P24, the gate of the MOS transistor P39, and the drain of the MOS transistor N24;

[0027] The bias unit outputs a second bias voltage V B2 to the gate of the MOS tube P18; the drain of the MOS tube P18 is electrically connected to the source of the MOS tube P19, and the bias unit outputs a fifth bias voltage V B5 to the gate of the MOS tube P19; the drain of the MOS tube P19 is electrically connected to the source of the MOS tube P20 and the source of the MOS tube P21; the gate of the MOS tube P20 is electrically connected to the gate of the MOS tube N25, and is electrically connected to the front signal output unit as a reverse input terminal; the gate of the MOS tube P21 is electrically connected to the gate of the MOS tube N24, and is electrically connected to the front signal output unit as a non-inverting input terminal; the drain of the MOS tube P20 is electrically connected to the gate of the MOS tube N20 and the gate and drain of the MOS tube N21; the drain of the MOS tube P21 is electrically connected to the gate of the MOS tube N23 and the gate and drain of the MOS tube N22;

[0028] The gate and drain of the MOS transistor P22 are electrically connected to the drain of the MOS transistor N23, the gate of the MOS transistor P23 and the gate of the MOS transistor P27; the drain of the MOS transistor P23 is electrically connected to the drain of the MOS transistor N25, the drain and gate of the MOS transistor P25 and the gate of the MOS transistor P26; the source of the MOS transistor N25 is electrically connected to the source of the MOS transistor N24 and the drain of the MOS transistor N26; the bias unit outputs a third bias voltage V B3 to the gate of the MOS tube N26, the source of the MOS tube N26 is electrically connected to the drain of the MOS tube N27; the bias unit outputs a sixth bias voltage V B6 To the gate of MOS tube N27;

[0029] The drain of the MOS transistor P26 is electrically connected to the drain of the MOS transistor P27, the source of the MOS transistor N30 and the drain of the MOS transistor N31; the drain of the MOS transistor P39 is electrically connected to the drain of the MOS transistor P40, the source of the MOS transistor N28 and the drain of the MOS transistor N29; the bias unit outputs a third bias voltage V B3 To the gate of MOS tube N28 and the gate of MOS tube N30; the bias unit outputs a sixth bias voltage V B6 To the gate of MOS tube N29 and the gate of MOS tube N31;

[0030] The drain of the MOS transistor N28 is electrically connected to the first input terminal of the Class-AB differential output unit as the first output terminal; the drain of the MOS transistor N30 is electrically connected to the second input terminal of the Class-AB differential output unit as the second output terminal;

[0031] The gate of the MOS transistor P28 is electrically connected to the gate of the MOS transistor P29; the drain of the MOS transistor P28 is electrically connected to the source of the MOS transistor P30, and the drain of the MOS transistor P29 is electrically connected to the source of the MOS transistor P31; the bias unit outputs a fifth bias voltage V B5 to the gate of the MOS tube P30 and the gate of the MOS tube P31; the drain of the MOS tube P30 is electrically connected to the third input terminal of the Class-AB differential output unit as the third output terminal; the drain of the MOS tube P31 is electrically connected to the fourth input terminal of the Class-AB differential output unit as the fourth output terminal;

[0032] The source of the MOS transistor N20 , the source of the MOS transistor N21 , the source of the MOS transistor N22 , the source of the MOS transistor N23 , the source of the MOS transistor N27 , the source of the MOS transistor N29 and the source of the MOS transistor N31 are all grounded.

[0033] Further, the Class-AB differential output unit includes MOS transistor P16, MOS transistor P32, MOS transistor P33, MOS transistor P34, MOS transistor P35, MOS transistor P36, MOS transistor P37, MOS transistor P38, MOS transistor P41, MOS transistor P42, MOS transistor N32, MOS transistor N33, MOS transistor N34, MOS transistor N37, MOS transistor N38, MOS transistor N39, MOS transistor N40, MOS transistor N41, MOS transistor N42 and capacitor C5, capacitor C6, capacitor C7, capacitor C8;

[0034] The source of the MOS transistor P34, the source of the MOS transistor P35, the source of the MOS transistor P36, and the source of the MOS transistor P42 are all electrically connected to the external power supply VDD1;

[0035] The drain of the MOS transistor P33 and the source of the MOS transistor N33 are electrically connected to the first output end of the constant-span rail-to-rail folded common-source common-gate input unit as the first input end; the drain of the MOS transistor P41 and the source of the MOS transistor N34 are electrically connected to the second output end of the constant-span rail-to-rail folded common-source common-gate input unit as the second input end; the source of the MOS transistor P33 and the drain of the MOS transistor N33 are electrically connected to the third output end of the constant-span rail-to-rail folded common-source common-gate input unit as the third input end. The source of the MOS tube P41 and the drain of the MOS tube N34 are electrically connected to the fourth output terminal of the constant cross rail-to-rail folded common source and common gate input unit as the fourth input terminal; the gate of the MOS tube P33 is electrically connected to the gate of the MOS tube P41, the gate and drain of the MOS tube P37, and the drain of the MOS tube N38; the gate of the MOS tube N33 is electrically connected to the gate of the MOS tube N34, the gate and drain of the MOS tube 40, and the drain of the MOS tube P38;

[0036] The bias unit outputs a first bias voltage V B1 to the gate of the MOS tube N38; the source of the MOS tube N38 is electrically connected to the drain of the MOS tube N39, and the bias unit outputs a sixth bias voltage V B6 to the gate of the MOS tube N39; the source of the MOS tube N40 is electrically connected to the drain and gate of the MOS tube N41;

[0037] The gate and drain of the MOS transistor P34 are electrically connected to the source of the MOS transistor P37; the bias unit outputs a fourth bias voltage V B4 to the gate of the MOS tube P35; the drain of the MOS tube P35 is electrically connected to the source of the MOS tube P38, and the bias unit outputs an eighth bias voltage V B8 To the gate of MOS tube P38;

[0038] The gate of the MOS transistor P36 is electrically connected to one end of the capacitor C5, the source of the MOS transistor P33 and the drain of the MOS transistor N33. The other end of the capacitor C5 is electrically connected to the drain of the MOS transistor P36, one end of the capacitor C6 and the drain of the MOS transistor N37, and is electrically connected to the post-signal receiving unit as a reverse output end; the gate of the MOS transistor N37 is electrically connected to the other end of the capacitor C6, the drain of the MOS transistor P33 and the source of the MOS transistor N33; the gate of the MOS transistor P42 is electrically connected to one end of the capacitor C7, the source of the MOS transistor P41 and the drain of the MOS transistor N34, the other end of the capacitor C7 is electrically connected to the drain of the MOS transistor P42, one end of the capacitor C8 and the drain of the MOS transistor N42, and is electrically connected to the post-signal receiving unit as a unidirectional output end; the gate of the MOS transistor N42 is electrically connected to the other end of the capacitor C8, the drain of the MOS transistor P41 and the source of the MOS transistor N34;

[0039] The source of the MOS transistor N37, the source of the MOS transistor N39, the source of the MOS transistor N41 and the source of the MOS transistor N42 are all grounded.

[0040] Further, the external clock module outputs the S1 clock signal to the clock switch 9S1, the clock switch 10S1, the clock switch 11S1, the clock switch 12S1 and the clock switch 13S1;

[0041] The external clock module outputs the S2 clock signal to the clock switch 5S2, the clock switch 6S2, the clock switch 7S2, and the clock switch 8S2;

[0042] The S1 clock signal and the S2 clock signal are two-phase non-overlapping clocks.

[0043] Furthermore, the clock switch 9S1, the clock switch 10S1, the clock switch 11S1, the clock switch 12S1, the clock switch 13S1, the clock switch 5S2, the clock switch 6S2, the clock switch 7S2, and the clock switch 8S2 are transmission gates.

[0044] After adopting the above technical solution, the present invention has the following advantages compared with the background technology:

[0045] 1. The constant transconductance rail-to-rail folded common source and common gate input unit adopts NMOS and PMOS differential pair structures to achieve rail-to-rail input, adopts the maximum current method to ensure input constant transconductance, and adopts common source and common gate structure to improve input stage gain; the Class-AB differential output unit adopts a Class AB output stage with a transconductance linear ring structure, which can improve the output swing of the op amp and effectively improve the problem that the input and output dynamic range of traditional op amps cannot be rail-to-rail. It can be applied to circuits such as fully differential switched capacitor integrators that have high requirements on the op amp input common mode range and output swing and require differential output in specific scenarios.

[0046] 2. Using switched capacitor common-mode feedback, the sampled common-mode voltage is isolated from the input common-mode voltage and has better stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A circuit diagram of a bias unit of the rail-to-rail fully differential folded cascode operational amplifier of the present invention;

[0048] Figure 2 It is a partial circuit diagram of the rail-to-rail fully differential folded cascode operational amplifier of the present invention;

[0049] Figure 3 A circuit diagram of a switched capacitor common-mode feedback unit of the rail-to-rail fully differential folded cascode operational amplifier of the present invention;

[0050] Figure 4 A circuit diagram of the external clock module of the present invention;

[0051] Figure 5 The waveform diagram is a diagram of the S1 clock signal and the S2 clock signal output by the external clock module of the present invention.

[0052] Description of reference numerals:

[0053] 1. Bias unit; 2. Constant cross rail-to-rail folded common source and common gate input unit; 3. Class-AB differential output unit. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0055] In addition, it should be noted that the terms "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element of the present invention must have a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0056] When an element is referred to as being “fixed to” or “disposed on” or “provided on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0057] Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances. Example

[0058] Please refer to Figure 1-5 As shown, this embodiment provides a rail-to-rail fully differential folded cascode operational amplifier, including a bias unit 1, a constant-transistor rail-to-rail folded cascode input unit 2 and a Class-AB differential output unit 3.

[0059] The same-direction input terminal and the inverting input terminal of the constant-span rail-to-rail folded common-source and common-gate input unit 2 are electrically connected to the front-end signal output unit, the output terminal of the constant-span rail-to-rail folded common-source and common-gate input unit 2 is electrically connected to the input terminal of the Class-AB differential output unit 3, and the same-direction output terminal and the inverting output terminal of the Class-AB differential output unit 3 are electrically connected to the rear-end signal receiving unit.

[0060] The bias unit 1 is electrically connected to the external bias module, and the external bias module outputs a bias current I bias1 To bias unit 1, bias unit 1 outputs a first bias voltage V B1 , the fourth bias voltage V B4 , the sixth bias voltage V B6 and the eighth bias voltage V B8 To Class-AB differential output unit 3; bias unit 1 outputs a second bias voltage V B2 , the third bias voltage V B3 , the fifth bias voltage V B5 and the sixth bias voltage V B6 To the constant-span rail-to-rail folded common-source common-gate input unit 2.

[0061] Please refer to Figure 1 and Figure 2 As shown, Figure 1 and Figure 2Specifically, the bias unit 1 includes MOS transistors P10, P11, P12, P13, P14, P15, N11, N12, N13, N14, N15, N16, N17, N18, and N19.

[0062] The source of the MOS transistor P10 , the source of the MOS transistor P11 , the source of the MOS transistor P13 , and the source of the MOS transistor P14 are all electrically connected to the external power source VDD1 .

[0063] The gate and drain of the MOS transistor P10 are electrically connected to the gate of the MOS transistor P11 and the drain of the MOS transistor N13, and outputs a second bias voltage V B2 To the constant cross rail-to-rail folded common source and common gate input unit 2. The external bias module outputs the bias current I bias1 To the drain and gate of the MOS tube N11, the gate of the MOS tube N13, the gate of the MOS tube N16 and the gate of the MOS tube N18, and output the first bias voltage V B1 To Class-AB differential output unit 3. The source of MOS transistor N11 is electrically connected to the drain, gate, gate of MOS transistor N12, gate of MOS transistor N14, gate of MOS transistor N17 and gate of MOS transistor N19, and outputs the sixth bias voltage V B6 To the constant cross rail-to-rail folded common source and common gate input unit 2. The source of the MOS tube N13 is electrically connected to the drain of the MOS tube N14.

[0064] The drain of the MOS transistor P11 is electrically connected to the source of the MOS transistor P12, the gate of the MOS transistor P12 is electrically connected to the gate and drain of the MOS transistor P13 and the drain of the MOS transistor N16, and outputs a fifth bias voltage V B5 To the constant cross rail-to-rail folded common source and common gate input unit 2. The source of MOS tube N16 is electrically connected to the drain of MOS tube N17; the drain of MOS tube P12 is electrically connected to the gate and drain of MOS tube N15, and outputs the third bias voltage V B3 To the constant-span rail-to-rail folded common-source common-gate input unit 2.

[0065] The gate and drain of the MOS transistor P14 are electrically connected to the source of the MOS transistor P15, and output a fourth bias voltage V B4 To the Class-AB differential output unit 3. The gate and drain of the MOS transistor P15 are electrically connected to the drain of the MOS transistor N18, and outputs the eighth bias voltage V B8To the Class-AB differential output unit 3. The source of the MOS transistor N18 is electrically connected to the drain of the MOS transistor N19.

[0066] The source of the MOS transistor N12, the source of the MOS transistor N1, the source of the MOS transistor N15, the source of the MOS transistor N17 and the source of the MOS transistor N19 are all grounded.

[0067] Specifically, the constant cross rail-to-rail folded common source and common gate input unit 2 includes MOS tube P16, MOS tube P17, MOS tube P18, MOS tube P19, MOS tube P20, MOS tube P21, MOS tube P22, MOS tube P23, MOS tube P24, MOS tube P25, MOS tube P26, MOS tube P27, MOS tube P28, MOS tube P29, MOS tube P30, MOS tube P31, MOS tube P39, MOS tube P40, MOS tube N20, MOS tube N21, MOS tube N22, MOS tube N23, MOS tube N24, MOS tube N25, MOS tube N26, MOS tube N27, MOS tube N28, MOS tube N29, MOS tube N30 and MOS tube N31.

[0068] The source of MOS transistor P16, the source of MOS transistor P17, the source of MOS transistor P18, the source of MOS transistor P22, the source of MOS transistor P23, the source of MOS transistor P24, the source of MOS transistor P25, the source of MOS transistor P26, the source of MOS transistor P27, the source of MOS transistor P28, the source of MOS transistor P29, the source of MOS transistor P39 and the source of MOS transistor P40 are all electrically connected to the external power supply VDD1.

[0069] The gate of MOS transistor P16 is electrically connected to the gate and drain of MOS transistor P17, the drain of MOS transistor N20 and the gate of MOS transistor P40. The drain of MOS transistor P16 is electrically connected to the gate and drain of MOS transistor P24, the gate of MOS transistor P39 and the drain of MOS transistor N24.

[0070] Bias unit 1 outputs a second bias voltage V B2 To the gate of MOS transistor P18, that is, the gate and drain of MOS transistor P10 are electrically connected to the gate of MOS transistor P18. The drain of MOS transistor P18 is electrically connected to the source of MOS transistor P19, and bias unit 1 outputs a fifth bias voltage V B5To the gate of MOS transistor P19, that is, the drain of MOS transistor P11 is electrically connected to the gate of MOS transistor P19; the drain of MOS transistor P19 is electrically connected to the source of MOS transistor P20 and the source of MOS transistor P21. The gate of MOS transistor P20 is electrically connected to the gate of MOS transistor N25, and is electrically connected to the front signal output unit as a reverse input terminal. The gate of MOS transistor P21 is electrically connected to the gate of MOS transistor N24, and is electrically connected to the front signal output unit as a non-inverting input terminal. The drain of MOS transistor P20 is electrically connected to the gate of MOS transistor N20 and the gate and drain of MOS transistor N21; the drain of MOS transistor P21 is electrically connected to the gate of MOS transistor N23 and the gate and drain of MOS transistor N22.

[0071] The gate and drain of MOS transistor P22 are electrically connected to the drain of MOS transistor N23, the gate of MOS transistor P23 and the gate of MOS transistor P27. The drain of MOS transistor P23 is electrically connected to the drain of MOS transistor N25, the drain and gate of MOS transistor P25 and the gate of MOS transistor P26; the source of MOS transistor N25 is electrically connected to the source of MOS transistor N24 and the drain of MOS transistor N26. Bias unit 1 outputs a third bias voltage V B3 To the gate of MOS transistor N26, that is, the drain of MOS transistor P12 is electrically connected to the gate of MOS transistor N26. The source of MOS transistor N26 is electrically connected to the drain of MOS transistor N27; bias unit 1 outputs a sixth bias voltage V B6 To the gate of the MOS transistor N27, that is, the source of the MOS transistor N11 is electrically connected to the gate of the MOS transistor N27.

[0072] The drain of MOS transistor P26 is electrically connected to the drain of MOS transistor P27, the source of MOS transistor N30 and the drain of MOS transistor N31; the drain of MOS transistor P39 is electrically connected to the drain of MOS transistor P40, the source of MOS transistor N28 and the drain of MOS transistor N29. Bias unit 1 outputs a third bias voltage V B3 The bias unit 1 outputs the sixth bias voltage V B6 The gate of the MOS transistor N29 and the gate of the MOS transistor N31, that is, the source of the MOS transistor N11 is electrically connected to the gate of the MOS transistor N29 and the gate of the MOS transistor N31. The drain of the MOS transistor N28 is electrically connected to the first input terminal of the Class-AB differential output unit 3 as the first output terminal; the drain of the MOS transistor N30 is electrically connected to the second input terminal of the Class-AB differential output unit 3 as the second output terminal.

[0073] The gate of MOS transistor P28 is electrically connected to the gate of MOS transistor P29; the drain of MOS transistor P28 is electrically connected to the source of MOS transistor P30, and the drain of MOS transistor P29 is electrically connected to the source of MOS transistor P31. Bias unit 1 outputs a fifth bias voltage V B5 The gate of the MOS transistor P30 and the gate of the MOS transistor P31, that is, the drain of the MOS transistor P11 is electrically connected to the gate of the MOS transistor P30 and the gate of the MOS transistor P31. The drain of the MOS transistor P30 is electrically connected to the third input terminal of the Class-AB differential output unit 3 as the third output terminal; the drain of the MOS transistor P31 is electrically connected to the fourth input terminal of the Class-AB differential output unit 3 as the fourth output terminal.

[0074] The source of the MOS transistor N20, the source of the MOS transistor N21, the source of the MOS transistor N22, the source of the MOS transistor N23, the source of the MOS transistor N27, the source of the MOS transistor N29 and the source of the MOS transistor N31 are all grounded.

[0075] Specifically, the Class-AB differential output unit 3 includes MOS transistor P16, MOS transistor P32, MOS transistor P33, MOS transistor P34, MOS transistor P35, MOS transistor P36, MOS transistor P37, MOS transistor P38, MOS transistor P41, MOS transistor P42, MOS transistor N32, MOS transistor N33, MOS transistor N34, MOS transistor N37, MOS transistor N38, MOS transistor N39, MOS transistor N40, MOS transistor N41, MOS transistor N42 and capacitor C5, capacitor C6, capacitor C7, and capacitor C8.

[0076] The source of the MOS transistor P34 , the source of the MOS transistor P35 , the source of the MOS transistor P36 , and the source of the MOS transistor P42 are all electrically connected to the external power source VDD1 .

[0077] The drain of MOS transistor P33 and the source of MOS transistor N33 are electrically connected to the first output end of the constant-cross-rail-to-rail folded common-source common-gate input unit 2 as the first input end; that is, the drain of MOS transistor N28 is electrically connected to the drain of MOS transistor P33 and the source of MOS transistor N33. The drain of MOS transistor P41 and the source of MOS transistor N34 are electrically connected to the second output end of the constant-cross-rail-to-rail folded common-source common-gate input unit 2 as the second input end, that is, the drain of MOS transistor N30 is electrically connected to the drain of MOS transistor P41 and the source of MOS transistor N34. The source of MOS transistor P33 and the drain of MOS transistor N33 are electrically connected to the third output end of the constant-cross-rail-to-rail folded common-source common-gate input unit 2 as the third input end; that is, the drain of MOS transistor P30 is electrically connected to the source of MOS transistor P33 and the drain of MOS transistor N33. The source of MOS transistor P41 and the drain of MOS transistor N34 are electrically connected to the fourth output terminal of the constant cross rail-to-rail folded common source and common gate input unit 2 as the fourth input terminal, that is, the drain of MOS transistor P31 is electrically connected to the source of MOS transistor P41 and the drain of MOS transistor N34. The gate of MOS transistor P33 is electrically connected to the gate of MOS transistor P41, the gate and drain of MOS transistor P37, and the drain of MOS transistor N38; the gate of MOS transistor N33 is electrically connected to the gate of MOS transistor N34, the gate and drain of MOS transistor 40, and the drain of MOS transistor P38.

[0078] Bias unit 1 outputs a first bias voltage V B1 The gate of the MOS tube N38 is electrically connected to the drain of the MOS tube N11, the gate of the MOS tube N38 is electrically connected to the drain of the MOS tube N39, and the bias unit 1 outputs the sixth bias voltage V B6 The gate of the MOS transistor N39, that is, the source of the MOS transistor N11 is electrically connected to the gate of the MOS transistor N39. The source of the MOS transistor N40 is electrically connected to the drain and gate of the MOS transistor N41.

[0079] The gate and drain of the MOS transistor P34 are electrically connected to the source of the MOS transistor P37; the bias unit 1 outputs a fourth bias voltage V B4 The gate of the MOS transistor P35, that is, the gate and drain of the MOS transistor P14 are electrically connected to the gate of the MOS transistor P35. The drain of the MOS transistor P35 is electrically connected to the source of the MOS transistor P38. The bias unit 1 outputs the eighth bias voltage V B8 To the gate of the MOS transistor P38, that is, the gate and drain of the MOS transistor P15 are electrically connected to the gate of the MOS transistor P38.

[0080] The gate of MOS transistor P36 is electrically connected to one end of capacitor C5, the source of MOS transistor P33 and the drain of MOS transistor N33. The other end of capacitor C5 is electrically connected to the drain of MOS transistor P36, one end of capacitor C6 and the drain of MOS transistor N37, and is electrically connected to the post-signal receiving unit as a reverse output end. The gate of MOS transistor N37 is electrically connected to the other end of capacitor C6, the drain of MOS transistor P33 and the source of MOS transistor N33. The gate of MOS transistor P42 is electrically connected to one end of capacitor C7, the source of MOS transistor P41 and the drain of MOS transistor N34. The other end of capacitor C7 is electrically connected to the drain of MOS transistor P42, one end of capacitor C8 and the drain of MOS transistor N42, and is electrically connected to the post-signal receiving unit as a non-inverting output end. The gate of MOS transistor N42 is electrically connected to the other end of capacitor C8, the drain of MOS transistor P41 and the source of MOS transistor N34.

[0081] The source of the MOS transistor N37, the source of the MOS transistor N39, the source of the MOS transistor N41, and the source of the MOS transistor N42 are all grounded.

[0082] The constant transconductance rail-to-rail folded cascode input unit 2 of the rail-to-rail fully differential folded cascode operational amplifier uses both NMOS and PMOS differential pair structures to achieve rail-to-rail input, uses the maximum current method to achieve input constant transconductance, and uses switched capacitor common-mode feedback. Its sampled common-mode voltage is isolated from the input common-mode voltage, and has good stability. The Class-AB differential output unit 3 of the rail-to-rail fully differential folded cascode operational amplifier uses a Class-AB differential output stage with a translinear ring structure to effectively improve the output swing of the operational amplifier.

[0083] The explanation for constant transconductance is as follows:

[0084] Assume that the relationship between the non-inverting input terminal and the reverse input terminal is V in+ >V in- , we can get:

[0085] ;

[0086] ;

[0087] ;

[0088] ;

[0089] Among them, V id is the small signal differential input voltage, I nr and I np is the tail current of the differential pair of NMOS and PMOS tubes, ɡ mp andɡ mnThey are the transconductance of the differential pair of NMOS and PMOS tubes respectively.

[0090] From the circuit we can see

[0091] ;

[0092] ;

[0093] ;

[0094] Among them, I o is the output current of the input stage;

[0095] When only the PMOS tube differential pair is working and the NMOS tube differential pair is turned off, we can get:

[0096] I nr pr =I rmax , mn < mp，max = m，max ;

[0097] I o = m，max ·V id ;

[0098] When only the NMOS tube differential pair is working and the PMOS tube differential pair is turned off, we can get:

[0099] I pr nr =I rmax , mp < mn，max = m，max ;

[0100] I o = m，max ·V id ;

[0101] When both the PMOS tube and the NMOS tube are turned on, we can get:

[0102] I pr =I nr =I rmax , mp，max = mn，max = m，max ;

[0103] I o = m，max ·V id ;

[0104] Among them, m，max is the maximum transconductance of the complementary differential pair, I​​rmax is the maximum value of tail current, ɡ mn，max andɡ mp，max They are the maximum transconductance of the differential pair of NPMOS and PMOS tubes respectively. The maximum current selection circuit can select the maximum value of the PMOS differential input pair tube current, which can keep the input stage transconductance constant. = .

[0105] Please refer to Figure 2 and Figure 3 As shown, further, the rail-to-rail fully differential folded common-source common-gate operational amplifier also includes a switched capacitor common-mode feedback unit, the same-direction input terminal and the inverting input terminal of the switched capacitor common-mode feedback unit are electrically connected to the same-direction output terminal and the inverting output terminal of the Class-AB differential output unit 3, and the output terminal of the switched capacitor common-mode feedback unit is electrically connected to the constant-span rail-to-rail folded common-source common-gate input unit 2, providing a seventh bias voltage V for the constant-span rail-to-rail folded common-source common-gate input unit 2. B7 .

[0106] Specifically, the switch capacitor common mode feedback unit includes MOS transistor N32, MOS transistor P32, clock switch 9S1, clock switch 10S1, clock switch 11S1, clock switch 12S1, clock switch 13S1, clock switch 5S2, clock switch 6S2, clock switch 7S2, clock switch 8S2 and capacitor C1, capacitor C2, capacitor C3, capacitor C4. The external clock module outputs the S1 clock signal to control the on and off of the clock switch 9S1, clock switch 10S1, clock switch 11S1, clock switch 12S1, and clock switch 13S1; the external clock module outputs the S2 clock signal to control the on and off of the clock switch 5S2, clock switch 6S2, clock switch 7S2, and clock switch 8S2. In this embodiment, the clock switch 9S1, clock switch 10S1, clock switch 11S1, clock switch 12S1, clock switch 13S1, clock switch 5S2, clock switch 6S2, clock switch 7S2, and clock switch 8S2 are transmission gates.

[0107] One end of the clock switch 9S1, one end of the clock switch 12S1 and the source of the MOS transistor P32 are all electrically connected to the external power source VDD1.

[0108] The other end of the clock switch 9S1 is electrically connected to one end of the capacitor C4 and one end of the clock switch 5S2, and the other end of the clock switch 5S2 is electrically connected to one end of the clock switch 6S2 and the reverse output end of the Class-AB differential output unit 3, that is, the other end of the clock switch 5S2 is electrically connected to the other end of the capacitor C5. The other end of the clock switch 6S2 is electrically connected to one end of the clock switch 11S1 and one end of the capacitor C1.

[0109] The other end of the clock switch 12S1 is electrically connected to one end of the capacitor C3 and one end of the clock switch 7S2, and the other end of the clock switch 7S2 is electrically connected to one end of the clock switch 8S2 and the same-direction output end of the Class-AB differential output unit 3, that is, the other end of the clock switch 7S2 is electrically connected to the other end of the capacitor C7. The other end of the clock switch 8S2 is electrically connected to one end of the clock switch 13S1 and one end of the capacitor C2.

[0110] The other end of capacitor C4 is electrically connected to the other end of capacitor C3, the other end of capacitor C1, the other end of capacitor C2, one end of clock switch 10S1 and the gate of MOS transistor N32. The drain of MOS transistor N32 is electrically connected to the gate and drain of MOS transistor P32, and outputs the seventh bias voltage V B7 To the constant cross rail-to-rail folded common source and common gate input unit 2; that is, the drain of MOS tube N32 is electrically connected to the gate and drain of MOS tube P32, the gate of MOS tube P28 and the gate of MOS tube P29. Bias unit 1 outputs the sixth bias voltage V B6 The other end of the clock switch 10S1 , ie, the source of the MOS transistor N11 is electrically connected to the other end of the clock switch 10S1 .

[0111] The other end of the clock switch 11S1, the other end of the clock switch 13S1 and the source of the MOS transistor N32 are all grounded.

[0112] Please refer to the attached Figure 4 and Figure 5 Specifically, the external clock module outputs the S1 clock signal to the clock switch 9S1, the clock switch 10S1, the clock switch 11S1, the clock switch 12S1 and the clock switch 13S1; the external clock module outputs the S2 clock signal to the clock switch 5S2, the clock switch 6S2, the clock switch 7S2 and the clock switch 8S2; and the S1 clock signal and the S2 clock signal are two-phase non-overlapping clocks. When the S1 clock signal is at a high level, the clock switch 9S1, the clock switch 10S1, the clock switch 11S1, the clock switch 12S1 and the clock switch 13S1 are turned on; when the S2 clock signal is at a high level, the clock switch 5S2, the clock switch 6S2, the clock switch 7S2 and the clock switch 8S2 are turned on.

[0113] In this embodiment, capacitors C1, C2, C3 and C4 are feedback capacitors, and their capacitance values ​​are equal, all C. Then the total charge on the feedback capacitors at the S1 and S2 clock phases are respectively:

[0114]

[0115]

[0116] According to the law of charge conservation, we can get

[0117]

[0118] From the formula, we can see that the feedback voltage V CMFB By outputting the common-mode voltage V OCM With the common mode voltage V CM The difference between the sixth bias voltage V B6 When V OCM When the disturbance increases, V CMFB Rise synchronously, pull down the voltage V B7 , the current I flowing through MOS tube P4 and MOS tube P5 DP4 ,I DP5 The gate voltage V of MOS tube P36 rises. OPG1 And the gate voltage V of MOS tube P42 OPG2 increases, thereby lowering V OCM Complete negative feedback and finally stabilize the output common mode voltage V OCM In this switched capacitor common-mode feedback structure, the common-mode voltage V CM The power supply voltage is directly sampled by capacitors with equal capacitance, which is isolated from the input common-mode voltage and has better stability; equal capacitance helps reduce the error caused by capacitor mismatch. When used in circuits with clock switches, it can effectively reduce the power consumption of common-mode feedback circuits.

[0119] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A rail-to-rail fully differential folded cascode operational amplifier, characterized in that: It includes a bias unit, a constant-span rail-to-rail folded common-source common-gate input unit, and a Class-AB differential output unit; The same-direction input terminal and the inverting input terminal of the constant-span rail-to-rail folded common-source common-gate input unit are electrically connected to the front-end signal output unit, the output terminal of the constant-span rail-to-rail folded common-source common-gate input unit is electrically connected to the input terminal of the Class-AB differential output unit, and the same-direction output terminal and the inverting output terminal of the Class-AB differential output unit are electrically connected to the rear-end signal receiving unit; The bias unit is electrically connected to an external bias module, and the external bias module outputs a bias current I bias1 To the bias unit, the bias unit outputs a first bias voltage V B1 , the fourth bias voltage V B4 , the sixth bias voltage V B6 and the eighth bias voltage V B8 To the Class-AB differential output unit; the bias unit outputs a second bias voltage V B2 , the third bias voltage V B3 , the fifth bias voltage V B5 and the sixth bias voltage V B6 To the constant-span rail-to-rail folded cascode input unit; The device further comprises a switched capacitor common-mode feedback unit, wherein the same-direction input terminal and the inverting input terminal of the switched capacitor common-mode feedback unit are electrically connected to the same-direction output terminal and the inverting output terminal of the Class-AB differential output unit, and the output terminal of the switched capacitor common-mode feedback unit is electrically connected to the constant-span rail-to-rail folded common-source common-gate input unit, so as to provide a seventh bias voltage V for the constant-span rail-to-rail folded common-source common-gate input unit. B7 ; The switch capacitor common mode feedback unit includes MOS transistor N32, MOS transistor P32, clock switch 9S1, clock switch 10S1, clock switch 11S1, clock switch 12S1, clock switch 13S1, clock switch 5S2, clock switch 6S2, clock switch 7S2, clock switch 8S2 and capacitors C1, C2, C3 and C4; One end of the clock switch 9S1, one end of the clock switch 12S1 and the source of the MOS transistor P32 are all electrically connected to the external power supply VDD1; The other end of the clock switch 9S1 is electrically connected to one end of the capacitor C4 and one end of the clock switch 5S2, the other end of the clock switch 5S2 is electrically connected to one end of the clock switch 6S2 and the reverse output end of the Class-AB differential output unit, and the other end of the clock switch 6S2 is electrically connected to one end of the clock switch 11S1 and one end of the capacitor C1; The other end of the clock switch 12S1 is electrically connected to one end of the capacitor C3 and one end of the clock switch 7S2, the other end of the clock switch 7S2 is electrically connected to one end of the clock switch 8S2 and the same-direction output end of the Class-AB differential output unit, and the other end of the clock switch 8S2 is electrically connected to one end of the clock switch 13S1 and one end of the capacitor C2; The other end of the capacitor C4 is electrically connected to the other end of the capacitor C3, the other end of the capacitor C1, the other end of the capacitor C2, one end of the clock switch 10S1 and the gate of the MOS transistor N32, the drain of the MOS transistor N32 is electrically connected to the gate and drain of the MOS transistor P32, and outputs the seventh bias voltage V B7 To the constant cross rail-to-rail folded common source and common gate input unit; the bias unit outputs a sixth bias voltage V B6 To the other end of the clock switch 10S1; The other end of the clock switch 11S1, the other end of the clock switch 13S1 and the source of the MOS transistor N32 are all grounded; The bias unit includes MOS transistor P10, MOS transistor P11, MOS transistor P12, MOS transistor P13, MOS transistor P14, MOS transistor P15, MOS transistor N11, MOS transistor N12, MOS transistor N13, MOS transistor N14, MOS transistor N15, MOS transistor N16, MOS transistor N17, MOS transistor N18 and MOS transistor N19; The source of the MOS transistor P10, the source of the MOS transistor P11, the source of the MOS transistor P13 and the source of the MOS transistor P14 are all electrically connected to the external power supply VDD1; The gate and drain of the MOS transistor P10 are electrically connected to the gate of the MOS transistor P11 and the drain of the MOS transistor N13, and outputs a second bias voltage V B2 To the constant-span rail-to-rail folded common-source common-gate input unit; the external bias module outputs the bias current I bias1 To the drain and gate of the MOS tube N11, the gate of the MOS tube N13, the gate of the MOS tube N16 and the gate of the MOS tube N18, and output the first bias voltage V B1 To the Class-AB differential output unit; the source of the MOS tube N11 is electrically connected to the drain, gate, gate of the MOS tube N12, gate of the MOS tube N14, gate of the MOS tube N17 and gate of the MOS tube N19, and outputs a sixth bias voltage V B6 To the constant-cross-rail-to-rail folded common-source common-gate input unit; the source of the MOS tube N13 is electrically connected to the drain of the MOS tube N14; The drain of the MOS transistor P11 is electrically connected to the source of the MOS transistor P12, the gate of the MOS transistor P12 is electrically connected to the gate and drain of the MOS transistor P13 and the drain of the MOS transistor N16, and outputs a fifth bias voltage V B5 To the constant cross rail-to-rail folded common source and common gate input unit, the source of the MOS tube N16 is electrically connected to the drain of the MOS tube N17; the drain of the MOS tube P12 is electrically connected to the gate and drain of the MOS tube N15, and outputs a third bias voltage V B3 To the constant-span rail-to-rail folded cascode input unit; The gate and drain of the MOS transistor P14 are electrically connected to the source of the MOS transistor P15, and output a fourth bias voltage V B4 To the Class-AB differential output unit; the gate and drain of the MOS tube P15 are electrically connected to the drain of the MOS tube N18, and outputs the eighth bias voltage V B8 To the Class-AB differential output unit, the source of the MOS tube N18 is electrically connected to the drain of the MOS tube N19; The source of the MOS tube N12, the source of the MOS tube N1, the source of the MOS tube N15, the source of the MOS tube N17 and the source of the MOS tube N19 are all grounded; The constant-span rail-to-rail folded common-source common-gate input unit includes MOS transistor P16, MOS transistor P17, MOS transistor P18, MOS transistor P19, MOS transistor P20, MOS transistor P21, MOS transistor P22, MOS transistor P23, MOS transistor P24, MOS transistor P25, MOS transistor P26, MOS transistor P27, MOS transistor P28, MOS transistor P29, MOS transistor P30, MOS transistor P31, MOS transistor P39, MOS transistor P40, MOS transistor N20, MOS transistor N21, MOS transistor N22, MOS transistor N23, MOS transistor N24, MOS transistor N25, MOS transistor N26, MOS transistor N27, MOS transistor N28, MOS transistor N29, MOS transistor N30 and MOS transistor N31; The source of the MOS transistor P16, the source of the MOS transistor P17, the source of the MOS transistor P18, the source of the MOS transistor P22, the source of the MOS transistor P23, the source of the MOS transistor P24, the source of the MOS transistor P25, the source of the MOS transistor P26, the source of the MOS transistor P27, the source of the MOS transistor P28, the source of the MOS transistor P29, the source of the MOS transistor P39 and the source of the MOS transistor P40 are all electrically connected to the external power supply VDD1; The gate of the MOS transistor P16 is electrically connected to the gate and drain of the MOS transistor P17, the drain of the MOS transistor N20, and the gate of the MOS transistor P40; the drain of the MOS transistor P16 is electrically connected to the gate and drain of the MOS transistor P24, the gate of the MOS transistor P39, and the drain of the MOS transistor N24; The bias unit outputs a second bias voltage V B2 to the gate of the MOS tube P18; the drain of the MOS tube P18 is electrically connected to the source of the MOS tube P19, and the bias unit outputs a fifth bias voltage V B5 to the gate of the MOS tube P19; the drain of the MOS tube P19 is electrically connected to the source of the MOS tube P20 and the source of the MOS tube P21; the gate of the MOS tube P20 is electrically connected to the gate of the MOS tube N25, and is electrically connected to the front signal output unit as a reverse input terminal; the gate of the MOS tube P21 is electrically connected to the gate of the MOS tube N24, and is electrically connected to the front signal output unit as a non-inverting input terminal; the drain of the MOS tube P20 is electrically connected to the gate of the MOS tube N20 and the gate and drain of the MOS tube N21; the drain of the MOS tube P21 is electrically connected to the gate of the MOS tube N23 and the gate and drain of the MOS tube N22; The gate and drain of the MOS transistor P22 are electrically connected to the drain of the MOS transistor N23, the gate of the MOS transistor P23 and the gate of the MOS transistor P27; the drain of the MOS transistor P23 is electrically connected to the drain of the MOS transistor N25, the drain and gate of the MOS transistor P25 and the gate of the MOS transistor P26; the source of the MOS transistor N25 is electrically connected to the source of the MOS transistor N24 and the drain of the MOS transistor N26; the bias unit outputs a third bias voltage V B3 to the gate of the MOS tube N26, the source of the MOS tube N26 is electrically connected to the drain of the MOS tube N27; the bias unit outputs a sixth bias voltage V B6 To the gate of MOS tube N27; The drain of the MOS transistor P26 is electrically connected to the drain of the MOS transistor P27, the source of the MOS transistor N30 and the drain of the MOS transistor N31; the drain of the MOS transistor P39 is electrically connected to the drain of the MOS transistor P40, the source of the MOS transistor N28 and the drain of the MOS transistor N29; the bias unit outputs a third bias voltage V B3 To the gate of MOS tube N28 and the gate of MOS tube N30; the bias unit outputs a sixth bias voltage V B6 To the gate of MOS tube N29 and the gate of MOS tube N31; The drain of the MOS transistor N28 is electrically connected to the first input terminal of the Class-AB differential output unit as the first output terminal; the drain of the MOS transistor N30 is electrically connected to the second input terminal of the Class-AB differential output unit as the second output terminal; The gate of the MOS transistor P28 is electrically connected to the gate of the MOS transistor P29; the drain of the MOS transistor P28 is electrically connected to the source of the MOS transistor P30, and the drain of the MOS transistor P29 is electrically connected to the source of the MOS transistor P31; the bias unit outputs a fifth bias voltage V B5 to the gate of the MOS tube P30 and the gate of the MOS tube P31; the drain of the MOS tube P30 is electrically connected to the third input terminal of the Class-AB differential output unit as the third output terminal; the drain of the MOS tube P31 is electrically connected to the fourth input terminal of the Class-AB differential output unit as the fourth output terminal; The source of the MOS tube N20, the source of the MOS tube N21, the source of the MOS tube N22, the source of the MOS tube N23, the source of the MOS tube N27, the source of the MOS tube N29 and the source of the MOS tube N31 are all grounded; The Class-AB differential output unit includes MOS transistor P16, MOS transistor P32, MOS transistor P33, MOS transistor P34, MOS transistor P35, MOS transistor P36, MOS transistor P37, MOS transistor P38, MOS transistor P41, MOS transistor P42, MOS transistor N32, MOS transistor N33, MOS transistor N34, MOS transistor N37, MOS transistor N38, MOS transistor N39, MOS transistor N40, MOS transistor N41, MOS transistor N42 and capacitors C5, C6, C7 and C8; The source of the MOS transistor P34, the source of the MOS transistor P35, the source of the MOS transistor P36, and the source of the MOS transistor P42 are all electrically connected to the external power supply VDD1; The drain of the MOS transistor P33 and the source of the MOS transistor N33 are electrically connected to the first output end of the constant-span rail-to-rail folded common-source common-gate input unit as the first input end; the drain of the MOS transistor P41 and the source of the MOS transistor N34 are electrically connected to the second output end of the constant-span rail-to-rail folded common-source common-gate input unit as the second input end; the source of the MOS transistor P33 and the drain of the MOS transistor N33 are electrically connected to the third output end of the constant-span rail-to-rail folded common-source common-gate input unit as the third input end. The source of the MOS tube P41 and the drain of the MOS tube N34 are electrically connected to the fourth output terminal of the constant cross rail-to-rail folded common source and common gate input unit as the fourth input terminal; the gate of the MOS tube P33 is electrically connected to the gate of the MOS tube P41, the gate and drain of the MOS tube P37, and the drain of the MOS tube N38; the gate of the MOS tube N33 is electrically connected to the gate of the MOS tube N34, the gate and drain of the MOS tube 40, and the drain of the MOS tube P38; The bias unit outputs a first bias voltage V B1 to the gate of the MOS tube N38; the source of the MOS tube N38 is electrically connected to the drain of the MOS tube N39, and the bias unit outputs a sixth bias voltage V B6 to the gate of the MOS tube N39; the source of the MOS tube N40 is electrically connected to the drain and gate of the MOS tube N41; The gate and drain of the MOS transistor P34 are electrically connected to the source of the MOS transistor P37; the bias unit outputs a fourth bias voltage V B4 to the gate of the MOS tube P35; the drain of the MOS tube P35 is electrically connected to the source of the MOS tube P38, and the bias unit outputs an eighth bias voltage V B8 To the gate of MOS tube P38; The gate of the MOS transistor P36 is electrically connected to one end of the capacitor C5, the source of the MOS transistor P33 and the drain of the MOS transistor N33. The other end of the capacitor C5 is electrically connected to the drain of the MOS transistor P36, one end of the capacitor C6 and the drain of the MOS transistor N37, and is electrically connected to the post-signal receiving unit as a reverse output end; the gate of the MOS transistor N37 is electrically connected to the other end of the capacitor C6, the drain of the MOS transistor P33 and the source of the MOS transistor N33; the gate of the MOS transistor P42 is electrically connected to one end of the capacitor C7, the source of the MOS transistor P41 and the drain of the MOS transistor N34, the other end of the capacitor C7 is electrically connected to the drain of the MOS transistor P42, one end of the capacitor C8 and the drain of the MOS transistor N42, and is electrically connected to the post-signal receiving unit as a unidirectional output end; the gate of the MOS transistor N42 is electrically connected to the other end of the capacitor C8, the drain of the MOS transistor P41 and the source of the MOS transistor N34; The source of the MOS transistor N37, the source of the MOS transistor N39, the source of the MOS transistor N41 and the source of the MOS transistor N42 are all grounded.

2. The rail-to-rail fully differential folded cascode operational amplifier according to claim 1, characterized in that: The capacitance values ​​of the capacitors C1 , C2 , C3 and C4 are equal.

3. The rail-to-rail fully differential folded cascode operational amplifier according to claim 1, characterized in that: The external clock module outputs the S1 clock signal to the clock switch 9S1, the clock switch 10S1, the clock switch 11S1, the clock switch 12S1 and the clock switch 13S1; The external clock module outputs the S2 clock signal to the clock switch 5S2, the clock switch 6S2, the clock switch 7S2, and the clock switch 8S2; The S1 clock signal and the S2 clock signal are two-phase non-overlapping clocks.

4. The rail-to-rail fully differential folded cascode operational amplifier according to claim 1, characterized in that: The clock switch 9S1 , the clock switch 10S1 , the clock switch 11S1 , the clock switch 12S1 , the clock switch 13S1 , the clock switch 5S2 , the clock switch 6S2 , the clock switch 7S2 , and the clock switch 8S2 are transmission gates.

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