High-speed high-side gate drive circuit capable of resisting high-voltage instantaneous noise interference

Abstract

The invention relates to a driving chip in an analog integrated circuit, in particular to a high-speed high-side gate driving circuit capable of resisting high-voltage instantaneous noise interference, which comprises a double-pulse generation circuit, a low-voltage pulse signal SET and a low-voltage pulse signal RESET, the high-voltage level shift circuit is used for converting the low-voltage narrow pulse signal SET and the low-voltage narrow pulse signal RESET into a high-voltage narrow pulse signal VDS and a high-voltage narrow pulse signal VDR; the instantaneous noise digital filter circuit is used for carrying out noise filtering on the high-voltage narrow pulse signal VDS and the high-voltage narrow pulse signal VDR; the RS trigger is used for receiving the high-voltage narrow pulse signal VDS and the high-voltage narrow pulse signal VDR which are subjected to noise filtering processing and sending a trigger signal to the output-stage driving circuit; the output-stage driving circuit is used for outputting a driving signal HO to drive the grid electrode of the high-side power tube; according to the invention, the signal transmission delay time is reduced, and the instantaneous noise resistance is improved.

Description

Technical Field

[0001] The invention relates to a driving chip in an analog integrated circuit, and in particular to a high-speed high-side gate driving circuit resistant to high-voltage transient noise interference. Background Art

[0002] Transient noise is one of the biggest challenges faced by high-voltage power driver chips. It is caused by the voltage of the floating ground suddenly changing from zero volts to the bus voltage or from the bus voltage to zero volts during the switching process of the driven high-voltage power device. Transient noise can affect the normal working process of the low-voltage to high-voltage conversion inside the high-voltage power device driver chip, causing failure states such as latch-on and latch-off on the high-voltage side. Figure 1 This is a circuit diagram of a traditional half-bridge driver chip. In order to suppress transient noise To interfere with the low voltage to high voltage process, the traditional half-bridge driver chip will Figure 1 Add the corresponding pulse filter RC circuit (i.e. Figure 1 The part indicated by 003 in the figure) is used to eliminate the influence of transient noise. The larger the noise filter width of the pulse filter RC circuit, the easier it is to filter out the noise signal, but the greater the transmission delay introduced. The minimum filter width of the pulse filter RC circuit must meet the following two conditions: First, the filter width must be smaller than the width of the effective signal during normal operation to ensure that the effective signal will not be filtered out and can trigger the subsequent RS trigger (i.e. Figure 1 The second is to make the filter width larger than the maximum width of the noise signal to ensure that the noise signal is completely filtered out. The traditional pulse filter RC circuit will introduce additional delays that affect the overall delay of the transmission channel, thereby limiting the operating frequency of the half-bridge driver chip.

[0003] In order to solve the problem of additional delay introduced by traditional pulse filtering RC circuits, many research institutions and scholars have proposed different transient noise suppression methods. Fairchild Semiconductor has proposed a method using a voltage-current-voltage (VIV) converter ( Figure 2The noise suppression technology of the part indicated by 006 in FIG. 1 is used. When the VB voltage rises, the transient noise generates a transient voltage drop across the resistors R1 and R2. The voltage drop introduced by the resistor R2 turns on M5, and introduces the noise current I1 under the action of the current mirrors M1 and M2. The voltage drop introduced by the transient noise at R1 turns on M7, generating the noise current I3. When I1=I3, I3 and I1 cancel each other out, and the potential at point C is about half of the power supply voltage, which will not turn off M9 and M10, so the output signal will not be affected by the noise current. Similarly, point D will not be affected by the noise current. Thus, the influence of the common-mode noise introduced by the transient noise is eliminated. However, this structure cannot filter out the differential-mode noise introduced by the different voltage drops across R1 and R2 due to process deviations. In order to filter out the differential-mode noise, an RC filter circuit is still required. Summary of the invention

[0004] In order to solve the problem of interference of transient noise of high-voltage power driver chip on the low-voltage to high-voltage conversion process, the present invention provides a high-speed high-side gate drive circuit that is resistant to high-voltage transient noise interference, reduces the overall delay of signal transmission, and improves the transient noise suppression capability.

[0005] Specific solutions include:

[0006] A double pulse generating circuit, used for receiving an input signal HI and generating a low voltage pulse signal SET and a low voltage pulse signal RESET;

[0007] A high-voltage level shift circuit, used for converting a low-voltage narrow pulse signal SET into a high-voltage narrow pulse signal VDS, and converting a low-voltage narrow pulse signal RESET into a high-voltage narrow pulse signal VDR;

[0008] The instantaneous noise digital filter circuit is used for performing noise filtering processing on the high-voltage narrow pulse signal VDS and the high-voltage narrow pulse signal VDR;

[0009] The RS trigger is used to receive the high-voltage narrow pulse signal VDS and the high-voltage narrow pulse signal VDR after noise filtering, and send the trigger signal to the output stage drive circuit;

[0010] The output stage driving circuit is used to output a driving signal HO to drive the gate of the high-side power tube.

[0011] Furthermore, the transient noise digital filter circuit includes an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, a buffer BUFFER1, a buffer BUFFER2, a buffer BUFFER3, a buffer BUFFER4, a NAND gate NAND1 and a NAND gate NAND2, wherein:

[0012] The input end of the inverter INV1 is connected to the high voltage level shift circuit, and the output end of the inverter INV1 is connected to the input end of the buffer BUFFER1 and the input end of the inverter INV4;

[0013] The input end of the inverter INV2 is connected to the high voltage level shift circuit, and the output end of the inverter INV2 is connected to the input end of the buffer BUFFER2 and the input end of the inverter INV3;

[0014] The output end of the buffer BUFFER1 and the output end of the inverter INV3 are connected to the input end of the NAND gate NAND1, and the output end of the buffer BUFFER2 and the output end of the inverter INV4 are connected to the input end of the NAND gate NAND2;

[0015] The output end of the NAND gate NAND1 is connected to the input end of the buffer BUFFER3, and the output end of the NAND gate NAND2 is connected to the input end of the buffer BUFFER4;

[0016] The output end of the buffer BUFFER3 and the output end of the buffer BUFFER4 are connected to an RS trigger.

[0017] Furthermore, the high-voltage level shift circuit includes an LDMOS tube LDM1, an LDMOS tube LDM2, a resistor R1, a resistor R2, a Zener diode D1 and a Zener diode D2, wherein:

[0018] The gate of the LDMOS tube LDM1 is connected to the dual pulse generating circuit, and the source of the LDMOS tube LDM1 is grounded; the drain of the LDMOS tube LDM1 is connected to one end of the resistor R1 and the anode of the Zener diode D1, and the connection point is connected to the input end of the inverter INV1 as the output end of the high-voltage reset pulse signal VDS; the other end of the resistor R1 and the cathode of the Zener diode D1 are both connected to the high-voltage side power supply voltage VB;

[0019] The gate of the LDMOS tube LDM2 is connected to the dual pulse generating circuit, the source of the LDMOS tube LDM2 is grounded, the drain of the LDMOS tube LDM2 is connected to one end of the resistor R2 and the anode of the Zener diode D2, and the connection point is connected to the input end of the inverter INV2 as the output end of the high-voltage reset pulse signal VDR; the other end of the resistor R2 and the cathode of the Zener diode D2 are both connected to the high-voltage side power supply voltage VB.

[0020] Furthermore, the gate of the LDMOS tube LDM1 is connected to the low-voltage pulse signal SET output by the dual pulse generating circuit; the gate of the LDMOS tube LDM1 is connected to the low-voltage pulse signal RESET output by the dual pulse generating circuit.

[0021] Further, the reset terminal R of the RS flip-flop is connected to the output terminal of the buffer BUFFER4, the set terminal S of the RS flip-flop is connected to the output terminal of the buffer BUFFER3, and the Q terminal of the RS flip-flop is connected to the output stage driving circuit.

[0022] Beneficial effects of the present invention:

[0023] The present invention discloses a high-speed high-side gate drive circuit capable of resisting transient noise interference. By adding a transient noise digital filter circuit to the high-side gate drive circuit, the signal transmission delay time can be effectively reduced and the transient noise resistance capability can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is the schematic diagram of the high-side driver circuit with a traditional pulse filter RC circuit;

[0025] Figure 2 The schematic diagram of the high-side driver circuit with a voltage-current-voltage converter is shown below;

[0026] Figure 3 The schematic diagram of the high-side driving circuit with transient noise digital filtering circuit of the present invention;

[0027] Figure 4 It is a transient noise suppression process when the driving output HO of the present invention is at a low level or a high level;

[0028] Figure 5 It is the turn-on delay and turn-off delay from the input signal HI to the output signal HO of the present invention. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] The present invention provides a high-speed high-side gate drive circuit that is resistant to high-voltage transient noise interference, such as Figure 3 As shown, including:

[0031] A double pulse generating circuit, used for receiving an input signal HI and generating a low voltage pulse signal SET and a low voltage pulse signal RESET;

[0032] A high-voltage level shift circuit, used for converting a low-voltage narrow pulse signal SET into a high-voltage narrow pulse signal VDS, and converting a low-voltage narrow pulse signal RESET into a high-voltage narrow pulse signal VDR;

[0033] The instantaneous noise digital filter circuit is used for performing noise filtering processing on the high-voltage narrow pulse signal VDS and the high-voltage narrow pulse signal VDR;

[0034] The RS trigger is used to receive the high-voltage narrow pulse signal VDS and the high-voltage narrow pulse signal VDR after noise filtering, and send the trigger signal to the output stage drive circuit;

[0035] The output stage driving circuit is used to output a driving signal HO to drive the gate of the high-side power tube.

[0036] Specifically, Figure 3 The portion indicated by 007 indicates that the transient noise digital filter circuit includes an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, a buffer BUFFER1, a buffer BUFFER2, a buffer BUFFER3, a buffer BUFFER4, a NAND gate NAND1 and a NAND gate NAND2, wherein:

[0037] The input end of the inverter INV1 is used as an input end of the transient noise digital filter circuit, which is connected to the high-voltage reset pulse signal VDS output by the high-voltage level shift circuit; the output end of the inverter INV1 is connected to the input end of the buffer BUFFER1 and the input end of the inverter INV4;

[0038] The input end of the inverter INV2 is used as another input end of the transient noise digital filter circuit (, which is connected to the high-voltage reset pulse signal VDR output by the high-voltage level shift circuit; the output end of the inverter INV2 is connected to the input end of the buffer BUFFER2 and the input end of the inverter INV3;

[0039] The output end of the buffer BUFFER1 and the output end of the inverter INV3 are connected to the input end of the NAND gate NAND1, and the output end of the buffer BUFFER2 and the output end of the inverter INV4 are connected to the input end of the NAND gate NAND2;

[0040] The output end of the NAND gate NAND1 is connected to the input end of the buffer BUFFER3, and the output end of the NAND gate NAND2 is connected to the input end of the buffer BUFFER4;

[0041] The output end of the buffer BUFFER3 and the output end of the buffer BUFFER4 are connected to an RS trigger.

[0042] Specifically, the high-voltage level shift circuit includes two circuits with completely identical structures, one including an LDMOS tube LDM1, a resistor R1, and a Zener diode D1, and the other including an LDMOS tube LDM2, a resistor R2, and a Zener diode D2; the gate of the LDMOS tube LDM1 is connected to a low-voltage set pulse signal SET output by a front-stage low-voltage side pulse generating circuit, the drain of the LDMOS tube LDM1 is connected to one end of the resistor R1 and an anode of the Zener diode D1 and outputs a high-voltage reset pulse signal VDS, the source of the LDMOS tube LDM1 is connected to a power ground GND, and the other end of the resistor R1 and a cathode of the Zener diode D1 are both connected to a high-voltage side power supply voltage VB; similarly, the gate of the LDMOS tube LDM2 is connected to a low-voltage reset pulse signal RESET output by a front-stage low-voltage side pulse generating circuit, the drain of the LDMOS tube LDM2 is connected to one end of the resistor R2 and an anode of the Zener diode D2 and outputs a high-voltage reset pulse signal VDR, the source of the LDMOS tube LDM2 is connected to the power ground GND, and the other end of the resistor R2 and a cathode of the Zener diode D2 are both connected to the high-voltage side power supply voltage VB.

[0043] Specifically, the reset terminal R of the RS trigger is connected to the output terminal of the buffer BUFFER4, the set terminal S of the RS trigger is connected to the output terminal of the buffer BUFFER3, and the Q terminal of the RS trigger is connected to the output stage driving circuit. The RS trigger and the output stage driving circuit are both connected to the high-voltage side power supply voltage VB and the high-voltage side floating ground VS at the same time.

[0044] Figure 3 The logic truth table of the input signals VDS and VDR and the output signals R and S of the transient noise digital filter circuit is shown in the following table:

[0045]

[0046] The high voltage transient noise is filtered out through the transient noise digital filter circuit and the low delay transmission of the signal is achieved.

[0047] In order to verify the rationality of the scheme, a high-side gate drive circuit with a transient noise digital filter circuit is designed through the standard high-voltage BCD process. The transmission delay and transient noise resistance of the high-side gate drive circuit are simulated and analyzed as follows: Figure 4 , Figure 5As shown. The simulation results show that: the transient noise interferes with the high-voltage level shift circuit and produces an obvious noise signal. After the interference signal is filtered out by the transient noise digital filter circuit, the gate drive output HO is normal. The overall delay time of the input signal HI through the high-side gate drive circuit of the present invention is as low as 21ns, which greatly reduces the signal transmission delay compared to the traditional transient noise suppression method. Therefore, adding a transient noise digital filter circuit to the high-side gate drive circuit can effectively reduce the signal transmission delay time of the high-side gate drive circuit and improve the ability to resist transient noise.

[0048] In the present invention, unless otherwise clearly stipulated and limited, the terms such as "installation", "setting", "connection", "fixation" and "rotation" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0049] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high-speed high-side gate drive circuit resistant to high-voltage transient noise interference, characterized in that: include: A double pulse generating circuit, used for receiving an input signal HI and generating a low voltage pulse signal SET and a low voltage pulse signal RESET; A high-voltage level shift circuit, used for converting a low-voltage narrow pulse signal SET into a high-voltage narrow pulse signal VDS, and converting a low-voltage narrow pulse signal RESET into a high-voltage narrow pulse signal VDR; The instantaneous noise digital filter circuit is used for performing noise filtering processing on the high-voltage narrow pulse signal VDS and the high-voltage narrow pulse signal VDR; The RS trigger is used to receive the high-voltage narrow pulse signal VDS and the high-voltage narrow pulse signal VDR after noise filtering, and send the trigger signal to the output stage drive circuit; The output stage driving circuit is used to output a driving signal HO to drive the gate of the high-side power tube.

2. The high-speed high-side gate drive circuit resistant to high-voltage transient noise interference according to claim 1, characterized in that: The instantaneous noise digital filter circuit includes an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, a buffer BUFFER1, a buffer BUFFER2, a buffer BUFFER3, a buffer BUFFER4, a NAND gate NAND1 and a NAND gate NAND2, wherein: The input end of the inverter INV1 is connected to the high voltage level shift circuit, and the output end of the inverter INV1 is connected to the input end of the buffer BUFFER1 and the input end of the inverter INV4; The input end of the inverter INV2 is connected to the high voltage level shift circuit, and the output end of the inverter INV2 is connected to the input end of the buffer BUFFER2 and the input end of the inverter INV3; The output end of the buffer BUFFER1 and the output end of the inverter INV3 are connected to the input end of the NAND gate NAND1, and the output end of the buffer BUFFER2 and the output end of the inverter INV4 are connected to the input end of the NAND gate NAND2; The output end of the NAND gate NAND1 is connected to the input end of the buffer BUFFER3, and the output end of the NAND gate NAND2 is connected to the input end of the buffer BUFFER4; The output end of the buffer BUFFER3 and the output end of the buffer BUFFER4 are connected to an RS trigger.

3. The high-speed high-side gate drive circuit resistant to high-voltage transient noise interference according to claim 2, characterized in that: The high-voltage level shift circuit includes an LDMOS tube LDM1, an LDMOS tube LDM2, a resistor R1, a resistor R2, a Zener diode D1 and a Zener diode D2, wherein: The gate of the LDMOS tube LDM1 is connected to the dual pulse generating circuit, and the source of the LDMOS tube LDM1 is grounded; the drain of the LDMOS tube LDM1 is connected to one end of the resistor R1 and the anode of the Zener diode D1, and the connection point is connected to the input end of the inverter INV1 as the output end of the high-voltage reset pulse signal VDS; the other end of the resistor R1 and the cathode of the Zener diode D1 are both connected to the high-voltage side power supply voltage VB; The gate of the LDMOS tube LDM2 is connected to the dual pulse generating circuit, the source of the LDMOS tube LDM2 is grounded, the drain of the LDMOS tube LDM2 is connected to one end of the resistor R2 and the anode of the Zener diode D2, and the connection point is connected to the input end of the inverter INV2 as the output end of the high-voltage reset pulse signal VDR; the other end of the resistor R2 and the cathode of the Zener diode D2 are both connected to the high-voltage side power supply voltage VB.

4. The high-speed high-side gate drive circuit resistant to high-voltage transient noise interference according to claim 3, characterized in that: The gate of the LDMOS tube LDM1 is connected to the low-voltage pulse signal SET output by the double pulse generating circuit; the gate of the LDMOS tube LDM1 is connected to the low-voltage pulse signal RESET output by the double pulse generating circuit.

5. The high-speed high-side gate drive circuit resistant to high-voltage transient noise interference according to claim 2, characterized in that: The reset terminal R of the RS flip-flop is connected to the output terminal of the buffer BUFFER4, the set terminal S of the RS flip-flop is connected to the output terminal of the buffer BUFFER3, and the Q terminal of the RS flip-flop is connected to the output stage driving circuit.

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