Display device and driving method thereof

Abstract

The invention provides a display device and a driving method thereof. The display device comprises a display panel, the display panel comprises N partitions divided in the scanning direction, each partition comprises M rows of pixel units, each pixel unit comprises a pixel circuit and a light-emitting device, and N and M are positive integers; the driving circuit is electrically connected with the pixel units, and the driving circuit is used for generating oblique wave signals, inputting the oblique wave signals to the pixel units and sequentially controlling the pixel units of each of the N partitions to carry out data writing and light emitting in the driving period of one frame of picture; wherein the ramp signal comprises a plurality of pulse periods in the driving period of one frame of picture, the driving period of the pixel unit of each partition comprises a data writing stage and a light emitting stage, the data writing stage is prior to the light emitting stage, and the light emitting stage comprises the plurality of pulse periods of the ramp signal. According to the display device and the driving method thereof provided by the invention, the flicker problem of the display panel when the display panel displays a low-gray-scale picture can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device and a driving method thereof. Background Art

[0002] The light-emitting time of the pixel unit of a traditional MLED display panel is concentrated in the second half of the driving cycle of a frame, and the ramp signal Sweep has only one pulse cycle in the driving cycle of a frame. Therefore, when displaying low-grayscale images, the light-emitting time of a traditional MLED display panel may be less than 10%, which will cause obvious flickering in the displayed image. This flickering phenomenon not only affects the viewing experience, but may also cause visual fatigue to users.

[0003] Therefore, how to effectively improve the flicker problem when displaying low grayscale images while maintaining the advantages of MLED display panels has become a technical problem that needs to be urgently solved in the current field of MLED display technology. Summary of the invention

[0004] The embodiments of the present application provide a display device and a driving method thereof, which are intended to improve the flickering problem of a display panel when displaying low grayscale images.

[0005] An embodiment of the present application provides a display device, comprising: a display panel, the display panel comprising N partitions divided along a scanning direction, each partition comprising M rows of pixel units, each pixel unit comprising a pixel circuit and a light-emitting device, and N and M are both positive integers; and a driving circuit, electrically connected to the pixel unit, the driving circuit being used to generate a ramp signal, input the ramp signal to the pixel unit, and sequentially control the pixel units of each of the N partitions to write data and emit light within a driving cycle of a frame; wherein the ramp signal comprises a plurality of pulse periods within a driving cycle of a frame, the driving cycle of the pixel units of each partition comprises a data writing phase and a light-emitting phase, the data writing phase precedes the light-emitting phase, and the light-emitting phase comprises a plurality of pulse periods of the ramp signal.

[0006] An embodiment of the present application also provides a driving method for a display device, wherein a display panel of the display device includes N partitions divided along a scanning direction, each partition includes M rows of pixel units, each pixel unit includes a pixel circuit and a light-emitting device, and N and M are both positive integers. The driving method includes: generating a ramp signal, wherein the ramp signal includes multiple pulse periods within a driving cycle of a frame; inputting the ramp signal to multiple pixel units; and within the driving cycle of a frame, sequentially controlling the pixel units of each of the N partitions to write data and emit light; wherein the driving cycle of the pixel units of each partition includes a data writing stage and a light-emitting stage, wherein the data writing stage precedes the light-emitting stage, and the light-emitting stage includes multiple pulse periods of the ramp signal.

[0007] The embodiment of the present application divides the display panel into N partitions along the scanning direction, and sequentially controls the pixel units of each partition in the N partitions to write data and emit light within the driving cycle of a frame, and at the same time uses a ramp signal containing multiple pulse cycles within the driving cycle of a frame to control the luminescence time of the pixel unit, thereby achieving the dispersion of the luminescence time. Compared with the traditional global synchronous luminescence, the scheme of the embodiment of the present application includes multiple sub-luminescence stages within the driving cycle of a frame, and each sub-luminescence stage corresponds to a pulse cycle of the ramp signal, so that each pixel unit emits light multiple times within the driving cycle of a frame. This partition multi-pulse driving method allows the pixel units in each partition to emit light multiple times within a frame cycle, rather than just once. This decentralized luminescence method can make the luminescence of the entire display panel more uniform in time. Therefore, even in a low grayscale picture, the luminescence time can be evenly distributed throughout the driving cycle, thereby effectively improving the flicker problem.

[0008] In addition, the embodiment of the present application effectively eliminates the problem of uneven picture caused by inconsistent transistor characteristics by compensating the threshold voltages of the second transistor and the seventh transistor, thereby further improving the display quality.

[0009] In addition, the embodiment of the present application introduces a technical solution of Vdd compensation so that the current Ids of the seventh transistor is independent of Vdd, thereby effectively reducing the impact of power supply voltage fluctuations on the display effect and improving the stability of the display. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a display device provided in an embodiment of the present application.

[0011] Figure 2 This is a first schematic diagram of the technical solution of the display device and the driving method thereof provided in the embodiments of the present application.

[0012] Figure 3 This is a second schematic diagram of the technical solution of the display device and the driving method thereof provided in the embodiments of the present application.

[0013] Figure 4 It is a circuit diagram of a first embodiment of a pixel unit in a multi-partitioned display device provided by an embodiment of the present application.

[0014] Figure 5 yes Figure 4 The waveform diagram of the signal of the pixel unit shown.

[0015] Figure 6 It is a circuit diagram of a second embodiment of a pixel unit in a multi-partitioned display device provided by an embodiment of the present application.

[0016] Figure 7 It is a circuit diagram of a third embodiment of a pixel unit in a multi-partitioned display device provided by an embodiment of the present application.

[0017] Figure 8 yes Figure 7 The waveform diagram of the signal of the pixel unit shown.

[0018] Fig. 9 4 is a waveform diagram of a signal of a pixel unit in a single-partition display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] The specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0020] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0021] The embodiments of the present application may be combined with each other.

[0022] refer to Figure 1 The display device provided in the embodiments of the present application may be, for example, a Micro-LED display device. Of course, the display device may also be a Mini-LED display device or an OLED display device. The embodiments of the present application are described using a Micro-LED display device.

[0023] The display device includes a source driving circuit, a gate driving circuit, a timing controller, a light emitting controller, a power management chip, a substrate, a data line DATA, a scan line SCAN, a power line (VDD, VSS), a light emitting control signal line EM, a pixel array, an encapsulation layer, a polarizer, a color filter, etc.

[0024] The substrate may be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), etc. The pixel array is composed of a plurality of pixel units PX arranged in rows and columns, and each pixel unit PX includes a light-emitting device and a driving circuit. The driving circuit includes a TFT device, which is used to control the brightness of each light-emitting device of the display device. The TFT device includes low-temperature polycrystalline silicon (LTPS) and a metal oxide TFT. The TFT device may adopt a dual-gate structure, and the light-emitting device is electrically connected to the TFT device. The light-emitting device includes a light-emitting layer, an electron transport layer, a hole transport layer, a cathode and an anode, etc. Each level of the gate driving unit in the gate driving circuit controls a row of pixel units PX, and the gate driving unit is used to control the TFT device to realize the gating of the pixel unit PX. Each level of the gate driving unit is mainly composed of a thin film transistor (TFT) and a capacitor. The source driving circuit is used to provide a data signal to the pixel unit PX. The timing controller is used to receive externally input image data and synchronization signals, and generate signals required by the gate driving circuit and the source driving circuit. The power management chip is used to provide the required operating voltage for each part of the display device.

[0025] In addition, the display device of the present application may also integrate an embedded touch control circuit, which is electrically connected to the display driving circuit, and implements the touch control function and the display function in a time division multiplexing manner.

[0026] The embodiment of the present application provides a display device including a display panel and a driving circuit, wherein the driving circuit includes at least one of the above-mentioned source driving circuit, gate driving circuit, timing controller, light emitting controller, and power management chip. Figure 1 shown.

[0027] refer to Figure 2 and Figure 3 The display panel includes N partitions divided along a scanning direction SD, each partition includes M rows of pixel units, each pixel unit includes a pixel circuit and a light-emitting device LED, and N and M are both positive integers.

[0028] The driving circuit is electrically connected to the pixel unit, and is used to generate a ramp signal Sweep, input the ramp signal Sweep to the pixel unit, and sequentially control the pixel unit of each partition in the N partitions to write data and emit light within a driving cycle of a frame.

[0029] The ramp signal Sweep includes multiple pulse cycles in a driving cycle of a frame, and the driving cycle of each partitioned pixel unit includes a data writing phase and a light emitting phase. The data writing phase precedes the light emitting phase in time, and the light emitting phase includes multiple pulse cycles of the ramp signal Sweep, such as Figure 5 , Figure 8 and Fig. 9 shown.

[0030] The ramp signal Sweep output terminal of the driving circuit is electrically connected to a plurality of pixel units of the display panel. The driving circuit is used to generate a ramp signal Sweep and provide the ramp signal Sweep to the plurality of pixel units through the ramp signal Sweep output terminal.

[0031] refer to Figure 4 , the pixel circuit of the pixel unit in the Jth partition includes a pulse width modulation module PWM and a pulse amplitude modulation module PAM, the pulse width modulation module PWM is electrically connected to the pulse amplitude modulation module PAM, the pulse amplitude modulation module PAM is electrically connected to the light emitting device LED, and the ramp signal Sweep input end of the pulse width modulation module PWM is electrically connected to the ramp signal Sweep output end of the driving circuit. Wherein, J is a positive integer.

[0032] The pulse width modulation module PWM is used to control the light-emitting time of the light-emitting device LED, and the pulse amplitude modulation module PAM is used to control the light-emitting current of the light-emitting device LED.

[0033] The pulse width modulation module PWM includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 and a first capacitor C1 .

[0034] The pixel circuit further includes a first light emitting control signal EM1 input terminal, a first power signal Vdd input terminal, a scan signal S(J) input terminal, a first data signal Data-PWM input terminal and a ramp signal Sweep input terminal.

[0035] The gate of the first transistor T1 is electrically connected to an input terminal of a first light emitting control signal EM1.

[0036] The gate of the second transistor T2 is electrically connected to the second node B, and one of the source and the drain of the second transistor T2 is electrically connected to one of the source and the drain of the first transistor T1.

[0037] The gate of the third transistor T3 is electrically connected to the input terminal of the first light emitting control signal EM1, one of the source and the drain of the third transistor T3 is electrically connected to the other of the source and the drain of the second transistor T2, and the other of the source and the drain of the third transistor T3 is electrically connected to the input terminal of the first power supply signal Vdd.

[0038] The gate of the fourth transistor T4 is electrically connected to the scan signal S(J) input terminal, one of the source and the drain of the fourth transistor T4 is electrically connected to the second node B, and the other of the source and the drain of the fourth transistor T4 is electrically connected to one of the source and the drain of the second transistor T2.

[0039] The gate of the fifth transistor T5 is electrically connected to the scan signal S(J) input terminal, one of the source and the drain of the fifth transistor T5 is electrically connected to the first data signal Data-PWM input terminal, and the other of the source and the drain of the fifth transistor T5 is electrically connected to the other of the source and the drain of the second transistor T2.

[0040] One end of the first capacitor C1 is electrically connected to the second node B, and the other end of the first capacitor C1 is electrically connected to the ramp signal Sweep input terminal.

[0041] The pulse amplitude modulation module PAM comprises a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a second capacitor C2.

[0042] The pixel circuit further includes a second light emitting control signal EM2 input terminal, a constant current source signal CCG input terminal or a second data signal Data-PAM input terminal and a second power signal Vss input terminal.

[0043] The gate of the sixth transistor T6 is electrically connected to the input terminal of the first light emitting control signal EM1 , and one of the source and the drain of the sixth transistor T6 is electrically connected to the input terminal of the first power signal Vdd.

[0044] A gate of the seventh transistor T7 is electrically connected to the first node A, and one of a source and a drain of the seventh transistor T7 is electrically connected to the other of a source and a drain of the sixth transistor T6.

[0045] The gate of the eighth transistor T8 is electrically connected to the second light-emitting control signal EM2 input terminal or the scan signal S(J) input terminal, one of the source and the drain of the eighth transistor T8 is electrically connected to the constant current source signal CCG input terminal or the second data signal Data-PAM input terminal, and the other of the source and the drain of the eighth transistor T8 is electrically connected to one of the source and the drain of the seventh transistor T7.

[0046] The gate of the ninth transistor T9 is electrically connected to the second light emitting control signal EM2 input terminal or the scanning signal S(J) input terminal, one of the source and the drain of the ninth transistor T9 is electrically connected to the first node A, and the other of the source and the drain of the ninth transistor T9 is electrically connected to the other of the source and the drain of the seventh transistor T7.

[0047] The gate of the tenth transistor T10 is electrically connected to the input terminal of the first light emitting control signal EM1 or the fourth node D, one of the source and the drain of the tenth transistor T10 is electrically connected to the other of the source and the drain of the seventh transistor T7, and the other of the source and the drain of the tenth transistor T10 is electrically connected to the anode of the light emitting device LED.

[0048] The gate of the eleventh transistor T11 is electrically connected to the second light control signal EM2 input terminal, one of the source and the drain of the eleventh transistor T11 is electrically connected to the anode of the light emitting device LED, and the other of the source and the drain of the eleventh transistor T11 is electrically connected to the second power supply signal Vss input terminal.

[0049] One end of the second capacitor C2 is electrically connected to the first node A, and the other end is electrically connected to the first power signal Vdd input terminal.

[0050] refer to Figure 4 and Figure 5 The driving circuit is used to write the first data signal Data-PWM to the second node B of the pulse width modulation module PWM and write the constant current source signal CCG to the first node A of the pulse amplitude modulation module PAM during the data writing phase. The threshold voltage Vth1 of the second transistor T2 is compensated to V(data-pwm)+Vth1, and the threshold voltage Vth2 of the seventh transistor T7 is compensated to Vccg+Vth2.

[0051] In the light-emitting stage, the first light-emitting control signal EM1 input terminal receives the low-level first light-emitting control signal EM1, the sixth transistor T6 and the tenth transistor T10 are turned on, and the light-emitting device LED emits light. The voltage of the second node B decreases as the voltage of the Sweep signal decreases. When the voltage of the second node B V(data-pwm)+Vth1-V∆sweep(t)-Vdd<the threshold voltage Vth1 of the second transistor T2, the second transistor T2 is turned on, the first power supply signal Vdd is written to the first node A, the seventh transistor T7 is turned off, and the light-emitting device LED stops emitting light.

[0052] In the light emitting stage, the voltage of the first node A is Vccg+Vth2, and the voltage of the second node B is V(data-pwm)+Vth1.

[0053] In the light emitting stage, the current Ids of the seventh transistor T7=K*(Vccg-Vref)^2, wherein K is a constant.

[0054] The driving circuit is used to generate a first light-emitting control signal EM1 and a second light-emitting control signal EM2. The first light-emitting control signal EM1 is at a high level in the data writing stage and at a low level in the light-emitting stage, and the second light-emitting control signal EM2 is at a low level in the data writing stage and at a high level in the light-emitting stage; or the first light-emitting control signal EM1 is at a low level in the data writing stage and at a high level in the light-emitting stage, and the second light-emitting control signal EM2 is at a high level in the data writing stage and at a low level in the light-emitting stage.

[0055] The driving circuit is used to sequentially provide M scanning signals S(J) to the M rows of pixel units in the Jth partition. The scanning signal S(J) is at a low level during the data writing phase of the pixel units in the partition and at a high level during the light emitting phase; or the scanning signal S(J) is at a high level during the data writing phase of the pixel units in the partition and at a low level during the light emitting phase.

[0056] An embodiment of the present application further provides a method for driving a display device, the method comprising: Generate a ramp signal Sweep, wherein the ramp signal Sweep includes a plurality of pulse periods within a driving period of one frame; Inputting a ramp signal Sweep to the plurality of pixel units; and In a driving cycle of a frame, pixel units in each of the N partitions are sequentially controlled to write data and emit light; The driving cycle of the pixel unit of each partition includes a data writing phase and a light emitting phase. The data writing phase precedes the light emitting phase. The light emitting phase includes a plurality of pulse cycles of the ramp signal Sweep.

[0057] The driving method also includes: In the data writing phase, a first data signal Data-PWM is written into a second node B of a pulse width modulation module PWM of a pixel circuit, and a constant current source signal CCG is written into a first node A of a pulse amplitude modulation module PAM of a pixel circuit; The threshold voltage Vth1 of the second transistor T2 is compensated to V(data-pwm)+Vth1, and the threshold voltage Vth2 of the seventh transistor T7 is compensated to Vccg+Vth2.

[0058] The driving method also includes: During the lighting phase: The first light emitting control signal EM1 input terminal receives the first light emitting control signal EM1 of low level, the sixth transistor T6 and the tenth transistor T10 are turned on, and the light emitting device LED emits light; The voltage of the second node B decreases as the voltage of the Sweep signal decreases. When the voltage of the second node B V(data-pwm)+Vth1-V∆sweep(t)-Vdd<the threshold voltage Vth1 of the second transistor T2, the second transistor T2 is turned on, the first power signal Vdd is written to the first node A, the seventh transistor T7 is turned off, and the light-emitting device LED stops emitting light.

[0059] The driving method also includes: A first light-emitting control signal EM1 and a second light-emitting control signal EM2 are generated. The first light-emitting control signal EM1 is at a high level in the data writing stage and at a low level in the light-emitting stage, and the second light-emitting control signal EM2 is at a low level in the data writing stage and at a high level in the light-emitting stage; or the first light-emitting control signal EM1 is at a low level in the data writing stage and at a high level in the light-emitting stage, and the second light-emitting control signal EM2 is at a high level in the data writing stage and at a low level in the light-emitting stage.

[0060] The driving method also includes: In the data writing phase, M scanning signals S(J) are sequentially provided to the M rows of pixel units in the Jth partition. The scanning signal S(J) is at a low level in the data writing phase of the pixel units in the partition and at a high level in the light emitting phase; or the scanning signal S(J) is at a high level in the data writing phase of the pixel units in the partition and at a low level in the light emitting phase. Wherein, J is a positive integer.

[0061] In the light emitting stage, the voltage of the first node A is Vccg+Vth2, and the voltage of the second node B is V(data-pwm)+Vth1.

[0062] Example 1 The micro-LED display panel of the embodiment of the present application includes a plurality of pixel units, and the plurality of pixel units are distributed in N partitions divided by the micro-LED display panel along a scanning direction SD, and each partition includes M rows of pixel units.

[0063] Each pixel unit includes a pixel circuit and a light emitting device LED. In this embodiment, the pixel circuit adopts a structure of 11 transistors (T1-T11) and 2 capacitors (C1, C2). The pixel circuit cooperates with the constant current source signal CCG and Figure 5 The timing shown realizes multi-partition multi-pulse operation.

[0064] For each pixel unit, the driving cycle of a frame includes a data writing stage and a light-emitting stage. The data writing stage is located before the light-emitting stage. In the data writing stage, the scanning signals S(J) transmitted by the M scanning lines in the Jth partition are low-level signals, the first light-emitting control signal EM1 is a high-level signal, the second light-emitting control signal EM2 is a low-level signal, and the ramp signal Sweep is a high-level signal. The light-emitting stage includes multiple sub-light-emitting stages. In the first sub-light-emitting stage, the ramp signal Sweep is a signal with a linearly decreasing voltage; in the second and subsequent sub-light-emitting stages, the ramp signal Sweep is first a high-level signal and then becomes a signal with a linearly decreasing voltage. Wherein, J is a positive integer.

[0065] In the pixel circuit of the embodiment of the present application, all transistors are P-type transistors. Of course, these transistors may also be N-type transistors.

[0066] refer to Figure 4 , the pixel circuit of this embodiment includes: A first transistor T1, a gate of which is electrically connected to the first light emitting control signal EM1 input terminal, and a source of which is electrically connected to the first power supply signal Vdd input terminal; a second transistor T2, having a gate electrically connected to the second node B and a source electrically connected to the drain of the first transistor T1; a third transistor T3, whose gate is electrically connected to the input terminal of the first light emitting control signal EM1, whose source is electrically connected to the drain of the second transistor T2, and whose drain is electrically connected to the input terminal of the first power supply signal Vdd; a fourth transistor T4, having a gate electrically connected to the scan signal S(J) input terminal, a source electrically connected to the second node B, and a drain electrically connected to the source of the second transistor T2; a fifth transistor T5, having a gate electrically connected to the scan signal S(J) input terminal, a source electrically connected to the first data signal Data-PWM input terminal, and a drain electrically connected to the drain of the second transistor T2; a sixth transistor T6, whose gate is electrically connected to the first light emitting control signal EM1 input terminal, and whose source is electrically connected to the first power supply signal Vdd input terminal; a seventh transistor T7, a gate of which is electrically connected to the first node A, and a source of which is electrically connected to the drain of the sixth transistor T6; an eighth transistor T8, whose gate is electrically connected to the input terminal of the second light emitting control signal EM2, whose source is electrically connected to the input terminal of the constant current source signal CCG, and whose drain is electrically connected to the source of the seventh transistor T7; a ninth transistor T9, having a gate electrically connected to the input terminal of the second light emitting control signal EM2, a source electrically connected to the first node A, and a drain electrically connected to the drain of the seventh transistor T7; a tenth transistor T10, whose gate is electrically connected to the input terminal of the first light emitting control signal EM1, whose source is electrically connected to the drain of the seventh transistor T7, and whose drain is electrically connected to the anode of the light emitting device LED; an eleventh transistor T11, a gate of which is electrically connected to the input terminal of the second light emitting control signal EM2, a source of which is electrically connected to the anode of the light emitting device LED, and a drain of which is electrically connected to the input terminal of the second power supply signal Vss; A first capacitor C1, one end of which is electrically connected to the first node A, and the other end of which is electrically connected to the first power signal Vdd input terminal; The second capacitor C2 has one end electrically connected to the second node B, and the other end electrically connected to the ramp signal Sweep input terminal.

[0067] Referring to Table 1 and Figure 4 、 Figure 5 , the specific working process of the display device in this embodiment is as follows: Data writing stage: Data signals are written and compensated to each row of pixel units in sequence. In this stage, the first data signal Data-PWM is written to the second node B of the pixel circuit, and the threshold voltage Vth1 of the second transistor T2 in the diode mode is compensated to V(data-pwm)+Vth1. The voltage of the constant current source signal CCG is written to the first node A, and the threshold voltage Vth2 of the seventh transistor T7 in the diode mode is compensated to Vccg+Vth2. After writing the data, the voltages of the second node B and the first node A are stored through the first capacitor C1 and the second capacitor C2 respectively. Each row of pixel units is sequentially controlled by the scan signal S(J) for data writing and compensation.

[0068] Light emitting stage: The first light emitting control signal EM1 is at a low level, enabling the sixth transistor T6 and the tenth transistor T10 to turn on. The voltage of the first node A is Vccg+Vth2-Vdd<Vth2, the seventh transistor T7 turns on, and the light emitting device LED starts to emit light. The light emitting current of the seventh transistor T7 is K*(Vccg+Vth2-Vdd-Vth2)^2 = K*(Vccg-Vdd)^2. The voltage of the second node B decreases as the voltage of the ramp signal Sweep decreases. When the voltage of the second node B Vdata+Vth1-V∆sweep(t)-Vdd<Vth1, the second transistor T2 turns on, the first power supply signal Vdd is written to the first node A, and the seventh transistor T7 turns off, and the light emitting device LED stops emitting light.

[0069] In the light emitting stage, the voltage of the first node A is Vccg+Vth2 or V(data-pam)+Vth2, and the voltage of the second node B is coupled by the ramp signal Sweep to Vdata+Vth1, and the comparison and light emission are repeated. This comparison process is performed multiple times to achieve multi-pulse light emission. That is, the light emitting stage of the light emitting device LED in the driving period of one frame of the picture includes multiple sub-light emitting stages, and each sub-light emitting stage corresponds to one pulse period of the ramp signal Sweep.

[0070] Table 1

[0071] Reference Figure 5 and Figure 6 , in the display device provided by the embodiment of the present application, the pulse amplitude modulation module PAM further includes a twelfth transistor T12 and a thirteenth transistor T13.

[0072] The pixel circuit also includes a reference voltage signal Vref input terminal.

[0073] The gate of the twelfth transistor T12 is electrically connected to the second light emitting control signal EM2 or the scanning signal S(J) input terminal, one of the source and the drain of the twelfth transistor T12 is electrically connected to the reference voltage signal Vref input terminal, and the other of the source and the drain of the twelfth transistor T12 is electrically connected to the third node C.

[0074] The gate of the thirteenth transistor T13 is electrically connected to the first light emitting control signal EM1 input terminal, one of the source and the drain of the thirteenth transistor T13 is electrically connected to the first power signal Vdd input terminal, and the other of the source and the drain of the thirteenth transistor T13 is electrically connected to the third node C.

[0075] In the data writing phase, the driving circuit is also used to write a reference voltage signal Vref to the third node C.

[0076] In the light-emitting stage, the first light-emitting control signal EM1 input terminal receives the low-level first light-emitting control signal EM1, the thirteenth transistor T13 is turned on, the voltage of the third node C changes from Vref to Vdd and is coupled to the first node A, the seventh transistor T7 is turned off, and the light-emitting device LED stops emitting light.

[0077] The driving method also includes: In the data writing phase, the reference voltage signal Vref is written to the third node C.

[0078] During the lighting phase: The first light emitting control signal EM1 input terminal receives the low level first light emitting control signal EM1, the thirteenth transistor T13 is turned on, so that the voltage of the third node C changes from Vref to Vdd and is coupled to the first node A, the seventh transistor T7 is turned off, and the light emitting device LED stops emitting light.

[0079] Example 2 Embodiment 2 is similar to embodiment 1, except that embodiment 2 adds a Vdd compensation function on the basis of embodiment 1. Specifically, the pixel circuit of this embodiment adopts a structure of 13 transistors and 2 capacitors, and compared with embodiment 1, a twelfth transistor T12 and a thirteenth transistor T13 are added to realize Vdd compensation.

[0080] refer to Figure 6 The pixel circuit of this embodiment is based on the embodiment 1 and adds: a twelfth transistor T12, whose gate is electrically connected to the input terminal of the second light emitting control signal EM2, whose source is electrically connected to the input terminal of the reference voltage signal Vref, and whose drain is electrically connected to the third node C; The thirteenth transistor T13 has a gate electrically connected to the input terminal of the first light emitting control signal EM1, a source electrically connected to the input terminal of the first power signal Vdd, and a drain electrically connected to the third node C.

[0081] In this structure, the light-emitting current of the seventh transistor T7 is K*(Vccg+Vth2+Vdd-Vref-Vdd-Vth2)^2=k*(Vccg-Vref)^2, which realizes compensation for Vdd. Specifically, when the first light-emitting control signal EM1 turns on the thirteenth transistor T13, the voltage of the third node C changes from the reference voltage Vref to Vdd, which causes the voltage of the first node A to change from the original Vccg+Vth2 to Vccg+Vth2+Vdd-Vref. Therefore, the current of the seventh transistor T7 is Ids=K*(Vg-Vs-Vth)^2=K*(Vccg+Vth2+Vdd-Vref-Vdd-Vth2)^2=K*(Vccg-Vref)^2. This process realizes Vdd compensation, so that the light-emitting current Ids is independent of Vdd.

[0082] Reference Table 2 Figure 5 and Figure 6 The specific working process of the display device of this embodiment is as follows: Data writing phase: Each row of pixel units performs data signal writing and compensation in turn. At this stage, the first data signal Data-PWM is written to the second node B of the pixel circuit, and the threshold voltage Vth1 of the second transistor T2 in diode mode is compensated to V(data-pwm)+Vth1. The voltage of the constant current source signal CCG is written to the first node A, and the threshold voltage Vth2 of the seventh transistor T7 in diode mode is compensated to Vccg+Vth2. After writing the data, the voltages of the second node B and the first node A are stored by the first capacitor C1 and the second capacitor C2, respectively. Each row of pixel units is controlled in turn by the scanning signal S(J) to perform data writing and compensation.

[0083] During the light-emitting stage, the first light-emitting control signal EM1 is at a low level. The voltage of the third node C changes from Vref to Vdd and is coupled to the first node A, causing the voltage of the first node A to change from Vccg + Vth2 to Vccg + Vth2 + Vdd - Vref. The voltage of the first node A is Vccg + Vth2 - Vdd < Vth2, and the seventh transistor T7 is turned on, and the light-emitting device LED starts to emit light. The light-emitting current of the seventh transistor T7 is Ids = K*(Vg - Vs - Vth2)^2 = K*(Vccg + Vth2 + Vdd - Vref - Vdd - Vth2)^2 = K*(Vccg - Vref)^2, and this process realizes Vdd compensation. During the process of the light-emitting device LED emitting light, the voltage of the second node B decreases as the voltage of the ramp signal Sweep decreases. When the voltage of the second node B, Vdata + Vth1 - V∆sweep(t) - Vdd < Vth1, the second transistor T2 is turned on, and the first power supply signal Vdd is written to the first node A, and the seventh transistor T7 is turned off, and the light-emitting device LED stops emitting light.

[0084] Table 2

[0085] Reference Figure 7 and Figure 8 In the display device provided by the embodiment of the present application, the pulse amplitude modulation module PAM further includes a fourteenth transistor T14 and a third capacitor C3.

[0086] The gate of the fourteenth transistor T14 is electrically connected to the input terminal of the second light-emitting control signal EM2. One of the source and drain of the fourteenth transistor T14 is electrically connected to the input terminal of the second power supply signal Vss, and the other of the source and drain of the fourteenth transistor T14 is electrically connected to the fourth node D.

[0087] One end of the third capacitor C3 is electrically connected to the fourth node D, and the other end is electrically connected to the input terminal of the first power supply signal Vdd.

[0088] During the data writing stage, the driving circuit is further configured to write a reference voltage signal Vref to the third node C and write a second power supply signal Vss to the fourth node D.

[0089] During the light-emitting stage: The voltage of the fourth node D is the voltage of the second power supply signal Vss, and the tenth transistor T10 is turned on, and the light-emitting device LED emits light; The voltage of the second node B decreases as the voltage of the Sweep signal decreases. When the voltage of the second node B V(data-pwm)+Vth1-V∆sweep(t)-Vdd<the threshold voltage Vth1 of the second transistor T2, the second transistor T2 is turned on, the first power signal Vdd is written to the fourth node D, the tenth transistor T10 is turned off, and the light-emitting device LED stops emitting light.

[0090] In the light emitting stage, the voltage of the first node A is V(data-pam)+Vth2, and the voltage of the second node B is V(data-pwm)+Vth1.

[0091] In the light emitting stage, the current Ids of the seventh transistor T7=K*(V(data-pam)-Vref)^2, wherein K is a constant.

[0092] The driving method also includes: In the data writing phase, the reference voltage signal Vref is written to the third node C, and the second power signal Vss is written to the fourth node D.

[0093] In the light-emitting stage, the voltage of the fourth node D is the voltage of the second power signal Vss, the tenth transistor T10 is turned on, and the light-emitting device LED emits light; the voltage of the second node B decreases as the voltage of the Sweep signal decreases, and when the voltage of the second node B V(data-pwm)+Vth1-V∆sweep(t)-Vdd<the threshold voltage Vth1 of the second transistor T2, the second transistor T2 is turned on, the first power signal Vdd is written to the fourth node D, the tenth transistor T10 is turned off, and the light-emitting device LED stops emitting light.

[0094] In the light emitting stage, the voltage of the first node A is Vccg+Vth2 or V(data-pam)+Vth2, and the voltage of the second node B is V(data-pwm)+Vth1.

[0095] Example 3 Embodiment 3 is similar to Embodiment 2, except that Embodiment 3 proposes a pixel circuit having a structure of 14 transistors and 3 capacitors, and realizes Vth / Vdd compensation.

[0096] refer to Figure 7 The pixel circuit of the display device of this embodiment is based on the embodiment 2 and adds: a fourteenth transistor T14, whose gate is electrically connected to the second light emitting control signal EM2 input terminal, whose source is electrically connected to the second power supply signal Vss input terminal, and whose drain is electrically connected to the fourth node D; The third capacitor C3 has one end electrically connected to the fourth node D, and the other end electrically connected to the first power signal Vdd input terminal.

[0097] Meanwhile, the gate of the tenth transistor T10 is changed to be electrically connected to the fourth node D, and the source of the eighth transistor T8 is changed to be electrically connected to the second data signal Data-PAM input terminal.

[0098] Referring to Table 3, Figure 7 and Figure 8 , the specific working process of the display device in this embodiment is as follows: Data writing stage: The voltage V(data-pwm) of the first data signal Data-PWM is written into the second node B, and the threshold voltage Vth1 of the second transistor T2 in the diode mode is compensated to V(data-pwm)+Vth1. The voltage Vdata of the second data signal Data-PAM is written into the first node A, and the threshold voltage Vth2 of the seventh transistor T7 in the diode mode is compensated to V(data-pam)+Vth2. A reference voltage signal Vref is written into the third node C, and a second power supply signal Vss is written into the fourth node D. After writing the data, the voltages of the second node B, the first node A, and the fourth node D are stored through the first capacitor C1, the second capacitor C2, and the third capacitor C3 respectively.

[0099] Light emitting stage: The first light emission control signal EM1 is at a low level, the thirteenth transistor T13 is turned on, the voltage of the third node C changes from Vref to Vdd and is coupled to the first node A. The voltage of the first node A changes from V(data-pam)+Vth2 to V(data-pam)+Vth2+Vdd-Vref. The voltage of the fourth node D remains the voltage of the second power supply signal Vss, the tenth transistor T10 remains turned on, the voltage of the first node A is V(data-pam)+Vth2-Vdd<Vth2, the seventh transistor T7 is turned on, and the light emitting device LED starts to emit light. The light emitting current of the seventh transistor T7 is K*(V(data-pam)+Vth2+Vdd-Vref-Vdd-Vth2)^2 = K*(V(data-pam)-Vref)^2, realizing Vdd compensation. During the light emitting process, the voltage of the second node B decreases as the voltage of the ramp signal Sweep decreases. When the voltage V(data-pwm)+Vth1-V∆sweep(t)-Vdd<Vth1 of the second node B, the second transistor T2 is turned on, the first power supply signal Vdd is written into the fourth node D, the tenth transistor T10 is turned off, and the light emitting device LED stops emitting light.

[0100] When data is written to the pixel units in other partitions, the voltages of the first node A and the third node C of the pixel units in this partition (the Jth partition) remain unchanged, and the voltage of the second node B is coupled to V(data-pwm)+Vth1 by the ramp signal Sweep, and the comparison luminescence is repeated. This comparison luminescence is performed multiple times to achieve multi-pulse luminescence.

[0101] Table 3

[0102] Since the first power signal Vdd input terminal will generate different loads depending on the screen content, there may be certain instability and voltage drop. In this embodiment, since one plate of the third capacitor C3 is connected to the first power signal Vdd input terminal, the change of the first power signal Vdd will be coupled to the gate of the tenth transistor T10. In this way, the difference between the gate voltage Vg and the source voltage Vs of the tenth transistor T10 can remain relatively stable, thereby offsetting the influence of the fluctuation of the first power signal Vdd and ensuring the stability of the current (the current formula is Ids=K*(Vg-Vs-Vth)^2).

[0103] Through the above technical solutions, the embodiments of the present application realize multi-partition multi-pulse light emission, effectively improving the flicker problem of the micro-light-emitting diode display panel when displaying low grayscale images, and at the same time improving the display uniformity and stability through various compensation mechanisms.

[0104] The technical solution of the embodiment of the present application can be applied to multi-partition single ramp signal multi-pulse luminescence, the waveform is as follows Figure 5 , Figure 8 As shown, it can also be applied to single-partition single-slope signal multi-pulse luminescence, the waveform is as follows Fig. 9As shown, the light-emitting stage includes multiple sub-light-emitting stages. In the data writing stage, the second light-emitting control signal EM2 is a low-level signal. In the first sub-light-emitting stage of the light-emitting stage, the second light-emitting control signal EM2 is a high-level signal. In the second and subsequent sub-light-emitting stages of the light-emitting stage, the second light-emitting control signal EM2 is first a low-level signal and then a high-level signal. That is to say, before or during each sub-light-emitting stage, each row of pixel units is reset by the low-level second light-emitting control signal EM2. The ramp signal Sweep is a signal with a linearly decreasing voltage; in the second and subsequent sub-light-emitting stages, the ramp signal Sweep is first a high-level signal and then becomes a signal with a linearly decreasing voltage. Single partition means that the micro-light-emitting diode display panel is not divided into multiple partitions; a single ramp signal means that a ramp signal output end is electrically connected to all pixel units of the entire micro-light-emitting diode display panel; multiple pulses mean that the ramp signal includes multiple sub-light-emitting stages in the light-emitting stage of the driving cycle of each frame, and each sub-light-emitting stage is a comparison light-emitting time. The number of pulses can be customized to 1 or more as needed.

[0105] The embodiment of the present application divides the display panel into N partitions along the scanning direction SD, and sequentially controls the pixel units of each partition in the N partitions to write data and emit light within the driving cycle of a frame, and at the same time uses a ramp signal containing multiple pulse cycles within the driving cycle of a frame to control the luminous time of the pixel unit, thereby achieving the dispersion of the luminous time. Compared with the traditional global synchronous luminescence, the scheme of the embodiment of the present application includes multiple sub-luminous stages within the driving cycle of a frame, and each sub-luminous stage corresponds to a pulse cycle of the ramp signal, so that each pixel unit emits light multiple times within the driving cycle of a frame. This partition multi-pulse driving method allows the pixel units in each partition to emit light multiple times within a frame cycle, rather than just once. This decentralized luminescence method can make the luminescence of the entire display panel more uniform in time. Therefore, even in a low grayscale picture, the luminous time can be evenly distributed throughout the driving cycle, thereby effectively improving the flicker problem.

[0106] In addition, the embodiment of the present application effectively eliminates the problem of uneven picture caused by inconsistent transistor characteristics by compensating the threshold voltages of the second transistor T2 and the seventh transistor T7, thereby further improving the display quality.

[0107] In addition, the embodiment of the present application introduces a technical solution of Vdd compensation, so that the current Ids of the seventh transistor T7 is independent of Vdd, thereby effectively reducing the impact of power supply voltage fluctuations on the display effect and improving the stability of the display.

[0108] The embodiments of the present application are described in detail above, and the contents of this specification should not be construed as limiting the scope of protection of the present application.

Claims

1. A display device, characterized in that: include: A display panel, wherein the display panel includes N partitions divided along a scanning direction (SD), each partition includes M rows of pixel units, each pixel unit includes a pixel circuit and a light emitting device (LED), and N and M are both positive integers; as well as A driving circuit, electrically connected to the pixel unit, the driving circuit is used to generate a ramp signal (Sweep), input the ramp signal (Sweep) to the pixel unit, and sequentially control the pixel unit of each of the N partitions to write data and emit light within a driving cycle of a frame; The ramp signal (Sweep) includes multiple pulse cycles within a driving cycle of a frame, and the driving cycle of the pixel unit in each partition includes a data writing stage and a light-emitting stage. The data writing stage precedes the light-emitting stage, and the light-emitting stage includes multiple pulse cycles of the ramp signal (Sweep).

2. The display device according to claim 1, characterized in that The ramp signal (Sweep) output terminal of the driving circuit is electrically connected to the plurality of pixel units of the display panel, and the driving circuit is used to generate the ramp signal (Sweep) and provide the ramp signal (Sweep) to the plurality of pixel units through the ramp signal (Sweep) output terminal; The pixel circuit includes a pulse width modulation module (PWM) and a pulse amplitude modulation module (PAM), the pulse width modulation module (PWM) is electrically connected to the pulse amplitude modulation module (PAM), the pulse amplitude modulation module (PAM) is electrically connected to the light emitting device (LED), and the ramp signal (Sweep) input end of the pulse width modulation module (PWM) is electrically connected to the ramp signal (Sweep) output end of the driving circuit.

3. The display device according to claim 2, characterized in that: The pulse width modulation module (PWM) comprises: A first transistor (T1), wherein a gate of the first transistor (T1) is electrically connected to an input terminal of a first light emitting control signal (EM1); a second transistor (T2), wherein a gate of the second transistor (T2) is electrically connected to a second node (B), and one of a source and a drain of the second transistor (T2) is electrically connected to one of a source and a drain of the first transistor (T1); a third transistor (T3), wherein a gate of the third transistor (T3) is electrically connected to the first light emitting control signal (EM1) input terminal, one of a source and a drain of the third transistor (T3) is electrically connected to the other of a source and a drain of the second transistor (T2), and the other of a source and a drain of the third transistor (T3) is electrically connected to the first power supply signal (Vdd) input terminal; a fourth transistor (T4), wherein a gate of the fourth transistor (T4) is electrically connected to an input terminal of a scanning signal S(J), one of a source and a drain of the fourth transistor (T4) is electrically connected to the second node (B), and the other of a source and a drain of the fourth transistor (T4) is electrically connected to one of a source and a drain of the second transistor (T2); a fifth transistor (T5), wherein a gate of the fifth transistor (T5) is electrically connected to the scan signal S(J) input terminal, one of a source and a drain of the fifth transistor (T5) is electrically connected to the first data signal (Data-PWM) input terminal, and the other of the source and the drain of the fifth transistor (T5) is electrically connected to the other of the source and the drain of the second transistor (T2); and a first capacitor (C1), one end of the first capacitor (C1) being electrically connected to the second node (B), and the other end of the first capacitor (C1) being electrically connected to the ramp signal (Sweep) input end; Wherein, J is a positive integer.

4. The display device according to claim 2, characterized in that: The pulse amplitude modulation module (PAM) comprises: a sixth transistor (T6), wherein a gate of the sixth transistor (T6) is electrically connected to the first light emitting control signal (EM1) input terminal, and one of a source and a drain of the sixth transistor (T6) is electrically connected to the first power supply signal (Vdd) input terminal; a seventh transistor (T7), wherein a gate of the seventh transistor (T7) is electrically connected to the first node (A), and one of a source and a drain of the seventh transistor (T7) is electrically connected to the other of a source and a drain of the sixth transistor (T6); an eighth transistor (T8), wherein a gate of the eighth transistor (T8) is electrically connected to a second light emitting control signal (EM2) input terminal or the scanning signal S(J) input terminal, one of a source and a drain of the eighth transistor (T8) is electrically connected to a constant current source signal (CCG) input terminal or a second data signal (Data-PAM) input terminal, and the other of a source and a drain of the eighth transistor (T8) is electrically connected to one of a source and a drain of the seventh transistor (T7); a ninth transistor (T9), wherein a gate of the ninth transistor (T9) is electrically connected to the second light emitting control signal (EM2) input terminal or the scanning signal S (J) input terminal, one of a source and a drain of the ninth transistor (T9) is electrically connected to the first node (A), and the other of the source and the drain of the ninth transistor (T9) is electrically connected to the other of the source and the drain of the seventh transistor (T7); a tenth transistor (T10), wherein a gate of the tenth transistor (T10) is electrically connected to the first light emission control signal (EM1) input terminal or the fourth node (D), one of a source and a drain of the tenth transistor (T10) is electrically connected to the other of a source and a drain of the seventh transistor (T7), and the other of a source and a drain of the tenth transistor (T10) is electrically connected to an anode of the light emitting device (LED); an eleventh transistor (T11), a gate of the eleventh transistor (T11) being electrically connected to the second light emission control signal (EM2) input terminal, one of a source and a drain of the eleventh transistor (T11) being electrically connected to the anode of the light emitting device (LED), and the other of a source and a drain of the eleventh transistor (T11) being electrically connected to a second power supply signal (Vss) input terminal; and A second capacitor (C2), one end of the second capacitor (C2) is electrically connected to the first node (A), and the other end is electrically connected to the first power signal (Vdd) input terminal.

5. The display device according to claim 4, characterized in that The pulse amplitude modulation module (PAM) further comprises: a twelfth transistor (T12), wherein a gate of the twelfth transistor (T12) is electrically connected to an input terminal of the second light emitting control signal (EM2) or the scanning signal S(J), one of a source and a drain of the twelfth transistor (T12) is electrically connected to an input terminal of a reference voltage signal (Vref), and the other of a source and a drain of the twelfth transistor (T12) is electrically connected to a third node (C); and A thirteenth transistor (T13), wherein the gate of the thirteenth transistor (T13) is electrically connected to the first light emitting control signal (EM1) input terminal, one of the source and the drain of the thirteenth transistor (T13) is electrically connected to the first power supply signal (Vdd) input terminal, and the other of the source and the drain of the thirteenth transistor (T13) is electrically connected to the third node (C).

6. The display device according to claim 5, characterized in that: In the light emitting stage, the current Ids of the seventh transistor (T7) is Ids=K*(Vccg-Vref)^2 or Ids=K*(V(data-pam)-Vref)^2, wherein K is a constant.

7. The display device according to claim 4, characterized in that The pulse amplitude modulation module (PAM) further comprises: a fourteenth transistor (T14), wherein a gate of the fourteenth transistor (T14) is electrically connected to the second light emission control signal (EM2) input terminal, one of a source and a drain of the fourteenth transistor (T14) is electrically connected to the second power supply signal (Vss) input terminal, and the other of a source and a drain of the fourteenth transistor (T14) is electrically connected to a fourth node (D); and A third capacitor (C3), one end of the third capacitor (C3) is electrically connected to the fourth node (D), and the other end of the third capacitor is electrically connected to the first power signal (Vdd) input terminal.

8. The display device according to claim 2, characterized in that: The driving circuit is used to write a first data signal (Data-PWM) to a second node (B) of the pulse width modulation module (PWM) during the data writing phase, and to write a constant current source signal (CCG) to a first node (A) of the pulse amplitude modulation module (PAM), wherein a threshold voltage Vth1 of the second transistor (T2) is compensated to V(data-pwm)+Vth1, and a threshold voltage Vth2 of the seventh transistor (T7) is compensated to Vccg+Vth2.

9. The display device according to claim 8, characterized in that: During the light-emitting phase: The first light emitting control signal (EM1) input terminal receives a low-level first light emitting control signal (EM1), the sixth transistor (T6) and the tenth transistor (T10) are turned on, and the light emitting device (LED) emits light; When the voltage V(data-pwm)+Vth1-V∆sweep(t)-Vdd of the second node (B) is less than the threshold voltage Vth1 of the second transistor (T2), the second transistor (T2) is turned on, the first power signal (Vdd) is written to the first node (A), the seventh transistor (T7) is turned off, and the light-emitting device (LED) stops emitting light.

10. The display device according to claim 8, characterized in that: In the data writing phase, the driving circuit is further used to write a reference voltage signal (Vref) to the third node (C); or In the data writing phase, the driving circuit is further used to write a reference voltage signal (Vref) to the third node (C) and write a second power supply signal (Vss) to the fourth node (D).

11. The display device according to claim 10, characterized in that: During the light-emitting phase: The first light-emitting control signal (EM1) input terminal receives a low-level first light-emitting control signal (EM1), the thirteenth transistor (T13) is turned on, the voltage of the third node (C) changes from Vref to Vdd and is coupled to the first node (A), the seventh transistor (T7) is turned off, and the light-emitting device (LED) stops emitting light.

12. The display device according to claim 11, characterized in that: During the light-emitting phase: The voltage of the fourth node (D) is the voltage of the second power signal (Vss), the tenth transistor (T10) is turned on, and the light emitting device (LED) emits light; When the voltage V(data-pwm)+Vth1-V∆sweep(t)-Vdd of the second node (B) is less than the threshold voltage Vth1 of the second transistor (T2), the second transistor (T2) is turned on, the first power signal (Vdd) is written to the fourth node (D), the tenth transistor (T10) is turned off, and the light-emitting device (LED) stops emitting light.

13. The display device according to claim 8, characterized in that In the light emitting stage, the voltage of the first node (A) is Vccg+Vth2 or V(data-pam)+Vth2, and the voltage of the second node (B) is V(data-pwm)+Vth1.

14. A method for driving a display device, characterized in that: The display panel of the display device includes N partitions divided along a scanning direction (SD), each partition includes M rows of pixel units, each pixel unit includes a pixel circuit and a light emitting device (LED), N and M are both positive integers, and the driving method includes: Generate a ramp signal (Sweep), wherein the ramp signal (Sweep) includes a plurality of pulse periods within a driving period of one frame; Inputting the ramp signal (Sweep) to the plurality of pixel units; and In a driving cycle of one frame, the pixel unit of each of the N partitions is sequentially controlled to write data and emit light; The driving cycle of the pixel unit in each partition includes a data writing phase and a light emitting phase. The data writing phase precedes the light emitting phase. The light emitting phase includes a plurality of pulse cycles of the ramp signal (Sweep).

15. The driving method according to claim 14, characterized in that: The driving method further includes: In the data writing phase, a first data signal (Data-PWM) is written into a second node (B) of a pulse width modulation module (PWM) of the pixel circuit, and a constant current source signal (CCG) is written into a first node (A) of a pulse amplitude modulation module (PAM) of the pixel circuit; The threshold voltage Vth1 of the second transistor (T2) is compensated to V(data-pwm)+Vth1, and the threshold voltage Vth2 of the seventh transistor (T7) is compensated to Vccg+Vth2.

16. The driving method according to claim 15, characterized in that: The driving method further includes: During the light-emitting phase: The first light emitting control signal (EM1) input terminal receives a low-level first light emitting control signal (EM1), the sixth transistor (T6) and the tenth transistor (T10) are turned on, and the light emitting device (LED) emits light; When the voltage V(data-pwm)+Vth1-V∆sweep(t)-Vdd of the second node (B) is less than the threshold voltage Vth1 of the second transistor (T2), the second transistor (T2) is turned on, the first power signal (Vdd) is written to the first node (A), the seventh transistor (T7) is turned off, and the light-emitting device (LED) stops emitting light.

17. The driving method according to claim 15, characterized in that: The driving method further includes: In the data writing phase, writing a reference voltage signal (Vref) to the third node (C); or In the data writing phase, a reference voltage signal (Vref) is written to the third node (C), and a second power supply signal (Vss) is written to the fourth node (D).

18. The driving method according to claim 17, characterized in that: The driving method further includes: During the light-emitting phase: The first light-emitting control signal (EM1) input terminal receives a low-level first light-emitting control signal (EM1), the thirteenth transistor (T13) is turned on, so that the voltage of the third node (C) changes from Vref to Vdd and is coupled to the first node (A), the seventh transistor (T7) is turned off, and the light-emitting device (LED) stops emitting light.

19. The driving method according to claim 18, characterized in that: The driving method further includes: During the light-emitting phase: The voltage of the fourth node (D) is the voltage of the second power signal (Vss), the tenth transistor (T10) is turned on, and the light emitting device (LED) emits light; When the voltage V(data-pwm)+Vth1-V∆sweep(t)-Vdd of the second node (B) is less than the threshold voltage Vth1 of the second transistor (T2), the second transistor (T2) is turned on, the first power signal (Vdd) is written to the fourth node (D), the tenth transistor (T10) is turned off, and the light-emitting device (LED) stops emitting light.

20. The driving method according to claim 15, characterized in that: In the light emitting stage, the voltage of the first node (A) is Vccg+Vth2 or V(data-pam)+Vth2, and the voltage of the second node (B) is V(data-pwm)+Vth1.

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