A method for compensating for CDR channel asymmetry in a high-speed transmission system

Abstract

The application discloses a compensation method for CDR channel asymmetry in a high-speed transmission system i and a decision error e i of a current received symbol, attempts to match a continuous received decision bit stream with a special bit sequence pattern to calculate inter-symbol interference ISI, and then uses the calculated inter-symbol interference ISI to compensate for the asymmetry of the channel The application provides a compensation method for CDR channel asymmetry in a high-speed transmission system, which is simple to implement, has a faster convergence speed and better performance.

Description

Technical Field

[0001] This invention relates to the field of information transmission technology, and more specifically, to a compensation method for the asymmetry of CDR channels in high-speed transmission systems. Background Technology

[0002] Clock and data recovery (CDR) is one of the most challenging key technologies in modern high-speed serial data transmission. Compared to other clock and data recovery techniques based on double baud rate sampling rates, such as the Bang-Bang algorithm, the Mueller-Mueller phase detector (MMPD)-based clock and data recovery circuit (MM-CDR) offers unparalleled advantages in terms of power consumption and chip area due to its single baud rate sampling rate.

[0003] The clock and data recovery circuit (MM-CDR) based on the Mueller-Mueller phase detector (MMPD) analyzes the sampled data at a single baud rate to infer the channel impulse response of the current channel. It then continuously adjusts its sampling clock until it is aligned with the center of the data, ultimately achieving optimal reception performance. The principle of MM-CDR in adjusting the sampling clock is to make the suffix h1 of the channel impulse response equal to the prefix h of the channel impulse response. -1 .

[0004] like Figure 1 As shown, assuming the channel impulse response is symmetrical, when the suffix h1 of the channel impulse response is greater than the prefix h of the channel impulse response... -1 At this time, sampling is too early (Phase Early); when the suffix h1 of the channel impulse response is less than the prefix h of the channel impulse response. -1 When sampling is too early (Phase Late), the function of the clock and data recovery circuit (MM-CDR) based on the Mueller-Mueller phase detector (MMPD) is to output the phase detection of the sampling clock as early or late.

[0005] The greatest advantage of the clock and data recovery circuit (MM-CDR) based on the Mueller-Mueller phase detector (MMPD) is that, because it requires baud rate sampling, the sampling rate is halved, thus eliminating the need for a higher-speed sampler. However, given a channel with an asymmetric channel response, i.e., h1 ≠ h... -1 If this happens, the MM-CDR will lock in the incorrect position. In this case, some corrections are needed to lock the CDR in the correct position.

[0006] The issue of clock and data recovery circuits (MM-CDR) based on Mueller-Mueller phase detectors (MMPDs) failing to lock onto the correct sampling position when operating in asymmetric channels has been addressed. Research has been conducted on traditional MM-CDRs, and various improvement methods have been proposed.

[0007] Some solutions propose improved methods for eye diagram maximization. These methods add an eye diagram change trend estimation module, which estimates the trend of eye diagram changes, providing an estimate of whether the eye diagram is increasing or decreasing. The CDR then adjusts the sampling phase based on this trend. The drawback of this approach is that the algorithm for estimating the eye diagram change trend is relatively complex and can only operate within specific channel impulse responses.

[0008] Some schemes propose a combination of a Mueller-Mueller phase detector (MMPD) and a decision feedback equalizer (DFE). Since the value c0 of the first tap of the decision feedback equalizer reflects the channel asymmetry to some extent, in this scheme, the decision feedback equalizer sends its first tap value c0 to the Mueller-Mueller phase detector (MMPD) in real time; the Mueller-Mueller phase detector (MMPD) uses this value c0 to compensate for the channel asymmetry. In practice, the Mueller-Mueller phase detector (MMPD) typically multiplies the value c0 by an empirical value α, and then uses α*c0 to compensate for the channel asymmetry. The drawback of this scheme is that the value of the empirical value α depends on the current channel impulse response, resulting in a relatively large error in its configuration in practice.

[0009] Therefore, there is an urgent need for technologies that can be effectively used in high-speed transmission systems with asymmetric channels. Summary of the Invention

[0010] This invention overcomes the shortcomings of the prior art and provides a compensation method for the asymmetry of CDR channels in high-speed transmission systems that is simple to implement, has a fast convergence speed, and good performance.

[0011] The technical solution of the present invention is as follows:

[0012] A compensation method for the asymmetry of CDR channels in high-speed transmission systems includes the decision bit d of the currently received symbol. i The decision error e of the currently received symbol i The process involves matching continuously received decision bit streams with a specific bit sequence pattern to calculate inter-symbol interference (ISI); then, the calculated ISI is used to compensate for channel asymmetry, specifically including the following steps:

[0013] 1) Pre-designed steps: Design at least three special bit sequence patterns to be matched, with a fixed length of N. patLen Select N patNumThere are N special bit sequence patterns; where every two special bit sequence patterns form a matching special bit sequence pattern, and these two matching special bit sequence patterns differ in only one bit, with the remaining N bits being different. patLen -1 bit sequences are all identical;

[0014] 2) Comparison and verification steps: The latest N patLen The decision bits of each received symbol are respectively This is used as a bit sequence pattern to be verified;

[0015] If the bit sequence pattern to be verified is a pre-stored special bit sequence pattern in step 1), then it is assumed to be pre-stored as pattern0; when the matching pattern1, which is a group with pattern0, appears in a previous special bit sequence pattern to be verified, then the decision error information of pattern0 and pattern1 is used to complete an ISI calculation. After the calculation is completed, all matching records of pattern0 and pattern1 are cleared; proceed to the next step.

[0016] If the matching pattern1, which is grouped with pattern0, does not appear in any previous pattern to be verified, then pattern0 stores the current decision error e. i ;

[0017] If the bit sequence pattern to be verified is not a pre-stored special bit sequence pattern in step 1), then continue to compare and verify the decision bit information and decision error information of the next received symbol.

[0018] 3) Filtering Processing Steps: Based on the processing in step 2), and the current position of the received symbol, an ISI calculation has been completed. Then, another alpha filter is performed to obtain a new ISI filtering result. filter ;

[0019] 4) Sampling adjustment steps: Adjust the prescaler h of the current channel impulse response. -1 Is the difference between the suffix h1 and the channel impulse response greater than the newly obtained ISI filtering result obtained in step 3)? filter If it is greater than the newly obtained ISI filter result, then ISI filter If the sampling is too early, then the sampling is too early; if it is less than the newly obtained ISI filter result, then the ISI is too early. filter If the sampling is too late, adjust the sampling accordingly and repeat step 2) to wait for comparison and verification of the next received symbol until the CDR is locked to the correct position.

[0020] Furthermore, the length value in step 1) is configurable.

[0021] Furthermore, the calculation workload of the preset configuration in step 1) is simplified by setting...

[0022] Furthermore, the equalizer provides the decision bits d of the currently received symbol. i The decision error e of the currently received symbol i .

[0023] Furthermore, the filtering calculation process is as follows:

[0024] ISI filter =ISI filter *(1-α filter )+ISI*α filter

[0025] Where, α filter The filter factor has a configurable value; the filtering result is ISI. filter The initial value is 0.

[0026] The advantages of this invention compared to the prior art are:

[0027] This invention estimates channel asymmetry by calculating residual inter-symbol interference (ISI). A Mueller-Mueller phase detector (MMPD) samples this estimate to compensate for channel asymmetry, achieving the goals of simple implementation, fast convergence speed, and good performance. This enables the improved Mueller-Mueller phase detector (MMPD) to be effectively used in high-speed transmission systems with asymmetric channels. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the existing MMPD processing;

[0029] Figure 2 This is a flowchart illustrating the specific processing steps in the comparison and verification of this invention.

[0030] Figure 3 This is a schematic diagram of the improved MMPD processing according to the present invention;

[0031] Figure 4 This is a flowchart of the processing of the present invention. Detailed Implementation

[0032] Embodiments of the present invention are described in detail below, wherein the same or similar reference numerals denote the same or similar elements or elements with similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and should not be construed as limiting the present invention.

[0033] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless defined as herein.

[0034] The numbering of steps mentioned in the various embodiments is merely for descriptive convenience and does not imply a sequential relationship. Different steps in each specific embodiment can be combined in different orders to achieve the inventive objective of this invention. Furthermore, the structures and modules not described in detail in this invention can all be implemented using conventional techniques, and therefore will not be described in detail further.

[0035] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0036] As shown in the figure, a compensation method for the asymmetry of CDR channels in high-speed transmission systems includes the decision bit d of the currently received symbol. i The decision error e of the currently received symbol i The process involves matching continuously received decision bit streams with a specific bit sequence pattern to calculate inter-symbol interference (ISI); then, the calculated ISI is used to compensate for channel asymmetry. Specifically, the steps include:

[0037] 1) Pre-designed steps: Design at least three sets of special bit sequence patterns to be matched, with a fixed length of N. patLen The length value is configurable. To simplify calculations, set... Select N patNum N patNum / 2 groups) of special bit sequence patterns; where every two special bit sequence patterns form a matching special bit sequence pattern group, and these two matching special bit sequence patterns differ in only one bit, with the remaining N bits being different. patLen -1 bit sequences are all identical;

[0038] 2) Comparison and verification steps: The decision bits d of the currently received symbol provided by the equalizer i The decision error e of the currently received symbol i The latest N patLen The decision bits of each received symbol are respectively This is used as a bit sequence pattern to be verified;

[0039] If the bit sequence pattern to be verified is a pre-stored special bit sequence pattern in step 1), then it is assumed to be pre-stored as pattern0; when the matching pattern1, which is a group with pattern0, appears in a previous special bit sequence pattern to be verified, then the decision error information of pattern0 and pattern1 is used to complete an ISI calculation. After the calculation is completed, all matching records of pattern0 and pattern1 are cleared; proceed to the next step.

[0040] If the matching pattern1, which is grouped with pattern0, does not appear in any previous pattern to be verified, then pattern0 stores the current decision error e. i ;

[0041] If the bit sequence pattern to be verified is not a pre-stored special bit sequence pattern in step 1), then continue to compare and verify the decision bit information and decision error information of the next received symbol.

[0042] 3) Filtering Processing Steps: Based on the processing in step 2), and the current position of the received symbol, an ISI calculation has been completed. Then, another alpha filter is performed to obtain a new ISI filtering result. filter The filtering calculation process is as follows:

[0043] ISI filter =ISI filter *(1-α filter )+ISI*α filter

[0044] Where, α filter The filter factor has a configurable value; the filtering result is ISI. filter The initial value is 0.

[0045] 4) Sampling adjustment steps: Adjust the prescaler h of the current channel impulse response. -1 Is the difference between the suffix h1 and the channel impulse response greater than the newly obtained ISI filtering result obtained in step 3)? filter If it is greater than the newly obtained ISI filter result, then ISI filter If the sampling is too early, then the sampling is too early; if it is less than the newly obtained ISI filter result, then the ISI is too early. filter If the sampling is too late, adjust the sampling accordingly and repeat step 2) to wait for comparison and verification of the next received symbol until the CDR is locked to the correct position.

[0046] Compared to traditional methods that do not use inter-symbol interference compensation for channel asymmetry, the clock and data recovery circuit (MM-CDR) decision criterion of the traditional Mueller-Mueller phase detector (MMPD) is: when the channel impulse response prescaler h... -1 Subtract the suffix h1 from the channel impulse response and check if it is greater than 0. If it is greater than 0, the sampling is too early (Phase Early); if it is less than 0, the sampling is too late (Phase Late). Therefore, using inter-symbol interference to compensate for channel asymmetry can greatly reduce the error, and it is simple to implement and has a fast convergence speed.

[0047] Specific examples are as follows:

[0048] 1) Preset steps: For example, fix the length of the bit sequence pattern to be matched to 5 bits, and select only 8 (4 groups) bit sequence patterns. Specifically, establish the information data as shown in the table below, where every two patterns are a matching pattern.

[0049]

[0050]

[0051] 2) Comparison and verification steps: The decision bits d of the currently received symbol provided by the equalizer i The decision error e of the currently received symbol i The decision bits for the latest 5 received symbols are d. i d i-1 d i-2 d i-3 d i-4 Then value = 16 * d i +8*d i-1 +4*d i-2 +2*d i-3 +d i-4 ,according to Figure 2 Perform a match detection and attempt to calculate the ISI once.

[0052] If as Figure 2 If matchFlag=1 during processing, it means that an ISI calculation has been completed at the position of the current received symbol, and then the next alpha filtering is performed to obtain a new ISI filtering result.

[0053] If as Figure 2 If matchFlag=0 during processing, it means that the pattern match was unsuccessful at the current received symbol position, and the process returns to wait for the next received symbol.

[0054] 3) Filtering Processing Steps: Based on the processing in step 2), and the current position of the received symbol, an ISI calculation has been completed. Then, another alpha filter is performed to obtain a new ISI filtering result. filter The filtering calculation process is as follows:

[0055] ISI filter =ISI filter *(1-α filter )+ISI*α filter

[0056] Where, α filter The filter factor has a configurable value; the filtering result is ISI. filter The initial value is 0.

[0057] 4) Sampling adjustment steps: Adjust the prescaler h of the current channel impulse response. -1 Is the difference between the suffix h1 and the channel impulse response greater than the newly obtained ISI filtering result obtained in step 3)? filter If it is greater than the newly obtained ISI filter result, then ISI filter If the sampling is too early, then the sampling is too early; if it is less than the newly obtained ISI filter result, then the ISI is too early. filter If the sampling is too late, adjust the sampling accordingly and repeat step 2) to wait for comparison and verification of the next received symbol until the CDR is locked to the correct position.

[0058] In summary, this scheme estimates the channel asymmetry by calculating the residual inter-symbol interference (ISI), and the Mueller-Mueller phase detector (MMPD) samples this estimate to compensate for the channel asymmetry, achieving the goals of simple implementation, fast convergence speed, and good performance.

[0059] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the concept of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for compensating for CDR channel asymmetry in a high speed transmission system, the method comprising: decision bits of a current received symbol and a decision error of the current received symbol The decision bits of the current received symbol are matched with a special bit sequence pattern to calculate the inter-symbol interference ISI, and then the calculated inter-symbol interference ISI is used to compensate the asymmetry of the channel, which includes the following steps: ​ 1) preset step: design at least three groups of special bit sequence patterns to be matched, with fixed length of , and select special bit sequence patterns; wherein each two special bit sequence patterns are a group of matched special bit sequence patterns, and the two matched special bit sequence patterns in the group only differ in one bit, and the remaining bit sequences are all the same; 2) alignment verification step: the current latest The decision bits of the individual received symbols are taken as a bit sequence pattern to be verified; If the bit sequence pattern to be verified is one of the pre-stored special bit sequence patterns in step 1), assuming it is pre-stored as pattern0; when a matching pattern1 in the same group as pattern0 appears in some previous special bit sequence pattern to be verified, a ISI calculation is completed using the decision error information of both pattern0 and pattern1, and after the calculation is completed, all the matching records of pattern0 and pattern1 are cleared; the next step is entered; If the matching pattern1 which is a group with pattern0 does not appear in some of the previous patterns to be verified, pattern0 saves the current decision error ; If the bit sequence pattern to be verified is not one of the pre-stored special bit sequence patterns in step 1), the decision bit information and the decision error information of the next received symbol are compared and verified; 3) filtering step: according to the processing of step 2), the position of the current received symbol, the ISI calculation is completed, then the alpha filtering is performed again to obtain the new ISI filtering result ; 4) Sampling adjustment step: Determine the prefix of the current channel impulse response. Postscript of the channel impulse response Is the difference greater than the newly obtained ISI filtering result in step 3)? If it is greater than the newly obtained ISI filter result If so, the sampling is too early; If less than the newly obtained ISI filtered result then the sampling is late; make a corresponding sampling adjustment, and repeat the above step 2) of waiting for the correlation to verify the next received symbol until the CDR locks to the correct position.

2. The method of claim 1, wherein the method is characterized by: The length value in step 1) is configurable.

3. The method of claim 1, wherein the method further comprises: determining a first phase difference between the first and second CDR channels; and adjusting the first phase difference to compensate for the non-symmetry of the first and second CDR channels. Simplifying the preset configuration in step 1) to set .

4. The method of claim 1, wherein the method further comprises: determining a first phase difference between the first and second CDR channels; and adjusting the first phase difference to compensate for the non-symmetry of the first and second CDR channels. The equalizer provides a decision bit of the current received symbol and a decision error of the current received symbol .

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