Distortion calibration circuit and method for analog-to-digital conversion, electronic equipment and medium

Abstract

The invention provides a distortion calibration circuit and method for analog-to-digital conversion, electronic equipment and a medium, and is characterized in that the circuit comprises a jitter signal generation module; the first input end of the first signal calculation module is used for connecting an analog input signal, and the second input end is connected with the output end of the jitter signal generation module; the input end of the target input buffer is connected with the output end of the first signal calculation module; the first input end of the compensation module is connected with the output end of the target input buffer; the input end of the analog-to-digital converter is connected with the output end of the compensation module; the first input end of the second signal calculation module is connected with the output end of the analog-to-digital converter, and the second input end of the second signal calculation module is connected with the output end of the jitter signal generation module; the input end of the harmonic coefficient generation module is connected with the output end of the second signal calculation module, and the output end is connected with the second input end of the compensation module. Signal distortion caused by nonlinearity in the input buffer can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of distortion calibration for analog-to-digital conversion, and in particular to a distortion calibration circuit, method, electronic equipment and medium for analog-to-digital conversion. Background Art

[0002] Linearity is an important indicator to measure the relationship between the output and input of a system or device. Linearity is usually expressed in percentage or decibel (dB). Higher linearity means that the system or device can respond to changes in the input signal in a more linear manner, while lower linearity means that there is greater nonlinear distortion.

[0003] Currently, since high-bandwidth analog-to-digital converters (ADCs) generate large loads on the input, inputting the input signal into a wideband ADC without losing signal integrity places high demands on the drive capability of the previous input. These requirements come from the fact that driving a large amount of sampling capacitance (~pF) in a very short sampling time (hundreds of picoseconds) may cause dynamic distortion of the input buffer. In addition, the power supply voltage margin with similar input swing will also cause large static distortion, which leads to the urgent need to calibrate the distortion of the input buffer and mitigate nonlinearity. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides a distortion calibration circuit, method, electronic device, and medium for analog-to-digital conversion, which can improve signal distortion caused by nonlinearity in an input buffer.

[0005] In a first aspect, an embodiment of the present invention provides a distortion calibration circuit for analog-to-digital conversion, comprising: A jitter signal generating module, used for generating a jitter signal; a first signal calculation module, wherein a first input terminal of the first signal calculation module is used to connect an analog input signal, a second input terminal of the first signal calculation module is connected to an output terminal of the jitter signal generation module, and the first signal calculation module is used to add the analog input signal and the jitter signal; a target input buffer, wherein an input end of the target input buffer is connected to an output end of the first signal calculation module; a compensation module, wherein a first input terminal of the compensation module is connected to an output terminal of the target input buffer; an analog-to-digital converter, wherein an input end of the analog-to-digital converter is connected to an output end of the compensation module; a second signal calculation module, wherein a first input terminal of the second signal calculation module is connected to the output terminal of the analog-to-digital converter, and a second input terminal of the second signal calculation module is connected to the output terminal of the jitter signal generation module, and is used for subtracting the signal output by the analog-to-digital converter from the output result of the jitter signal generation module; A harmonic coefficient generating module, wherein the input end of the harmonic coefficient generating module is connected to the output end of the second signal calculating module, and the output end of the harmonic coefficient generating module is connected to the second input end of the compensation module.

[0006] In some embodiments of the present invention, the jitter signal generating module includes: A first jitter signal generating submodule, used to generate a first jitter sub-signal; A second jitter signal generating submodule, used to generate a second jitter sub-signal; The first signal calculation module also includes: a first capacitive coupler, wherein the first capacitive coupler is respectively connected to an output end of the first jitter signal generating submodule, an input position of the analog input signal, and a first input end of the target input buffer; A second capacitive coupler, wherein the second capacitive coupler is respectively connected to an output end of the second jitter signal generating submodule, an input position of the analog input signal, and a second input end of the target input buffer.

[0007] In some embodiments of the present invention, the compensation module includes: a harmonic compensation diode load, and the harmonic compensation diode load is connected to the target input buffer.

[0008] In some embodiments of the present invention, the harmonic coefficient generation module includes: A plurality of comparators, wherein an input end of each of the comparators is respectively connected to an output end of the second signal calculation module; A plurality of counters, wherein the input end of each counter is respectively connected to the output end of the corresponding comparator; A plurality of accumulators, wherein the input end of each accumulator is respectively connected to the output end of the corresponding counter; The averager has an input end connected to the output end of each accumulator, and the output end of the averager is connected to the input end of the compensation module.

[0009] In a second aspect, an embodiment of the present invention provides a distortion calibration method for analog-to-digital conversion. Based on the distortion calibration method for analog-to-digital conversion as described in any one of the first aspects, the method includes: The first signal calculation module performs an addition calculation on the analog input signal and the jitter signal to obtain a first signal, and inputs the first signal to a target input buffer, wherein the jitter signal is provided by the jitter signal generation module; The target input buffer isolates and processes the first signal and inputs the first signal to the compensation module; The compensation module performs harmonic compensation on the first signal according to the harmonic coefficient to obtain a second signal, and inputs the second signal to the analog-to-digital converter, wherein the harmonic coefficient is generated by the harmonic coefficient generation module; The analog-to-digital converter performs analog-to-digital conversion on the second signal to obtain a target digital signal; A second signal calculation module performs a subtraction calculation on the target digital signal and the jitter signal to obtain a third signal, and inputs the third signal to the harmonic coefficient generation module; The harmonic coefficient generating module calculates the third signal and the jitter signal, and updates the harmonic coefficient according to the calculation result.

[0010] In some embodiments of the present invention, the harmonic coefficient generation module includes an accumulator, a plurality of comparators, a plurality of counters and a plurality of accumulators, each of the comparators is connected to each of the counters in a one-to-one correspondence, each of the accumulators is connected to each of the counters in a one-to-one correspondence, the averager is connected to the accumulator, the averager is connected to the compensation module, wherein a voltage threshold is preset in the comparator, and the voltage threshold in each of the comparators is different, the harmonic coefficient generation module calculates the third signal based on a preset harmonic coefficient generation algorithm to obtain a harmonic coefficient, and inputs the harmonic coefficient into the compensation module, including: The comparator compares the voltage threshold with the second signal to obtain a comparison result; When the comparison result is less than the absolute value of the voltage threshold, the third signal is assigned a value of 0; When the comparison result is greater than the absolute value of the voltage threshold, the third signal is assigned a value of 1; The counter multiplies the third signal by the jitter signal to obtain a multiplication result; The accumulator adds the multiplication results passed through the same comparator and counter to obtain an addition result; The averager averages the addition results output by each of the accumulators to obtain the harmonic coefficient.

[0011] In some embodiments of the present invention, the jitter signal generation module includes: a first jitter signal generation submodule, used to generate a first jitter sub-signal; a second jitter signal generation submodule, used to generate a second jitter sub-signal; the first signal calculation module also includes: a first capacitive coupler, the first capacitive coupler is respectively connected to the output end of the first jitter signal generation submodule, the input position of the analog input signal, and the first input end of the target input buffer; a second capacitive coupler, the second capacitive coupler is respectively connected to the output end of the second jitter signal generation submodule, the input position of the analog input signal, and the second input end of the target input buffer; The first signal calculation module performs an addition calculation on the analog input signal and the jitter signal to obtain a first signal, and inputs the first signal to a target input buffer, including: The first jitter signal generating submodule generates the first jitter sub-signal, and inputs the first jitter sub-signal to the first capacitive coupler; The first capacitive coupler couples the analog input signal with the first jitter sub-signal, and the coupled analog input signal is input into the target input buffer through the first input terminal of the target input buffer; The second jitter signal generating submodule generates the second jitter sub-signal, and inputs the second jitter sub-signal to the second capacitive coupler; The second capacitive coupler couples the analog input signal and the second jitter sub-signal, and the coupled analog input signal is input into the target input buffer through the second input terminal of the target input buffer.

[0012] In some embodiments of the present invention, the compensation module includes a harmonic compensation diode load, and the compensation module performs harmonic compensation on the first signal according to the harmonic coefficient to obtain a second signal, and inputs the second signal to the analog-to-digital converter, including: The compensation module adjusts the harmonic compensation diode load according to the harmonic coefficient.

[0013] In a third aspect, an embodiment of the present invention provides an electronic device, comprising a distortion calibration circuit for analog-to-digital conversion as described in the second aspect above.

[0014] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the distortion calibration method for analog-to-digital conversion as described in the first aspect above.

[0015] The distortion calibration circuit for analog-to-digital conversion according to the embodiment of the present invention has at least the following beneficial effects: a jitter signal generating module, used to generate a jitter signal; a first signal calculating module, wherein the first input end of the first signal calculating module is used to connect an analog input signal, the second input end of the first signal calculating module is connected to the output end of the jitter signal generating module, and the first signal calculating module is used to add the analog input signal and the jitter signal; a target input buffer, wherein the input end of the target input buffer is connected to the output end of the first signal calculating module; and a compensation module, wherein the first input end of the compensation module is connected to the output end of the target input buffer. The output end is connected; an analog-to-digital converter, the input end of the analog-to-digital converter is connected to the output end of the compensation module; a second signal calculation module, the first input end of the second signal calculation module is connected to the output end of the analog-to-digital converter, and the second input end of the second signal calculation module is connected to the output end of the jitter signal generation module, for subtracting the signal output by the analog-to-digital converter from the output result of the jitter signal generation module; a harmonic coefficient generation module, the input end of the harmonic coefficient generation module is connected to the output end of the second signal calculation module, and the output end of the harmonic coefficient generation module is connected to the second input end of the compensation module. By adding a random jitter signal to the input, after passing through the nonlinear system of the target input buffer, the size of the jitter signal is affected by the nonlinear system and becomes nonlinear. At this time, the jitter signal added before is subtracted from the output signal, and the jitter signal affected by the nonlinear system can be obtained. After that, the compensation module is adjusted according to the harmonic coefficient generated by the jitter signal, and the signal distortion caused by the nonlinearity of the target input buffer can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a structural schematic diagram of a distortion calibration circuit for analog-to-digital conversion provided by an embodiment of the present invention; Figure 2 is a schematic structural diagram of a first signal calculation module, a target input buffer and a compensation module provided by an embodiment of the present invention; Figure 3 is a flow chart of a distortion calibration method for analog-to-digital conversion provided by an embodiment of the present invention; Figure 4 It is a sequential change of adding a jitter signal and subtracting a jitter signal in a linear system provided by an embodiment of the present invention; Figure 5 It is a sequential change of adding a jitter signal and subtracting a jitter signal in a nonlinear system provided by an embodiment of the present invention; Reference numerals: jitter signal generating module 100; first signal calculating module 200; target input buffer 300; compensation module 400; analog-to-digital converter 500; second signal calculating module 600; harmonic coefficient generating module 700; first jitter signal generating submodule 121; second jitter signal generating submodule 122; first reference voltage generating module 123; second reference voltage generating module 124; comparator 710; counter 720; accumulator 730; averager 740. DETAILED DESCRIPTION

[0017] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0018] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0019] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0020] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0021] The control method of the embodiment of the present invention is further described below based on the accompanying drawings.

[0022] Reference Figure 1 , Figure 1 A schematic diagram of a distortion calibration circuit for analog-to-digital conversion provided by an embodiment of the present invention, the distortion calibration circuit for analog-to-digital conversion includes but is not limited to: A jitter signal generating module 100, used to generate a jitter signal; A first signal calculation module 200, wherein a first input terminal of the first signal calculation module 200 is used to connect an analog input signal, a second input terminal of the first signal calculation module 200 is connected to an output terminal of the jitter signal generation module 100, and the first signal calculation module 200 is used to add the analog input signal and the jitter signal; A target input buffer 300, an input end of the target input buffer 300 is connected to an output end of the first signal calculation module 200; A compensation module 400, a first input terminal of the compensation module 400 is connected to an output terminal of the target input buffer 300; An analog-to-digital converter 500, wherein an input end of the analog-to-digital converter 500 is connected to an output end of the compensation module 400; A second signal calculation module 600, wherein a first input terminal of the second signal calculation module 600 is connected to an output terminal of the analog-to-digital converter 500, and a second input terminal of the second signal calculation module 600 is connected to an output terminal of the jitter signal generation module 100, and is used to subtract a signal output by the analog-to-digital converter 500 from an output result of the jitter signal generation module 100; The harmonic coefficient generating module 700 has an input end connected to the output end of the second signal calculating module 600 , and an output end of the harmonic coefficient generating module 700 connected to the second input end of the compensation module 400 .

[0023] It should be noted that the reference Figure 1-Figure 2 , the jitter signal generated by the jitter signal generation module 100 is constant in size, but the positive and negative signs are random. The first signal calculation module 200 can be an adder for performing addition operations on the input signals. The added signals are then input together into the target input buffer 300. During this process, the jitter signal and the analog input signal will undergo the same distortion process. The target input buffer 300 has an isolation effect. The first input end of the compensation module 400 is connected to the output end of the target input buffer 300, and the second input end is connected to the output end of the harmonic coefficient generation module 700. The analog-to-digital converter 500 is used to convert the analog signal into a digital signal. The second calculation module can be a subtractor for performing subtraction operations on the signal output by the analog-to-digital converter 500 and the added random jitter signal, which is equivalent to subtracting the random jitter signal added before, so that the jitter signal can be obtained by the nonlinear system, that is, the target input buffer 300. The calculated signal is then input into the harmonic coefficient generation module 700 to generate harmonic coefficients, which is equivalent to converting the impact of the nonlinear system into harmonic coefficients for signal distortion calibration of the model output by the target input buffer 300 .

[0024] In another embodiment, the jitter signal generating module 100 includes: A first jitter signal generating submodule 121, configured to generate a first jitter sub-signal; A second jitter signal generating submodule 122, configured to generate a second jitter sub-signal; The first signal calculation module 200 also includes: A first capacitive coupler, the first capacitive coupler is respectively connected to an output end of the first jitter signal generating submodule 121, an input position of the analog input signal, and a first input end of the target input buffer; The second capacitive coupler is respectively connected to the output end of the second jitter signal generating submodule 122, the input position of the analog input signal, and the second input end of the target input buffer.

[0025] It should be noted that the first jitter sub-signal output by the first jitter signal generating submodule 121 intersects with the analog input signal at the first capacitor coupler, and further, a first reference voltage generating module 123 is also provided at the intersection, and the first reference voltage signal output by the first reference voltage generating module 123 is a DC voltage, which is used to perform a DC bias on the signal at the intersection, and then the signal is input into the target input buffer through the first input end of the target input buffer. Similarly, the second jitter sub-signal output by the second jitter signal generating submodule 122 intersects with the analog input signal at the second capacitor coupler, and further, a second reference voltage generating module 124 is also provided at the intersection, and the second reference voltage signal output by the second reference voltage generating module 124 is a DC voltage, which is used to perform a DC bias on the signal at the intersection, and then the signal is input into the target input buffer through the second input end of the target input buffer.

[0026] In another embodiment, the compensation module 400 includes: a harmonic compensation diode load connected to the target input buffer 300 .

[0027] It should be noted that the compensation module 400 includes an adjustable harmonic compensation diode load, namely HC-DL, which is a diode-connected transistor, and its gate terminal voltage is controlled by a distortion calibration circuit for analog-to-digital conversion. Because the target input buffer 300 includes two MOS tubes, namely corresponding to the two sides of the input terminal, it can be understood that, corresponding to the design of the MOS tube, two harmonic compensation diode loads are also correspondingly provided, and the source and drain of the MOS tube are respectively connected to the harmonic compensation diode load, that is, the target input buffer 300 is connected in parallel with the harmonic compensation diode load.

[0028] In another embodiment, the harmonic coefficient generation module 700 includes: A plurality of comparators 710, wherein an input end of each comparator 710 is respectively connected to an output end of the second signal calculation module 600; A plurality of counters 720, wherein the input end of each counter 720 is respectively connected to the output end of the corresponding comparator 710; A plurality of accumulators 730, wherein an input end of each accumulator 730 is respectively connected to an output end of a corresponding counter 720; The averager 740 and the input ends of the accumulators 730 are respectively connected to the output ends of the accumulators 730 , and the output end of the averager is connected to the input end of the compensation module 400 .

[0029] It should be noted that the multiple comparators 710 in the harmonic coefficient generation module 700 use the same type of comparators 710, the multiple counters 720 also use the same type of counters 720, and the multiple accumulators 730 use the same type of accumulators 730. This is to maintain the uniformity of the processing of the signal output by the second signal calculation module 600.

[0030] Reference Figure 3 , Figure 3 A flowchart of a distortion calibration circuit for analog-to-digital conversion provided by an embodiment of the present invention is provided. Based on the distortion calibration circuit for analog-to-digital conversion, the distortion calibration method for analog-to-digital conversion includes but is not limited to: Step S100, the first signal calculation module 200 performs addition calculation on the analog input signal and the jitter signal to obtain a first signal, and inputs the first signal to the target input buffer 300, wherein the jitter signal is provided by the jitter signal generation module 100; Step S200, the target input buffer 300 isolates the first signal and inputs it to the compensation module 400; Step S300, the compensation module 400 performs harmonic compensation on the first signal according to the harmonic coefficient to obtain a second signal, and inputs the second signal to the analog-to-digital converter 500, and the harmonic coefficient is generated by the harmonic coefficient generation module 700; Step S400, the analog-to-digital converter 500 performs analog-to-digital conversion on the second signal to obtain a target digital signal; Step S500, the second signal calculation module 600 performs a subtraction calculation on the target digital signal and the jitter signal to obtain a third signal, and inputs the third signal to the harmonic coefficient generation module 700; In step S600 , the harmonic coefficient generating module 700 calculates the third signal and the jitter signal, and updates the harmonic coefficient according to the calculation result.

[0031] It should be noted that after the jitter signal generating module 100 generates a random jitter signal, the jitter signal is input into the first signal calculating module 200. The first signal calculating module 200 adds the jitter signal and the analog input signal to obtain a first signal, and then inputs the first signal into the first buffer, and then inputs the first signal into the compensation module 400 through the first buffer. The compensation module 400 performs harmonic compensation on the first signal to obtain a second signal, which is quantized by the analog-to-digital converter 500 and then subtracted from the previously added random jitter signal in the digital domain through the second signal calculating module 600 to obtain a third signal. The harmonic coefficient generating module 700 calculates the third signal, obtains the harmonic coefficient, and then inputs it into the compensation module 400 for adjustment, and then enters the next cycle. The obtained harmonic coefficient is positively correlated with the harmonic size of the uncalibrated output signal.

[0032] In another embodiment, the harmonic coefficient generation module 700 includes an accumulator 730, a plurality of comparators 710, a plurality of counters 720 and a plurality of accumulators 730, each comparator 710 is connected to each counter 720 in one-to-one correspondence, each accumulator 730 is connected to each counter 720 in one-to-one correspondence, an averager 740 is connected to the accumulator 730, and the averager 740 is connected to the compensation module 400, wherein a voltage threshold is preset in the comparator 710, and the voltage threshold in each comparator 710 is different, and the harmonic coefficient generation module 700 calculates the third signal based on a preset harmonic coefficient generation algorithm to obtain a harmonic coefficient, and inputs the harmonic coefficient into the compensation module 400, including: The comparator 710 compares the voltage threshold with the second signal to obtain a comparison result; When the comparison result is less than the absolute value of the voltage threshold, the third signal is assigned a value of 0; When the comparison result is greater than the absolute value of the voltage threshold, the third signal is assigned a value of 1; The counter 720 multiplies the third signal by the jitter signal to obtain a multiplication result; The accumulator 730 adds the multiplication results of the same comparator 710 and the counter 720 to obtain an addition result; The averager averages the addition results output by each accumulator 730 to obtain a harmonic coefficient.

[0033] It should be noted that the second signal will be compared with the voltage thresholds in multiple groups of comparators 710 in turn. For example, if the value range of the second signal is between ±1, the voltage thresholds in different comparators 710 are set to -0.9, 0.8...0.1, 0.2...0.9 respectively, and the second signal is input into different comparison values ​​in turn. If the absolute value of the second signal is less than the voltage threshold corresponding to the comparator 710 for calculation, the third signal is assigned a value of 0. If the absolute value of the second signal is greater than the voltage threshold, the third signal is assigned a value of 1. Each comparator 710 is connected to a counter 720. The third signal output by the comparator 710 is input into the counter 720. The counter 720 multiplies the input third signal and the jitter signal to obtain a multiplication result. For example, if the third signal is 0, the multiplication result is 0. If the third signal is 1, the multiplication result is the size of the jitter signal. Assuming that the entire workflow will be repeated N times, and assuming that there are M comparators 710, M counters 720 and M accumulators 730, the accumulator 730 will add the multiplication results input N times to the harmonic coefficient generation module 700 and processed by the counter 720 and the comparator 710, and input the addition result to the averager 740, then there are M addition results in the averager 740, and at this time, the M average results are averaged to obtain the harmonic coefficient. This ensures that the relevant harmonic coefficients are obtained stably. Such a design can obtain more accurate harmonic coefficients, thereby more finely compensating for higher-order harmonics. Finally, the obtained harmonic coefficients are used to adjust the compensation circuit in the background.

[0034] In another embodiment, the jitter signal generating module includes: a first jitter signal generating submodule 121, used to generate a first jitter sub-signal; a second jitter signal generating submodule 122, used to generate a second jitter sub-signal; the first signal calculating module also includes: a first capacitor coupler, the first capacitor coupler is respectively connected to the output end of the first jitter signal generating submodule 121, the input position of the analog input signal, and the first input end of the target input buffer; a second capacitor coupler, the second capacitor coupler is respectively connected to the output end of the second jitter signal generating submodule 122, the input position of the analog input signal, and the second input end of the target input buffer.

[0035] The first signal calculation module performs an addition calculation on the analog input signal and the jitter signal to obtain a first signal, and inputs the first signal to a target input buffer, including: The first jitter signal generating submodule 121 generates a first jitter sub-signal, and inputs the first jitter sub-signal to the first capacitive coupler; The first capacitive coupler couples the analog input signal with the first jitter sub-signal, and the coupled analog input signal is input into the target input buffer through the first input terminal of the target input buffer; The second jitter signal generating submodule 122 generates a second jitter sub-signal, and inputs the second jitter sub-signal to the second capacitive coupler; The second capacitive coupler couples the analog input signal with the second jitter sub-signal, and the coupled analog input signal is input into the target input buffer through the second input terminal of the target input buffer.

[0036] It should be noted that the first jitter sub-signal output by the first jitter signal generating submodule 121 intersects with the analog input signal at the first capacitor coupler, and further, a first reference voltage generating module 123 is also provided at the intersection, and the first reference voltage signal output by the first reference voltage generating module 123 is a DC voltage, which is used to DC bias the signal at the intersection, and then the signal is input into the target input buffer through the first input end of the target input buffer. It can be understood that in order to make the two input ends of the target input buffer 300 in phase, correspondingly, the second jitter sub-signal output by the second jitter signal generating submodule 122 intersects with the analog input signal at the second capacitor coupler, and further, a second reference voltage generating module 124 is also provided at the intersection, and the second reference voltage signal output by the second reference voltage generating module 124 is a DC voltage, which is used to DC bias the signal at the intersection, and then the signal is input into the target input buffer through the second input end of the target input buffer. That is, two sets of jitter signal generating submodules, capacitor couplers, and reference voltage modules are provided. The first jitter sub-signal and the second jitter sub-signal have the same magnitude.

[0037] In another embodiment, the compensation module 400 includes a harmonic compensation diode load, and the compensation module 400 performs harmonic compensation on the first signal according to the harmonic coefficient to obtain a second signal, and inputs the second signal to the analog-to-digital converter 500, including: The compensation module 400 adjusts the harmonic compensation diode load according to the harmonic coefficient.

[0038] It should be noted that after the harmonic coefficient generation module 700 inputs the harmonic coefficient to the compensation module 400 , the signal distortion caused by the nonlinearity of the target input buffer 300 can be effectively improved by adjusting the harmonic compensation diode load in the compensation module 400 according to the harmonic coefficient.

[0039] The following provides specific embodiments: refer to Figure 4For example, this is a linear system, where the horizontal axis is input and the vertical axis is output. The thinnest line is the general input signal, and the thick dashed line is the input signal with random jitter added. After adding the jitter signal, its output signal increases by Vd. The thick solid line is the same random jitter subtracted from the output. In a linear system, the thick solid line part returns to the position of the thinnest line after the jitter is subtracted.

[0040] refer to Figure 5 , for a nonlinear system that needs to be calibrated, such as Figure 5 , the thinnest line is the input and output curve of the signal, the horizontal axis is the input, and the vertical axis is the output. After adding random jitter, the output signal thick dashed line is not directly translated, but has a certain nonlinear upward offset. The jitter signal directly subtracted from the output part is not affected by nonlinearity, and the thick solid curve is directly translated compared to the thick dashed curve. Through such processing, it can be found that by changing the positive and negative signs of the jitter, the restored thick solid curve is different. For example, as shown in the figure, when the jitter Vd is positive, the restored thick solid curve has the largest nonlinearity when it is close to VFS. It can be imagined that when the jitter Vd is negative, the restored thick solid curve has the largest nonlinearity when it is close to 0. This property of random jitter can be used to evaluate the nonlinear area in different situations. By adding random jitter (constant size, random positive and negative signs) to the input, after passing through the nonlinear system of the input buffer, the size of this jitter is affected by the nonlinear system and becomes nonlinear. At this time, the random jitter added before is subtracted from the output signal, and the influence of the random jitter on the nonlinear system can be obtained.

[0041] An embodiment of the present application also provides an electronic device, comprising the distortion calibration circuit for analog-to-digital conversion as described above.

[0042] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the distortion calibration method for analog-to-digital conversion is implemented.

[0043] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0044] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0045] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions under the shared conditions without violating the spirit of the present invention. These equivalent deformations or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A distortion calibration circuit for analog-to-digital conversion, characterized in that: include: A jitter signal generating module, used for generating a jitter signal; a first signal calculation module, wherein a first input terminal of the first signal calculation module is used to connect an analog input signal, a second input terminal of the first signal calculation module is connected to an output terminal of the jitter signal generation module, and the first signal calculation module is used to add the analog input signal and the jitter signal; a target input buffer, wherein an input end of the target input buffer is connected to an output end of the first signal calculation module; a compensation module, wherein a first input terminal of the compensation module is connected to an output terminal of the target input buffer; an analog-to-digital converter, wherein an input end of the analog-to-digital converter is connected to an output end of the compensation module; a second signal calculation module, wherein a first input terminal of the second signal calculation module is connected to the output terminal of the analog-to-digital converter, and a second input terminal of the second signal calculation module is connected to the output terminal of the jitter signal generation module, and is used for subtracting the signal output by the analog-to-digital converter from the output result of the jitter signal generation module; A harmonic coefficient generating module, wherein the input end of the harmonic coefficient generating module is connected to the output end of the second signal calculating module, and the output end of the harmonic coefficient generating module is connected to the second input end of the compensation module.

2. The distortion calibration circuit for analog-to-digital conversion according to claim 1, characterized in that: The jitter signal generating module comprises: A first jitter signal generating submodule, used to generate a first jitter sub-signal; A second jitter signal generating submodule, used to generate a second jitter sub-signal; The first signal calculation module also includes: a first capacitive coupler, wherein the first capacitive coupler is respectively connected to an output end of the first jitter signal generating submodule, an input position of the analog input signal, and a first input end of the target input buffer; A second capacitive coupler, wherein the second capacitive coupler is respectively connected to an output end of the second jitter signal generating submodule, an input position of the analog input signal, and a second input end of the target input buffer.

3. The distortion calibration circuit for analog-to-digital conversion according to claim 1, characterized in that: The compensation module includes: a harmonic compensation diode load, and the harmonic compensation diode load is connected to the target input buffer.

4. The distortion calibration circuit for analog-to-digital conversion according to claim 2, characterized in that: The harmonic coefficient generation module comprises: A plurality of comparators, wherein an input end of each of the comparators is respectively connected to an output end of the second signal calculation module; A plurality of counters, wherein the input end of each counter is respectively connected to the output end of the corresponding comparator; A plurality of accumulators, wherein the input end of each accumulator is respectively connected to the output end of the corresponding counter; The averager has an input end connected to the output end of each accumulator, and the output end of the averager is connected to the input end of the compensation module.

5. A distortion calibration method for analog-to-digital conversion, characterized in that: Based on the distortion calibration circuit for analog-to-digital conversion according to any one of claims 1 to 4, the method comprises: The first signal calculation module performs an addition calculation on the analog input signal and the jitter signal to obtain a first signal, and inputs the first signal to a target input buffer, wherein the jitter signal is provided by the jitter signal generation module; The target input buffer isolates and processes the first signal and inputs the first signal into the compensation module; The compensation module performs harmonic compensation on the first signal according to the harmonic coefficient to obtain a second signal, and inputs the second signal into an analog-to-digital converter, wherein the harmonic coefficient is generated by the harmonic coefficient generation module; The analog-to-digital converter performs analog-to-digital conversion on the second signal to obtain a target digital signal; A second signal calculation module performs a subtraction calculation on the target digital signal and the jitter signal to obtain a third signal, and inputs the third signal to the harmonic coefficient generation module; The harmonic coefficient generating module calculates the third signal and the jitter signal, and updates the harmonic coefficient according to the calculation result.

6. The distortion calibration method for analog-to-digital conversion according to claim 5, characterized in that: The harmonic coefficient generation module includes a plurality of comparators, a plurality of counters, a plurality of accumulators and an averager, each of the comparators is connected to each of the counters in a one-to-one correspondence, each of the accumulators is connected to each of the counters in a one-to-one correspondence, the averager is connected to the accumulator, and the averager is connected to the compensation module, wherein a voltage threshold is preset in the comparator, and the voltage threshold in each comparator is different, the harmonic coefficient generation module calculates the third signal based on a preset harmonic coefficient generation algorithm to obtain a harmonic coefficient, and inputs the harmonic coefficient into the compensation module, including: The comparator compares the voltage threshold with the second signal to obtain a comparison result; When the comparison result is less than the absolute value of the voltage threshold, the third signal is assigned a value of 0; When the comparison result is greater than the absolute value of the voltage threshold, the third signal is assigned a value of 1; The counter multiplies the third signal by the jitter signal to obtain a multiplication result; The accumulator adds the multiplication results passed through the same comparator and counter to obtain an addition result; The averager averages the addition results output by each of the accumulators to obtain the harmonic coefficient.

7. The distortion calibration method for analog-to-digital conversion according to claim 5, characterized in that: The jitter signal generation module includes: a first jitter signal generation submodule, used to generate a first jitter sub-signal; a second jitter signal generation submodule, used to generate a second jitter sub-signal; the first signal calculation module also includes: a first capacitive coupler, the first capacitive coupler is respectively connected to the output end of the first jitter signal generation submodule, the input position of the analog input signal, and the first input end of the target input buffer; a second capacitive coupler, the second capacitive coupler is respectively connected to the output end of the second jitter signal generation submodule, the input position of the analog input signal, and the second input end of the target input buffer; The first signal calculation module performs an addition calculation on the analog input signal and the jitter signal to obtain a first signal, and inputs the first signal to a target input buffer, including: The first jitter signal generating submodule generates the first jitter sub-signal, and inputs the first jitter sub-signal to the first capacitive coupler; The first capacitive coupler couples the analog input signal with the first jitter sub-signal, and the coupled analog input signal is input into the target input buffer through the first input terminal of the target input buffer; The second jitter signal generating submodule generates the second jitter sub-signal, and inputs the second jitter sub-signal to the second capacitive coupler; The second capacitive coupler couples the analog input signal and the second jitter sub-signal, and the coupled analog input signal is input into the target input buffer through the second input terminal of the target input buffer.

8. The distortion calibration method for analog-to-digital conversion according to claim 5, characterized in that: The compensation module includes a harmonic compensation diode load, and the compensation module performs harmonic compensation on the first signal according to the harmonic coefficient to obtain a second signal, and inputs the second signal to the analog-to-digital converter, including: The compensation module adjusts the harmonic compensation diode load according to the harmonic coefficient.

9. An electronic device, characterized in that: A distortion calibration circuit for analog-to-digital conversion comprising any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the distortion calibration method for analog-to-digital conversion according to any one of claims 5 to 8.

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