Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the semiconductor device comprises a plurality of storage units which are distributed in different layers, are stacked in a direction perpendicular to a substrate, and are periodically distributed; each layer comprises a plurality of columns of storage units; and the relaxation buffer layer is positioned between the substrate and the storage unit. The semiconductor device provided by the embodiment of the invention can be provided with more layers of stacked storage units, so that the storage density of the semiconductor device can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to but are not limited to the field of design and manufacturing of semiconductor devices, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a common system memory widely used in personal computers, laptops and consumer electronics. Traditionally known DRAM has multiple repeated "memory cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many storage units as possible on a limited substrate, and the architecture and ideas of 3D DRAM came into being. Among them, using silicon / silicon germanium (Si / SiGe) stacking as a channel layer and sacrificial layer is a solution to realize 3D DRAM devices.

[0004] Since the lattice mismatch between Si and Ge is as high as 4%, the SiGe layer epitaxially grown on the Si substrate will produce strain due to the lattice mismatch. The strain will be released after the Si / SiGe multilayer stacking, resulting in an increase in defects in the channel formed by the Si layer, causing device degradation and seriously affecting the performance of DRAM. Summary of the invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0006] The embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and an electronic device. The semiconductor device can have more layers of stacked storage units, thereby improving the storage density of the semiconductor device.

[0007] An embodiment of the present application provides a semiconductor device, the semiconductor device comprising:

[0008] A plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to the substrate and distributed periodically; each layer includes a plurality of columns of memory cells;

[0009] A relaxed buffer layer is located between the substrate and the memory cell.

[0010] In an exemplary embodiment of the present application, a lattice constant of the relaxed buffer layer in a relaxed state is different from a lattice constant of the substrate.

[0011] In an exemplary embodiment of the present application, the relaxed buffer layer may include a first relaxed buffer layer and a second relaxed buffer layer, the first relaxed buffer layer is located between the substrate and the second relaxed buffer layer, and the second relaxed buffer layer is located between the first relaxed buffer layer and the memory cell;

[0012] Along a direction away from the substrate, the lattice constant of the first relaxed buffer layer changes, and the lattice constant of the second relaxed buffer layer remains unchanged;

[0013] Dislocations are present in both the first relaxed buffer layer and the second relaxed buffer layer, and a dislocation density in the first relaxed buffer layer is greater than a dislocation density in the second relaxed buffer layer.

[0014] In an exemplary embodiment of the present application, the first relaxed buffer layer is a film layer in which strain is completely relaxed at least in a region on a side away from the substrate.

[0015] In an exemplary embodiment of the present application, the material of the substrate may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide and indium phosphide.

[0016] In an exemplary embodiment of the present application, the material of the relaxed buffer layer may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.

[0017] In an exemplary embodiment of the present application, the memory cell includes a transistor, and the transistor includes a semiconductor column; the main material of the semiconductor column can be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.

[0018] In an exemplary embodiment of the present application, the material of the substrate and the main material of the semiconductor pillar may both be silicon, and the material of the relaxed buffer layer may be silicon germanium.

[0019] In an exemplary embodiment of the present application, the material of the substrate may be silicon, the material of the relaxed buffer layer may be selected from any one or more of gallium arsenide, aluminum gallium arsenide and indium gallium arsenide, and the main material of the semiconductor column may be gallium arsenide or indium gallium arsenic.

[0020] In an exemplary embodiment of the present application, the semiconductor device may further include an isolation layer, wherein the isolation layer is located between the relaxed buffer layer and the memory cell and is configured to isolate the relaxed buffer layer from the memory cell.

[0021] In an exemplary embodiment of the present application, the transistor may further include a gate electrode surrounding at least a portion of a sidewall of the semiconductor pillar.

[0022] In an exemplary embodiment of the present application, the semiconductor pillar may extend along a first direction parallel to the substrate.

[0023] In an exemplary embodiment of the present application, the memory cell may further include a capacitor connected to the transistor in the same memory cell.

[0024] In an exemplary embodiment of the present application, the semiconductor device may further include: a plurality of bit lines extending in a direction perpendicular to the substrate.

[0025] In an exemplary embodiment of the present application, the transistors of two columns of memory cells that are located in different layers and adjacent to each other along the first direction may be connected to the same bit line.

[0026] In an exemplary embodiment of the present application, the semiconductor device may further include: a plurality of word lines extending along a second direction parallel to the substrate.

[0027] In an exemplary embodiment of the present application, the transistors of a column of the memory cells located in the same layer and arranged along the second direction may be connected to the same word line.

[0028] The embodiment of the present application also provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises a plurality of memory cells and a relaxed buffer layer; the plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to a substrate and distributed periodically, and the memory cells comprise transistors;

[0029] The method for manufacturing the semiconductor device comprises:

[0030] forming the relaxed buffer layer on the substrate, and making the relaxed buffer layer a relaxed film layer;

[0031] The plurality of memory cells are formed on a side of the relaxed buffer layer away from the substrate.

[0032] In an exemplary embodiment of the present application, forming the relaxed buffer layer on the substrate and making the relaxed buffer layer a relaxed film layer may include:

[0033] A first relaxed buffer layer is grown on one side of the substrate by using an epitaxial process; wherein the lattice constant of the first relaxed buffer layer changes along a direction away from the substrate, dislocations are present in the first relaxed buffer layer, and a region of the first relaxed buffer layer on a side away from the substrate is a film layer in which strain is completely relaxed;

[0034] A second relaxed buffer layer is grown on a side of the first relaxed buffer layer away from the substrate using an epitaxial process, and the lattice structure of the second relaxed buffer layer is consistent with the lattice structure of the first relaxed buffer layer away from the substrate; the first relaxed buffer layer and the second relaxed buffer layer constitute the relaxed buffer layer.

[0035] In an exemplary embodiment of the present application, forming the plurality of memory cells on a side of the relaxed buffer layer away from the substrate may include:

[0036] forming an isolation layer on a side of the relaxed buffer layer away from the substrate by using an epitaxial process;

[0037] Semiconductor layers and sacrificial layers are alternately grown on a side of the isolation layer away from the substrate by using an epitaxial process, so as to obtain a stacked structure consisting of alternating semiconductor layers and sacrificial layers.

[0038] In an exemplary embodiment of the present application, the lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate, and the lattice constant of the relaxed buffer layer in a relaxed state is between the lattice constants of the sacrificial layer and the semiconductor layer.

[0039] In an exemplary embodiment of the present application, forming the plurality of storage units may further include: after obtaining the stacking structure,

[0040] A patterning process is performed on the semiconductor layer in the stacked structure so that the semiconductor layer forms a semiconductor column of the transistor, and a gate electrode is formed on at least a portion of the sidewall of the semiconductor column. The semiconductor column and the gate electrode constitute the transistor.

[0041] In an exemplary embodiment of the present application, the method for manufacturing the semiconductor device may further include: forming a capacitor connected to the transistor, wherein the transistor and the capacitor connected thereto constitute the storage unit.

[0042] An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the above embodiment of the present application.

[0043] The semiconductor device and the manufacturing method thereof of the embodiments of the present application introduce a relaxed buffer layer between the substrate and the storage unit, which can reduce the lattice mismatch between the substrate and the epitaxial stack structure (such as the Si / SiGe stack structure) during the manufacturing process of the semiconductor device, thereby reducing the strain accumulation in the epitaxial stack structure. Under the same conditions, the maximum number of layers that can be stacked in the epitaxial stack structure can be increased.

[0044] In addition, the introduction of the relaxed buffer layer can increase the tensile strain in the channel region of the transistor, which can improve the electron mobility in the channel region and further increase the operating speed of the transistor (eg, switching speed).

[0045] Moreover, the introduction of the relaxed buffer layer can reduce the strain accumulation of the epitaxial sacrificial layer (for example, the SiGe epitaxial sacrificial layer) in the epitaxial stack structure during the manufacturing process of the semiconductor device, so that under the same conditions, the critical thickness of the epitaxial sacrificial layer increases, thereby obtaining a thicker epitaxial sacrificial layer, which can reduce the process difficulty of 3D semiconductor device processing.

[0046] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The objects and advantages of the present application can be realized and obtained by the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0048] Figure 1A A schematic longitudinal cross-sectional view of a semiconductor device provided for an exemplary embodiment of the present application;

[0049] Figure 1B for Figure 1A A top view of the semiconductor device shown;

[0050] Figure 2 A process flow chart of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application;

[0051] Figure 3A A schematic longitudinal cross-sectional view of a semiconductor device after forming a first relaxed buffer layer provided by an exemplary embodiment of the present application;

[0052] Figure 3B for Figure 3A A top view of the semiconductor device shown;

[0053] Figure 4 A schematic longitudinal cross-sectional view of a semiconductor device provided in an exemplary embodiment of the present application after CMP is performed on the surface of a first relaxed buffer layer;

[0054] Figure 5A A schematic longitudinal cross-sectional view of a semiconductor device after forming a second relaxed buffer layer provided by an exemplary embodiment of the present application;

[0055] Figure 5B for Figure 5AA top view of the semiconductor device shown;

[0056] Fig. 6A A schematic longitudinal cross-sectional view of a semiconductor device after forming a stacked structure provided by an exemplary embodiment of the present application;

[0057] Figure 6B for Fig. 6A A top view of the semiconductor device shown;

[0058] Fig. 7A A schematic longitudinal cross-sectional view of a semiconductor device after forming a semiconductor column provided by an exemplary embodiment of the present application;

[0059] Figure 7B for Fig. 7A A top view of the semiconductor device shown;

[0060] Fig. 8A A schematic longitudinal cross-sectional view of a semiconductor device after a bit line is formed, provided as an exemplary embodiment of the present application;

[0061] Figure 8B for Fig. 8A A top view of the semiconductor device shown;

[0062] Fig. 9A A schematic longitudinal cross-sectional view of a semiconductor device after removing a sacrificial layer provided by an exemplary embodiment of the present application;

[0063] Fig. 9B for Fig. 9A A top view of the semiconductor device shown;

[0064] Fig. 10A A schematic longitudinal cross-sectional view of a semiconductor device after word lines are formed provided by an exemplary embodiment of the present application;

[0065] Fig. 10B for Fig. 10A A top view of the semiconductor device shown;

[0066] The meanings of the symbols in the accompanying drawings are:

[0067] 10-substrate; 21-first relaxed buffer layer; 22-second relaxed buffer layer; 30-isolation layer; 31-first insulating layer; 32-second insulating layer; 40-semiconductor layer; 41-semiconductor column; 42-first electrode region; 43-channel region; 44-second electrode region; 45-third electrode region; 50-sacrificial layer; 61-first trench; 62-second trench; 70-bit line; 80-word line; 81-gate insulating layer; 82-gate electrode; 90-transistor; 100-capacitor; 101-dielectric layer; 102-fourth electrode layer; 110-storage unit. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0069] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values ​​shown in the drawings.

[0070] The ordinal numbers such as "first" and "second" in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0071] In this application, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0072] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0073] In this application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, a channel region refers to a region where current mainly flows.

[0074] In the present application, the first electrode region may be a drain electrode and the second electrode region may be a source electrode, or the first electrode region may be a source electrode and the second electrode region may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present application, unless otherwise specified, the "source electrode" and the "drain electrode" may be interchanged.

[0075] In the present disclosure, "electrical connection" or "connection" includes situations where constituent elements are connected together through an element having some electrical function, such as electrical signal connection (coupled connection, such as coupled to), or physical direct connection. There is no particular limitation on "element having some electrical function" as long as it can transfer electrical signals between connected constituent elements. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0076] In this application, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0077] In some embodiments of the present application, "film" and "layer" can be interchanged. For example, "semiconductor layer" can sometimes be replaced by "semiconductor film". Similarly, "insulating film" can sometimes be replaced by "insulating layer".

[0078] The term "A and B are arranged in the same layer" in this application means that A and B are distributed on the same horizontal plane, or although not on the same horizontal plane, they are in different areas of the same support surface. In one embodiment, A and B are formed simultaneously by subjecting the same film layer to the same patterning process.

[0079] In the embodiments of the present application, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned on a film layer to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be exactly the same.

[0080] Epitaxially grown Si on Si substrate 1-x Ge xThe layer will produce strain due to lattice mismatch. When the strain exceeds the critical value, dislocation will occur, causing strain relaxation. With the increase of Ge concentration, the critical thickness decreases exponentially. According to theoretical calculations, Si is grown directly on Si substrate. 0.8 Ge 0.2 The critical thickness of the layer relaxation is about 15nm, the critical thickness of the metastable state is about 250nm, and the growth of Si 0.7 Ge 0.3 The critical thickness for layer relaxation is only about 8 nm, and the critical thickness for metastable state is about 100 nm.

[0081] In the process of realizing 3D DRAM devices with Si / SiGe stacking, due to the requirements of the selective etching process of SiGe and Si, the Ge concentration cannot be reduced indefinitely. Therefore, in order to obtain more stacking layers and achieve higher integration, it is necessary to seek new methods to achieve more layers of Si / Si while ensuring the quality of the stacking crystal. 1-x Ge x Laminated structure.

[0082] An embodiment of the present application provides a semiconductor device.

[0083] Figure 1A A schematic longitudinal cross-sectional view of a semiconductor device provided for an exemplary embodiment of the present application; Figure 1B for Figure 1A A top view of the semiconductor device shown.

[0084] like Figure 1A and Figure 1B As shown, the semiconductor device comprises:

[0085] A plurality of memory cells 110 are distributed in different layers, stacked in a direction perpendicular to the substrate 10 and distributed periodically; each layer includes a plurality of columns of memory cells 110, the memory cells 110 include transistors 90, and the transistors 90 include semiconductor pillars 41;

[0086] The relaxed buffer layer 20 is a relaxed film layer and is located between the substrate 10 and the memory cell 110 .

[0087] The semiconductor device described in the embodiment of the present application introduces a relaxed buffer layer between the substrate and the storage unit, which can reduce the lattice mismatch between the substrate and the epitaxial stack structure (such as the Si / SiGe stack structure) during the manufacturing process of the semiconductor device, thereby reducing the strain accumulation in the epitaxial stack structure. Under the same conditions, the number of layers that can be stacked in the epitaxial stack structure can be increased.

[0088] In addition, the introduction of the relaxed buffer layer can increase the tensile strain in the channel region of the transistor, which can improve the electron mobility in the channel region and further increase the operating speed of the transistor (eg, switching speed).

[0089] Moreover, the introduction of the relaxed buffer layer can reduce the strain accumulation of the epitaxial sacrificial layer (for example, the SiGe epitaxial sacrificial layer) in the epitaxial stack structure during the manufacturing process of the semiconductor device, so that under the same conditions, the critical thickness of the epitaxial sacrificial layer increases, thereby obtaining a thicker epitaxial sacrificial layer, which can reduce the process difficulty of 3D semiconductor device processing.

[0090] In an exemplary embodiment of the present application, the semiconductor pillars 41 of the transistors of the plurality of memory cells 110 located in the same layer may be formed by the same semiconductor layer 40 ;

[0091] The semiconductor layer 40 and the relaxed buffer layer 20 are both epitaxial layers grown epitaxially on the substrate.

[0092] In an exemplary embodiment of the present application, the lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate. For example, if the material of the substrate is silicon and the material of the relaxed buffer layer is silicon germanium, the lattice constant of the relaxed buffer layer in a relaxed state is greater than the lattice constant of the substrate; if the material of the substrate is germanium and the material of the relaxed buffer layer is silicon, the lattice constant of the relaxed buffer layer in a relaxed state is less than the lattice constant of the substrate.

[0093] In an exemplary embodiment of the present application, Figure 1A As shown, the relaxed buffer layer 20 may include a first relaxed buffer layer 21 and a second relaxed buffer layer 22, the first relaxed buffer layer 21 is located between the substrate and the second relaxed buffer layer 22, and the second relaxed buffer layer 22 is located between the first relaxed buffer layer 21 and the memory cell 110;

[0094] Along the direction from the substrate 10 to the second relaxed buffer layer 22, the lattice constant of the first relaxed buffer layer 21 changes, and the lattice constant of the second relaxed buffer layer 22 remains unchanged;

[0095] Both the first relaxed buffer layer 21 and the second relaxed buffer layer 22 have dislocations therein, and the dislocation density in the first relaxed buffer layer 21 is greater than the dislocation density in the second relaxed buffer layer 22 .

[0096] In an exemplary embodiment of the present application, the first relaxed buffer layer is a film layer in which strain is completely relaxed at least in a region on a side away from the substrate.

[0097] In an exemplary embodiment of the present application, the material of the substrate may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide and indium phosphide.

[0098] In an exemplary embodiment of the present application, the material of the relaxed buffer layer may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.

[0099] In an exemplary embodiment of the present application, the main material of the semiconductor pillar may be selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.

[0100] In an exemplary embodiment of the present application, the material of the substrate and the main material of the semiconductor pillar may both be silicon, and the material of the relaxed buffer layer may be silicon germanium.

[0101] In an exemplary embodiment of the present application, the material of the substrate may be silicon, the material of the relaxed buffer layer may be selected from any one or two of gallium arsenide, aluminum gallium arsenide and indium gallium arsenide, and the main material of the semiconductor column may be gallium arsenide or indium gallium arsenic.

[0102] In an exemplary embodiment of the present application, the semiconductor device may further include an isolation layer 30, which is located between the relaxed buffer layer and the memory cell and is configured to isolate the relaxed buffer layer from the memory cell. In the semiconductor device shown in FIG1 , a first insulating layer 31 is used as the isolation layer 30.

[0103] In an exemplary embodiment of the present application, Figure 1A As shown, the transistor 90 may further include a gate electrode 82 , which surrounds at least a portion of a sidewall of the semiconductor pillar 41 .

[0104] In an exemplary embodiment of the present application, Figure 1A As shown, the transistor 90 includes a first electrode region 42 , a channel region 43 , and a second electrode region 44 in sequence, and the gate electrode 82 surrounds at least a portion of the sidewall of the channel region 43 .

[0105] Here, surrounding can be understood as partial surrounding or full surrounding. In some embodiments, the surrounding can be full surrounding, that is, the entire side wall of the channel region is surrounded by the gate electrode, and the cross-section of the gate electrode after surrounding is a closed ring. The cross-section is intercepted along a direction perpendicular to the substrate and parallel to the second direction. For example, in some embodiments, the surrounding can be partial surrounding, that is, part of the side wall of the channel region is surrounded by the gate electrode, and the cross-section after surrounding is not closed, but presents a ring shape. For example, a ring with an opening or two independent semiconductor layers. For example, the opposite side surfaces of the channel region are surrounded by the gate electrode, and the cross-section of the gate electrode is a ring with two openings.

[0106] In an exemplary embodiment of the present application, the semiconductor pillar 41 may extend along a first direction parallel to the substrate 10. The first direction may be as follows: Figure 1A and Figure 1B The X direction is shown.

[0107] In an exemplary embodiment of the present application, Figure 1A As shown, the memory cell 110 may further include a capacitor 100 , which is connected to the transistor 90 in the same memory cell 110 .

[0108] In an exemplary embodiment of the present application, Figure 1A and Figure 1B As shown, the semiconductor device may further include: a plurality of bit lines 70 extending in a direction perpendicular to the substrate 10. The direction perpendicular to the substrate 10 may be as follows: Figure 1A The Z direction is shown.

[0109] In an exemplary embodiment of the present application, Figure 1A As shown, the transistors 90 of two columns of memory cells 110 located in different layers and adjacent to each other along the first direction may be connected to the same bit line 70 .

[0110] In an exemplary embodiment of the present application, Figure 1A and Figure 1B As shown, the semiconductor device may further include: a plurality of word lines 80 extending along a second direction parallel to the substrate 10. The second direction may be as follows: Figure 1B Y direction shown.

[0111] In an exemplary embodiment of the present application, Figure 1B As shown, the transistors 90 of a column of memory cells 110 located in the same layer and arranged along the second direction may be connected to the same word line 80 .

[0112] The semiconductor layer can be understood as semiconductor material, where its shape and structure are not emphasized but only its function.

[0113] In the present application, spacing can be understood as being separated, and can be achieved by a physical structural disconnection or an electrical characteristic disconnection. For example, the semiconductor layer between the effective channels corresponding to the two transistors is modified to achieve insulation to achieve electrical spacing between the two channels.

[0114] In an exemplary embodiment of the present application, the electrode material of the gate electrode may be any one or more of the following different types of materials:

[0115] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0116] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0117] Of course, it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0118] In an exemplary embodiment of the present application, the material of the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0119] Low-K materials, such as silicon oxide.

[0120] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. may be included. Exemplarily, for example, at least one of the following may be included but is not limited to: high-K materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2).

[0121] The above-mentioned memory cell may be a memory cell including a transistor, wherein the transistor may be an access transistor, and the memory cell may further include other components, such as a capacitor in a 1T1C memory cell, or a read transistor and a storage node in a 2T0C memory cell.

[0122] In an exemplary embodiment of the present application, the material of the dielectric layer may be silicon oxide or a High-K dielectric material, that is, a dielectric material with a dielectric constant K≥3.9. The High-K dielectric material may include but is not limited to at least one of the following: aluminum oxide (Al2O3) and hafnium oxide.

[0123] In an exemplary embodiment of the present application, the semiconductor device may be a 3D memory, for example, a 3D DRAM or the like. The 3D memory may be a 1T1C or 2T (including a read transistor and a write transistor) structure.

[0124] An embodiment of the present application also provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a plurality of memory cells and a relaxed buffer layer; the plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to a substrate and distributed periodically, and the memory cells include transistors.

[0125] The semiconductor device provided in the above embodiment of the present application can be obtained through the manufacturing method.

[0126] Figure 2 A process flow chart of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application.

[0127] like Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0128] forming the relaxed buffer layer on the substrate, and making the relaxed buffer layer a relaxed film layer;

[0129] The plurality of memory cells are formed on a side of the relaxed buffer layer away from the substrate.

[0130] The manufacturing method of the semiconductor device described in the embodiment of the present application introduces a relaxed buffer layer between the substrate and the storage unit, which can reduce the lattice mismatch between the substrate and the epitaxial stack structure (such as the Si / SiGe stack structure) during the manufacturing process of the semiconductor device, thereby reducing the strain accumulation in the epitaxial stack structure. Under the same conditions, the number of layers that can be stacked in the epitaxial stack structure can be increased.

[0131] In addition, the introduction of the relaxed buffer layer can increase the tensile strain in the channel region of the transistor, which can improve the electron mobility in the channel region and further increase the operating speed of the transistor (eg, switching speed).

[0132] Moreover, the introduction of the relaxed buffer layer can reduce the strain accumulation of the epitaxial sacrificial layer (for example, the SiGe epitaxial sacrificial layer) in the epitaxial stack structure during the manufacturing process of the semiconductor device, so that under the same conditions, the critical thickness of the epitaxial sacrificial layer increases, thereby obtaining a thicker epitaxial sacrificial layer, which can reduce the process difficulty of 3D semiconductor device processing.

[0133] In an exemplary embodiment of the present application, forming the relaxed buffer layer on the substrate and making the relaxed buffer layer a relaxed film layer may include:

[0134] A first relaxed buffer layer is grown on one side of the substrate by using an epitaxial process; wherein, along the direction from the substrate to the second relaxed buffer layer, the lattice constant of the first relaxed buffer layer is changed, dislocations are present in the first relaxed buffer layer, and a region of the first relaxed buffer layer on a side away from the substrate is a film layer with completely relaxed strain;

[0135] A second relaxed buffer layer is grown on a side of the first relaxed buffer layer away from the substrate using an epitaxial process, and the lattice structure of the second relaxed buffer layer is consistent with the lattice structure of the first relaxed buffer layer away from the substrate; the first relaxed buffer layer and the second relaxed buffer layer constitute the relaxed buffer layer.

[0136] In an exemplary embodiment of the present application, forming the plurality of memory cells on a side of the relaxed buffer layer away from the substrate may include:

[0137] forming an isolation layer on a side of the relaxed buffer layer away from the substrate by using an epitaxial process;

[0138] Semiconductor layers and sacrificial layers are alternately grown on a side of the isolation layer away from the substrate by using an epitaxial process, so as to obtain a stacked structure consisting of alternating semiconductor layers and sacrificial layers.

[0139] In an exemplary embodiment of the present application, the lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate, and the lattice constant of the relaxed buffer layer in a relaxed state is between the lattice constants of the sacrificial layer and the semiconductor layer.

[0140] In an exemplary embodiment of the present application, forming the plurality of storage units may further include: after obtaining the stacking structure,

[0141] A patterning process is performed on the semiconductor layer in the stacked structure so that the semiconductor layer forms a semiconductor column of the transistor, and a gate electrode is formed on at least a portion of the sidewall of the semiconductor column. The semiconductor column and the gate electrode constitute the transistor.

[0142] In an exemplary embodiment of the present application, the method for manufacturing the semiconductor device may further include: forming a capacitor connected to the transistor, wherein the transistor and the capacitor connected thereto constitute the storage unit.

[0143] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology. The "photolithography process" mentioned in this embodiment includes coating of film layers, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.

[0144] Figure 3A A schematic longitudinal cross-sectional view of a semiconductor device after forming a first relaxed buffer layer provided by an exemplary embodiment of the present application; Figure 3B for Figure 3A A top view of the semiconductor device shown; Figure 4 A schematic longitudinal cross-sectional view of a semiconductor device provided in an exemplary embodiment of the present application after CMP is performed on the surface of a first relaxed buffer layer; Figure 5A A schematic longitudinal cross-sectional view of a semiconductor device after forming a second relaxed buffer layer provided by an exemplary embodiment of the present application; Figure 5B for Figure 5A A top view of the semiconductor device shown; Fig. 6A A schematic longitudinal cross-sectional view of a semiconductor device after forming a stacked structure provided by an exemplary embodiment of the present application; Figure 6B for Fig. 6A A top view of the semiconductor device shown; Fig. 7A A schematic longitudinal cross-sectional view of a semiconductor device after forming a semiconductor column provided by an exemplary embodiment of the present application; Figure 7B for Fig. 7A A top view of the semiconductor device shown; Fig. 8A A schematic longitudinal cross-sectional view of a semiconductor device after a bit line is formed, provided as an exemplary embodiment of the present application; Figure 8B for Fig. 8A A top view of the semiconductor device shown; Fig. 9A A schematic longitudinal cross-sectional view of a semiconductor device after removing a sacrificial layer provided by an exemplary embodiment of the present application; Fig. 9B for Fig. 9A A top view of the semiconductor device shown; Fig. 10A A schematic longitudinal cross-sectional view of a semiconductor device after word lines are formed provided by an exemplary embodiment of the present application; Fig. 10B for Fig. 10A A top view of the semiconductor device shown.

[0145] like FIG. 3A to FIG. 10B and Figure 1A and Figure 1B As shown, in an exemplary embodiment of the present application, the method for manufacturing the semiconductor device may include the following process.

[0146] S10 : providing a substrate 10 , and epitaxially growing a first relaxed buffer layer 21 on the substrate 10 .

[0147] Exemplarily, step S10 may include:

[0148] S11: providing a substrate 10, and performing surface treatment on the substrate 10, including but not limited to: baking the water vapor on the surface of the substrate 10 at a low temperature, and then heating it to a high temperature and removing impurity elements such as C and O on the surface of the substrate 10 in a H2 atmosphere, so that the surface of the substrate 10 presents a clean and fresh Si atomic layer;

[0149] S12: epitaxially growing a first relaxed buffer layer 21 on the surface of the surface treated substrate 10, comprising: firstly, at a certain temperature T1 (for example, T1<600°C), using polycarbonate active silicon dioxide (DCS) and germanium (GeH4) as precursors to grow Si with a certain thickness t1 (for example, t1>10nm); 1-y Ge y , then raise the temperature to T2 (for example, T1≤T2≤850℃) and grow Si with a certain thickness t2 (for example, t2>100nm) 1-y Ge y , and then annealing is performed at T2 to make Si 1- y Ge y The Si on the surface away from the substrate and the nearby surface 1-y Ge y The lattice constant of the film is close to or reaches that of crystalline Si 1-y Ge y Lattice constant, i.e. Si 1-y Ge y Surface Si 1-y Ge y The film is a film layer in which the strain is completely relaxed, and a first relaxed buffer layer 21 is obtained, such as Figure 3A and Figure 3B As shown; wherein, along the direction away from the substrate 10, the lattice constant of the first relaxed buffer layer 21 is changed until the surface away from the substrate side and the Si near the surface 1-y Ge y The lattice constant of the film is close to or reaches that of crystalline Si 1-y Ge y Lattice constant.

[0150] Strain relaxation will cause the roughness of the film surface to increase, such as Figure 3A As shown, the surface of the first relaxed buffer layer 21 has many protrusions. In this embodiment, the protrusions can be as high as tens of nanometers or even higher. In addition, the cross-sectional TEM image of the slice shows that the Si / Si 1-y Ge y A large number of dislocations (not shown) can be observed on the interface, which are gradually suppressed during the film growth process. The threading dislocation density on the surface of the first relaxed buffer layer 21 is about 1×10 6 Pieces / cm 2 Up to 5×10 7 Pieces / cm 2 .

[0151] S20: performing a planarization process on the surface of the first relaxed buffer layer 21 .

[0152] Exemplarily, step S20 may include:

[0153] S21: grinding and polishing the surface of the first relaxed buffer layer 21 by a chemical mechanical polishing (CMP) process, wherein the height of the protrusions on the surface of the first relaxed buffer layer 21 can be reduced to within a few nanometers after grinding and polishing, for example, the surface roughness (RMS) of the surface of the first relaxed buffer layer 21 is less than 2 nm;

[0154] S22: Using organic reagents and inorganic reagents to repeatedly clean the surface of the first relaxed buffer layer 21 after grinding and polishing, the cleaned first relaxed buffer layer 21 is as follows: Figure 4 shown.

[0155] S30 : epitaxially growing a second relaxed buffer layer 22 on a side of the first relaxed buffer layer 21 away from the substrate 10 .

[0156] Exemplarily, step S30 may include: epitaxially growing Si with a certain thickness t3 (for example, t3 ≥ 10 nm) at a certain temperature T3 (T3 ≤ T2). 1-y Ge y layer, and make the Si 1-y Ge y The first relaxed buffer layer 21 is completely relaxed according to the surface of the Si 1-y Ge y Lattice growth (i.e. unstrained Si 1-y Ge y layer), and obtain a second relaxed buffer layer 22, such as Figure 5A and Figure 5B As shown; wherein, the dislocation density in the second relaxed buffer layer 22 is significantly smaller than the dislocation density in the first relaxed buffer layer 21.

[0157] S40: epitaxially growing a first insulating layer 31 on a side of the second relaxed buffer layer 22 away from the substrate 10, and epitaxially growing a semiconductor layer 40 and a sacrificial layer 50 in an alternating manner on a side of the first insulating layer 31 away from the substrate 10, to obtain a stacked structure consisting of alternatingly stacked semiconductor layers 40 and sacrificial layers 50.

[0158] Exemplarily, step S40 may include:

[0159] S41: epitaxial growth of the first insulating layer 31, comprising: at a temperature T3, using DCS as a precursor to perform Si epitaxial growth on a side of the second relaxed buffer layer 22 away from the substrate 10, to obtain a first insulating layer 31 formed of a Si epitaxial layer, wherein the thickness of the first insulating layer 31 is t4 (for example, 5 nm≤t4≤100 nm); the first insulating layer 31 serves as an isolation layer between the second relaxed buffer layer 22 and the stacked structure for insulation;

[0160] S42: epitaxial growth of the stacked structure, including: continuing to maintain the temperature at T3, using DCS and GeH4 as precursors to alternately epitaxially grow Si on the side of the first insulating layer 31 away from the substrate 10 1-x Ge x (y≤x) and the superlattice structure of Si, we get Si / Si 1-x Ge x Stacked structure; wherein the Si epitaxial layer is used as the semiconductor layer 40 for subsequently forming the source / drain electrodes and the channel of the transistor; Si 1-x Ge x The epitaxial layer is a strained layer, serving as a sacrificial layer 50, such as Fig. 6A and Figure 6B shown.

[0161] Since the stacking structure is in the relaxed Si 1-y Ge y The coherent epitaxial formation is carried out on the layer, and the stacking structure is relatively relaxed Si 1-y Ge y The lattice mismatch of the layer is smaller than the mismatch of the stacked structure relative to the Si substrate, so the strain accumulation in the stacked structure will be greatly reduced, which means that the critical thickness of the stacked structure that can achieve co-lattice growth is increased. Therefore, the solution of the embodiment of the present application can further increase the number of stacked layers of the Si / SiGe stacked structure, thereby improving the storage density of 3D semiconductor devices.

[0162] S50 : performing patterned etching on the stack structure to form first trenches 61 and second trenches 62 penetrating through the semiconductor layers 40 in the stack structure to obtain a patterned stack structure; and filling the first trenches 61 and the second trenches 62 with a second insulating layer 32 .

[0163] Exemplarily, step S50 may include:

[0164] S51: using a photolithography method to define a pattern of a first groove 61 and a second groove 62 to be formed on a top surface of the stack structure away from the substrate 10, etching the stack structure in a direction toward the substrate 10, and forming a plurality of first grooves 61 and a plurality of second grooves 62 penetrating each semiconductor layer 40 in the stack structure; wherein each first groove 61 extends in a direction perpendicular to the substrate 10 and in a first direction parallel to the substrate 10, and the plurality of first grooves 61 are spaced apart in a second direction parallel to the substrate 10, and the plurality of first grooves 61 space each semiconductor layer 40 into a plurality of semiconductor pillars 41 extending in the first direction and spaced apart in the second direction; each second groove 62 extends in a direction perpendicular to the substrate 10 and in the second direction, and the plurality of second grooves 62 are spaced apart in the first direction;

[0165] The first direction may be as follows Fig. 7A and Figure 7B The X direction shown, the second direction can be as follows Figure 7B The Y direction shown, which is perpendicular to the substrate 10, can be as follows Fig. 7A The Z direction shown; the first trench 61 and the second trench 62 may expose the first insulating layer 31, for example, the first trench 61 and the second trench 62 may extend to the surface or the inside of the first insulating layer 31 away from the substrate 10;

[0166] S52: Fill the first trench 61 and the second trench 62 with the second insulating layer 32. Fig. 7A and Figure 7B The second insulating layer 32 is used to separate two adjacent columns of memory cells along the first direction and to separate memory cells located in different layers.

[0167] Exemplarily, the material of the second insulating layer 32 can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K<3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films, and also includes air (i.e. forming an air gap).

[0168] S60 : etching to form a bit line hole in the semiconductor pillar 41 , and forming a bit line 70 in the bit line hole.

[0169] For example, step S60 may include: etching the patterned stacked structure in a direction toward the substrate 10, forming a bit line hole penetrating each semiconductor pillar 41 of different layers in the patterned stacked structure, forming a bit line 70 in the bit line hole, and connecting the bit line 70 to each semiconductor pillar 41, such as Fig. 8A and Figure 8Bshown.

[0170] Exemplarily, there may be one bit line hole between two adjacent second grooves 62 in the first direction; the bit line hole may extend in a direction perpendicular to the substrate 10 and expose the first insulating layer 31. For example, the bit line hole may extend to the surface or interior of the first insulating layer 31 away from the substrate 10, and the formed bit line 70 also extends in a direction perpendicular to the substrate 10.

[0171] Exemplarily, the material of the bit line can be selected from any one or more of other metal materials with similar properties such as tungsten, molybdenum, cobalt, etc. The bit line can be a single-layer or multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN) and tungsten (W).

[0172] S70 : etching and removing the sacrificial layer 50 .

[0173] Exemplarily, step S70 may include: using photolithography to define a photolithography pattern, etching and removing the second insulating layer 32 in the first trench 61, and exposing the sacrificial layer 50 in the patterned stacked structure on the sidewall of the first trench 61; using a selective etching process to remove the sacrificial layer 50; and filling the space vacated after etching and removing the sacrificial layer 50 and the first trench 61 with the second insulating layer 32, such as Fig. 9A and Fig. 9B shown.

[0174] S80: forming word lines and gate electrodes of transistors.

[0175] A semiconductor pillar 41 between two adjacent second trenches 62 is subsequently used to form two transistors 90 connected to the same bit line 70. Fig. 10A As shown, along the direction away from the bit line 70, the semiconductor column 41 includes a first electrode region 42, a channel region 43, a second electrode region 44 and a third electrode region 45 in sequence, one of the first electrode region 42 and the second electrode region 412 is used as the source electrode of the transistor, the other is used as the drain electrode of the transistor, and the third electrode region 45 is used as the inner electrode of the capacitor connected to the transistor. The transistor is connected to the bit line 70 through the first electrode region 42, and the transistor is connected to the third electrode region of the capacitor through the second electrode region 44.

[0176] Exemplarily, step S80 may include:

[0177] S81: using photolithography to define a photolithography pattern, and etching away the second insulating layer 32 in a portion of the first trench 61 to expose at least a portion of the sidewall of the channel region 43 of the semiconductor pillar 41;

[0178] S82: depositing a gate insulating layer 81 and a gate electrode 82 on the exposed sidewalls of the channel region 43 in sequence, forming the gate insulating layer 81 and the gate electrode 82 surrounding at least a portion of the sidewalls of the channel region 43, and the semiconductor pillar 41 and the gate electrode 82 constitute a transistor 90;

[0179] S83: Connecting gate electrodes 82 of a plurality of transistors located in the same layer and spaced apart along the second direction together to form a word line 80 extending along the second direction, wherein the gate electrodes 82 of the transistors serve as a part of the word line 80. Fig. 10A and Fig. 10B or, a single word line 80 extending along the second direction is formed, and the gate electrodes 82 of a column of transistors located in the same layer and spaced apart along the second direction are connected to the same word line 80.

[0180] Exemplarily, step S81 may further include: after exposing at least a portion of the sidewall of the channel region 43 of the semiconductor pillar 41 and before performing step S82,

[0181] A selective etching process is used to remove the second insulating layer 32 between the semiconductor pillars 41 of different layers, exposing the entire sidewall of the channel region 43 of the semiconductor pillar 41;

[0182] Step S82 may include: sequentially depositing a gate insulating layer 81 and a gate electrode 82 on the entire exposed sidewall surface of the channel region 43 of the semiconductor pillar 41 to form a gate insulating layer 81 and a gate electrode 82 that completely surround the channel region 43 .

[0183] Step S80 may further include: after step S83,

[0184] S84 : using the second insulating layer 32 to fill the gaps between adjacent semiconductor pillars 41 .

[0185] S90: forming a capacitor.

[0186] Exemplarily, step S90 may include:

[0187] S91: using photolithography to define a photolithography pattern, and etching away the second insulating layer 32 in a portion of the first trench 61 to expose at least a portion of the sidewall of the third electrode region 45 of the semiconductor pillar 41;

[0188] S92: sequentially depositing a dielectric layer 101 and a fourth electrode layer 102 on the exposed sidewalls of the third electrode region 45 to form the dielectric layer 101 and the fourth electrode layer 102 surrounding at least a portion of the sidewalls of the third electrode region 45. The third electrode region 45, the dielectric layer 101 and the fourth electrode layer 102 constitute a capacitor 100. The fourth electrode layer 102 surrounding the third electrode region 45 serves as an external electrode of the capacitor 100. The transistor 90 and the capacitor 100 constitute a storage unit 110. Figure 1A and Figure 1B The semiconductor device shown.

[0189] Exemplarily, step S91 may further include: after exposing at least a portion of the sidewall of the third electrode region 45 of the semiconductor pillar 41 and before performing step S92,

[0190] A selective etching process is used to remove the second insulating layer 32 between the semiconductor pillars 41 of different layers, exposing the entire side wall of the third electrode region 45 of the semiconductor pillar 41;

[0191] Step S92 may include: sequentially depositing a dielectric layer 101 and a fourth electrode layer 102 on the entire exposed sidewall surface of the third electrode region 45 of the semiconductor pillar 41 to form the dielectric layer 101 and the fourth electrode layer 102 completely surrounding the third electrode region 45 .

[0192] Exemplarily, step S90 may further include: after step S92,

[0193] S93: fill the gaps between adjacent semiconductor pillars 41 with the second insulating layer 32 , and insulate two adjacent storage cells 110 located in different layers and two adjacent storage cells 110 located in the same layer and spaced apart along the second direction through the second insulating layer 32 .

[0194] Exemplarily, the material of the second insulating layer 32 is not limited to one, that is, the material of the second insulating layer 32 used in each step may be the same or different.

[0195] An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the above embodiment of the present application.

[0196] In an exemplary embodiment of the present application, the electronic device may be: a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0197] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A plurality of memory cells are distributed in different layers, stacked in a direction perpendicular to the substrate and distributed periodically; each layer includes a plurality of columns of memory cells; A relaxed buffer layer is located between the substrate and the memory cell.

2. The semiconductor device according to claim 1, wherein: The lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate.

3. The semiconductor device according to claim 1, wherein: The relaxed buffer layer includes a first relaxed buffer layer and a second relaxed buffer layer, the first relaxed buffer layer is located between the substrate and the second relaxed buffer layer, and the second relaxed buffer layer is located between the first relaxed buffer layer and the storage unit; Along a direction away from the substrate, the lattice constant of the first relaxed buffer layer changes, and the lattice constant of the second relaxed buffer layer remains unchanged; Dislocations are present in both the first relaxed buffer layer and the second relaxed buffer layer, and a dislocation density in the first relaxed buffer layer is greater than a dislocation density in the second relaxed buffer layer.

4. The semiconductor device according to claim 3, characterized in that The first relaxed buffer layer is a film layer in which strain is completely relaxed at least in a region on a side away from the substrate.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The material of the substrate is selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide and indium phosphide; and / or, The material of the relaxed buffer layer is selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide; and / or, The memory cell includes a transistor, and the transistor includes a semiconductor column; a main material of the semiconductor column is selected from any one or more of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, indium arsenide and indium phosphide.

6. The semiconductor device according to claim 5, characterized in that The material of the substrate and the main material of the semiconductor pillar are both silicon, and the material of the relaxed buffer layer is silicon germanium; or, The material of the substrate is silicon, the material of the relaxed buffer layer is selected from any one or more of gallium arsenide, aluminum gallium arsenide and indium gallium arsenide, and the main material of the semiconductor column is gallium arsenide or indium gallium arsenide.

7. The semiconductor device according to claim 5, characterized in that The semiconductor device further includes an isolation layer, which is located between the relaxed buffer layer and the memory cell and is configured to isolate the relaxed buffer layer from the memory cell; and / or, The transistor further comprises a gate electrode, wherein the gate electrode surrounds at least a portion of a sidewall of the semiconductor pillar; and / or, The semiconductor pillar extends along a first direction parallel to the substrate; and / or, The memory cell further comprises a capacitor connected to the transistor in the same memory cell; and / or, The semiconductor device further comprises: a plurality of bit lines extending in a direction perpendicular to the substrate; and / or, The transistors of two columns of the memory cells located in different layers and adjacent to each other along the first direction are connected to the same bit line; The semiconductor device further comprises: a plurality of word lines extending along a second direction parallel to the substrate; and / or, The transistors of a column of the memory cells located in the same layer and arranged along the second direction are connected to the same word line.

8. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device comprises a plurality of memory cells and a relaxed buffer layer; the plurality of memory cells are distributed in different layers, stacked along a direction perpendicular to the substrate and distributed periodically, and the memory cells comprise transistors; The method for manufacturing the semiconductor device comprises: forming the relaxed buffer layer on the substrate, and making the relaxed buffer layer a relaxed film layer; The plurality of memory cells are formed on a side of the relaxed buffer layer away from the substrate.

9. The manufacturing method according to claim 8, characterized in that: Forming the relaxed buffer layer on the substrate and making the relaxed buffer layer a relaxed film layer comprises: A first relaxed buffer layer is grown on one side of the substrate by using an epitaxial process; wherein the lattice constant of the first relaxed buffer layer changes along a direction away from the substrate, dislocations are present in the first relaxed buffer layer, and a region of the first relaxed buffer layer on a side away from the substrate is a film layer in which strain is completely relaxed; A second relaxed buffer layer is grown on a side of the first relaxed buffer layer away from the substrate using an epitaxial process, and the lattice structure of the second relaxed buffer layer is consistent with the lattice structure of the first relaxed buffer layer away from the substrate; the first relaxed buffer layer and the second relaxed buffer layer constitute the relaxed buffer layer.

10. The manufacturing method according to claim 9, characterized in that: Forming the plurality of memory cells on a side of the relaxed buffer layer away from the substrate comprises: forming an isolation layer on a side of the relaxed buffer layer away from the substrate by using an epitaxial process; Semiconductor layers and sacrificial layers are alternately grown on a side of the isolation layer away from the substrate by using an epitaxial process, so as to obtain a stacked structure consisting of alternating semiconductor layers and sacrificial layers.

11. The manufacturing method according to claim 10, characterized in that: The lattice constant of the relaxed buffer layer in a relaxed state is different from the lattice constant of the substrate, and the lattice constant of the relaxed buffer layer in a relaxed state is between the lattice constants of the sacrificial layer and the semiconductor layer.

12. The manufacturing method according to claim 10, characterized in that: Forming the plurality of storage units further comprises: after obtaining the stacking structure, Performing a patterning process on the semiconductor layer in the stacked structure so that the semiconductor layer forms a semiconductor column of the transistor, and forming a gate electrode on at least a portion of the sidewall of the semiconductor column, wherein the semiconductor column and the gate electrode constitute the transistor; and / or The method for manufacturing the semiconductor device further includes: forming a capacitor connected to the transistor, wherein the transistor and the capacitor connected thereto constitute the memory cell.

13. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 7.

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