Random data distribution

Abstract

A method for random data distribution from a source row to a destination row in a memory array includes receiving a plurality of address pairs, where each address pair includes a source address of a source cell in a source row and a destination address of a destination cell in a destination row, storing the source addresses in cells of a column associated with the destination cell, creating a Boolean algebraic expression that defines a dependency between each of the source addresses and a value stored in each of the source cells, where applying the Boolean algebraic expression to any one of the source addresses provides the value of one of the source cells, applying the Boolean algebraic expression simultaneously to the plurality of columns storing the source addresses, and writing a plurality of results simultaneously to the destination row.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application 18 / 067,744, filed December 19, 2022, which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to data distribution in memory, and more particularly to random data distribution in a memory unit equipped with multiple row decoders and multiple column decoders. Background Technology

[0004] Most cryptographic applications require, for example, random numbers in key generation, salts in certain signature schemes, and random numbers. Ideally, random numbers are generated using entropy obtained from a high-quality source (e.g., the operating system's randomness application programming interface (API)); however, extracting randomness from the running system is slow.

[0005] Random numbers can also be generated using data stored in memory. For example, this can be achieved by receiving a set of bit addresses from a random row in a memory array, from which values ​​can be copied. In a standard memory array, shift operations can be used to move bits from a specific position in a memory row to a new position within that row. A shift operation moves each bit in a row one or more positions to the right or left from its original position (a specific cell in the row of memory). In each shift operation, the entire row is shifted; that is, all bits in the row are moved to the left or right.

[0006] Now for reference Figure 1 , Figure 1 This is a schematic diagram of an exemplary portion of row P before and after a shift operation, where row P can store 16 bits in 16 cells p0, p1, ..., p15. Row P1 shows the original value of row P, and row P2 shows the value of row P after a "left shift by one bit" operation. It can be noted that the values ​​of all cells in row P2 are shifted one position to the left compared to row P1; that is, cell p0 in row P2 has the value of cell p1 in row P1, cell p1 in row P2 has the value of cell p2 in row P1, and so on. Cell p15 is the last cell in row P, therefore, there is no cell from which its value can be retrieved. Accordingly, the value of cell p15 is set to zero. When data is to be randomly distributed, i.e., when the values ​​of several individual bits should be copied to another location in memory, a bit shift operation could be used for each such individual bit, but this is a lengthy and expensive operation in terms of time and computational resources. Summary of the Invention

[0007] According to an embodiment of the application, there is provided a method for random data distribution from a source row to a destination row in a memory array. The method comprises: receiving a plurality of address pairs, wherein each pair comprises a source address of a source cell in a source row and a destination address of a destination cell in a destination row, in each address pair, a value stored in the source cell is to be distributed to the destination cell; and for each of the plurality of address pairs, storing the source address in a cell of a column associated with the destination cell; creating a Boolean algebraic expression defining a dependency between each of the source addresses and the value stored in each of the source cells, wherein applying the Boolean algebraic expression to any of the source addresses provides the value of one of the source cells; and simultaneously applying the Boolean algebraic expression to the plurality of columns storing the source addresses and writing a plurality of results simultaneously to the destination row, thereby distributing data from the source row to the destination row.

[0008] Further, according to an embodiment of the application, the step of applying the Boolean algebraic expression further comprises: simultaneously activating a plurality of rows in the memory array.

[0009] Further, according to an embodiment of the application, the memory array comprises non-volatile storage cells.

[0010] Further, according to an embodiment of the application, the memory array comprises non-destructive storage cells.

[0011] Further, according to an embodiment of the application, the cells storing the source addresses and the destination cells are located in the same column of a multi-bit processor cell.

[0012] Further, according to an embodiment of the application, the step of creating the Boolean algebraic expression comprises: using a Karnaugh map.

[0013] According to an embodiment of the application, there is provided a system for random data distribution from a plurality of source cells to a plurality of destination cells, the system comprising: a memory array comprising cells arranged in rows and columns; a multi-bit processor cell storing a plurality of source addresses of a plurality of source cells in a plurality of columns, each source address being stored in a column associated with one of the destination cells; a Boolean expression builder for constructing a Boolean expression describing a dependency between the source addresses and a plurality of source values stored in the source cells; and a data distributor for simultaneously activating a plurality of cells on the columns according to the Boolean expression and writing a result provided on each of the columns to one of the plurality of destination cells associated with the column.

[0014] Further, according to embodiments of the present application, the multi-bit processor unit includes a multi-row decoder for simultaneously selecting multiple rows of the memory array according to the Boolean expression.

[0015] Further, according to embodiments of the present application, the memory array includes non-volatile storage cells.

[0016] Further, according to embodiments of the present application, the memory array includes non-destructive storage cells. BRIEF DESCRIPTION OF DRAWINGS

[0017] The subject matter regarded as the application is particularly pointed out and distinctly claimed in the concluding portion of the specification. The application, however, both as to organization and method of operation, together with objects, features, and advantages thereof, can best be understood by reference to the following detailed description when read with the accompanying drawings in which:

[0018] Figure 1 is a schematic diagram of an exemplary portion of a row of a memory array storing 16 bits, before and after a shift operation;

[0019] Figure 2 is a schematic diagram of an exemplary source row from which particular bits are to be distributed to a destination row;

[0020] Figure 3 is a schematic diagram of a truth table representing the correlation between addresses and values of a source row of Figure 2 ;

[0021] Figure 4 is a schematic diagram of a random data distribution unit constructed and operative according to embodiments of the present application;

[0022] Figure 5 is a schematic diagram of a multi-bit processor unit used by a random data distribution unit constructed and operative according to embodiments of the present application of Figure 4 ;

[0023] Figure 6 is a schematic diagram of a portion of a memory array component of a multi-bit processor unit of Figure 5 ;

[0024] Figure 7 is a schematic diagram of a matrix representing a Karnaugh map of a truth table of Figure 3 ;

[0025] Figure 8A and Figure 8B are schematic diagrams of possible paths through the matrix of Figure 3 for rearranging the addresses and values of a truth table of Figure 7 ;

[0026] It should be appreciated that for illustrative purposes, the elements shown in the figures are not necessarily to scale. For example, the dimensions of some of the elements can be exaggerated relative to other elements for clarity. Also, where considered appropriate, reference numerals can be repeated among the figures to indicate corresponding or analogous elements. DETAILED DESCRIPTION

[0027] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the application. However, it will be apparent to one skilled in the art that the application can be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the application.

[0028] Generating random numbers can be accomplished by distributing random bits from one memory location to another. Applicant has realized that the in-memory Boolean operations natively supported by devices equipped with a multi-row decoder and a multi-column decoder (e.g., the commercially available associative processing unit (APU) from GSI Technology, Inc. of the United States) can be used to distribute the values of cells from a specified address in a source row to a specified address in a destination row by creating a Boolean algebraic expression that describes the correlation between the set of addresses of row A whose contents need to be copied.

[0029] Reference is now made to Figure 2 , Figure 2 is a schematic illustration of a source row P from which certain bits should be distributed to a destination row Q. In this example, it is predetermined that the values of the bits stored in the cells at addresses p2, p6, p7, p9, p10 and pl4 of the source row P should be distributed to the cells at addresses ql4, q5, ql l, q4, ql and q10 of the destination row Q, respectively. In other words, the value of the cell at address p2 should be copied to the cell at address ql4, the value of the cell at address p6 should be copied to the cell at address q5, and so on. It can be appreciated that the addresses from which the contents of the cells should be copied are known in advance and given as input, i.e., it is predefined that the value in the cell at address ql4 should be taken from the cell at address p2. It can be noted that, for example, the value of cell pl l should not be distributed to any cell in the destination row Q.

[0030] Reference is now made to Figure 3 , Figure 3is a schematic representation of a truth table 30 that represents the correlation between the addresses and the values of a row P. In the truth table 30, each bit of the source address is a parameter. A 4-bit address can represent all of the relevant addresses of a 16-bit row P (0000, 0001, …, 1111), and the parameters of the truth table are the four-bit addresses, each bit stored in the following columns: A, B, C, and D. The value of the bit stored in each address in the row P is stored in the “bit value” column of the truth table 30.

[0031] The simplest Boolean algebraic expression that represents the subset of entries in the truth table 30 that should be distributed to the new location (i.e., entries 2, 6, 7, 9, 10, 14) is described as a sum-of-products (SOP), as shown in expression 1:

[0032] A'B'CD' + A'BCD' + A'BCD + AB'C'D + AB'CD' + ABCD' expression 1

[0033] Each of the products represents an entry in the truth table 30. The expression A'B'CD' reflects entry 2 in the table, i.e., the address 0010 in row P4. The expression A'BCD' reflects entry 6, A'BCD reflects entry 7, AB'C'D' reflects entry 9, AB'CD' reflects entry 10, ABCD' reflects entry 14, and the sum is the expression that includes only the specified entries. It can be noted that although the bit value in address 11 in row P is 1, the Boolean algebraic expression that reflects that entry in the truth table 30 is not part of the final Boolean algebraic expression because its bit should not be distributed.

[0034] Applicants have realized that devices equipped with a multi-row decoder and a multi-column decoder (such as those described in U.S. Patent No. 9,558,812 (entitled “SRAM multi-cell operations”), which is commonly owned by the Applicant and incorporated herein by reference, and U.S. Patent No. 10,832,746 (entitled “Non-volatile in-memory computing device”), which is commonly owned by the Applicant and incorporated herein by reference) can provide a random distribution of bits from a source cell in a source row P to a destination cell in a destination row Q.

[0035] This distribution can be accomplished by storing the address of the source cell in a column of memory cells, applying a Boolean algebraic operation simultaneously to the column (mapping the address of the source cell to the value stored therein), and storing the result in a destination cell of the memory cells.

[0036] Reference is now made to Figure 4 , Figure 4is a schematic diagram of a random data distribution unit 400 configured and operative in accordance with an embodiment of the application. The random data distribution unit 400 comprises a multi-bit processor unit 410, a Boolean algebra expression builder 420, and a data distributor 430.

[0037] Reference is now made to Figure 5 , Figure 5 The multi-bit processor unit 410 used by the random data distribution unit 400 is schematically illustrated. The multi-bit processor unit 410 comprises a memory array 510, a multi-row decoder 520, a multi-column decoder 530, and a controller 540.

[0038] The memory array 510 can be any suitable memory array, for example, a volatile or non-volatile memory array (e.g., resistive random-access memory (ReRAM), 3T DRAM), destructive or non-destructive memory array (e.g., 6T, 8T, 10T, or 12T SRAM), and can comprise pure storage cells arranged in rows and columns. Cells in a column can be connected by a bit line 513. Cells in a row can be connected by a word line 515, which can activate cells in multiple columns simultaneously. Data, including inputs, intermediate results, and outputs, can be stored in columns of the memory array 510.

[0039] The multi-row decoder 520 can be any suitable row decoder capable of activating multiple rows simultaneously. The multi-row decoder 520 can activate two or more rows of the memory array 510 at a time.

[0040] When multiple rows are activated, a selected column of the memory array 510 can provide simultaneous computation for the activated rows when performing a read operation, and simultaneous write operations for the activated rows when performing a write operation.

[0041] The multi-column decoder 530 can comprise any suitable column decoder capable of activating multiple columns simultaneously, and any suitable sensing circuitry capable of sensing values on any bit line connecting cells of a column. The multi-column decoder 530 can provide results of applying Boolean operations on multiple cells in each column that are activated simultaneously by the multi-row decoder 520. The multi-column decoder 530 can select which sensed columns to write back to the memory array 510, and can write values from multiple sensing circuitry components simultaneously.

[0042] The controller 540 can control activation of the multi-row decoder 520 and the multi-column decoder 530. The controller 540 can indicate to the multi-row decoder 520 which rows to activate for a current operation (read or write), and can indicate to the multi-column decoder 530 which columns to output from and which rows to write data to in a selective write operation.

[0043] The controller 540 can communicate with the Boolean algebraic expression builder 420 and the data distributor 430 of the random data distribution unit 400 to activate the multi-row decoder 520 to implement the Boolean algebraic expression generated by the Boolean algebraic expression builder 420.

[0044] The Boolean algebraic expression builder 420 can receive a source row P in the multi-bit processor unit 410 from which data should be distributed and a list of cells in the source row P. The Boolean algebraic expression builder 420 can create a suitable truth table related to the row P (similar to the truth table 30) and can create suitable Boolean algebraic expressions applicable to the related entries in the truth table (containing only expressions related to specific cells of the source row P that need to be distributed), as described herein.

[0045] The Boolean algebraic expression builder 420 can utilize an external tool (e.g., the Espresso heuristic logic minimizer, source code of which is available from the University of California, Berkeley website and GitHub) to create the Boolean algebraic expressions representing the truth table 30 that describes the correlation between the source row P addresses and values.

[0046] The data distributor 430 can first initialize all cells of the destination row Q to 0 and can then simultaneously activate multiple cells in multiple columns of the multi-bit processor unit 410 according to the Boolean algebraic expressions created by the Boolean algebraic expression builder 420. The data distributor 430 can subsequently write the results of the Boolean algebraic operations received by the multi-column decoder 530 into the destination row Q in the multi-bit processor unit 410.

[0047] Reference is now made to Figure 6 , Figure 6 is a schematic diagram of a portion 60 of the memory array 510. Rows A, B, C, and D of the segment 62 store addresses of cells in the source row P (e.g., addresses from which bits should be copied, referred to as source addresses). For example, column 62-c1 stores the address 1010 and column 62-c4 stores the address 1001. The data distributor 430 can activate the relevant rows in the columns of the portion 60 to perform Boolean algebraic operations on all activated columns and can write the results received on each column into the cells in the same column in the row Q. It can be appreciated that the cells storing the source addresses and the destination cells can be located in the same column, as shown in Figure 6 .

[0048] In alternative embodiments, the source addresses and the destination cells can be located on different columns of the multi-bit processor unit 410, in which case the data distributor 430 can have a configuration that associates each column storing a source address with a column of relevant destination cells.

[0049] In another alternative embodiment, the source cells can be located in different rows of the multi-bit processor unit 410, and the Boolean expression builder 420 can have a configuration of addresses of the source cells according to which the Boolean algebraic expression is to be built.

[0050] As described above, the source addresses and the destination addresses (to which values are to be written) are provided as inputs, and each of the provided source addresses (from which values are to be copied) can be stored directly in a column of the multi-bit processor unit associated with a destination cell to which a value stored in a cell pointed to by the source address is to be copied.

[0051] The multi-bit processor unit can perform the Boolean operations on the multiple columns simultaneously, compute the SOPs on the address segments 62 of the partial 60 by column, and store the results in the cells of the destination row Q. After operation of the data distributor 430, each cell in the destination row Q to which a value is to be copied has the value of the relevant source cell, while all other cells have a value of 0.

[0052] In an alternative embodiment, the Boolean algebraic expression builder 420 can create a Karnaugh map to create a simplified Boolean algebraic expression from the truth table 30. A Karnaugh map is a method of simplifying Boolean algebraic expressions.

[0053] In a Karnaugh map, the truth table is represented as a two-dimensional grid in which the cells are ordered such that two consecutive values differ in only one bit, and each cell position represents one combination of input conditions. The cells in the grid, also referred to as "minterms," represent the corresponding output values of the Boolean algebraic expression (similar to the "bit value" column of the truth table 30). Groups of 1s or 0s in the Karnaugh map can be identified and can be used to write a minimal Boolean algebraic expression representing the required logic. The SOP created from the Karnaugh map can be simpler than the SOP created from the truth table 30, optionally containing fewer Boolean operations.

[0054] Reference is now made to Figure 7 , Figure 7 is a schematic diagram of a matrix 70 representing the Karnaugh map of the truth table 30. In the matrix 70, the parameters A and B of the addresses of the cells of the row P (columns A and B of the truth table 30) are grouped into columns, and the parameters C and D of the addresses of the cells of the row P (columns C and D of the truth table 30) are grouped into rows. The values stored in the cells of the row P (the "bit value" column of the truth table 30) are the values of the relevant cells of the matrix 70.

[0055] Reference is now made to Figure 8A and Figure 8B , Figure 8A and Figure 8Bis a schematic of the possible paths through the matrix 70 that are used to rearrange the addresses and values of the row P and store these addresses and values in the columns of the multi-bit processor unit 410, while maintaining a distance of 1 bit between consecutive entries.

[0056] Using Figure 8A Using the path shown, the addresses can be arranged in the following order: 0000, 0100, 1100, 1000, 1001, 1101, 0101, 0001, 0011, 0111, 1111, 1011, 1010, 1110, 0110, and 0010. The Boolean algebra expression builder 420 can use this arrangement to create the simplified Boolean algebra expression 2 (below), but it will be appreciated that many other paths can be used to determine the order of the addresses.

[0057] Once the addresses are arranged, the Boolean algebra expression builder 420 can create a simplified Boolean algebra expression whose parameters provide the bit values for only the selected addresses to compute the bit values for each address of the row P. The method of constructing a Boolean expression using a Karnaugh map is defined in https: / / en.wikipedia.org / wiki / Karnaugh_map.

[0058] The Boolean expression associated with the Karnaugh map 70 is defined in the following expression 2:

[0059] AB’C’D + A’BCD + AB’CD + CD’ expression 2

[0060] Using expression 2 can provide faster distribution of data from the source row P to the destination row Q.

[0061] Embodiments of the invention can distribute the values of multiple bits in one location (the source row P) to another location in memory simultaneously without performing multiple shift operations or accessing memory. Each bit can be distributed from one address of the source unit to a second address of the destination unit simultaneously.

[0062] While certain features have been illustrated and described, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.

Claims

1. A method for random data distribution from a source row to a destination row in a memory array, the method comprising: receiving a plurality of address pairs, wherein each pair includes a source address of a source cell in the source row and a destination address of a destination cell in the destination row, wherein in each address pair, a value stored in the source cell is to be distributed to the destination cell; storing, for each of the plurality of address pairs, the source address in a cell of a column associated with the destination cell; creating a Boolean algebraic expression that defines a dependency between each of the source addresses and a value stored in each of the source cells, wherein applying the Boolean algebraic expression to any one of the source addresses provides a value of the one of the source cells; and simultaneously applying the Boolean algebraic expression to a plurality of columns storing the source addresses and simultaneously writing a plurality of results to the destination row, thereby distributing data from the source row to the destination row.

2. The method of claim 1, wherein, The applying the Boolean algebraic expression further comprises simultaneously activating a plurality of rows in the memory array.

3. The method of claim 2, wherein, The memory array comprises non-volatile storage cells.

4. The method of claim 2, wherein, The memory array comprises non-destructive storage cells.

5. The method of claim 1, wherein, The cells storing the source addresses and the destination cell are in a same column of a multi-bit processor cell.

6. The method of claim 1, wherein, The creating a Boolean algebraic expression comprises using a Karnaugh map.

7. A system for random data distribution from a plurality of source cells to a plurality of destination cells, the system comprising: a memory array comprising cells arranged in rows and columns; a multi-bit processor cell storing a plurality of source addresses of the plurality of source cells in a plurality of columns, each source address in a column associated with one of the plurality of destination cells; a Boolean expression builder to construct a Boolean expression describing an association between the source addresses and a plurality of source values stored in the source cells; and a data distributor to simultaneously activate a plurality of cells on the columns according to the Boolean expression and write a result provided on each of the columns to one of the plurality of destination cells associated with the one of the columns.

8. The system of claim 7, wherein, The multi-bit processor cell comprises a multi-row decoder to simultaneously select a plurality of rows of the memory array according to the Boolean expression.

9. The system of claim 7, wherein, The memory array comprises non-volatile storage cells.

10. The system of claim 7, wherein, The memory array comprises non-destructive storage cells.

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