Data defragmentation method and data storage system

Abstract

The invention provides a data defragmentation method and a data storage system. The method comprises the steps that a plurality of candidate logic intervals are determined from a plurality of logic intervals according to access popularity information, and the access popularity information reflects host access popularity corresponding to the logic intervals respectively; after the plurality of candidate logic intervals are determined, a first logic interval in the plurality of candidate logic intervals is determined as a target logic interval according to response time information, and the response time information reflects storage device response time corresponding to the plurality of candidate logic intervals respectively; and instructing the storage device to perform defragmentation on the target data belonging to the target logic interval. Therefore, the operation efficiency of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a data defragmentation method and a data storage system. Background Art

[0002] During storage product use, due to constant write, delete, and read operations, and the inherent limitations of flash media, fragmentation is inevitable. This creates logically continuous but physically discontinuous data, which reduces data read performance and impacts the user experience. Currently, common defragmentation mechanisms include the host specifying a logical range for defragmentation, or the storage controller automatically selecting blocks containing less valid data for defragmentation. However, neither of these methods defragments data that is frequently read by the host. As a result, even after repeated defragmentation, users often experience persistently low storage device performance. Summary of the Invention

[0003] The present invention provides a data defragmentation method and a data storage system, which can improve the above-mentioned problem and further enhance the operating performance of the storage device.

[0004] An embodiment of the present invention provides a data defragmentation method for a host system, wherein the host system is connected to a storage device, wherein the storage device includes a memory module, and the data defragmentation method includes: determining multiple candidate logical intervals from multiple logical intervals based on access heat information, wherein the access heat information reflects the host access heat corresponding to the multiple logical intervals respectively, and the total number of the multiple candidate logical intervals is less than the total number of the multiple logical intervals; after determining the multiple candidate logical intervals, determining a first logical interval among the multiple candidate logical intervals as a target logical interval based on response time information, wherein the response time information reflects the storage device response time corresponding to the multiple candidate logical intervals respectively; and instructing the storage device to perform defragmentation on target data belonging to the target logical interval.

[0005] An embodiment of the present invention further provides a data storage system, which includes a storage device and a host system. The host system is connected to the storage device. The storage device includes a memory module. The host system is used to: determine a plurality of candidate logical intervals from a plurality of logical intervals based on access heat information, wherein the access heat information reflects the host access heat corresponding to the plurality of logical intervals respectively, and the total number of the plurality of candidate logical intervals is less than the total number of the plurality of logical intervals; after determining the plurality of candidate logical intervals, determine the first logical interval among the plurality of candidate logical intervals as a target logical interval based on response time information, wherein the response time information reflects the storage device response time corresponding to the plurality of candidate logical intervals respectively; and instruct the storage device to perform defragmentation on the target data belonging to the target logical interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0007] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0008] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0009] Figure 4 is a schematic diagram of dividing multiple logical intervals according to an embodiment of the present invention;

[0010] Figure 5 is a schematic diagram showing determination of a target logical interval based on host access heat and storage device response time according to an embodiment of the present invention;

[0011] Figure 6 FIG. 4 is a flow chart of a data defragmentation method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0013] Figure 1 Schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a laptop computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to this. In addition, the storage device 12 can include a solid-state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0014] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0015] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of a voltage (also known as a threshold voltage). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules having the same or similar characteristics.

[0016] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered the control core of the memory device 12 and is used to control the memory device 12. For example, the memory controller 123 can be used to control or manage all or part of the operation of the memory device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices, or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0017] The memory controller 123 can send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, and the present invention is not limited thereto. The memory module 122 can receive the command sequence from the memory controller 123 and access the memory cells within the memory module 122 according to the command sequence.

[0018] Figure 2 FIG is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0019] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage all or part of the operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0020] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0021] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data accuracy. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits), and the present invention is not limited thereto.

[0022] Figure 3 FIG is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile data storage.

[0023] In one embodiment, a physical unit may include a physical programming unit. For example, a physical programming unit is also referred to as a physical programming unit. In one embodiment, a physical erasing unit may include multiple physical programming units. For example, a physical erasing unit may be considered a physical block.

[0024] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit may be adjusted according to practical needs and are not limited by the present invention. In one embodiment, a physical programming unit may be considered a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, but the present invention is not limited to this.

[0025] In one embodiment, a physical programming unit is the smallest unit to which data is written synchronously in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be programmed synchronously to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0026] In one embodiment, multiple physical programming cells in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple physical programming cells in the physical erase unit to change the threshold voltages of at least some of the memory cells in the physical programming cells. By performing an erase operation on a physical erase unit, data stored in the physical erase unit can be cleared.

[0027] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also known as user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0028] In one embodiment, if a physical unit does not store valid data, the physical unit may be associated with the idle area 32. Furthermore, the physical units in the idle area 32 may be erased to clear the data in the physical units. In one embodiment, the physical units in the idle area 32 are also referred to as idle physical units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0029] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cells, the physical cells may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0030] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management unit. A logical unit may be mapped to one or more physical units.

[0031] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is currently not mapped by any logical unit, the memory control circuit 23 may determine that the physical unit does not currently store any valid data.

[0032] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data read, write, or erase based on the information in the management table (i.e., the logical-to-physical mapping table).

[0033] In the following embodiments, operations performed by the host system 11 may be considered to be performed by a processor of the host system 11. For example, the processor of the host system 11 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices or a combination of these devices.

[0034] Figure 4 This is a schematic diagram of dividing multiple logical intervals according to an embodiment of the present invention. Figure 4In one embodiment, the host system 11 may divide the logical addresses LBA(1) to LBA(z) into a plurality of intervals (also referred to as logical intervals) R(1) to R(y). For example, interval R(1) may cover logical addresses LBA(1) to LBA(x), interval R(i) may cover logical addresses LBA(i) to LBA(j), and interval R(y) may cover logical addresses LBA(y) to LBA(z). Each logical address in the logical addresses LBA(1) to LBA(z) may correspond to Figure 3 Each of the intervals R(1)-R(y) may include multiple consecutive logical units. In addition, the logical addresses LBA(1)-LBA(z) may cover all or at least part of the logical addresses (or logical units) accessible to the host system 11.

[0035] In one embodiment, the total number of logic units contained in each interval of the intervals R(1) to R(y) is fixed and / or the same. For example, each interval of the intervals R(1) to R(y) may contain 1024 consecutive logic units. In one embodiment, the total number of logic units contained in each interval of the intervals R(1) to R(y) may also be non-fixed and / or dynamically adjustable. In one embodiment, the total number of logic units contained in two intervals of the intervals R(1) to R(y) may also be different. In other words, the total number of logic units contained in each interval may also be adjusted according to practical needs, and the present invention is not limited thereto.

[0036] In one embodiment, the host system 11 may monitor the host system's access behavior (or access behavior) to the storage device 12 to obtain access heat information. The access heat information may reflect the host access heat corresponding to each of the multiple logical intervals (e.g., intervals R(1)-R(y)).

[0037] It should be noted that in the following embodiments, interval R(i) in interval R(1) to R(y) is used as an example for description. In addition, the following description of interval R(i) can also be applied to any of intervals R(1) to R(y).

[0038] In one embodiment, the host access heat corresponding to interval R(i) may reflect the frequency with which the logical units within interval R(i) are accessed (or stored) by the host system 11. For example, a higher host access heat corresponding to interval R(i) indicates a higher frequency with which the logical units within interval R(i) are accessed by the host system 11.

[0039] In one embodiment, the host system 11 may obtain counting information (also referred to as first counting information) based on the access behavior. The first counting information may reflect the number of host accesses (also referred to as first host access count) to the interval R(i) within a certain time range (also referred to as the first time range). For example, within the first time range, each time the host system 11 accesses a logical unit within the interval R(i) (e.g., the host system 11 reads data belonging to the logical unit), the host system 11 may increment the first counting information by "1" to update the first counting information. The updated first counting information may reflect the first host access count.

[0040] In one embodiment, the host system 11 may obtain another counting information (also referred to as second counting information) based on the access behavior. The second counting information may reflect the number of host accesses (also referred to as second host access count) to the interval R(i) within another time range (also referred to as the second time range). For example, the second time range is temporally ordered after the first time range, and the time length of the first time range is the same as the time length of the second time range. For example, within the second time range, each time the host system 11 accesses a logical unit located in the interval R(i) (for example, the host system 11 reads data belonging to this logical unit), the host system 11 may add "1" to the second counting information to update the second counting information. The updated second counting information may reflect the second host access count.

[0041] In one embodiment, if the second count information is greater than the first count information, it indicates that the host access popularity corresponding to interval R(i) gradually increases over time. In one embodiment, if the second count information is equal to the first count information, it indicates that the host access popularity corresponding to interval R(i) remains unchanged over time. Alternatively, in one embodiment, if the second count information is less than the first count information, it indicates that the host access popularity corresponding to interval R(i) decreases over time.

[0042] In one embodiment, the host system 11 can obtain access popularity information corresponding to interval R(i) based on the first counting information and the second counting information. For example, the host system 11 can subtract the first counting information from the second counting information to obtain the difference between the first and second counting information. For example, this difference can be used to reflect the change (or trend) in host access popularity corresponding to interval R(i) over time. Then, the host system 11 can obtain access popularity information corresponding to interval R(i) based on this difference.

[0043] In one embodiment, the access heat information corresponding to interval R(i) may include an evaluation value (also referred to as a heat evaluation value). For example, this heat evaluation value may be positively correlated with the host access heat corresponding to interval R(i). That is, the larger the heat evaluation value, the higher the host access heat corresponding to interval R(i). In one embodiment, the host system 11 may input the difference between the first counting information and the second counting information into a preset algorithm or use this difference to look up a table to obtain the heat evaluation value.

[0044] In one embodiment, after obtaining the access popularity information, the host system 11 may determine a plurality of candidate logical intervals from the intervals R(1) to R(y) based on the access popularity information. It should be noted that the total number of candidate logical intervals must be less than the total number of intervals R(1) to R(y). In other words, in the process of determining the candidate logical intervals from the intervals R(1) to R(y), a portion of the logical intervals in the intervals R(1) to R(y) will be selected as candidate logical intervals, while another portion of the logical intervals in the intervals R(1) to R(y) will be excluded from the candidate logical intervals.

[0045] In one embodiment, the host access heat corresponding to each of the multiple candidate logical intervals is higher than the host access heat corresponding to the remaining logical intervals that are not among the multiple candidate logical intervals. For example, assuming that interval R(i) is determined to be a candidate logical interval, and interval R(y) is not a candidate logical interval, the host access heat corresponding to interval R(i) will be higher than the host access heat corresponding to interval R(y).

[0046] In one embodiment, the host system 11 may determine the host access heat corresponding to each interval in the intervals R(1)~R(y) based on the access heat information. Then, the host system 11 may sort the intervals R(1)~R(y) from high to low or from low to high based on the host access heat. In one embodiment, assuming that the higher the ranked intervals are, the higher the host access heat corresponding to the intervals R(1)~R(y), the host system 11 may select multiple intervals with relatively higher rankings from the sorted intervals R(1)~R(y) as the candidate logical intervals. Alternatively, in one embodiment, assuming that the lower the ranked intervals are, the higher the host access heat corresponding to the intervals R(1)~R(y), the host system 11 may select multiple intervals with relatively lower rankings from the sorted intervals R(1)~R(y) as the candidate logical intervals.

[0047] In one embodiment, after determining the candidate logical intervals, the host system 11 may determine at least one logical interval (also referred to as a first logical interval) among the candidate logical intervals as the target logical interval based on the response time information. For example, the first logical interval may include interval R(i). The response time information may reflect the storage device response time corresponding to each of the candidate logical intervals.

[0048] In one embodiment, when the host system 11 sends a read command to the storage device 12 to instruct access to a logical unit within interval R(i) (e.g., to read data from the logical unit), the host system 11 may monitor the processing time or response time of the storage device 12 in response to the read command. The host system 11 may then determine the storage device response time corresponding to interval R(i) based on the processing time or response time of the storage device 12 in response to the read command. For example, the processing time or response time of the storage device 12 in response to the read command may be positively correlated with the storage device response time corresponding to interval R(i). That is, a longer processing time or response time of the storage device 12 in response to the read command indicates a longer storage device response time corresponding to interval R(i). The host system 11 may then obtain response time information corresponding to interval R(i) based on the storage device response time corresponding to interval R(i). For example, the response time information corresponding to interval R(i) may reflect the storage device response time corresponding to interval R(i).

[0049] In one embodiment, the host system 11 may evaluate the degree of data fragmentation corresponding to the interval R(i) based on the response time information corresponding to the interval R(i). For example, the response time of the storage device corresponding to the interval R(i) may be positively correlated with the degree of data fragmentation corresponding to the interval R(i). That is, if the response time of the storage device corresponding to the interval R(i) is longer, the host system 11 may determine that the degree of data fragmentation corresponding to the interval R(i) is higher. In addition, the degree of data fragmentation corresponding to the interval R(i) may be positively correlated with the degree of dispersion of the data belonging to the interval R(i) in the memory module 122. That is, if the degree of data fragmentation corresponding to the interval R(i) is higher, it means that the degree of dispersion of the data belonging to the interval R(i) in the memory module 122 is higher (that is, the data fragmentation is more serious).

[0050] In one embodiment, the host system 11 can obtain a fragmentation assessment value corresponding to interval R(i) based on the response time information corresponding to interval R(i). For example, the storage device response time corresponding to interval R(i) can be positively correlated with the fragmentation assessment value. Furthermore, the fragmentation assessment value can reflect the degree of data fragmentation corresponding to interval R(i). For example, the fragmentation assessment value can be positively correlated with the degree of data fragmentation corresponding to interval R(i).

[0051] In one embodiment, when the host system 11 sends a read command to the storage device 12 to instruct access to a logical unit within interval R(i) (e.g., to read data from the logical unit), the host system 11 may determine the unit response time corresponding to interval R(i) based on the monitored storage device response time corresponding to interval R(i) and the read data length corresponding to the read command. For example, the read data length may reflect the data length of the data instructed to be read by the read command.

[0052] In one embodiment, the host system 11 can divide the monitored storage device response time (ΔT) corresponding to interval R(i) by the read data length (ΔS) corresponding to the read command to obtain the unit response time (UT) corresponding to interval R(i). That is, UT = ΔT / ΔS. The host system 11 can then obtain the fragmentation assessment value corresponding to interval R(i) based on this unit response time.

[0053] In one embodiment, the unit response time corresponding to interval R(i) may be positively correlated with the fragmentation assessment value corresponding to interval R(i). That is, the longer the unit response time corresponding to interval R(i), the larger the fragmentation assessment value corresponding to interval R(i). In one embodiment, the host system 11 may input this unit response time into a preset algorithm or perform a table lookup to obtain the fragmentation assessment value corresponding to interval R(i).

[0054] In one embodiment, the host system 11 may determine whether the unit response time corresponding to interval R(i) is greater than an average response time. If the unit response time corresponding to interval R(i) is greater than the average response time, the host system 11 may add an adjustment value (e.g., "1") to the fragmentation assessment value corresponding to interval R(i) to update the fragmentation assessment value corresponding to interval R(i). However, if the unit response time corresponding to interval R(i) is not greater than the average response time, the host system 11 may not add the adjustment value to the fragmentation assessment value corresponding to interval R(i) (i.e., the fragmentation assessment value corresponding to interval R(i) is not updated).

[0055] In one embodiment, the host system 11 may obtain the average response time based on the unit response time corresponding to each interval in the intervals R(1) to R(y). In other words, the average response time may reflect the average value of the unit response time corresponding to each interval in the intervals R(1) to R(y).

[0056] In one embodiment, after instructing the storage device 12 to perform defragmentation on the data belonging to the interval R(i), the host system 11 may reset the fragmentation assessment value corresponding to the interval R(i). For example, the host system 11 may reset the fragmentation assessment value corresponding to the interval R(i) to an initial value (e.g., "0").

[0057] In one embodiment, after determining interval R(i) as a candidate logical interval, the host system 11 may determine whether the fragmentation evaluation value corresponding to interval R(i) is greater than a preset value. If the fragmentation evaluation value corresponding to interval R(i) is greater than the preset value, the host system 11 may determine interval R(i) as the target logical interval. However, if the fragmentation evaluation value corresponding to interval R(i) is not greater than (e.g., less than or equal to) the preset value, the host system 11 may not determine interval R(i) as the target logical interval.

[0058] In one embodiment, after determining the target logical interval, the host system 11 may instruct the storage device 12 to perform defragmentation on the data within the target logical interval (also referred to as target data). For example, the target data may be valid data. Alternatively, the target data may not include invalid data. For example, the host system 11 may send a specially designed developer instruction or other operational instruction to the storage device 12 to instruct the storage device 12 to perform defragmentation on the data within the target logical interval.

[0059] Figure 5 Schematic diagram of determining a target logical interval based on host access heat and storage device response time according to an embodiment of the present invention. Figure 5 , continued by Figure 4 In an embodiment, the host system 11 may select, from the intervals R(1) to R(y), a plurality of intervals CR(1) to CR(k) with relatively high host access heat as candidate logical intervals based on the access heat information. Then, the host system 11 may further select, from the intervals CR(1) to CR(k) (i.e., candidate logical intervals), intervals TR(1) to TR(p) with relatively long storage device response times (equivalent to relatively high data fragmentation levels) as target logical intervals based on the response time information. After determining the target logical intervals, the host system 11 may instruct the storage device 12 to perform defragmentation on the data (i.e., target data) belonging to the intervals TR(1) to TR(p) (i.e., target logical intervals).

[0060] In one embodiment, when performing a defragmentation operation on target data belonging to the target logical interval, the memory control circuit 23 may centrally store data (i.e., target data) with a degree of fragmentation exceeding a predetermined level in at least one physical unit (also referred to as a target physical unit) in the memory module 122. For example, assuming the target logical interval includes interval R(i), the memory control circuit 23 may query the logical-to-physical mapping information corresponding to interval R(i) to determine the multiple physical units (also referred to as reference physical units) mapped to the multiple logical units in interval R(i). The memory control circuit 23 may read data (i.e., target data) from these reference physical units in a distributed manner and then centrally store the read target data in the target physical units in the memory module 122. This achieves the beneficial technical effect of adjusting the target data, originally stored in a fragmented manner in the memory module 122 (i.e., the reference physical units) initiated by the host system 11, to a centralized storage format that supports continuous access (e.g., continuous reads) in the memory module 122, thereby improving the subsequent access efficiency of the host system 11 and the storage device 12 to the target data.

[0061] In one embodiment, the memory control circuit 23 may also determine the total number of idle physical cells in the memory module 122. For example, the idle physical cells do not store valid data. In one embodiment, the memory control circuit 23 may determine whether the total number of idle physical cells is less than a threshold value. For example, the threshold value may be 10, 15, or another value.

[0062] In one embodiment, the memory control circuit 23 (or the storage device 12) performs the aforementioned defragmentation on the target data belonging to the target logical interval based on the instruction of the host system 11 only when the total number of idle physical units is not less than (e.g., greater than or equal to) the threshold value. For example, if the total number of idle physical units is still relatively sufficient (i.e., the total number of idle physical units is not less than the threshold value), the memory control circuit 23 may perform the aforementioned defragmentation on the target data belonging to the target logical interval based on the instruction of the host system 11, thereby improving the subsequent operating performance of the storage device 12 through the optimized data defragmentation mechanism.

[0063] However, in one embodiment, if the total number of idle physical units is less than the threshold, indicating that new idle physical units need to be released urgently, the memory control circuit 23 can determine which physical erase units (e.g., physical erase units storing relatively less valid data) to perform the aforementioned defragmentation on based on the amount of valid data stored in each physical erase unit. Thus, when new idle physical units need to be released urgently, new idle physical units can be released at a relatively fast speed.

[0064] In one embodiment, the aforementioned defragmentation can be considered one of multiple types of data cleanup operations. In one embodiment, while performing defragmentation on the target data within the target logical interval, the memory control circuit 23 may also simultaneously perform garbage collection (GC), wear leveling (WL), or other types of data cleanup operations on the target data to further improve the subsequent operational performance of the storage device 12. These operations are not detailed here.

[0065] Figure 6 This is a flow chart of a data defragmentation method according to an embodiment of the present invention. Figure 6 In step S601, multiple candidate logical intervals are determined from multiple logical intervals based on access popularity information, wherein the access popularity information reflects the host access popularity corresponding to each of the multiple logical intervals, and the total number of the multiple candidate logical intervals is less than the total number of the multiple logical intervals. After the multiple candidate logical intervals are determined, in step S602, a first logical interval among the multiple candidate logical intervals is determined as a target logical interval based on response time information, wherein the response time information reflects the storage device response time corresponding to each of the multiple candidate logical intervals. In step S603, the storage device is instructed to perform defragmentation on the target data belonging to the target logical interval.

[0066] However, Figure 6 The steps have been described in detail above and will not be repeated here. Figure 6 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 6 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0067] In summary, the data defragmentation method and data storage system proposed in the embodiments of the present invention can be initiated by a host system, and based on the host access popularity and storage device response time corresponding to the logical interval, a target logical interval is determined, thereby instructing the storage device to perform defragmentation on the target data belonging to the target logical interval. Compared to the traditional method in which the storage device itself may simply refer to the amount of valid data to select the physical blocks to be defragmented, the data defragmentation method and data storage system proposed in the embodiments of the present invention can prioritize defragmentation for data with both high host access popularity and high storage device response time, thereby better improving the operating efficiency of the storage device.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data defragmentation method, characterized in that: A method for defragmenting data in a host system connected to a storage device including a memory module includes: Determining a plurality of candidate logical intervals from the plurality of logical intervals according to the access popularity information, wherein the access popularity information reflects host access popularity corresponding to the plurality of logical intervals, and a total number of the plurality of candidate logical intervals is less than a total number of the plurality of logical intervals; After determining the plurality of candidate logical intervals, determining a first logical interval among the plurality of candidate logical intervals as a target logical interval based on response time information, wherein the response time information reflects storage device response times corresponding to the plurality of candidate logical intervals respectively; and The storage device is instructed to perform defragmentation on target data belonging to the target logical extent.

2. The data defragmentation method according to claim 1, wherein the host access heat corresponding to each logical interval in the multiple candidate logical intervals is higher than the host access heat corresponding to the remaining logical intervals in the multiple logical intervals that do not belong to the multiple candidate logical intervals.

3. The data defragmentation method according to claim 1 , wherein the access popularity information includes first access popularity information, the first access popularity information reflecting the first host access popularity corresponding to the first logical interval, and the data defragmentation method further comprises: Obtaining first counting information, wherein the first counting information reflects a number of first host accesses to the first logical interval within a first time range; obtaining second counting information, wherein the second counting information reflects a number of second host accesses to the first logical interval within a second time range, wherein the first time range is different from the second time range; and The first access popularity information is obtained according to the first counting information and the second counting information.

4. The data defragmentation method according to claim 1 , wherein the response time information includes first response time information, the first response time information reflecting a response time of a first storage device corresponding to the first logical interval, and the step of determining the first logical interval among the plurality of candidate logical intervals as the target logical interval based on the response time information comprises: Obtaining a first fragmentation evaluation value based on a response time of the first storage device, wherein the first fragmentation evaluation value reflects a first data fragmentation degree corresponding to the first logical interval; as well as The first logical interval is determined as the target logical interval according to the first fragmentation evaluation value.

5. The data defragmentation method according to claim 4 , wherein the step of obtaining the first fragmentation evaluation value according to the response time of the first storage device comprises: determining a unit response time corresponding to the first logical interval according to a response time of the first storage device and a read data length corresponding to a read instruction; as well as The first fragmentation evaluation value is obtained according to the unit response time.

6. The data defragmentation method according to claim 5, wherein the step of obtaining the first fragmentation evaluation value according to the unit response time comprises: If the unit response time is greater than the average response time, adding an adjustment value to the first fragmentation evaluation value to update the first fragmentation evaluation value; as well as After performing the defragmentation on the data belonging to the first logical interval, the first fragmentation evaluation value is reset.

7. The data defragmentation method according to claim 4, wherein the step of determining the first logical interval as the target logical interval according to the first fragmentation evaluation value comprises: In response to the first fragmentation evaluation value being greater than a preset value, the first logical interval is determined as the target logical interval.

8. The data defragmentation method according to claim 1 , wherein the storage device performs the defragmentation on the target data belonging to the target logical interval based on an instruction from the host system only when a total number of idle physical units in the memory module is not less than a critical value, wherein the idle physical units do not store valid data.

9. The data defragmentation method according to claim 1, wherein in performing the defragmentation operation on the target data belonging to the target logical interval, the storage device stores the target data with a fragmentation degree higher than a preset degree in the target physical units in the memory module.

10. A data storage system, characterized in that: include: storage device; as well as a host system connected to the storage device, The storage device includes a memory module, and the host system is configured to: Determining a plurality of candidate logical intervals from the plurality of logical intervals according to the access popularity information, wherein the access popularity information reflects host access popularity corresponding to the plurality of logical intervals, and a total number of the plurality of candidate logical intervals is less than a total number of the plurality of logical intervals; After determining the plurality of candidate logical intervals, determining a first logical interval among the plurality of candidate logical intervals as a target logical interval based on response time information, wherein the response time information reflects storage device response times corresponding to the plurality of candidate logical intervals respectively; as well as The storage device is instructed to perform defragmentation on target data belonging to the target logical extent.

11. The data storage system according to claim 10, wherein the host access heat corresponding to each logical interval in the multiple candidate logical intervals is higher than the host access heat corresponding to the remaining logical intervals in the multiple logical intervals that do not belong to the multiple candidate logical intervals.

12. The data storage system according to claim 10 , wherein the access popularity information includes first access popularity information, the first access popularity information reflects a first host access popularity corresponding to the first logical interval, and the host system is further configured to: Obtaining first counting information, wherein the first counting information reflects a number of first host accesses to the first logical interval within a first time range; Obtaining second counting information, wherein the second counting information reflects a number of second host accesses to the first logical interval within a second time range, wherein the first time range is different from the second time range; and The first access popularity information is obtained according to the first counting information and the second counting information.

13. The data storage system according to claim 10 , wherein the response time information includes first response time information, the first response time information reflecting a response time of the first storage device corresponding to the first logical interval, and the host system determining the first logical interval among the plurality of candidate logical intervals as the target logical interval based on the response time information comprises: Obtaining a first fragmentation evaluation value based on a response time of the first storage device, wherein the first fragmentation evaluation value reflects a first data fragmentation degree corresponding to the first logical interval; as well as The first logical interval is determined as the target logical interval according to the first fragmentation evaluation value.

14. The data storage system according to claim 13, wherein the operation of the host system obtaining the first fragmentation assessment value according to the response time of the first storage device comprises: determining a unit response time corresponding to the first logical interval according to a response time of the first storage device and a read data length corresponding to a read instruction; as well as The first fragmentation evaluation value is obtained according to the unit response time.

15. The data storage system according to claim 14, wherein the operation of the host system obtaining the first fragmentation assessment value according to the unit response time comprises: If the unit response time is greater than the average response time, adding an adjustment value to the first fragmentation evaluation value to update the first fragmentation evaluation value; as well as After performing the defragmentation on the data belonging to the first logical interval, the first fragmentation evaluation value is reset.

16. The data storage system according to claim 15, wherein the operation of the host system determining the first logical interval as the target logical interval according to the first fragmentation evaluation value comprises: In response to the first fragmentation evaluation value being greater than a preset value, the first logical interval is determined as the target logical interval.

17. The data storage system according to claim 10, wherein the storage device performs the defragmentation on the target data belonging to the target logical interval based on the instruction of the host system only when the total number of idle physical units in the memory module is not less than a critical value, wherein the idle physical units do not store valid data.

18. The data storage system according to claim 10, wherein in performing the defragmentation operation on the target data belonging to the target logical interval, the storage device stores the target data with a fragmentation degree higher than a preset degree in the target physical units in the memory module.

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