Chip-on-wafer layout method, layout device and preparation method of silicon capacitor
By establishing an XY two-dimensional Cartesian coordinate system on the wafer and dividing the exposure area, and arranging the chips in a way that is from large to small and centrally symmetrical, the warping problem caused by dense arrangement is solved, and the structural strength and manufacturing precision of the wafer are improved.
CN120671623BActive Publication Date: 2026-05-01SUZHOU SUNA PHOTOELECTRIC
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Patent Information
- Application Number
- CN202510696595.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-28
- Publication Date
- 2026-05-01
- Estimated Expiration
- 2045-05-28
AI Technical Summary
Technical Problem
In semiconductor manufacturing, the dense arrangement of chips can cause wafer warping.
Method used
The wafer-on-chip layout method is adopted. By establishing an XY two-dimensional rectangular coordinate system on the wafer, it is divided into four exposure areas. The chips are arranged in a way that is from large to small and centrally symmetrical, thus optimizing the arrangement rules of the exposure areas and chips.
Benefits of technology
It significantly improves the structural strength of the wafer, reduces the risk of warpage, enhances the precision and consistency of the manufacturing process, and strengthens the overall structural stability.
✦ Generated by Eureka AI based on patent content.
Abstract
The disclosure provides a wafer-on-chip layout method, a layout device and a preparation method of a silicon capacitor. In the layout method, an XY two-dimensional rectangular coordinate system is established with the center of the wafer as the origin, and an exposure area is arranged in each of the four wafer regions of the coordinate system. For each exposure area, each chip is arranged in the order of center, four corners, edge line and remaining empty position on the exposure area according to the size from large to small, and each chip is arranged symmetrically with the center of the exposure area. The application optimizes the exposure area division and the chip arrangement rule, not only realizes the optimized utilization of the center region of the wafer, but also enhances the structural strength of the center and the four corners of the exposure area, significantly improves the structural strength of the wafer, and effectively reduces the risk of wafer warping in subsequent processes.
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