Automatic test vector generation method and device, equipment, medium and program product

Abstract

The embodiment of the invention provides a method, equipment and device for automatic test vector generation, a medium and a program product, and relates to the field of chip design tools. The method includes constructing an implication graph based on a process of performing reasoning on a circuit design using an automatic test vector generation algorithm, the implication graph indicating a plurality of results resulting from a plurality of decisions during the reasoning process. The method further includes determining at least one unique implication point in the implication graph based on determining that the plurality of results meet a conflict condition. The method further includes determining a cause of an unmeasurable fault of the circuit design by analyzing the at least one unique implication. In this way, by constructing the implication graph based on the inference process of the circuit design and determining the at least one unique implication point causing the conflict from the implication graph, the reason of the untestable fault in the circuit design can be more efficiently located, and a designer can be assisted in rapidly iteratively testing the circuit design to improve the coverage rate and promote the yield climbing.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of chip design tools. More specifically, embodiments of the present disclosure relate to methods, apparatuses, devices, computer-readable storage media, and computer program products for automatic test pattern generation (ATPG). Background Art

[0002] Electronic design automation (EDA) tools are widely used in chip functional design, synthesis, verification, and simulation. ATPG tools are a key component of the EDA tool chain. During digital circuit testing, ATPG tools generate test patterns that can distinguish correct circuit behavior from faulty circuits caused by defects. These test patterns can be used for fault detection and to assist designers in locating the cause of a fault. Therefore, a solution for automated test pattern generation is needed to further improve the efficiency of fault detection and fault cause localization using ATPG tools. Summary of the Invention

[0003] Some related ATPG solutions have the problems of low fault coverage and high human resource consumption. Embodiments of the present disclosure provide a solution for performing fault detection and fault cause location using an ATPG tool to at least partially solve the above problems.

[0004] In a first aspect of the present disclosure, a method for automatic test vector generation is provided. The method includes: constructing an implication graph based on a process of performing reasoning on a circuit design using an automatic test vector generation algorithm, the implication graph indicating multiple results obtained from multiple decisions during the reasoning process. The method also includes: determining at least one unique implication point in the implication graph based on determining that the multiple results meet a conflict condition. The method also includes: determining a cause of an untestable fault in the circuit design by analyzing the at least one unique implication point.

[0005] In this way, by constructing an implication graph based on the reasoning process of the circuit design and determining at least one unique implication point causing the conflict from the implication graph, the cause of the untestable faults in the circuit design can be located more efficiently, and designers can be assisted to quickly iterate and test the circuit design to improve fault coverage and promote yield climbing.

[0006] In some embodiments of the first aspect, the type of the untestable fault includes at least one of the following: the automatic test vector generation solution fails to generate a test vector stimulus, the test vector stimulus generated by the automatic test vector generation solution does not meet the compression limit, or the test vector stimulus generated by the automatic test vector generation solution does not meet the test power consumption limit. In some embodiments of the first aspect, the method further includes: based on the determined cause of the untestable fault, generating a candidate solution for solving the untestable fault. In this way, various factors that affect test vector generation and coverage can be considered, such as low power consumption limits, compression limits, etc. In addition, candidate solutions for solving the fault can also be generated to assist designers in quickly iterating test circuit designs.

[0007] In some embodiments of the first aspect, the conflict condition includes a first conflict condition associated with a failure in solving an automatic test vector generation problem, and the method further includes: constructing the first conflict condition, wherein the first conflict condition indicates a logic value conflict occurs at a same node in the circuit design. In this manner, it is possible to facilitate detection of an untestable fault resulting from a failure in solving an automatic test vector generation problem and to facilitate locating the cause of the untestable fault.

[0008] In some embodiments of the first aspect, the method further includes: updating the implication graph by rolling back and updating at least one of the multiple decisions based on determining that the multiple results satisfy the first conflict condition; and determining one or more unique implication points from the updated implication graph to determine the cause of the untestable failure of the circuit design.

[0009] In some embodiments of the first aspect, determining the cause of the untestable fault of the circuit design by analyzing the at least one unique implication point includes: determining a set of root cause points based on the at least one unique implication point and the one or more unique implication points; sorting the root cause points in the set of root cause points by frequency or performing a set cover algorithm on the root cause points in the set of root cause points to determine at least one root cause point in the set of root cause points; and determining the cause of the untestable fault of the circuit design based on the at least one root cause point. In this way, historical decisions can be taken into account to more accurately analyze the cause of the untestable fault.

[0010] In some embodiments of the first aspect, determining a cause of an untestable fault in the circuit design based on the at least one root cause point includes determining at least one of the following associated with the at least one root cause point: an automatic test vector generation constraint, a circuit structure, a circuit test point, or a circuit observation point. In this way, a direct cause at the circuit design level can be determined based on a unique implication point in an implication graph, thereby facilitating the designer's location and resolution of untestable faults in the circuit design.

[0011] In some embodiments of the first aspect, the conflict condition includes a second conflict condition associated with an automatic test vector generation compression limit, and the method further includes: constructing the second conflict condition, wherein the second conflict condition indicates that a first predetermined scan unit of the circuit design is set to a predetermined value. In some embodiments of the first aspect, the first predetermined scan unit and the predetermined value are determined based on a record of previous automatic test vector generation compression of the circuit design not meeting the automatic test vector generation compression limit. In this manner, it is possible to facilitate detection of untestable faults in which the test vector stimulus generated by the automatic test vector generation solution does not meet the compression limit, and to facilitate locating the cause of the untestable fault.

[0012] In some embodiments of the first aspect, based on determining that the multiple results satisfy the conflict condition, determining at least one unique implication point in the implication graph includes: based on determining that the multiple results satisfy the second conflict condition, determining at least one unique implication point in the implication graph that causes the first predetermined scanning unit to be set to the predetermined value.

[0013] In some embodiments of the first aspect, determining the cause of the untestable fault in the circuit design by analyzing the at least one unique implication point includes: determining at least one root cause point by analyzing the at least one unique implication point; and determining at least one of the following items associated with the at least one root cause point for the circuit design: a circuit design constraint or an aggregation of multiple scan cells. In this way, the direct cause at the circuit design level can be determined based on the unique implication point in the implication graph, thereby facilitating designers to locate and resolve untestable faults in the circuit design.

[0014] In some embodiments of the first aspect, the conflict condition includes a third conflict condition associated with a test power consumption limit, and the method further includes: constructing the third conflict condition, wherein the third conflict condition indicates that a second predetermined scan unit of the circuit design is to be used. In some embodiments of the first aspect, the second predetermined scan unit is determined based on a record of previous automatic test vector generation for the circuit failing to meet the test power consumption limit. In this manner, it is possible to facilitate detection of untestable faults where test vector stimuli generated by the automatic test vector generation solution fail to meet the test power consumption limit, and to facilitate locating the cause of the untestable fault.

[0015] In some embodiments of the first aspect, based on determining that the multiple results satisfy the conflict condition, determining at least one implication point in the implication graph includes: based on determining that the multiple results satisfy the third conflict condition, determining at least one unique implication point in the implication graph that causes the second predetermined scanning unit to be used.

[0016] In some embodiments of the first aspect, the test power consumption limit includes a shift power consumption limit, and determining the cause of the untestable fault in the circuit design by analyzing the at least one unique implication point includes: determining at least one root cause point by analyzing the at least one unique implication point; and determining an ATPG constraint associated with the at least one root cause point for the circuit design. In this way, the direct cause at the circuit design level can be determined based on the unique implication point in the implication graph, thereby facilitating the designer to locate and resolve the untestable fault in the circuit design.

[0017] In some embodiments of the first aspect, testing power consumption limits includes capturing power consumption limits, and determining the cause of the untestable fault in the circuit design by analyzing the at least one unique implication point includes: determining at least one root cause point by analyzing the at least one unique implication point; and determining an aggregation of multiple scan cells associated with the at least one root cause point for the circuit design. In this way, direct causes at the circuit design level can be determined based on the unique implication points in the implication graph, thereby facilitating designers to locate and resolve untestable faults in the circuit design.

[0018] In some embodiments of the first aspect, the method further includes generating a first candidate solution for resolving the untestable fault, the first candidate solution comprising at least one of: adding a gated clock unit associated with the aggregation of the plurality of scan units; or adjusting the capture power consumption limit. In this manner, rapid iteration of the test circuit design can be facilitated to efficiently complete the test process.

[0019] In a second aspect of the present disclosure, an apparatus for automatic test vector generation is provided. The apparatus includes: a construction unit configured to construct an implication graph based on a process of reasoning a circuit design using an automatic test vector generation algorithm, the implication graph indicating multiple results obtained from multiple decisions during the reasoning process; a conflict determination unit configured to determine at least one unique implication point in the implication graph based on determining that the multiple results satisfy a conflict condition; and an analysis unit configured to determine a cause of an untestable fault in the circuit design by analyzing the at least one unique implication point.

[0020] In some embodiments of the second aspect, the type of the untestable fault includes at least one of the following: an automatic test vector generation solution fails to generate a test vector stimulus, a test vector stimulus generated by the automatic test vector generation solution does not meet a compression limit, or a test vector stimulus generated by the automatic test vector generation solution does not meet a test power consumption limit. In some embodiments of the second aspect, the apparatus further includes a generating unit configured to: generate a candidate solution for resolving the untestable fault based on the determined cause of the untestable fault.

[0021] In some embodiments of the second aspect, the conflict condition includes a first conflict condition associated with a failure in automatic test vector generation solution, and the device also includes a first conflict construction unit, which is configured to: construct the first conflict condition, and the first conflict condition indicates that a logic value conflict occurs at the same node in the circuit design.

[0022] In some embodiments of the second aspect, the apparatus further comprises a backtracking unit configured to: update the implication graph by backing off and updating at least one of the multiple decisions based on determining that the multiple results satisfy the first conflict condition; and determine one or more unique implication points from the updated implication graph for determining the cause of the untestable fault of the circuit design.

[0023] In some embodiments of the second aspect, determining the cause of the untestable fault of the circuit design by analyzing the at least one unique implication point includes: determining a root cause point set based on the at least one unique implication point and the one or more unique implication points; sorting the root cause points in the root cause point set according to frequency or performing a set cover algorithm on the root cause points in the root cause point set to determine at least one root cause point in the root cause point set; and determining the cause of the untestable fault of the circuit design based on the at least one root cause point.

[0024] In some embodiments of the second aspect, determining a cause of an untestable failure of the circuit design based on the at least one root cause point includes determining at least one of the following associated with the at least one root cause point: an automatic test vector generation constraint, a circuit structure, a circuit test point, or a circuit observation point.

[0025] In some embodiments of the second aspect, the conflict condition includes a second conflict condition associated with an automatic test vector generation compression limit, and the apparatus further includes a second conflict constructing unit configured to construct the second conflict condition, the second conflict condition indicating that a first predetermined scan unit of the circuit design is set to a predetermined value. In some embodiments of the second aspect, the first predetermined scan unit and the predetermined value are determined based on a record that a previous automatic test vector generation compression of the circuit design did not meet the automatic test vector generation compression limit.

[0026] In some embodiments of the second aspect, based on determining that the multiple results satisfy the conflict condition, determining at least one unique implication point in the implication graph includes: based on determining that the multiple results satisfy the second conflict condition, determining at least one unique implication point in the implication graph that causes the first predetermined scanning unit to be set to the predetermined value.

[0027] In some embodiments of the second aspect, determining the cause of the untestable fault of the circuit design by analyzing the at least one unique implication point includes: determining at least one root cause point by analyzing the at least one unique implication point; and determining at least one of the following items associated with the at least one root cause point for the circuit design: a circuit design constraint or an aggregation of multiple scan units.

[0028] In some embodiments of the second aspect, the conflict condition includes a third conflict condition associated with a test power consumption limit, and the apparatus further includes a third conflict constructing unit configured to construct the third conflict condition, wherein the third conflict condition indicates that a second predetermined scan unit of the circuit design is used. In some embodiments of the second aspect, the second predetermined scan unit is determined based on a record that a previous automatic test vector generation for the circuit does not meet the test power consumption limit.

[0029] In some embodiments of the second aspect, based on determining that the multiple results satisfy the conflict condition, determining at least one implication point in the implication graph includes: based on determining that the multiple results satisfy the third conflict condition, determining at least one unique implication point in the implication graph that causes the second predetermined scanning unit to be used.

[0030] In some embodiments of the second aspect, the test power consumption limit includes a shift power consumption limit, and determining the cause of the untestable fault of the circuit design by analyzing the at least one unique implication point includes: determining at least one root cause point by analyzing the at least one unique implication point; and determining an ATPG constraint associated with the at least one root cause point for the circuit design.

[0031] In some embodiments of the second aspect, the testing power consumption limit includes capturing power consumption limit, and determining the cause of the untestable fault of the circuit design by analyzing the at least one unique implication point includes: determining at least one root cause point by analyzing the at least one unique implication point; and determining an aggregation of multiple scan units associated with the at least one root cause point for the circuit design.

[0032] In some embodiments of the second aspect, the device also includes a first generation unit, which is configured to: generate a first candidate solution for resolving the untestable fault, the first candidate solution including at least one of the following: adding a gated clock unit associated with the aggregation of the multiple scan units; or adjusting the capture power consumption limit.

[0033] In a third aspect of the present disclosure, an electronic device is provided, comprising: at least one computing unit; and at least one memory, the at least one memory being coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions, when executed by the at least one computing unit, enabling the device to implement the method provided in the first aspect.

[0034] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program is executed by a processor to implement the method provided in the first aspect.

[0035] In a fifth aspect of the present disclosure, a computer program product is provided, comprising computer executable instructions, which implement part or all of the steps of the method of the first aspect when the instructions are executed by a processor.

[0036] It is understandable that the electronic device of the third aspect, the computer storage medium of the fourth aspect, or the computer program product of the fifth aspect provided above are all used to execute the method provided in the first aspect. Therefore, the explanation or description of the first aspect also applies to the third, fourth, and fifth aspects. In addition, the beneficial effects that can be achieved in the second, third, fourth, and fifth aspects can refer to the beneficial effects of the corresponding methods and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0038] Figure 1 A flowchart showing the chip design and manufacturing process;

[0039] Figure 2 shows a flowchart of an example process for ATPG according to some embodiments of the present disclosure;

[0040] Figure 3 A schematic diagram illustrating an example process of determining a unique implication point according to some embodiments of the present disclosure;

[0041] Figure 4 A schematic diagram illustrating an example process of determining a root cause point driven by a unique implication point from an implication graph according to some embodiments of the present disclosure;

[0042] Figure 5 A schematic diagram illustrating an example process for root cause analysis of ATPG according to some embodiments of the present disclosure is shown;

[0043] Figure 6A schematic diagram illustrating an example operation process of an ATPG tool that can implement some embodiments of the present disclosure;

[0044] Figure 7 A schematic diagram illustrating an example operation process of an interactive ATPG tool that can implement some embodiments of the present disclosure;

[0045] Figure 8 A schematic diagram illustrating an example process of performing root cause analysis of conflicts for a test cube according to some embodiments of the present disclosure is shown;

[0046] Figure 9 A schematic diagram illustrating an example process of analyzing the root causes of conflicts other than the test cube conflict resolution method according to some embodiments of the present disclosure is provided;

[0047] Figure 10 A schematic diagram showing a comparison between a test cube conflict resolution method and other conflict resolution methods according to some embodiments of the present disclosure;

[0048] Figure 11 A schematic diagram illustrating an example process for root cause analysis of compression conflicts according to some embodiments of the present disclosure;

[0049] Figure 12 A schematic diagram illustrating example root cause points for compression conflicts according to some embodiments of the present disclosure is shown;

[0050] Figure 13 A schematic diagram illustrating an example process for root cause analysis of power consumption conflicts according to some embodiments of the present disclosure is shown;

[0051] Figure 14 A schematic block diagram showing an apparatus for ATPG according to some embodiments of the present disclosure; and

[0052] Figure 15 A block diagram is shown of a computing device capable of implementing various embodiments of the present disclosure. DETAILED DESCRIPTION

[0053] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0054] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to." The term "based on" should be understood as "based at least in part on." The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment." The terms "first," "second," etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0055] As briefly mentioned above, ATPG tools are a crucial component of the EDA tool chain. In recent decades, with the advancement of advanced semiconductor processes, modern chips have become increasingly integrated. Chips can now perform more and more complex tasks per unit area, resulting in smaller and more complex designs. This presents significant challenges for chip production testing, making thorough chip testing, rapid yield analysis, and ramp-up crucial. Rapidly improving yield can significantly reduce chip manufacturing costs and increase the yield rate of complete systems entering the market. Entering the sub-micron era, tiny process geometries significantly impact the etching of complex layouts. In the early stages of chip manufacturing, yields could even drop below 30%. To achieve rapid yield increases, more efficient chip testing programs are often required. Therefore, EDA tools related to chip testing are becoming increasingly important throughout the entire production chain.

[0056] In the chip design-to-manufacturing process, the primary task of chip testing is to identify defective chips. To improve chip testability, engineers typically incorporate design for test (DFT) structures into chip designs and then use ATPG tools to generate test patterns. The typical process involves: generating test patterns using ATPG tools; obtaining a test coverage report; completing a diagnostic algorithm; obtaining a diagnostic report; and performing yield analysis based on the report.

[0057] To quickly achieve yield improvement, engineers typically set target coverage requirements. High coverage means efficient test vectors, and generating efficient test vectors plays a crucial role in rapidly increasing yield. Therefore, ATPG tools are a crucial component of the entire EDA tool chain. Given a circuit design and a fault list, ATPG tools logically model the physical defects that may occur in the chip. They then generate test vectors for each logic fault, either to detect it or to prove it is untestable.

[0058] At the end of the ATPG run, the tool reports fault coverage and the classification of each fault. Fault types can include testable faults (covered by test vectors), untestable faults (for which no test vectors exist), and unobserved faults. Testable faults directly impact actual fault coverage, while untestable and unobserved faults contribute to a gap between target coverage and actual coverage.

[0059] For designs with low coverage, DFT engineers perform coverage analysis to understand the cause and address it as appropriate. For example, engineers may try adding test points, adding additional DFT functions, or modifying the circuit design or ATPG constraints. However, as designs grow in size and complexity, fault classification alone becomes difficult to directly analyze the cause of low coverage and often requires extensive design knowledge and manpower.

[0060] To improve coverage and increase the efficiency of fault location, some commercial tools currently provide fault analysis methods. However, these tools are often limited to the conditions required for solving the ATPG algorithm and do not converge to root cause analysis at the circuit design level. As a result, they are of limited help in improving the coverage of DFT circuits.

[0061] For example, some proposals have proposed modeling unmeasured faults, categorizing them into three categories: 1) unobservable faults; 2) excitation conflict faults; and 3) reverse and forward implication (RFI) conflict faults. Once modeling is complete, discrete point sets associated with the faults can be constructed based on each of the three fault models. These discrete point sets consist of circuit model nodes, and the discrete points and their logic values ​​are displayed in the user interface for analysis.

[0062] For example, for unobservable faults, the observation point and fault point can be identified, and all discrete points along the path between them can be collected for analysis. If a blocking signal exists along the path, the source of the blocking signal can be identified, and all discrete points between it and the corresponding observation point can be collected. Furthermore, all discrete points and logic values ​​along the path between the blocking signal source associated with the excitation fault and the fault point, as well as all discrete points and logic values ​​along the path between the blocking signal source associated with the propagation fault and the fault propagation path, will also be added to the discrete point set.

[0063] For triggering conflict faults, the nodes involved in the conflict can be designated as conflict points and request points, and the circuit state can be established. The logical values ​​of the request points and conflict points are consistent. Discrete points that meet the following three conditions can be added to the discrete point set: points located on the path between the conflict point and the fault point and with a logical value opposite to the fault triggering requirement; points located on the path between the request point and the fault point and with a logical value consistent with the fault triggering requirement; and all nodes between the conflict point and the request point.

[0064] For RFI conflict faults, starting from the node with inconsistent logical values ​​when each conflict occurs, add all nodes with inconsistent logical values ​​on the fault excitation path and propagation path; identify the source points of the opposite signals on these inconsistent nodes, and add them to the fault excitation path and propagation path, as well as all required nodes on the path to the corresponding inconsistent node.

[0065] This solution proposes to collect the excitation path and propagation path of the target fault, as well as the discrete points on the path between the identified blocking signal source point, conflict point, and conflict signal value source point based on the connection relationship of the circuit and the intermediate state of the circuit nodes, and further input the discrete points into the software system for analysis. Although this solution can intuitively present the circuit state when blocking or conflict occurs during the fault resolution process in the visual interface of the circuit structure, it still requires designers to manually analyze the logic design for each untestable fault, so it is of limited help in improving low coverage at the design level. In addition, this solution does not consider other factors that affect test vector generation and coverage, such as low power consumption limitations, compression limitations, etc.

[0066] In order to at least partially solve the above-mentioned problems and other potential problems, various embodiments of the present disclosure provide a method, device, apparatus, medium and program product for ATPG. The method includes: based on the process of performing reasoning on a circuit design using an automatic test vector generation algorithm, constructing an implication graph, wherein the implication graph indicates multiple results obtained by multiple decisions during the reasoning process. The method also includes: based on determining that the multiple results meet a conflict condition, determining at least one unique implication point in the implication graph. The method also includes: determining the cause of the untestable fault of the circuit design by analyzing the at least one unique implication point.

[0067] In this way, by constructing an implication graph based on the reasoning process of the circuit design and determining at least one unique implication point that causes the conflict from the implication graph, the cause of the untestable fault in the circuit design can be located more efficiently, and designers can be assisted to quickly iterate the test circuit design to improve coverage, solve testability problems, and promote yield climbing.

[0068] In this article, the term "implication graph", also called "implication diagram", is a graphical tool used to represent the implication relationship between logical propositions. In the implication graph, each node represents a logical proposition, and each directed edge represents an implication relationship. If node A points to node B, it means that A implies B. Implication graphs can be used to represent the process of logical reasoning, and can be used to analyze the causes of conflicts in the reasoning process. In conflict analysis, the "unique implication point (UIP)" in the implication graph refers to a literal in the smallest unsatisfied clause that causes the conflict. This literal is the only cause of the entire conflict. In other words, the UIP can be considered as the cause of the conflict. It should be understood that the terms "implication graph" and "unique implication point" are general knowledge in the field of logic, and their specific details will not be repeated here.

[0069] Various exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings. Figure 1 A flowchart of a chip design and manufacturing process 100 is shown. The design and manufacturing process 100 begins with specification development 110. During specification development 110, the functional and performance requirements for the integrated circuit are determined. During chip design 120, circuit design is performed using EDA software to obtain, for example, a layout file for chip manufacturing. Depending on the type of circuit (e.g., digital or analog), design 120 may include different design steps. During manufacturing 140, integrated circuits are formed on a wafer through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing. During packaging 150, the wafer is cut into bare dies, which are then packaged through processes such as gluing, welding, and molding to form chips. The resulting chips are tested during testing 160 to ensure that the performance of the finished chips meets the requirements determined in specification development 110. Chips that pass the tests 170 can be delivered to customers. It should be understood that the above process is merely illustrative and does not limit the scope of this disclosure. In some cases, the chip design and manufacturing process may vary. For example, a tape-out may be performed before manufacturing 140. A small number of chips obtained from the tape-out may be used for testing to verify whether the chip design meets expectations. If it does not meet expectations, this indicates that the tape-out has failed and the chip design may need to be adjusted or redesigned.

[0070] In some embodiments, the design of digital circuits 120 may illustratively include architecture design 121, RTL design 123, functional simulation 125, synthesis 127, timing analysis 129, DFT 131, verification and checking 133, layout and routing 135, design rule checking (DRC) 137, and layout generation 139. Architecture design 121, for example, includes designing the architecture of the chip. For example, EDA software may be used to determine the types and number of components or subcircuits included in the chip system, as well as the functions, connections, and interactions of each component or subcircuit. During the RTL design 123 stage, the determined chip architecture may be described in code at the RTL level using a hardware programming language such as Verilog or VHDL. Functional simulation 125 is also referred to as RTL-level behavioral simulation or front-end simulation. The purpose of functional simulation is to analyze the correctness of the logical relationships of the designed circuit. In some cases, logical equivalence verification may be performed during the functional simulation 125 stage, for example, performing logical equivalence verification on the RTL code design before and after modification. Synthesis 127 can convert the RTL into a gate-level netlist. Synthesis 127 can include, for example, translation, optimization, and mapping. In one embodiment, the EDA software used for synthesis can first convert the RTL code into a general Boolean equation and compile it. The netlist can be optimized based on constraints such as delay and area imposed by the designer, and then the RTL netlist can be mapped to the process library to generate a gate-level netlist.

[0071] Timing analysis 129 is typically static timing analysis, primarily involving the calculation and estimation of timing for digital circuits. Timing analysis is performed on paths within a digital circuit to determine whether timing closure has been achieved, thereby ensuring that the timing of various circuits meets various timing requirements. This type of digital circuit verification is typically performed statically and does not require simulation of the digital logic.

[0072] At the DFT 131 stage, various hardware logics for improving chip testability (including controllability and observability) can be embedded in the design. By using this part of the logic, test vectors can be generated to achieve the purpose of testing large-scale digital circuits. DFT can, for example, include a test method based on a scan chain or a built-in self-test circuit (BIST). The scan chain includes multiple "shift registers (also called scan cells)" connected by flip-flops in the sequential circuit, and the input and output of each shift register can be observed separately. Using the scan chain, the test of complex sequential circuits can be converted into the test of combinational circuits.

[0073] The scan unit can have a shift mode and a capture mode. In shift mode, whenever the clock signal (clk) jumps, the test vector is input from the scan unit's shift input port SI and shifted along the scan chain through the first connected scan unit. The output port Q of the scan unit drives the combinational logic in the circuit under test, and the combinational logic outputs the corresponding value through the data input port D of the scan unit connected to it.

[0074] Once the test vector shift is complete, each scan unit can enter capture mode. In capture mode, each scan unit captures the current value of the data input port D at each clock signal transition. Each scan unit then enters shift mode again. In shift mode, these captured values ​​are shifted out of the scan chain output port one by one for comparison with the preset correct values. If the combinational logic is faulty and is triggered by the current test vector, the fault can be detected by the difference between the shifted values ​​and the correct values.

[0075] During the verification check 133 stage, the circuit may be formally verified and / or subjected to an equivalence check. Formal verification may use mathematical methods to prove the correctness or incorrectness of a circuit based on one or more formal specifications or attributes. Formal verification may include, for example, abstract interpretation, formal model checking (also known as property checking), and theorem proving. Equivalence checking may be used to verify consistency between the register transfer level design and the gate-level netlist, and between the gate-level netlist and the gate-level netlist. Equivalence checking may include the aforementioned logical equivalence verification, also known as combinatorial equivalence checking. Equivalence checking may also include timing equivalence checking.

[0076] In the stage of layout and routing 135, the chip circuit can be laid out (placement) and routed (routing). The layout can reasonably arrange the gate-level netlist generated by logic synthesis 127 in a rectangular area corresponding to the chip based on considerations such as area, critical path delay length, and power consumption. After this, the various components or sub-circuits that have been laid out can be routed to connect them. Routing generally expects the total routing to be short, the routing delay to meet timing requirements, and to comply with process routing rules (such as routing density). Although layout and routing are described separately here, this is only illustrative and does not limit the scope of this disclosure. In some cases, layout and routing can be performed simultaneously or alternately to achieve optimization of layout and routing.

[0077] During the DRC 137 stage, the layout can be checked for potential open circuits, short circuits, or adverse effects that violate design rules. After passing the DRC, a file representing the layout, such as a GDSII file, can be generated 139 by the EDA software. It will be understood that the above steps are merely exemplary and do not limit the scope of this disclosure. In the actual design process, the above steps can be added, deleted, or modified according to design needs. In addition, some of the above steps can be implemented by different EDA software or integrated into one or more EDA software. This disclosure is not limited to this.

[0078] Figure 2 A flowchart illustrating an example process 200 for ATPG according to some embodiments of the present disclosure is provided. Process 200 can be implemented by any suitable computing unit. For example, it can be executed by a computer or other electronic device with computing or circuit design capabilities. Specifically, for example, a computer processor can execute an EDA tool based on data and / or instructions stored in a memory to perform process 200.

[0079] like Figure 2 As shown, in block 210, the processor constructs an implication graph based on the process of performing reasoning on the circuit design using the ATPG algorithm. The implication graph indicates multiple results obtained from multiple decisions during the reasoning process. As described above, the implication graph can be used to represent the process of logical reasoning. That is, the implication graph can record the decisions made at each decision level during the reasoning process and the corresponding results obtained from the decision reasoning. According to the reasoning process (including making decisions and reasoning based on implication relationships), decision points (decision nodes) and implication points (implication nodes), as well as their parent-child node relationships, can be recorded, and the implication graph can be constructed based on this.

[0080] When using ATPG algorithms to reason about circuit designs, the nodes in the constructed implication graph can represent assignments to circuit logic units, such as those based on decisions made or circuit constraints. Directed edges in the implication graph can represent the reasons for the assignments, including logical relationship restrictions and various constraints.

[0081] When using an ATPG algorithm to reason about a circuit design, various assignment decisions are made to find a specific input vector (i.e., a test vector) that can trigger a specified fault in the circuit design. Therefore, if the reasoning is successful, a test cube can be generated. Conversely, if the reasoning fails, such as when an assignment conflict occurs, it can be determined that no suitable input vector exists to trigger the fault. In other words, the fault is an untestable fault associated with a test cube solution failure.

[0082] In some embodiments, a fan-based ATPG algorithm can be used to perform reasoning on a circuit design. The fan-based ATPG algorithm, also known as the FAN algorithm, uses path sensitization technology to find a path in the circuit so that errors in the path can be uniquely sensitized. The characteristic of the FAN algorithm is that it only makes decisions at the headline and only propagates at other gates, thereby reducing the decision space. It should be understood that any suitable ATPG algorithm, such as the D algorithm, can be applied in the embodiments of the present disclosure, and the scope of the present disclosure is not limited here. The process of performing reasoning on a circuit design using an ATPG algorithm will not be repeated in this article.

[0083] At block 220, the processor determines at least one unique implication point in the implication graph based on determining that the multiple results satisfy a conflict condition. In some embodiments, the conflict condition may include a first conflict condition associated with a failure in the automatic test vector generation solution. The first conflict condition is also referred to as a test cube solution conflict. In some embodiments, a test cube solution conflict can be constructed to indicate a logical value conflict at the same node in the circuit design, i.e., a failure to satisfy a logical relationship constraint. In other words, when a logical value conflict occurs at the same node in the circuit design during reasoning, the test cube solution fails, and the test cube solution conflict condition is satisfied.

[0084] Additionally or alternatively, the conflict condition may include a second conflict condition associated with the automatic test vector generation compression limit. The second conflict condition is also referred to as a compression conflict. In some embodiments, a compression conflict may be constructed to indicate that one or more predetermined scan units of the first type of the circuit design are set to a predetermined value. In other words, a compression conflict may be considered to have occurred when one or more predetermined scan units of the circuit design are set to a predetermined value during the reasoning process. This is because the use of specified bits of the scan unit may cause the compression of the scan chain to fail to meet the compression limit, such as the compression ratio. In some embodiments, the predetermined value of the predetermined scan unit may be determined based on a record of a previous compression solution failure. If the previous ATPG compression does not meet the ATPG compression limit, such as the compression ratio, the bit of the scan unit that failed the compression check may be recorded as the predetermined value of the predetermined scan unit.

[0085] Additionally or alternatively, the conflict condition may include a third conflict condition associated with the test power consumption limit. The third conflict condition is also referred to as a power consumption conflict. In some embodiments, the test power consumption limit may include a shift power consumption limit for the scan chain. Additionally or alternatively, the test power consumption limit may include a capture power consumption limit for the scan chain. Corresponding conflict conditions may be constructed based on the test power consumption limit. For example, a shift conflict condition may be constructed based on the shift power consumption limit, or a capture power consumption conflict condition may be constructed based on the capture power consumption limit.

[0086] In some embodiments, a power consumption conflict may be constructed to indicate that one or more predetermined scan cells of the second type of the circuit design are being used. The predetermined scan cells of the second type may be determined based on a previous record of ATPG failing to meet the test power consumption limit. For example, the scan cells used by the test cube that previously failed to meet the test power consumption limit may be recorded as the predetermined scan cells of the second type. In this way, when it is discovered during the reasoning process that such predetermined scan cells are used again, it may be considered that a power consumption conflict has occurred. This is because the use of a specific scan cell may mean that a large number of scan cells associated with it are being used, which may result in the scan cells used by the test cube failing to meet the test power consumption limit. Additionally or alternatively, in some embodiments, a power consumption conflict may be constructed to indicate that a certain number of scan cells for the circuit design are being used.

[0087] It should be understood that the above-mentioned conflict conditions are merely exemplary and the scope of the present disclosure is not limited thereto. Corresponding conflict conditions can be constructed based on the type of untestable fault to be detected and / or analyzed. For example, if the type of untestable fault to be detected includes the failure of ATPG solution to generate a test cube, then the test cube solution conflict or similar conflict conditions described above can be constructed to detect such faults. Similarly, if the type of untestable fault to be detected includes the test cube generated by ATPG solution not meeting the compression limit, then the compression conflict or similar conflict conditions described above can be constructed; if the type of untestable fault to be detected includes the test cube generated by ATPG solution not meeting the test power consumption limit, then the power consumption conflict or similar conflict conditions described above can be constructed to detect the corresponding untestable fault.

[0088] Continue to refer Figure 2 At block 220, if the result of the decision satisfies the established conflict condition, the processor further determines at least one unique implication point in the implication graph. At block 230, the processor analyzes the at least one unique implication point to determine the cause of the untestable fault in the circuit design. In some embodiments, the processor may also provide the determined cause of the untestable fault to a user. For example, the cause of the untestable fault may be provided to the user via a user interface.

[0089] As mentioned above, a unique implication point (UIP) is the cause of a conflict. The principle is that, in the historical decision-making and reasoning process leading to the current conflict, the key to the conflict was a core parent node. A UIP can be considered the key node in the current decision layer that caused the final conflict. A UIP can be defined as follows: if node A is the most recent decision node (i.e., the deepest decision point in the decision layer), then all paths from node A to the conflicting node must pass through the node that is the UIP.

[0090] Therefore, starting with the conflicting node, we can continuously replace the current inference point with its parent node until only one inference point remains in the conflicting decision layer, known as the first unique implication point (UIP). During this period, the parent nodes and all decision points in other decision layers are also recorded as UIPs. In this way, at least one UIP can be identified from the implication graph for further analysis.

[0091] Figure 3 FIG. 1 is a schematic diagram showing an example process of determining a unique implication point according to some embodiments of the present disclosure. Figure 3As shown in FIG, the ATPG constraints (labeled as constraint) obtained by statically learning the circuit can be additionally defined as unit clauses (labeled as unit) at the lowest decision layer (top-level) and added to the implication graph. Figure 3 In the example shown, the deepest decision point in the decision layer is the node marked as r=1@4, the first-UIP is the node marked as s=1@4, and all paths from the deepest decision point r=1@4 to the conflict node (marked as K conflict) must pass through the node marked as s=1@4, that is, the first-UIP.

[0092] Based on the at least one UIP determined, the processor determines the cause of the untestable fault of the circuit design by analyzing the UIP. It should be understood that the term "untestable fault" includes various types of faults, such as ATPG solution failure to generate a testcube, the test cube generated by ATPG solution does not meet the compression limit, the test cube generated by ATPG solution does not meet the test power consumption limit, and so on. In this article, the cause of the untestable fault of the circuit design determined by (multiple) UIPs in the implication graph is called a UIP-driven root cause point, also referred to as a root cause point for short. Examples of root cause points may include a specific UIP itself, a constraint on the node assignment that leads to a specific UIP, the first UIP itself, and so on. In some embodiments, the determined UIP can be directly used as the root cause point without the need to determine the root cause point based on the UIP. The circuit constraints, ATPG constraints, circuit structure and / or scan unit arrangement at the circuit design level associated with the root cause point can be regarded as the direct cause of the untestable fault.

[0093] Figure 4 FIG. 4 is a schematic diagram showing an example process 400 for determining a UIP driver root cause point from an implication graph according to some embodiments of the present disclosure. Figure 4 As shown in FIG, the ATPG constraints obtained from static learning (e.g., constraint n=0@0 and constraint m=0@0) are added to the implication graph. The ATPG constraints may correspond to the circuit features obtained from static learning. Figure 4 In the example shown, the UIP is the node 401 labeled j=1@2. Figure 4 Only one UIP is shown in FIG. , and the number of UIPs can be one or more depending on the structure of the implication graph.

[0094] In some embodiments, it is possible to backtrack from the found UIP to the lowest decision layer to determine the root cause point of the UIP drive associated with the UIP. For example, it is possible to backtrack from node 401 to the lowest decision layer, and determine the ATPG constraints involved during the backtracking as the root cause point of the UIP drive. In other words, the circuit features corresponding to these ATPG constraints can be considered to be the direct cause of the untestable faults at the circuit design level. Alternatively or additionally, the circuit logic unit corresponding to the UIP itself can be determined as the root cause point. Alternatively or additionally, the scan unit associated with the UIP can be determined as the root cause point. In some embodiments, the direct cause of the circuit design level corresponding to the root cause point, such as a specific ATPG constraint or a specific circuit structure, can be provided to the user to assist the user in quickly iterating the testability design.

[0095] In some embodiments, for a single fault, multiple rollbacks and updates can be performed to generate multiple reasoning processes and update the implication graph multiple times. One or more root causes can be determined from each updated implication graph to form a root cause set. Using this root cause set, the causes of conflicts can be better analyzed based on historical decisions, for example, identifying root causes that are more likely to lead to conflicts.

[0096] In some embodiments, based on the root cause point set, the root cause points in the root cause point set can be sorted by frequency to determine one or more frequently occurring root cause points as the cause of untestable faults at the circuit design level. In some examples, the frequently occurring root cause points may be logic that must be satisfied during the solution process, but is difficult to satisfy due to necessary circuit design constraints or excessive logic depth. For example, in Figure 4 In the example shown, node 401 marked as j=1@2, node 402 marked as h=1@1, and node 403 marked as block node may be root cause points that appear frequently during the solution process, which means that these nodes may be nodes that must meet specific logical values ​​regardless of any decision but cannot be met due to constraints.

[0097] Additionally or alternatively, for multiple faults, the identified root causes can be grouped into a root cause set, and a set cover algorithm can be applied to the root cause set to identify one or more root causes that cover as many faults as possible, as the causes of untestable faults at the circuit design level. In this way, by analyzing these root causes, the circuit design can be rapidly iterated to improve fault coverage.

[0098] In some embodiments, the processor may also generate candidate solutions for resolving the untestable fault based on the determined cause of the untestable fault. For example, the processor may provide the candidate solutions to a user through a user interface to assist the user in modifying the circuit design or constraints to improve fault coverage. In some embodiments, the corresponding candidate solutions may be determined based on the constructed conflict conditions and the determined root cause.

[0099] In some examples, when resolving test cube conflicts, candidate solutions can be generated based on the ATPG constraints, circuit structure, circuit test points, and / or circuit observation points associated with the root cause. For example, based on the frequency and decision-level information of the root cause, the user can be advised to add test point locations and test circuit structures to reduce the hierarchy depth. For example, if a high-frequency root cause repeatedly fails to solve when the value is 1, the user can be advised to add test points to increase the probability of its value being 0. If the high-frequency root cause is on the propagation path, the corresponding observation point can be recommended.

[0100] In some examples, for compression conflicts, candidate solutions can be generated based on the circuit constraints associated with the root cause. For example, a circuit constraint change can be recommended to reduce the specified bits used by the test cube in a particular scan unit. In some examples, candidate solutions can be generated based on the aggregation of multiple scan units associated with the root cause. For example, if the root cause is found to be clustered, the cause of the compression solution failure may be the presence of an aggregated logic cluster. Therefore, the corresponding circuit location can be found based on the root cause, and the user can be advised to interrupt the aggregated logic cluster based on the root cause, thereby reducing compression failures caused by the aggregation of specified bits.

[0101] In some examples, for power consumption conflicts, candidate solutions can be generated based on the ATPG constraints associated with the root cause points. For example, it can be suggested to modify the ATPG constraints to change the scan cells used, thereby reducing power consumption by reducing the number of scan cells used. Additionally or alternatively, candidate solutions can be generated based on the aggregation of multiple scan cells associated with the root cause points. For example, for capturing untestable faults caused by power consumption limits, if the scan cells used in the fault cone are relatively dense, or if a root cause point is found to be associated with a large number of scan cells, it can be suggested to add a clock gating unit associated with the aggregation of multiple scan cells at the corresponding root cause point, and it is suggested that the user try to meet the test power consumption limit by turning off more clocks. Additionally or alternatively, candidate solutions can be generated based on the test power consumption limit. For example, if after multiple iterative modifications, the coverage is still very low under the current test power consumption limit, the user can be suggested to modify the test power consumption limit.

[0102] References Figures 1 to 4 A scheme for ATPG according to some embodiments of the present disclosure is described. This scheme is based on implication graphs and conflict learning based on them. Therefore, compared with simple root cause analysis systems based only on circuit structure, it can discover and report constraint root causes and circuit structure root causes corresponding to implicit logical causes (for example, UIPs obtained from conflict learning), thereby promoting rapid yield rate increase. In addition, in this scheme, various types of conflict conditions, such as compression conflicts and power consumption conflicts, can also be constructed to analyze the causes of more types of untestable faults, so as to achieve the location and root cause analysis of a wider range of untestable faults.

[0103] The following will refer to Figures 5 to 13 The specific implementation of the scheme for ATPG according to some embodiments of the present disclosure is further described. Figure 5 A schematic diagram illustrates an example process 500 for root cause analysis of ATPG according to some embodiments of the present disclosure. Process 500 can be considered a specific example of process 200. Process 500 can be implemented by any suitable computing unit. For example, it can be executed by a computer or other electronic device with computing or circuit design capabilities. Specifically, for example, a computer processor can execute an EDA tool based on data and / or instructions stored in a memory to perform process 500.

[0104] like Figure 5 As shown, in box 501, the processor starts to execute ATPG. In box 502, the processor performs decision and implication relationship reasoning, and constructs an implication graph in box 503. In box 504, the processor checks whether a conflict occurs. If no conflict occurs, it can be considered that the solution is successful, and the processor ends process 500 at box 505. If a conflict occurs, the processor obtains conflict cause information from the conflict learning in box 506, such as one or more UIPs. In box 507, the processor further finds out the reason why the fault is untestable from the conflict cause information, that is, the direct cause of the UIP driving root cause point and the corresponding circuit design level. In some embodiments, the processor can also generate candidate solutions to solve untestable faults based on the reason why the fault is untestable, such as adjusting constraints or circuit structures. After a specific candidate solution is selected and executed, the processor can re-execute ATPG in box 508.

[0105] In some embodiments, the root cause analysis solution for ATPG according to the embodiments of the present disclosure can be integrated into existing ATPG tools, or can be added to existing ATPG tools as an independent debugging system in the form of an additional plug-in, thereby assisting DFT engineers in debugging low coverage issues and quickly iterating test circuit designs. In the entire test process, the solution provided by the embodiments of the present disclosure can be applied in the early stages of design to support users in interactive debugging, thereby quickly improving fault coverage. For example, users can directly modify constraints or test points to regenerate test vectors and repeatedly iterate the circuit until the expected coverage is achieved.

[0106] Figure 6 Schematic diagram of an example operation process 600 of an ATPG tool that can implement some embodiments of the present disclosure is shown. Process 600 can be performed by, for example, a processor of a computer implementing an ATPG tool based on data and / or instructions stored in a memory. Figure 6 As shown in the figure, in a conventional ATPG flow, users can customize ATPG algorithm initialization and select a large number of untestable faults or individual faults as the target fault list for processing. The processing process includes fault grouping, fault sampling, fault simulation, test vector generation, and vector storage. Once all faults are processed, a solution report and root cause report are output.

[0107] In particular, according to some embodiments of the present disclosure, the ATPG process further includes constructing an implication graph and learning conflict cause information from the conflict, such as one or more UIPs. Figure 5 The relevant description in [1] is omitted here. When a conflict occurs, if the decision is to abort the ATPG process, the corresponding ATPG constraint cause can be identified from the conflict cause information. For example, the root cause associated with the UIP can be identified and the ATPG constraint corresponding to the root cause at the circuit design level can be determined. Conversely, if the decision is not to abort the ATPG process, the conflict cause information can be recorded for re-execution of ATPG. For example, starting from the UIP in the conflict cause information, backtracking to a lower decision level can be performed to re-perform decision and implication relationship reasoning, thereby constructing a new implication graph.

[0108] Figure 7 FIG. 7 is a schematic diagram illustrating an example operational process 700 of an interactive ATPG tool that may implement some embodiments of the present disclosure. Figure 7As shown, interactive debugging functionality can be introduced into conventional ATPG flows to implement interactive DFT root cause analysis. In some examples, when the processor determines that an ATPG constraint has caused a fault to be untestable, the user can be advised to modify the corresponding ATPG constraint to continue solving. In this case, the user can choose to modify the constraint and re-execute ATPG. In other examples, when the processor determines that an insertion point has caused a fault to be untestable, the user can be advised to reinsert the test point to continue solving. Accordingly, the user can choose to reinsert the test point and re-execute ATPG.

[0109] Figure 8 A schematic diagram illustrates an example process 800 for performing root cause analysis of conflicts in a test cube, according to some embodiments of the present disclosure. Process 800 can be considered a specific example of process 200. Process 800 can be implemented by any suitable computing unit. For example, it can be executed by a computer or other electronic device with computing or circuit design capabilities. Specifically, a computer processor can execute an EDA tool based on data and / or instructions stored in a memory to perform process 800.

[0110] like Figure 8 As shown, when a test cube solution conflict occurs and the decision is made to abort the ATPG process, the cause of the untestable fault can be determined from the conflict cause information, and the process can be terminated. For example, the root cause associated with the UIP in the conflict cause information can be identified, and the circuit constraints, ATPG constraints, or specific circuit structures corresponding to the root cause at the circuit design level can be determined. Conversely, if the decision is not to abort the ATPG process, the decision can be backtracked from the UIP in the conflict cause information to lower decision levels to re-perform decision-making and implication reasoning, i.e., re-execute ATPG. When no test cube solution conflict occurs for a specific fault, the test cube solution for that fault is complete.

[0111] Figure 9 A schematic diagram illustrates an example process 900 for root cause analysis of conflict resolutions other than test cube conflict resolutions, according to some embodiments of the present disclosure. Process 900 can be considered a specific example of process 200. Process 900 can be implemented by any suitable computing unit. For example, it can be executed by a computer or other electronic device with computing or circuit design capabilities. Specifically, for example, a computer processor can execute an EDA tool based on data and / or instructions stored in a memory to perform process 900.

[0112] Other conflicts besides those resolved for the test cube may include the compression conflict and / or power consumption conflict discussed above, as well as any other suitable conflict types. Figure 9 As shown, if the test cube is successfully solved but other conflicts occur, causing the fault solution to fail, the conflict cause information can be similarly learned from the conflict, which is the reference above. Figures 2 to 4 The process of determining one or more UIPs from the conflicting nodes in the implication graph is described. Based on the conflicting cause information obtained, the cause of the undetectable fault can be further determined, that is, the cause of the undetectable fault can be further determined. Figures 2 to 4 The process described above determines one or more UIP driver root causes from the conflict nodes in the implication graph. Figure 8 Unlike the process 800 for resolving conflicts for testcube, the process 900 may not involve backtracking from the UIP determined based on other conflict resolutions, but only provide root cause analysis.

[0113] Figure 10 A schematic diagram showing a comparison between a test cube conflict resolution method and other conflict resolution methods according to some embodiments of the present disclosure is shown. Figure 10 As shown, in the combinatorial logic circuit portion (combinational portion), for a specific fault (marked as f), a logic value conflict (i.e., j=1@1, j=0@1) may occur at node 1001, resulting in a test cube solution conflict. This type of conflict node can be marked as a D-conf node. On the contrary, if no test cube solution conflict occurs and the test cube has been generated, other solution conflicts may still occur at a specific node 1002, resulting in a failure to solve the fault f. This type of conflict node can be marked as a C-conf node. Other examples of solution conflicts include the compression conflict and power consumption conflict described above. For example, if the compression check failure record of the previous fault solution records that the solution failed multiple times when the bit of the scan register (scan reg) k is 1, then during the reasoning process, when node 1002 is assigned k=1@1, it can be considered that a compression conflict has occurred.

[0114] Figure 11 A schematic diagram of an example process 1100 for root cause analysis of compression conflicts according to some embodiments of the present disclosure is shown. Process 1100 can be considered a specific example of process 200. Process 1100 can be implemented by any suitable computing unit. For example, it can be executed by a computer or other electronic device with computing or circuit design capabilities. Specifically, for example, an EDA tool can be implemented by a computer processor based on data and / or instructions stored in a memory to execute process 1100. Figure 11As shown, after executing ATPG to generate a test cube, it is possible to check whether the individual test cubes can meet the compression constraints. If the compression fails, that is, the compression constraints are not met, the failed cycle information (failed cycle info) can be recorded and then ATPG can be re-executed. The failed cycle information can include the specified bits of the specific scan unit recorded in the compression check failure record. Although not shown, the processor can provide the user with one or more UIPs associated with the specific bits of the specific scan unit in the failed cycle information and the root cause points obtained from these UIPs. The user can modify the constraints or circuit structure corresponding to the root cause points accordingly and then re-execute ATPG.

[0115] Specifically, re-executing ATPG may include re-solving the test cube and determining whether a test cube resolution conflict occurs. If the test cube is regenerated, the processor may continue to determine whether a compression conflict occurs. If no compression conflict occurs and fault resolution is complete, process 1100 may end. Conversely, if a compression conflict occurs, the processor may learn from the conflict to obtain conflict cause information, such as one or more UIPs that cause a specific bit of a specific scan unit to be used. The processor may further determine the cause of the untestable fault based on the conflict cause information, for example, by determining the root cause at the circuit design level from these UIPs.

[0116] Figure 12 Schematic diagram showing example root causes of compression conflicts according to some embodiments of the present disclosure. Figure 12 As shown in FIG, in the combinatorial logic circuit portion, the root cause of the use of the specified bit in the solution process of the current fault (labeled as fa) can be analyzed, namely, the combinatorial logic circuit structures (comblogic) 1201 and 1202. Figure 12 As shown, the corresponding specified bits are scanned into and out of specific scan cells 1203 and 1204 through the scan chain. The processor can further determine an associated constraint 1205 (labeled as constraint n=0@0) based on the root cause. In some embodiments, constraint 1205 can be provided to the user as a cause of the untestable fault. The processor can also provide the user with the following suggestion: by changing constraint 1205, the ATPG process can reduce the number of specified bits used by the generated test cube.

[0117] Figure 13A schematic diagram of an example process 1300 for root cause analysis of power consumption conflicts according to some embodiments of the present disclosure is shown. Process 1300 can be considered a specific example of process 200. Process 1300 can be implemented by any suitable computing unit. For example, it can be executed by a computer or other electronic device with computing or circuit design capabilities. Specifically, for example, an EDA tool can be implemented by a computer processor based on data and / or instructions stored in a memory to execute process 1300. Figure 13 As shown in FIG, after executing ATPG to generate test cubes, the test cubes can be merged and it can be determined whether the power consumption limit can be met.

[0118] If the shift power consumption check fails, that is, the shift power consumption limit is not met, the scan cell information of the failed test cube can be recorded, and then ATPG can be re-executed. The recorded cell information may include one or more specific scan cells recorded in the shift power consumption check failure record. Similarly, if the capture power consumption check fails, that is, the capture power consumption limit is not met, the scan cell information of the failed test cube can be recorded, and then ATPG can be re-executed. The recorded cell information may include one or more specific scan cells recorded in the capture power consumption check failure record. Although not shown, the processor can provide the user with one or more UIPs associated with the specific scan cells in the recorded cell information and the root cause points obtained from these UIPs. The user can modify the constraints or circuit structure corresponding to the root cause points accordingly, and then re-execute ATPG.

[0119] Specifically, re-executing ATPG may include re-solving the test cube and determining whether a test cube resolution conflict occurs. If the test cube is regenerated, the processor may continue to determine whether a power consumption conflict occurs. If no power consumption conflict occurs and fault resolution is complete, process 1300 may terminate. Conversely, if a power consumption conflict occurs, the processor may learn from the conflict to obtain conflict cause information, such as one or more UIPs that caused a specific scan unit to be used. The processor may further determine the cause of the untestable fault based on the conflict cause information, for example, by determining the root cause at the circuit design level from these UIPs.

[0120] In some examples, the processor may provide the ATPG constraints corresponding to the root cause points to the user, and may provide the following suggestions to the user: try to change the cells used by changing the ATPG constraints, thereby reducing the number of cells used to reduce power consumption. In some examples, for untestable faults caused by capture power consumption limits, if a root cause point is found to be associated with a large number of scan cells, the user may be advised to add a clock gating unit associated with the aggregation of multiple scan cells at the corresponding root cause point, and the user may be advised to try to meet the capture power consumption limits by turning off more clocks. In other examples, the user may also be advised to modify the test power consumption limits.

[0121] References Figures 1 to 13 This paper describes a solution for ATPG according to some embodiments of the present disclosure. By analyzing untestable faults in circuit designs using inferred process information, this solution can more directly pinpoint the causes of untestable faults and address low coverage. Furthermore, this solution provides end-to-end analysis, offering users candidate solutions for resolving untestable faults. This helps engineers quickly iterate test circuit designs in the early stages of production, accelerating yield improvement.

[0122] Example devices and equipment

[0123] Figure 14 FIG1 shows a block diagram of an apparatus 1400 for automatic test vector generation according to an embodiment of the present disclosure. Specifically, the apparatus 1400 may be an EDA software apparatus. The apparatus 1400 may include multiple modules for performing the following steps: Figure 2 The corresponding steps in the process discussed in Figure 14 As shown, the apparatus 1400 includes: a construction unit 1410, configured to: construct an implication graph based on a process of performing reasoning on a circuit design using an automatic test vector generation algorithm, wherein the implication graph indicates multiple results obtained by multiple decisions during the reasoning process; a conflict determination unit 1420, configured to: determine at least one unique implication point in the implication graph based on determining that the multiple results satisfy a conflict condition; and an analysis unit 1430, configured to: determine a cause of an untestable fault of the circuit design by analyzing the at least one unique implication point.

[0124] In some embodiments, the type of the untestable fault includes at least one of the following: an automatic test vector generation solution fails to generate a test vector stimulus, a test vector stimulus generated by the automatic test vector generation solution does not meet a compression constraint, or a test vector stimulus generated by the automatic test vector generation solution does not meet a test power consumption constraint. In some embodiments, the apparatus 1400 further includes a generation unit configured to generate a candidate solution for resolving the untestable fault based on the determined cause of the untestable fault.

[0125] In some embodiments, the conflict condition includes a first conflict condition associated with a failure in automatic test vector generation solution, and the device 1400 also includes a first conflict construction unit, which is configured to: construct the first conflict condition, and the first conflict condition indicates that a logic value conflict occurs at the same node in the circuit design.

[0126] In some embodiments, the apparatus 1400 further includes a backtracking unit configured to: update the implication graph by backing off and updating at least one of the multiple decisions based on determining that the multiple results satisfy the first conflict condition; and determine one or more unique implication points from the updated implication graph for determining the cause of the untestable fault of the circuit design.

[0127] In some embodiments, the analysis unit 1430 is further configured to: determine a root cause point set based on the at least one unique implication point and the one or more unique implication points; sort the root cause points in the root cause point set according to frequency or perform a set covering algorithm on the root cause points in the root cause point set to determine at least one root cause point in the root cause point set; and determine a cause of the untestable fault of the circuit design based on the at least one root cause point.

[0128] In some embodiments, the analyzing unit 1430 is further configured to determine at least one of the following items associated with the at least one root cause point: an automatic test vector generation constraint, a circuit structure, a circuit test point, or a circuit observation point.

[0129] In some embodiments, the conflict condition includes a second conflict condition associated with an automatic test vector generation compression limit, and the apparatus 1400 further includes a second conflict constructing unit configured to construct the second conflict condition, wherein the second conflict condition indicates that a first predetermined scan unit of the circuit design is set to a predetermined value. In some embodiments, the first predetermined scan unit and the predetermined value are determined based on a record that a previous automatic test vector generation compression of the circuit design did not meet the automatic test vector generation compression limit.

[0130] In some embodiments, the conflict determination unit 1420 is further configured to: based on determining that the multiple results satisfy the second conflict condition, determine at least one unique implication point in the implication graph that causes the first predetermined scanning unit to be set to the predetermined value.

[0131] In some embodiments, the analysis unit 1430 is further configured to: determine at least one root cause point by analyzing the at least one unique implication point; and determine at least one of the following items associated with the at least one root cause point for the circuit design: a circuit design constraint or an aggregation of multiple scan units.

[0132] In some embodiments, the conflict condition includes a third conflict condition associated with a test power consumption limit, and the apparatus 1400 further includes a third conflict constructing unit configured to construct the third conflict condition, wherein the third conflict condition indicates that a second predetermined scan unit of the circuit design is used. In some embodiments, the second predetermined scan unit is determined based on a record that a previous automatic test vector generation for the circuit does not meet the test power consumption limit.

[0133] In some embodiments, the conflict determination unit 1420 is further configured to: determine at least one unique implication point in the implication graph that causes the second predetermined scanning unit to be used based on determining that the multiple results satisfy the third conflict condition.

[0134] In some embodiments, the test power consumption limit includes a shift power consumption limit, and the analyzing unit 1430 is further configured to: determine at least one root cause point by analyzing the at least one unique implication point; and determine an ATPG constraint associated with the at least one root cause point for the circuit design.

[0135] In some embodiments, the testing power consumption limit includes capturing power consumption limit, and the analysis unit 1430 is further configured to: determine at least one root cause point by analyzing the at least one unique implication point; and determine an aggregation of multiple scan units associated with the at least one root cause point for the circuit design.

[0136] In some embodiments, the device 1400 also includes a first generation unit, which is configured to: generate a first candidate solution for solving the untestable fault, the first candidate solution including at least one of the following: adding a gated clock unit associated with the aggregation of the multiple scan units; or adjusting the capture power consumption limit.

[0137] Figure 15A schematic block diagram of an example device 1500 that can be used to implement an embodiment of the present disclosure is shown. As shown, device 1500 includes a computing unit 1501 that can perform various appropriate actions and processes based on computer program instructions stored in a random access memory (RAM) 1503 and / or a read-only memory (ROM) 1502 or loaded from a storage unit 1508 into the RAM 1503 and / or ROM 1502. Various programs and data required for the operation of device 1500 may also be stored in the RAM 1503 and / or ROM 1502. Computing unit 1501 and RAM 1503 and / or ROM 1502 are connected to each other via a bus 1504. An input / output (I / O) interface 1505 is also connected to bus 1504.

[0138] Various components in device 1500 are connected to I / O interface 1505, including an input unit 1506, such as a keyboard and mouse; an output unit 1507, such as various types of displays and speakers; a storage unit 1508, such as a magnetic disk and optical disk; and a communication unit 1509, such as a network card, a modem, a wireless communication transceiver, etc. Communication unit 1509 allows device 1500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0139] Computing unit 1501 may be a variety of general-purpose and / or specialized processing components with processing and computing capabilities. Some examples of computing unit 1501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. Computing unit 1501 performs the various methods and processes described above, such as process 200. For example, in some embodiments, process 200 may be implemented as a computer software program, specifically an EDA program, which is tangibly embodied in a machine-readable medium, such as storage unit 1508. In some embodiments, part or all of the computer program may be loaded and / or installed onto device 1500 via RAM and / or ROM and / or communication unit 1509. When the computer program is loaded into RAM and / or ROM and executed by computing unit 1501, one or more steps of process 200 described above may be performed. Alternatively, in other embodiments, the computing unit 1501 may be configured to perform the process 200 in any other appropriate manner (eg, by means of firmware).

[0140] In the above embodiments, the method flow can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a server or terminal, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a server or terminal or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, and a tape, etc.), an optical medium (e.g., a digital video disk (DVD), etc.), or a semiconductor medium (e.g., a solid-state drive, etc.).

[0141] In addition, although adopting specific order to describe each operation, this should be understood as requiring such operation to be carried out in the specific order shown or in sequential order, or requiring that all illustrated operations should be carried out to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although comprising some specific implementation details in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation also can be implemented in a plurality of implementations individually or in the mode of any suitable subcombination.

[0142] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A method for automatic test vector generation, characterized in that include: Based on a process of performing reasoning on a circuit design using an automatic test vector generation algorithm, constructing an implication graph, the implication graph indicating a plurality of results obtained from a plurality of decisions during the reasoning process; determining at least one unique implication point in the implication graph based on determining that the plurality of results satisfy a conflict condition; as well as By analyzing the at least one unique implication point, a cause of an untestable fault in the circuit design is determined.

2. The method according to claim 1, characterized in that The type of the undetectable fault includes at least one of the following: The automatic test vector generation solution fails and no test vector stimulus is generated, the test vector stimulus generated by the automatic test vector generation solution does not meet the compression limit, or the test vector stimulus generated by the automatic test vector generation solution does not meet the test power consumption limit.

3. The method according to claim 1 or 2, characterized in that Also includes: Based on the determined cause of the untestable fault, candidate solutions for resolving the untestable fault are generated.

4. The method according to any one of claims 1 to 3, characterized in that The conflict condition includes a first conflict condition associated with a failure to resolve the automatic test vector generation, the method further comprising: A first conflict condition is constructed, where the first conflict condition indicates that a logic value conflict occurs at a same node in the circuit design.

5. The method according to claim 4, characterized in that Also includes: updating the implication graph by rolling back and updating at least one decision of the plurality of decisions based on determining that the plurality of outcomes satisfy the first conflict condition; as well as One or more unique implication points are determined from the updated implication graph for use in determining the cause of the untestable failure of the circuit design.

6. The method according to claim 5, characterized in that Determining a cause of an untestable fault in the circuit design by analyzing the at least one unique implication point includes: Determining a root cause point set based on the at least one unique implication point and the one or more unique implication points; Sort the root cause points in the root cause point set according to frequency or perform a set covering algorithm on the root cause points in the root cause point set to determine at least one root cause point in the root cause point set; and Based on the at least one root cause point, a cause of an untestable failure of the circuit design is determined.

7. The method according to claim 6, characterized in that Determining a cause of an untestable fault of the circuit design based on the at least one root cause point includes determining at least one of the following associated with the at least one root cause point: Automatic test vector generation constraints, circuit structures, circuit test points or circuit observation points.

8. The method according to any one of claims 1 to 7, characterized in that The conflicting condition includes a second conflicting condition associated with an automatic test vector generation compression limit, the method further comprising: The second conflict condition is constructed, the second conflict condition indicating that a first predetermined scan cell of the circuit design is set to a predetermined value.

9. The method according to claim 8, characterized in that The first predetermined scan unit and the predetermined value are determined based on a record of previous automatic test vector generation compression of the circuit design not meeting the automatic test vector generation compression constraint.

10. The method according to claim 9, characterized in that Based on determining that the multiple results satisfy a conflict condition, determining at least one unique implication point in the implication graph includes: Based on determining that the plurality of results satisfy the second conflict condition, at least one unique implication point in the implication graph is determined that causes the first predetermined scanning unit to be set to the predetermined value.

11. The method according to claim 10, characterized in that Determining the cause of the untestable fault of the circuit design by analyzing the at least one unique implication point includes: Determine at least one root cause point by analyzing the at least one unique implication point; and At least one of the following associated with the at least one root cause point is determined for the circuit design: a circuit design constraint or an aggregation of a plurality of scan cells.

12. The method according to any one of claims 1 to 11, characterized in that The conflicting conditions include a third conflicting condition associated with testing power consumption limits, the method further comprising: The third conflict condition is constructed, the third conflict condition indicating that a second predetermined scan cell of the circuit design is used.

13. The method according to claim 12, characterized in that The second predetermined scan unit is determined based on a record that a previous automatic test vector generation for the circuit did not meet the test power consumption constraint.

14. The method according to claim 13, characterized in that Based on determining that the multiple results satisfy a conflict condition, determining at least one implication point in the implication graph includes: Based on determining that the plurality of results satisfy the third conflict condition, at least one unique implication point in the implication graph that causes the second predetermined scanning unit to be used is determined.

15. The method according to any one of claims 12 to 14, characterized in that The test power consumption limit includes a shift power consumption limit, and determining the cause of the untestable fault of the circuit design by analyzing the at least one unique implication point includes: Determine at least one root cause point by analyzing the at least one unique implication point; and ATPG constraints associated with the at least one root cause point are determined for the circuit design.

16. The method according to any one of claims 12 to 15, characterized in that The testing power consumption limit includes capturing the power consumption limit, and determining the cause of the untestable fault of the circuit design by analyzing the at least one unique implication point includes: Determine at least one root cause point by analyzing the at least one unique implication point; and An aggregation of a plurality of scan cells associated with the at least one root cause point for the circuit design is determined.

17. The method according to claim 16, characterized in that The method further includes generating a first candidate solution for resolving the untestable fault, the first candidate solution comprising at least one of the following: adding a clock gating unit associated with the aggregation of the plurality of scan units; or The capture power consumption limit is adjusted.

18. A device for automatic test vector generation, characterized in that: include: A construction unit is configured to: construct an implication graph based on a process of performing reasoning on a circuit design using an automatic test vector generation algorithm, wherein the implication graph indicates multiple results obtained from multiple decisions in the process of reasoning; a conflict determination unit configured to: determine at least one unique implication point in the implication graph based on determining that the multiple results satisfy a conflict condition; as well as The analyzing unit is configured to determine a cause of the untestable fault of the circuit design by analyzing the at least one unique implication point.

19. An electronic device comprising: at least one computing unit; At least one memory coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions, when executed by the at least one computing unit, causing the electronic device to perform the method according to any one of claims 1 to 17.

20. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the method according to any one of claims 1 to 17 is implemented.

21. A computer program product comprising computer executable instructions, wherein the computer executable instructions, when executed by a processor, implement the method according to any one of claims 1 to 17.

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