Board card correction method and device, board card and storage medium

Abstract

The embodiment of the invention provides a board card correction method and device, a board card and a storage medium, and relates to the field of satellite communication. The method comprises the following steps of: acquiring a transmitting power calibration value and a receiving power calibration value which are measured in advance by an FPGA (Field Programmable Gate Array) of a board card, and acquiring a transmitting frequency point of a transmitting channel and a receiving frequency point of a receiving channel which are configured by a CPU (Central Processing Unit) according to a frequency point configuration strategy corresponding to carrier leakage correction when receiving a load leakage correction starting signal sent by the CPU; detecting the single carrier frequency power of a transmitting frequency point and the carrier leakage frequency power of a receiving frequency point under the condition that the CPU controls the transmitting channel to transmit the load leakage test signal; and carrying out carrier leakage correction on the board card according to the single carrier frequency power, the carrier leakage frequency power, the transmitting power calibration value and the receiving power calibration value, thereby realizing automatic carrier leakage correction on the board card without manual intervention and manual adjustment, and improving correction accuracy by introducing the transmitting power calibration value and the receiving power calibration value.

Description

Technical Field

[0001] The present invention relates to the field of satellite communications, and in particular to a board calibration method, device, board and storage medium. Background Art

[0002] Satellite communication systems transmit data through wireless links between "earth stations" (ground equipment) and "satellites". Satellite communication systems require high-precision and high-reliability signal transmission to ensure data integrity and communication quality.

[0003] Carrier leakage occurs when the carrier component of the transmitted signal is not fully suppressed and leaks into the receiving channel, causing nonlinear effects and generating image signals. This leakage can cause image signals and other spurious signals in the receiving channel, affecting communication quality and system performance.

[0004] To solve these problems, engineers usually need to manually calibrate the boards in the satellite terminal, which requires a lot of manpower and time. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a board calibration method, device, board and storage medium.

[0006] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, the present invention provides a board calibration method, which is applied to an FPGA of a board, wherein a transmitting channel and a receiving channel of the board are connected via a radio frequency cable, and the board further includes a CPU, the method comprising: Obtaining a pre-measured transmit power calibration value and receive power calibration value; wherein the transmit power calibration value is obtained based on the output level of the transmit channel, the configuration value of the transmit channel, and the line loss parameter of the RF cable measured by the spectrum analyzer; and the receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer; Upon receiving a carrier leakage correction start signal sent by the CPU, obtaining a transmit frequency of the transmit channel and a receive frequency of the receive channel configured by the CPU according to a frequency configuration strategy corresponding to the carrier leakage correction; When the CPU controls the transmitting channel to transmit a carrier leakage test signal, detecting the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point; Carrier leakage correction is performed on the board according to the single carrier frequency power, the carrier leakage frequency power, the transmit power calibration value, and the receive power calibration value.

[0007] Optionally, the step of performing carrier leakage correction on the board according to the single carrier frequency power, the carrier leakage frequency power, the transmit power calibration value, and the receive power calibration value includes: Performing path loss correction on the single carrier frequency power using the transmit power calibration value to obtain a corrected single carrier frequency power; Performing path loss correction on the carrier leakage frequency power using the received power calibration value to obtain a corrected carrier leakage frequency power; Calculating a first power difference between the corrected single carrier frequency power and the corrected carrier leakage frequency power; If the first power difference does not meet the first preset condition, adjust the two first registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point until the first power difference meets the first preset condition, wherein the first register is a register related to carrier leakage.

[0008] Optionally, the method further includes: After the carrier leakage correction is completed, an interrupt signal is sent to the CPU so that the CPU reconfigures the transmit frequency of the transmit channel and the receive frequency of the receive channel according to the frequency configuration strategy corresponding to the transmit mirror frequency correction, and sends a transmit mirror frequency correction start signal to the FPGA.

[0009] Optionally, the method further includes: Upon receiving a transmit mirror frequency correction start signal sent by the CPU, obtaining a transmit frequency point of the transmit channel and a receive frequency point of the receive channel configured by the CPU according to a frequency configuration strategy corresponding to the transmit mirror frequency correction; When the CPU controls the transmitting channel to transmit a first image frequency test signal, detecting the single carrier frequency power of the transmitting frequency point and the transmitting image frequency power of the receiving frequency point; Performing path loss correction on the single carrier frequency power using the transmit power calibration value to obtain a corrected single carrier frequency power; Performing path loss correction on the transmit image frequency power using the receive power calibration value to obtain a corrected transmit image frequency power; Calculating a second power difference between the corrected single carrier frequency power and the corrected transmit image frequency power; If the second power difference does not meet the second preset condition, adjust the three second registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the transmit image frequency power of the receiving frequency point until the second power difference meets the second preset condition, wherein the second register is a register related to the transmit image frequency.

[0010] Optionally, the method further includes: After the transmit image frequency correction is completed, an interrupt signal is sent to the CPU so that the CPU reconfigures the transmit frequency of the transmit channel and the receive frequency of the receive channel according to the frequency configuration strategy corresponding to the receive image frequency correction, and sends a receive image frequency correction start signal to the FPGA.

[0011] Optionally, the method further includes: Upon receiving a receiving image frequency correction start signal sent by the CPU, obtaining a transmitting frequency point of the transmitting channel and a receiving frequency point of the receiving channel configured by the CPU according to a frequency configuration strategy corresponding to the receiving image frequency correction; When the CPU controls the transmitting channel to transmit a second image frequency test signal, detecting the single carrier frequency power of the transmitting frequency point and the receiving image frequency power of the receiving frequency point; Performing path loss correction on the single carrier frequency power using the transmit power calibration value to obtain a corrected single carrier frequency power; Performing path loss correction on the received image frequency power using the received power calibration value to obtain a corrected received image frequency power; Calculating a third power difference between the corrected single carrier frequency power and the corrected received image frequency power; If the third power difference does not satisfy the third preset condition, adjust the three third registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the reception image frequency power of the receiving frequency point until the third power difference satisfies the third preset condition, wherein the third register is a register related to the reception image frequency.

[0012] Optionally, the board further includes a memory, and the method further includes: After the carrier leakage correction, transmit image frequency correction or receive image frequency correction is completed, corresponding carrier leakage correction parameters, transmit image frequency correction parameters or receive image frequency correction parameters are generated and sent to the CPU, so that the CPU writes the carrier leakage correction parameters, transmit image frequency correction parameters or receive image frequency correction parameters into the memory, and calls the carrier leakage correction parameters, transmit image frequency correction parameters or receive image frequency correction parameters stored in the memory when the board is running.

[0013] In a second aspect, the present invention provides a board calibration device, which is applied to an FPGA of a board, wherein a transmitting channel and a receiving channel of the board are connected via a radio frequency cable, and the board also includes a CPU, and the device includes: an acquisition module, configured to obtain a pre-measured transmit power calibration value and a receive power calibration value; wherein the transmit power calibration value is obtained based on the output level of the transmit channel, the configuration value of the transmit channel, and the line loss parameter of the RF cable measured by the spectrum analyzer, and the receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer; upon receiving a carrier leakage correction start signal sent by the CPU, obtaining the transmit frequency point of the transmit channel and the receive frequency point of the receive channel configured by the CPU according to the frequency point configuration strategy corresponding to the carrier leakage correction; The correction module is used to control the transmission channel to transmit a carrier leakage test signal and detect the single carrier frequency power of the transmission frequency point and the carrier leakage frequency power of the receiving frequency point; and perform carrier leakage correction on the board according to the single carrier frequency power, the carrier leakage frequency power, the transmission power calibration value and the receiving power calibration value.

[0014] In a third aspect, the present invention provides a board card comprising a CPU and an FPGA, wherein the CPU sends a correction start signal to the FPGA, and the FPGA executes machine executable instructions according to the correction start signal to implement the board card correction method described in the first aspect.

[0015] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by an FPGA, implements the board correction method as described in the first aspect above.

[0016] The board calibration method, device, board and storage medium provided by the embodiment of the present invention are that the FPGA of the board obtains a pre-measured transmit power calibration value and a receive power calibration value, wherein the transmit power calibration value is obtained based on the output level of the transmit channel measured by the spectrum analyzer, the configuration value of the transmit channel and the line loss parameter of the RF cable, and the receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer; when a carrier leakage correction start signal sent by the CPU is received, the transmit frequency point of the transmit channel and the receive frequency point of the receive channel configured by the CPU according to the frequency point configuration strategy corresponding to the carrier leakage correction are obtained; when the CPU controls the transmit channel to transmit a carrier leakage test signal, the single carrier frequency power of the transmit frequency point and the carrier leakage frequency power of the receive frequency point are detected; and carrier leakage correction is performed on the board according to the single carrier frequency power, the carrier leakage frequency power, the transmit power calibration value and the receive power calibration value. Since the embodiment of the present invention realizes automatic carrier leakage correction of the board through FPGA control and CPU instruction scheduling, no manual adjustment is required. In addition, by introducing the transmit power calibration value and the receive power calibration value, the path loss in the radio frequency link is accurately compensated, ensuring that the measured value truly reflects the signal status, thereby improving the correction accuracy.

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A schematic structural block diagram of a board provided by an embodiment of the present invention is shown; Figure 2 A logical function framework diagram of an FPGA-PL provided by an embodiment of the present invention is shown; Figure 3 The schematic diagram of the process of a board calibration method provided by an embodiment of the present invention is shown. Figure 1 ; Figure 4 A schematic diagram showing the principle of board leakage and image frequency correction provided by an embodiment of the present invention is shown; Figure 5 The schematic diagram of the process of a board calibration method provided by an embodiment of the present invention is shown. Figure 2 ; Figure 6 The schematic diagram of the process of a board calibration method provided by an embodiment of the present invention is shown. Figure 3 ; Figure 7 A functional module block diagram of a board calibration device provided by an embodiment of the present invention is shown.

[0020] Icon: 100-board calibration device; 101-acquisition module; 102-calibration module. DETAILED DESCRIPTION

[0021] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely intended to represent selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0023] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0024] Please refer to Figure 1 is a block diagram of a board. The board includes a memory, a CPU, and an FPGA. The memory, CPU, and FPGA are electrically connected to each other, directly or indirectly, to enable data transmission or interaction. For example, these components may be electrically connected via one or more communication buses or signal lines.

[0025] The memory is used to store programs or data. The memory may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM).

[0026] The CPU is used to read / write data or programs stored in the memory and execute corresponding functions.

[0027] like Figure 2As shown, the programmable logic part FPGA-PL in the FPGA includes two independent beacon demodulation channels and corresponding frequency / power statistics modules, wherein the "self-check control" module is used to implement the board calibration method provided in the embodiment of the present invention.

[0028] It should be understood that Figure 1 The structure shown is only a schematic diagram of the structure of the board, and the board may also include Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0029] Please refer to Figure 3 The board calibration method provided by the embodiment of the present invention includes steps S101 to S104.

[0030] S101: Acquire a pre-measured transmit power calibration value and a receive power calibration value.

[0031] The transmit power calibration value is obtained based on the transmit channel output level, transmit channel configuration values, and RF cable line loss parameters measured by the spectrum analyzer. The receive power calibration value is obtained based on the transmit channel output level and receive channel receive level measured by the spectrum analyzer.

[0032] In this embodiment of the present invention, a signal source and a spectrum analyzer are connected via an RF cable. The signal source output power is set to 0 dBm, and the signal source is adjusted to transmit at different frequencies (for example, in 50 MHz increments). The displayed power value at each frequency is recorded on the spectrum analyzer, and the attenuation of the RF cable at each frequency is calculated. This attenuation value is then recorded as the RF cable line loss parameter.

[0033] Connect one end of the RF cable to the transmit channel of the board under test and the other end to a spectrum analyzer. Configure the board's transmit power to 0dBm and transmit at frequencies from 950MHz to 2400MHz in 50MHz increments. Use the spectrum analyzer to measure the actual power at each frequency and calculate the transmit power calibration value. The transmit power calibration value is calculated as: spectrum analyzer display value - (transmit configuration value - line loss parameter).

[0034] Record the transmit power calibration values ​​of all frequencies for power compensation of the transmit channel during subsequent board calibration.

[0035] Directly connect the transmit and receive channels of the board under test via an RF cable. Configure the transmit and receive channels to use the same frequency, symbol rate, and roll-off factor. Set the transmit power to -10dBm. Record the transmit level displayed on the spectrum analyzer (recorded as the transmit level display value) and the background level of the receive channel (recorded as the receive level display value). Calculate the receive power calibration value. Receive power calibration value = transmit level display value - receive level display value.

[0036] The receive power calibration values ​​of all frequency points are recorded for power compensation of the receive channel.

[0037] For the board to be calibrated, first check whether the board's software version supports the self-test procedure. If not, you need to update the software and load a firmware version that supports the self-test control register, transmit / receive frequency control, and calibration parameter storage.

[0038] If the board's software version supports the self-test program, press Ctrl+C in the board's serial terminal to enter UBOOT mode and enter the command to load and start the self-test program. After the program loads, the user is prompted to enter the previously recorded transmit power calibration value and receive power calibration value for power compensation during the calibration process.

[0039] The CPU writes these two parameters into specific registers of the FPGA, such as the transmit power calibration register TX_PWR_CALIB_REG and the receive power calibration register RX_PWR_CALIB_REG.

[0040] At the beginning of the calibration process, the CPU of the board to be calibrated initializes the self-test parameters, including configuring the transmit and receive frequencies to the current test frequency (such as 950MHz, 1000MHz, etc.), setting the transmit power to -10dBm, configuring the self-test control register, and selecting the self-test items to be executed.

[0041] The self-test items include carrier leakage correction, transmit image frequency correction, and receive image frequency correction. For each frequency point to be tested, the board must perform carrier leakage correction, transmit image frequency correction, and receive image frequency correction in sequence.

[0042] S102 , upon receiving a carrier leakage correction start signal sent by the CPU, obtaining a transmitting frequency of a transmitting channel and a receiving frequency of a receiving channel configured by the CPU according to a frequency configuration strategy corresponding to the carrier leakage correction.

[0043] In this embodiment of the present invention, for the transmit channel, the CPU sets the transmit frequency to "center frequency + 1 MHz" and the transmit power to 0 dBm. For the receive channel, the CPU configures the receive frequency to "transmit frequency - 2 MHz" and enables the analog AGC function.

[0044] Carrier leakage occurs at the receiving frequency, such as Figure 4 As shown, 2MHz on the baseband is the receiving frequency.

[0045] S103 , when the CPU controls the transmitting channel to transmit a carrier leakage test signal, detecting the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point.

[0046] In the embodiment of the present invention, the carrier leakage test signal is a single carrier whose frequency is 1 MHz greater than the center frequency. The FPGA detects the single carrier frequency power at the transmitting frequency point and the carrier leakage frequency power at the receiving frequency point at the baseband.

[0047] S104 , performing carrier leakage correction on the board according to the single carrier frequency power, the carrier leakage frequency power, the transmit power calibration value, and the receive power calibration value.

[0048] In a possible implementation, the implementation process of step S104 may be: S104-1, use the transmit power calibration value to perform path loss correction on the single carrier frequency power to obtain the corrected single carrier frequency power; use the receive power calibration value to perform path loss correction on the carrier leakage frequency power to obtain the corrected carrier leakage frequency power.

[0049] The transmit power calibration value is used to correct for power losses in the transmit channel due to hardware such as RF cables, filters, and power amplifiers. The FPGA adds the measured single-carrier frequency power at the transmit frequency point to the transmit power calibration value to obtain the corrected single-carrier frequency power.

[0050] The receive power calibration value is used to correct for signal gain or attenuation deviations in the receive channel due to hardware such as the LNA, filter, and ADC. The FPGA adds the measured carrier leakage frequency power at the receive frequency to the receive power calibration value to obtain the corrected carrier leakage frequency power.

[0051] S104-2, calculating a first power difference between the corrected single carrier frequency power and the corrected carrier leakage frequency power.

[0052] S104-3, when the first power difference does not meet the first preset condition, adjust the two first registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point until the first power difference meets the first preset condition.

[0053] The first preset condition is that the first power difference is less than a first threshold, and the first register is a register related to carrier leakage, that is, a register that affects carrier leakage.

[0054] In an embodiment of the present invention, the FPGA adjusts the register values ​​of the two first registers according to the first power difference, and after each adjustment is completed, returns to the step of detecting the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point, and recalculates the first power difference.

[0055] When the calculated first power difference is less than the first threshold, the carrier leakage correction is completed. At this time, the current register values ​​of the two first registers are recorded as carrier leakage correction parameters and sent to the CPU so that the CPU writes the carrier leakage correction parameters into the memory of the board. The carrier leakage correction parameters stored in the memory can be called when the board is running.

[0056] Exemplarily, the two first registers include a bias voltage register for transmitting I path (address 0xa5) and a bias voltage register for transmitting Q path (address 0xa7). Register 0xa5 is adjusted first, and then register 0xa7 is adjusted.

[0057] The adjustment process can be: first set the transmit I bias voltage to the minimum value, then wait 100ms and record the comparison power difference. If the I bias voltage reaches the maximum at this time, then enter the adjustment of the transmit Q bias voltage.

[0058] If the I-channel bias voltage has not reached the maximum, increase the I-channel bias voltage and wait for 100ms again and record the comparison power difference. Repeat the above operation until the I-channel bias voltage reaches the maximum.

[0059] The process of adjusting the transmit Q bias voltage is as follows: set the transmit Q bias voltage to the minimum value and wait for 100ms before recording the comparison power difference. If the transmit Q bias voltage reaches the maximum at this time, the adjustment of the register values ​​of the two registers related to carrier leakage is completed.

[0060] If the transmit Q-path bias voltage has not reached the maximum, increase the Q-path bias voltage and wait for 100ms again and record the comparison power difference. Repeat the above operation until the Q-path bias voltage reaches the maximum.

[0061] Please refer to Figure 5 After step S104, the board calibration method provided by the embodiment of the present invention further includes step S105.

[0062] S105, after the carrier leakage correction is completed, an interrupt signal is sent to the CPU so that the CPU reconfigures the transmit frequency of the transmit channel and the receive frequency of the receive channel according to the frequency configuration strategy corresponding to the transmit image frequency correction, and sends a transmit image frequency correction start signal to the FPGA.

[0063] In this embodiment of the present invention, for the transmit channel, the CPU sets the transmit frequency to "center frequency ± 1 MHz" and the transmit power to 0 dBm. For the receive channel, the CPU configures the receive frequency to "transmit frequency - 2 MHz" and enables the analog AGC function.

[0064] The transmit image frequency is generated at the receiving frequency, such as Figure 4 As shown, 1MHz on the baseband is the receiving frequency.

[0065] Further, please refer again to Figure 5 After step S105, the board calibration method provided by the embodiment of the present invention further includes steps S106 to S110.

[0066] S106 , upon receiving the transmit mirror frequency correction start signal sent by the CPU, obtaining the transmit frequency of the transmit channel and the receive frequency of the receive channel configured by the CPU according to the frequency configuration strategy corresponding to the transmit mirror frequency correction.

[0067] S107 , when the CPU controls the transmitting channel to transmit a first image frequency test signal, detecting the single carrier frequency power at the transmitting frequency point and the transmitting image frequency power at the receiving frequency point.

[0068] In an embodiment of the present invention, the first image frequency test signal is a single carrier frequency that is 1 MHz offset from the center frequency. The FPGA detects the single carrier frequency power at the transmitting frequency point and the transmit image frequency power at the receiving frequency point at the baseband.

[0069] S108, using the transmit power calibration value to perform path loss correction on the single carrier frequency power to obtain the corrected single carrier frequency power; using the receive power calibration value to perform path loss correction on the transmit image frequency power to obtain the corrected transmit image frequency power.

[0070] The FPGA adds the measured single carrier frequency power at the transmit frequency point to the transmit power calibration value to obtain the corrected single carrier frequency power. The FPGA adds the measured transmit image frequency power at the receive frequency point to the receive power calibration value to obtain the corrected transmit image frequency power.

[0071] S109, calculating a second power difference between the corrected single carrier frequency power and the corrected transmit image frequency power.

[0072] S110, when the second power difference does not meet the second preset condition, adjust the three second registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the transmission image frequency power of the receiving frequency point until the second power difference meets the second preset condition.

[0073] The second preset condition is that the second power difference is less than a second threshold value, and the second register is a register related to the transmit image frequency, that is, a register that affects the transmit image frequency.

[0074] In an embodiment of the present invention, the FPGA adjusts the register values ​​of the three second registers according to the second power difference, and after each adjustment is completed, returns to the step of detecting the single carrier frequency power of the transmitting frequency point and the transmission mirror frequency power of the receiving frequency point, and recalculates the second power difference.

[0075] When the calculated second power difference is less than the second threshold, the transmit mirror frequency correction is completed. At this time, the current register values ​​of the three second registers are recorded as transmit mirror frequency correction parameters and sent to the CPU so that the CPU writes the transmit mirror frequency correction parameters into the memory of the board. The transmit mirror frequency correction parameters stored in the memory can be called when the board is running.

[0076] Exemplarily, the three second registers include the amplitude factor register of the transmit I path (address 0xa3), the amplitude factor register of the transmit Q path (address 0xa4), and the transmit phase correction value register (address 0xa9). The 0xa3 register is adjusted first, then the 0xa9 register is adjusted, and finally the 0xa4 register is adjusted.

[0077] Please refer to Figure 6 After step S110, the board calibration method provided by the embodiment of the present invention further includes step S111.

[0078] S111, after the transmit image frequency correction is completed, an interrupt signal is sent to the CPU, so that the CPU reconfigures the transmit frequency of the transmit channel and the receive frequency of the receive channel according to the frequency configuration strategy corresponding to the receive image frequency correction, and sends a receive image frequency correction start signal to the FPGA.

[0079] In the embodiment of the present invention, for the transmit channel, the CPU sets the transmit frequency to be consistent with the center frequency and the transmit power to 0 dBm. For the receive channel, the CPU configures the receive frequency to be "center frequency - 2 MHz" and enables the analog AGC function.

[0080] The receiving image frequency is generated at the receiving frequency point, such as Figure 4 As shown, -3MHz on the baseband is the receiving frequency point.

[0081] Further, please refer again to Figure 6 After step S111, the board calibration method provided by the embodiment of the present invention further includes steps S112 to S116.

[0082] S112 , upon receiving a receiving image frequency correction start signal sent by the CPU, obtaining a transmitting frequency of a transmitting channel and a receiving frequency of a receiving channel configured by the CPU according to a frequency configuration strategy corresponding to the receiving image frequency correction.

[0083] S113 , when the CPU controls the transmitting channel to transmit a second image frequency test signal, the single carrier frequency power at the transmitting frequency point and the receiving image frequency power at the receiving frequency point are detected.

[0084] In an embodiment of the present invention, the second image frequency test signal is a single carrier with a frequency consistent with the center frequency. The FPGA detects the single carrier frequency power at the transmitting frequency point and the receiving image frequency power at the receiving frequency point at the baseband.

[0085] S114, using the transmit power calibration value to perform path loss correction on the single carrier frequency power to obtain the corrected single carrier frequency power; using the receive power calibration value to perform path loss correction on the receive image frequency power to obtain the corrected receive image frequency power.

[0086] The FPGA adds the measured single carrier frequency power at the transmit frequency point to the transmit power calibration value to obtain the corrected single carrier frequency power. The FPGA adds the measured receive image frequency power at the receive frequency point to the receive power calibration value to obtain the corrected transmit image frequency power.

[0087] S115 , calculating a third power difference between the corrected single carrier frequency power and the corrected received image frequency power.

[0088] S116, when the third power difference does not satisfy the third preset condition, adjust the three third registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the receiving image frequency power of the receiving frequency point until the third power difference satisfies the third preset condition.

[0089] The third preset condition is that the third power difference is less than a third threshold value, and the third register is a register related to the received image frequency, that is, a register that affects the received image frequency.

[0090] In an embodiment of the present invention, the FPGA adjusts the register values ​​of the three third registers according to the third power difference, and after each adjustment is completed, returns to the step of detecting the single carrier frequency power of the transmitting frequency point and the receiving image frequency power of the receiving frequency point, and recalculates the third power difference.

[0091] When the calculated third power difference is less than the third threshold, the receiving image frequency correction is completed. At this time, the current register values ​​of the three third registers are recorded as receiving image frequency correction parameters and sent to the CPU, so that the CPU writes the receiving image frequency correction parameters into the memory of the board card. The receiving image frequency correction parameters stored in the memory can be called when the board card is running.

[0092] Exemplarily, the three third registers include the amplitude factor register for receiving the I path (address 0xac), the amplitude factor register for receiving the Q path (address 0xad), and the receiving phase correction value register (address 0xae). The 0xac register is adjusted first, then the 0xad register is adjusted, and finally the 0xae register is adjusted.

[0093] After the board to be corrected completes carrier leakage correction, transmit image frequency correction, and receive image frequency correction at each frequency point, the FPGA exits the self-test program, restarts the board, and loads the normal operating software version.

[0094] The FPGA automatically reads the load-leakage correction parameters, the transmit image frequency correction parameters, and the receive image frequency correction parameters from the memory and writes them into the corresponding registers.

[0095] Connect the transmit channel of the board to the spectrum analyzer and configure the transmit frequency from 950MHz to 2400MHz in 50MHz steps.

[0096] Compare the transmit power values ​​at each frequency point measured by the spectrum analyzer with the calibrated transmit power values ​​to verify calibration accuracy. Also, observe whether the transmit waveform is normal and whether there is carrier leakage or image interference.

[0097] Use the serial port or host computer tools to set up multi-frequency transmission and reception tasks, and automatically complete the re-inspection process for multiple frequencies. If any frequency does not meet the standard, you can manually correct it or feedback to the hardware team for device troubleshooting.

[0098] After the calibration recheck is completed, install a physical shielding cover on the board to reduce electromagnetic wave leakage and external interference, and improve system stability.

[0099] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: (1) Through FPGA control and CPU instruction scheduling, the key performance indicators of the board, such as carrier leakage correction, transmit image frequency correction, and receive image frequency correction, are automatically corrected without manual intervention.

[0100] (2) By introducing the transmit power calibration value and the receive power calibration value, the path loss in the RF link is accurately compensated to ensure that the measured value truly reflects the signal status, thereby improving the correction accuracy.

[0101] (3) The correction process is divided into three independent modules: carrier leakage correction, transmit image frequency correction, and receive image frequency correction. It supports on-demand startup and interrupt response mechanisms, making it easy to integrate into the communication system as a standard functional module.

[0102] (4) By comparing the detected power difference with the preset conditions, the register values ​​related to carrier leakage and image frequency suppression are dynamically adjusted to form a closed-loop feedback correction mechanism to ensure the optimal correction effect.

[0103] (5) After the calibration is completed, the FPGA sends the generated calibration parameters to the CPU and writes them into the non-volatile memory to ensure that the board automatically loads these parameters when it is restarted or running, maintaining long-term stable performance.

[0104] In order to execute the corresponding steps in the above embodiments and various possible methods, an implementation method of the board calibration device 100 is given below. Figure 7 , Figure 7 This is a functional module diagram of a board calibration device 100 provided in an embodiment of the present invention. It should be noted that the basic principles and technical effects of the board calibration device 100 provided in this embodiment are the same as those of the above-mentioned embodiments. For the sake of simplicity, any parts not mentioned in this embodiment can be referred to the corresponding contents of the above-mentioned embodiments. The board calibration device 100 includes: The acquisition module 101 is used to obtain pre-measured transmission power calibration values ​​and receiving power calibration values; wherein, the transmission power calibration value is obtained based on the output level of the transmission channel measured by the spectrum analyzer, the configuration value of the transmission channel and the line loss parameters of the RF cable, and the receiving power calibration value is obtained based on the output level of the transmission channel and the receiving level of the receiving channel measured by the spectrum analyzer; when the carrier leakage correction start signal sent by the CPU is received, the transmission frequency of the transmission channel and the receiving frequency of the receiving channel configured by the CPU according to the frequency configuration strategy corresponding to the carrier leakage correction are obtained.

[0105] The correction module 102 is used to detect the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point when the CPU controls the transmitting channel to transmit the carrier leakage test signal; and perform carrier leakage correction on the board according to the single carrier frequency power, the carrier leakage frequency power, the transmitting power calibration value and the receiving power calibration value.

[0106] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a portion of code, and the module, program segment or a portion of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0107] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0108] If the functions are implemented as software modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or the portion of the technical solution itself, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes instructions for enabling a computer device (which can be a personal computer, a card, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0109] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A board calibration method, characterized in that: An FPGA is applied to a board, wherein a transmitting channel and a receiving channel of the board are connected via a radio frequency cable, and the board also includes a CPU. The method includes: Obtaining a pre-measured transmit power calibration value and receive power calibration value; wherein the transmit power calibration value is obtained based on the output level of the transmit channel, the configuration value of the transmit channel, and the line loss parameter of the RF cable measured by the spectrum analyzer; and the receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer; Upon receiving a carrier leakage correction start signal sent by the CPU, obtaining a transmit frequency of the transmit channel and a receive frequency of the receive channel configured by the CPU according to a frequency configuration strategy corresponding to the carrier leakage correction; When the CPU controls the transmitting channel to transmit a carrier leakage test signal, detecting the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point; Carrier leakage correction is performed on the board according to the single carrier frequency power, the carrier leakage frequency power, the transmit power calibration value, and the receive power calibration value.

2. The board calibration method according to claim 1, wherein: The step of performing carrier leakage correction on the board according to the single carrier frequency power, the carrier leakage frequency power, the transmit power calibration value, and the receive power calibration value includes: Performing path loss correction on the single carrier frequency power using the transmit power calibration value to obtain a corrected single carrier frequency power; Performing path loss correction on the carrier leakage frequency power using the received power calibration value to obtain a corrected carrier leakage frequency power; Calculating a first power difference between the corrected single carrier frequency power and the corrected carrier leakage frequency power; If the first power difference does not meet the first preset condition, adjust the two first registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point until the first power difference meets the first preset condition, wherein the first register is a register related to carrier leakage.

3. The board calibration method according to claim 1, wherein: The method further comprises: After the carrier leakage correction is completed, an interrupt signal is sent to the CPU so that the CPU reconfigures the transmit frequency of the transmit channel and the receive frequency of the receive channel according to the frequency configuration strategy corresponding to the transmit mirror frequency correction, and sends a transmit mirror frequency correction start signal to the FPGA.

4. The board calibration method according to claim 3, wherein: The method further comprises: Upon receiving a transmit mirror frequency correction start signal sent by the CPU, obtaining a transmit frequency point of the transmit channel and a receive frequency point of the receive channel configured by the CPU according to a frequency configuration strategy corresponding to the transmit mirror frequency correction; When the CPU controls the transmitting channel to transmit a first image frequency test signal, detecting the single carrier frequency power of the transmitting frequency point and the transmitting image frequency power of the receiving frequency point; Performing path loss correction on the single carrier frequency power using the transmit power calibration value to obtain a corrected single carrier frequency power; Performing path loss correction on the transmit image frequency power using the receive power calibration value to obtain a corrected transmit image frequency power; Calculating a second power difference between the corrected single carrier frequency power and the corrected transmit image frequency power; If the second power difference does not meet the second preset condition, adjust the three second registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the transmit image frequency power of the receiving frequency point until the second power difference meets the second preset condition, wherein the second register is a register related to the transmit image frequency.

5. The board calibration method according to claim 4, wherein: The method further comprises: After the transmit image frequency correction is completed, an interrupt signal is sent to the CPU so that the CPU reconfigures the transmit frequency of the transmit channel and the receive frequency of the receive channel according to the frequency configuration strategy corresponding to the receive image frequency correction, and sends a receive image frequency correction start signal to the FPGA.

6. The board calibration method according to claim 5, wherein: The method further comprises: Upon receiving a receiving image frequency correction start signal sent by the CPU, obtaining a transmitting frequency point of the transmitting channel and a receiving frequency point of the receiving channel configured by the CPU according to a frequency configuration strategy corresponding to the receiving image frequency correction; When the CPU controls the transmitting channel to transmit a second image frequency test signal, detecting the single carrier frequency power of the transmitting frequency point and the receiving image frequency power of the receiving frequency point; Performing path loss correction on the single carrier frequency power using the transmit power calibration value to obtain a corrected single carrier frequency power; Performing path loss correction on the received image frequency power using the received power calibration value to obtain a corrected received image frequency power; Calculating a third power difference between the corrected single carrier frequency power and the corrected received image frequency power; If the third power difference does not satisfy the third preset condition, adjust the three third registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the reception image frequency power of the receiving frequency point until the third power difference satisfies the third preset condition, wherein the third register is a register related to the reception image frequency.

7. The board calibration method according to claim 6, wherein: The board also includes a memory, and the method further includes: After the carrier leakage correction, transmit image frequency correction or receive image frequency correction is completed, corresponding carrier leakage correction parameters, transmit image frequency correction parameters or receive image frequency correction parameters are generated and sent to the CPU, so that the CPU writes the carrier leakage correction parameters, transmit image frequency correction parameters or receive image frequency correction parameters into the memory, and calls the carrier leakage correction parameters, transmit image frequency correction parameters or receive image frequency correction parameters stored in the memory when the board is running.

8. A board calibration device, characterized in that: An FPGA is applied to a board, wherein the transmitting channel and the receiving channel of the board are connected via a radio frequency cable, the board also includes a CPU, and the device includes: an acquisition module, configured to obtain a pre-measured transmit power calibration value and a receive power calibration value; wherein the transmit power calibration value is obtained based on the output level of the transmit channel, the configuration value of the transmit channel, and the line loss parameter of the RF cable measured by the spectrum analyzer, and the receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer; upon receiving a carrier leakage correction start signal sent by the CPU, obtaining the transmit frequency point of the transmit channel and the receive frequency point of the receive channel configured by the CPU according to the frequency point configuration strategy corresponding to the carrier leakage correction; The correction module is used to detect the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point when the CPU controls the transmitting channel to transmit a carrier leakage test signal; and perform carrier leakage correction on the board according to the single carrier frequency power, the carrier leakage frequency power, the transmitting power calibration value and the receiving power calibration value.

9. A board, characterized in that: The system comprises a CPU and an FPGA, wherein the CPU sends a correction start signal to the FPGA, and the FPGA executes machine executable instructions according to the correction start signal to implement the board correction method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the FPGA, the board correction method according to any one of claims 1 to 7 is implemented.

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