ARM (Advanced RISC Machines) and FPGA (Field Programmable Gate Array) board-level communication method and device based on FLEXBUS interface

Abstract

The invention discloses an ARM (Advanced RISC Machines) and FPGA (Field Programmable Gate Array) board-level communication method and device based on a FLEXBUS interface, ARM and FPGA communication is realized through the FLEXBUS interface, the interface supports high-speed data transmission and meets the requirements of large data volume and high real-time performance, the transmission rate and the data throughput are obviously superior to those of a traditional communication mode, the data bit width of the FLEXBUS interface is configurable, the data transmission efficiency can be optimized, and the data transmission efficiency is improved. The method is suitable for different application scenes, configuration parameters transmitted when an upper-layer application runs are analyzed at the ARM host end, FLEXBUS interface parameters are configured through a spidev driving interface, it is ensured that communication parameters are accurate and stable, in the data transmission process, the FPGA slave end analyzes verification data frames, data correctness and completeness are ensured, the ARM host end verifies data consistency, the error rate is calculated, the communication reliability is improved, and the data transmission efficiency is improved. In addition, the FPGA slave end can also convert the data into a parallel port communication format, uninterrupted transmission of data streams is achieved, in addition, a spidev driving interface provides a uniform interface for upper-layer application, and the interaction process is simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of ARM and FPGA board-level communication, and in particular to a FLEXBUS interface-based ARM and FPGA board-level communication method and device. Background Art

[0002] In modern embedded systems and high-performance computing, the combination of ARM processors and FPGAs (field-programmable gate arrays) has become a common hardware architecture. Traditional ARM-FPGA communication methods, such as SPI, I2C, and UART, can meet communication needs to a certain extent. However, in scenarios with high-speed data transmission and high real-time requirements, these communication methods often fall short. For example, although the SPI interface has a fast transmission speed, it is limited by its hardware design and protocol specifications, making it difficult to achieve uninterrupted transmission of large data volumes. I2C and UART interfaces are more suitable for low-speed, small-data-volume communication scenarios. Summary of the Invention

[0003] In view of this, the present invention proposes an ARM and FPGA board-level communication method and device based on the FLEXBUS interface, which can effectively solve the defects of the existing technology in scenarios with high-speed data transmission and high real-time requirements.

[0004] The technical solution of the present invention is achieved as follows: A board-level communication method between ARM and FPGA based on FLEXBUS interface, specifically comprising: The ARM host parses the configuration parameters passed in when the upper-layer application is running, and configures the FLEXBUS interface parameters through the spidev driver interface for communication with the FPGA slave. The FPGA slave is configured to receive FLEXBUS data frames, parse out the data, and convert it into parallel port communication for uninterrupted transmission of data streams.

[0005] As a further optional solution of the ARM and FPGA board-level communication method based on the FLEXBUS interface, the ARM host side includes: Parameter parsing module, used to parse the parameters passed in by the upper-layer application, including communication rate, data read / write size, and data read / write times; The data transceiver module is used to control the cyclic transmission and reception of data according to the parameters obtained by analysis; The rate calculation module is used to obtain the real-time time after the reading and writing is completed, and calculate the reading and writing time and reading and writing rate; The data processing module is used to verify the consistency of written data and read data through two-byte alignment, and calculate the number of error bytes and the bit error rate.

[0006] As a further optional solution of the ARM and FPGA board-level communication method based on the FLEXBUS interface, the parameter parsing module parses the parameters passed in by the upper-layer application, specifically including: Receive parameter data packets from upper layer applications through preset interfaces; Parse the format of the parameter data packet, identify and separate the communication rate parameter field, the data read and write size parameter field, and the data read and write number parameter field; Extract the communication rate parameter from the communication rate parameter field, extract the data read and write size parameter from the data read and write size parameter field, and extract the data read and write number parameter from the data read and write number parameter field; The extracted parameters are stored in the parameter storage area.

[0007] As a further optional solution of the ARM and FPGA board-level communication method based on the FLEXBUS interface, the data transceiver module controls the cyclic transmission and reception of data according to the parameters obtained by analysis, specifically including: Configure the data transmission rate according to the communication rate parameter; Determine the amount of data transferred each time based on the data read and write size parameters; Control the number of data cyclic transmission and reception according to the data reading and writing number parameters; Data is sent and received with the FPGA slave via the FLEXBUS interface and the spidev driver interface.

[0008] As a further optional solution of the ARM and FPGA board-level communication method based on the FLEXBUS interface, the data processing module verifies the consistency of the written data and the read data by two-byte alignment, and calculates the number of error bytes and the bit error rate, specifically including: Get write data and read data; Divide the write data and read data into multiple data pairs in a two-byte alignment manner; Compare each data pair, count the number of inconsistent data pairs, and get the number of error bytes; Calculate the bit error rate based on the number of errored bytes and the total number of data pairs.

[0009] As a further optional solution of the ARM and FPGA board-level communication method based on the FLEXBUS interface, the FPGA slave end is configured to parse the data after receiving the FLEXBUS data frame and convert it into parallel port communication, specifically including: The FPGA slave side continuously monitors and receives FLEXBUS data frames from the ARM host side through the configured FLEXBUS Slave peripheral interface; Parse the format of the received FLEXBUS data frame, identify and extract each field in the data frame, including the data header, data body and data footer; Align the parsed data to ensure that the data is aligned according to the predetermined byte boundaries; Convert the aligned data into parallel port communication format; The converted data is sent to the target device through the parallel communication interface of the FPGA slave side; After the data transmission is completed, the FPGA slave side can send a feedback signal to the ARM host side to confirm that the data has been successfully received and processed.

[0010] An ARM and FPGA board-level communication device based on a FLEXBUS interface, comprising: The configuration module is used to configure the spidev driver interface on the ARM host side, parse the parameters passed in when the upper-layer application is running through this interface, and configure the FLEXBUS interface parameters to achieve communication with the FPGA slave side; The conversion module is used to configure the FPGA slave end to receive FLEXBUS data frames, parse out the data, and convert it into parallel port communication to achieve uninterrupted transmission of data streams.

[0011] A computing device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the processor implements any one of the steps of the above-mentioned FLEXBUS interface-based ARM and FPGA board-level communication method.

[0012] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of any one of the above-mentioned methods for board-level communication between an ARM and an FPGA based on a FLEXBUS interface.

[0013] The beneficial effects of the present invention are as follows: communication between ARM and FPGA is achieved through the FLEXBUS interface, the FLEXBUS interface supports high-speed data transmission, and can meet communication scenarios with large data volumes and high real-time requirements. Compared with traditional communication methods (such as SPI, I2C, UART, etc.), the FLEXBUS interface has significant advantages in transmission rate and data throughput. The data bit width of the FLEXBUS interface is configurable, and the width of data transmission can be adjusted according to actual needs, thereby optimizing data transmission efficiency. This flexibility enables the FLEXBUS interface to adapt to data requirements in different application scenarios. The configuration parameters passed in when the upper-layer application is running are parsed on the ARM host side, and the FLEXBUS interface parameters are configured through the spidev driver interface. This parameter configuration method ensures the accuracy and stability of communication parameters and avoids errors caused by parameter configuration. Communication failures caused by improper communication. During the data transmission process, the FPGA slave side parses and verifies the format of the received FLEXBUS data frame to ensure the correctness and integrity of the data. At the same time, the data processing module on the ARM host side also verifies the consistency of the written data and the read data through two-byte alignment, calculates the number of error bytes and the error rate, and further improves the reliability of communication. After receiving the FLEXBUS data frame, the FPGA slave side can quickly parse out the valid data and convert it into the parallel port communication format. This data processing and conversion capability enables the FPGA slave side to flexibly adapt to the requirements of different communication protocols and data formats, and realize uninterrupted transmission of data streams. The spidev driver interface is configured on the ARM host side to provide a unified driver interface for upper-level applications. This design simplifies the interaction process between upper-level applications and underlying hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 This is a flow chart of a method for board-level communication between ARM and FPGA based on FLEXBUS interface of the present invention; Figure 2 This is a schematic diagram of the composition of an ARM and FPGA board-level communication system based on a FLEXBUS interface of the present invention; Figure 3 A schematic diagram of the composition of a computing device according to the present invention. DETAILED DESCRIPTION

[0016] The following is a clear and complete description of the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0017] refer to Figures 1 to 3 , a board-level communication method between ARM and FPGA based on FLEXBUS interface, specifically including: The ARM host parses the configuration parameters passed in when the upper-layer application is running, and configures the FLEXBUS interface parameters through the spidev driver interface for communication with the FPGA slave. The FPGA slave is configured to receive FLEXBUS data frames, parse out the data, and convert it into parallel port communication for uninterrupted transmission of data streams.

[0018] In this embodiment, communication between ARM and FPGA is achieved through the FLEXBUS interface. The FLEXBUS interface supports high-speed data transmission and can meet communication scenarios with large data volumes and high real-time requirements. Compared with traditional communication methods (such as SPI, I2C, UART, etc.), the FLEXBUS interface has significant advantages in transmission rate and data throughput. The data bit width of the FLEXBUS interface is configurable, and the data transmission width can be adjusted according to actual needs, thereby optimizing data transmission efficiency. This flexibility enables the FLEXBUS interface to adapt to data requirements in different application scenarios. The configuration parameters passed in when the upper-layer application is running are parsed on the ARM host side, and the FLEXBUS interface parameters are configured through the spidev driver interface. This parameter configuration method ensures the accuracy and stability of the communication parameters and avoids errors caused by improper parameter configuration. To avoid communication failures, during data transmission, the FPGA slave parses and verifies the format of the received FLEXBUS data frame to ensure the correctness and integrity of the data. At the same time, the data processing module on the ARM host also verifies the consistency of the written and read data through two-byte alignment, calculates the number of error bytes and the error rate, and further improves the reliability of communication. After receiving the FLEXBUS data frame, the FPGA slave can quickly parse out the valid data and convert it into the parallel port communication format. This data processing and conversion capability enables the FPGA slave to flexibly adapt to the requirements of different communication protocols and data formats, and realize uninterrupted transmission of data streams. The spidev driver interface is configured on the ARM host to provide a unified driver interface for upper-level applications. This design simplifies the interaction process between upper-level applications and underlying hardware.

[0019] It should be noted that on the ARM host side, the spidev driver interface is first configured. This interface is responsible for parsing the parameters passed in when the upper-level application is running. These parameters include communication rate, data read and write size, and data read and write times. After parsing the parameters, the ARM host side configures the FLEXBUS interface parameters through the spidev driver interface to communicate with the FPGA slave side. When communication is established, the ARM host side sends a communication request to the FPGA slave side through the FLEXBUS port. After the FPGA slave side receives the FLEXBUS data frame, it will parse the data content and then convert the data into a parallel port communication format. This conversion process enables the data stream to be transmitted uninterruptedly on the FPGA slave side, thereby improving communication efficiency. During the data transmission process, the data transceiver module on the ARM host side will control the cyclic transmission and reception of data based on the parameters previously parsed, which means that data can be transmitted continuously and stably between the ARM host side and the FPGA slave side.

[0020] Preferably, the ARM host terminal includes: Parameter parsing module, used to parse the parameters passed in by the upper-layer application, including communication rate, data read / write size, and data read / write times; The data transceiver module is used to control the cyclic transmission and reception of data according to the parameters obtained by analysis; The rate calculation module is used to obtain the real-time time after the reading and writing is completed, and calculate the reading and writing time and reading and writing rate; The data processing module is used to verify the consistency of written data and read data through two-byte alignment, and calculate the number of error bytes and the bit error rate.

[0021] In this embodiment, the parameter parsing module can parse the parameters passed in by the upper-layer application, including the communication rate, data read and write size, and the number of data read and write times. This flexibility enables the system to dynamically adjust the communication parameters according to different application scenarios and needs, thereby optimizing the communication performance; the data transceiver module controls the cyclic transceiver of data according to the parameters obtained by the analysis. This cyclic transceiver mechanism enables the system to transmit data continuously and stably, meeting the communication scenarios with large data volume and high real-time requirements. By adjusting the data transmission strategy according to parameters such as the communication rate and data read and write size, the data transceiver module can optimize the data transmission efficiency, reduce the data transmission delay and packet loss rate, and monitor the communication status in real time during the data transmission process to ensure the data transmission efficiency. Ensure the stability and reliability of data transmission. When communication anomalies occur, timely measures can be taken to deal with them to avoid data loss or damage. The rate calculation module obtains real-time time after reading and writing, calculates the reading and writing time and reading and writing rate. This real-time performance monitoring mechanism enables the system to understand the communication performance status in a timely manner and provide data support for performance optimization. The data processing module verifies the consistency of written data and read data through two-byte alignment to ensure the correctness and integrity of the data. This verification mechanism can promptly detect and correct errors that may occur during data transmission. Through data consistency verification and bit error rate statistics and analysis, the data processing module can significantly improve the quality of data transmission and reduce the possibility of data errors and loss.

[0022] Preferably, the parameter parsing module parses the parameters passed in by the upper layer application, specifically including: Receive parameter data packets from upper layer applications through preset interfaces; Parse the format of the parameter data packet, identify and separate the communication rate parameter field, the data read and write size parameter field, and the data read and write number parameter field; Extract the communication rate parameter from the communication rate parameter field, extract the data read and write size parameter from the data read and write size parameter field, and extract the data read and write number parameter from the data read and write number parameter field; The extracted parameters are stored in the parameter storage area.

[0023] In this embodiment, communication rate parameters, data read and write size parameters, and data read and write number parameters are accurately extracted from each parameter field to ensure the accuracy and integrity of the parameters. The extracted parameters are stored in the parameter storage area to ensure the security and accessibility of the parameters. The design of the parameter storage area usually takes into account the persistence and stability of the data, which can prevent the loss or damage of the parameters. During the parameter parsing process, the parameters can be checked and corrected to ensure the legality and validity of the parameters. When errors or abnormalities occur in the parameters, they can be discovered in time and measures can be taken to deal with them, avoiding communication failures caused by parameter errors. Through efficient parameter parsing and precise parameter extraction, the preparation time before communication configuration and data transmission is reduced, thereby reducing communication delays. Accurate parameter configuration makes data transmission more efficient and stable, and reduces the packet loss rate and retransmission rate during data transmission. This method of improving data transmission efficiency improves the overall performance of the system and meets communication scenarios with large data volumes and high real-time requirements.

[0024] Preferably, the data transceiver module controls the cyclic transmission and reception of data according to the parameters obtained by the analysis, specifically including: Configure the data transmission rate according to the communication rate parameter; Determine the amount of data transferred each time based on the data read and write size parameters; Control the number of data cyclic transmission and reception according to the data reading and writing number parameters; Data is sent and received with the FPGA slave via the FLEXBUS interface and the spidev driver interface.

[0025] In this embodiment, the data transmission rate is configured according to the communication rate parameters, so that the data transmission can accurately match the needs of the upper-layer application. No matter whether it is high-speed data transmission or low-speed data transmission, the best transmission effect can be achieved by adjusting the communication rate parameters. By accurately controlling the data transmission rate, the communication bandwidth can be more effectively utilized to avoid bandwidth waste or insufficient conditions, which improves the efficiency of data transmission and reduces communication costs. The amount of data transmitted each time is determined according to the data read and write size parameters, which can flexibly adapt to data transmission needs of different scales. No matter whether it is a small amount of data transmission or a large amount of data transmission, efficient transmission can be achieved by adjusting the data read and write size parameters. By reasonably setting the amount of data transmitted each time, the overhead in the transmission process, such as protocol headers, check codes, etc., can be reduced, thereby improving data transmission efficiency. The net load rate of data transmission is determined by the data reading and writing times parameter, and the number of cyclic data transmission and reception is controlled to achieve continuous and stable data transmission. This cyclic transmission and reception mechanism is particularly suitable for scenarios that require continuous transmission of large amounts of data, such as video streams, audio streams, etc. The cyclic transmission and reception mechanism reduces the need for manual intervention and realizes automatic management of data transmission, which reduces the complexity of operation and improves reliability and stability. Data is transmitted and received with the FPGA slave end through the FLEXBUS interface and the spidev driver interface, making full use of the high-speed transmission characteristics of the FLEXBUS interface to achieve high-speed and stable data transmission, meeting the communication scenarios with large data volumes and high real-time requirements. The spidev driver interface provides unified interface management for upper-layer applications, simplifying the interaction process with the underlying hardware.

[0026] Preferably, the data processing module verifies the consistency of written data and read data by two-byte alignment, and calculates the number of error bytes and the bit error rate, specifically including: Get write data and read data; Divide the write data and read data into multiple data pairs in a two-byte alignment manner; Compare each data pair, count the number of inconsistent data pairs, and get the number of error bytes; Calculate the bit error rate based on the number of errored bytes and the total number of data pairs.

[0027] In this embodiment, write data and read data are divided into multiple data pairs through two-byte alignment, and each data pair is compared. This verification method can accurately detect whether errors occur during data transmission. The two-byte alignment check helps to detect single-byte errors and some multi-byte errors, thereby improving the accuracy and reliability of data verification. By counting the number of inconsistent data pairs, the number of errored bytes is obtained, which can quantify the error situation and understand the degree of error during data transmission. The bit error rate is calculated based on the number of errored bytes and the total number of data pairs, which can evaluate the communication quality and understand the reliability of data transmission. The bit error rate calculation can understand the communication quality of the system under different conditions, thereby guiding system optimization. For example, when the bit error rate is high, it can be considered to adjust communication parameters, optimize the transmission protocol, or improve hardware design to reduce the bit error rate. Through two-byte alignment check, errored byte counting, and bit error rate calculation, the system can quickly locate problems in the data transmission process, which simplifies the troubleshooting process and reduces maintenance costs. Through long-term monitoring and analysis of the bit error rate, potential failure risks can be predicted and corresponding preventive measures can be taken in advance.

[0028] Preferably, the FPGA slave terminal is configured to receive the FLEXBUS data frame, parse the data, and convert it into parallel port communication, specifically including: The FPGA slave side continuously monitors and receives FLEXBUS data frames from the ARM host side through the configured FLEXBUS Slave peripheral interface; Parse the format of the received FLEXBUS data frame, identify and extract each field in the data frame, including the data header, data body and data footer; Align the parsed data to ensure that the data is aligned according to the predetermined byte boundaries; Convert the aligned data into parallel port communication format; The converted data is sent to the target device through the parallel communication interface of the FPGA slave side; After the data transmission is completed, the FPGA slave side can send a feedback signal to the ARM host side to confirm that the data has been successfully received and processed.

[0029] In this embodiment, the FPGA slave end can continuously monitor and receive FLEXBUS data frames from the ARM host end through the configured FLEXBUS Slave peripheral interface. This continuous monitoring mechanism ensures the real-time and integrity of the data and avoids data loss. The received FLEXBUS data frame is format parsed to accurately identify and extract each field in the data frame, including the data header, data body and data tail. This precise format parsing mechanism improves the accuracy and efficiency of data processing; the parsed data is aligned to ensure that the data is aligned according to the predetermined byte boundary. This alignment processing mechanism helps to ensure the consistency and correctness of the data in subsequent processing and avoids processing errors caused by data misalignment. The aligned data is easier to process and convert subsequently, thereby improving the efficiency of data processing; the aligned data is converted into a parallel port communication format, so that the FPGA slave end can communicate with the target device in parallel. This format conversion mechanism enhances It has flexibility and compatibility and meets different communication needs. Parallel port communication has a high data transmission rate. Through parallel port communication format conversion, the system can achieve high-speed and stable data transmission; the converted data is sent to the target device through the parallel port communication interface of the FPGA slave end. During the data transmission process, the integrity and accuracy of the data can be ensured, avoiding data loss or damage. After the data transmission is completed, the FPGA slave end can send a feedback signal to the ARM host end to confirm that the data has been successfully received and processed. This real-time feedback mechanism enhances reliability and stability, allowing the ARM host end to understand the data transmission status in a timely manner; the FPGA slave end can support a variety of communication methods and devices by configuring different communication interfaces and protocols. This flexibility can easily adapt to different application scenarios and needs. Parallel port communication format conversion and real-time feedback mechanism help reduce communication delays and improve real-time performance and response speed.

[0030] An ARM and FPGA board-level communication device based on a FLEXBUS interface, comprising: The configuration module is used to parse the configuration parameters passed in when the upper-layer application is running on the ARM host side, and configure the FLEXBUS interface parameters through the spidev driver interface to achieve communication with the FPGA slave side; The conversion module is used to configure the FPGA slave end to receive FLEXBUS data frames, parse out the data, and convert it into parallel port communication to achieve uninterrupted transmission of data streams.

[0031] A computing device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the processor implements any one of the steps of the above-mentioned FLEXBUS interface-based ARM and FPGA board-level communication method.

[0032] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of any one of the above-mentioned methods for board-level communication between an ARM and an FPGA based on a FLEXBUS interface.

[0033] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A board-level communication method between ARM and FPGA based on FLEXBUS interface, characterized in that: Specifically include: The ARM host parses the configuration parameters passed in when the upper-layer application is running, and configures the FLEXBUS interface parameters through the spidev driver interface for communication with the FPGA slave. The FPGA slave is configured to receive FLEXBUS data frames, parse out the data, and convert it into parallel port communication for uninterrupted transmission of data streams.

2. The ARM and FPGA board-level communication method based on FLEXBUS interface according to claim 1, characterized in that: The ARM host side includes: Parameter parsing module, used to parse the parameters passed in by the upper-layer application, including communication rate, data read / write size, and data read / write times; The data transceiver module is used to control the cyclic transmission and reception of data according to the parameters obtained by analysis; The rate calculation module is used to obtain the real-time time after the reading and writing is completed, and calculate the reading and writing time and reading and writing rate; The data processing module is used to verify the consistency of written data and read data through two-byte alignment, and calculate the number of error bytes and the bit error rate.

3. The ARM and FPGA board-level communication method based on FLEXBUS interface according to claim 2, characterized in that: The parameter parsing module parses the parameters passed in by the upper-layer application, specifically including: Receive parameter data packets from upper layer applications through preset interfaces; Parse the format of the parameter data packet, identify and separate the communication rate parameter field, the data read and write size parameter field, and the data read and write number parameter field; Extract the communication rate parameter from the communication rate parameter field, extract the data read and write size parameter from the data read and write size parameter field, and extract the data read and write number parameter from the data read and write number parameter field; The extracted parameters are stored in the parameter storage area.

4. The ARM and FPGA board-level communication method based on FLEXBUS interface according to claim 3 is characterized in that: The data transceiver module controls the cyclic transmission and reception of data according to the parameters obtained by the analysis, specifically including: Configure the data transmission rate according to the communication rate parameter; Determine the amount of data transferred each time based on the data read and write size parameters; Control the number of data cyclic transmission and reception according to the data reading and writing number parameters; Data is sent and received with the FPGA slave via the FLEXBUS interface and the spidev driver interface.

5. The ARM and FPGA board-level communication method based on FLEXBUS interface according to claim 4 is characterized in that: The data processing module verifies the consistency of written data and read data by two-byte alignment, and calculates the number of error bytes and the bit error rate, specifically including: Get write data and read data; Divide the write data and read data into multiple data pairs in a two-byte alignment manner; Compare each data pair, count the number of inconsistent data pairs, and get the number of error bytes; Calculate the bit error rate based on the number of errored bytes and the total number of data pairs.

6. The method for board-level communication between ARM and FPGA based on FLEXBUS interface according to claim 5, characterized in that: The FPGA slave terminal is configured to receive FLEXBUS data frames, parse the data, and convert it into parallel port communication, specifically including: The FPGA slave side continuously monitors and receives FLEXBUS data frames from the ARM host side through the configured FLEXBUS Slave peripheral interface; Parse the format of the received FLEXBUS data frame, identify and extract each field in the data frame, including the data header, data body and data footer; Align the parsed data to ensure that the data is aligned according to the predetermined byte boundaries; Convert the aligned data into parallel port communication format; The converted data is sent to the target device through the parallel communication interface of the FPGA slave side; After the data transmission is completed, the FPGA slave side can send a feedback signal to the ARM host side to confirm that the data has been successfully received and processed.

7. An ARM and FPGA board-level communication device based on FLEXBUS interface, characterized in that: include: The configuration module is used to parse the configuration parameters passed in when the upper-layer application is running on the ARM host side, and configure the FLEXBUS interface parameters through the spidev driver interface to achieve communication with the FPGA slave side; The conversion module is used to configure the FPGA slave end to receive FLEXBUS data frames, parse out the data, and convert it into parallel port communication to achieve uninterrupted transmission of data streams.

8. A computing device, characterized in that The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the ARM and FPGA board-level communication method based on the FLEXBUS interface according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium, characterized in that The storage medium stores a computer program, which, when executed by a processor, implements the steps of the ARM and FPGA board-level communication method based on the FLEXBUS interface described in any one of claims 1 to 6.

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