Pixel of display device and display device

Abstract

Disclosed are a pixel and a display device including the same. The pixel includes: a light emitting element; a constant current generating circuit for generating a constant current; the pulse generating circuit is used for generating a pulse signal; and an emission transistor providing a constant current to the light emitting element in response to the pulse signal. The pulse generating circuit includes: a plurality of inverters connected in series with each other, in which the plurality of inverters output a pulse signal at a pulse output node based on a voltage of a first node; and a feedback capacitor including a first electrode connected to the first node and a second electrode connected to the pulse output node.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device, and more particularly, to a pixel that drives a light emitting element in a pulse width modulation (PWM) method and a display device including the pixel. Background Art

[0002] A display device can display an image by driving a light-emitting element (such as a micron light-emitting diode (μLED) or an organic light-emitting diode (OLED)) using a pulse amplitude modulation (PAM) method or a pulse width modulation (PWM) method. In the PAM method, grayscale can be expressed by adjusting the amount (or amplitude) of the driving current supplied to the light-emitting element. In the PWM method, grayscale can be expressed by adjusting the time (or pulse width) during which the driving current is supplied to the light-emitting element. Summary of the Invention

[0003] The wavelength of light emitted by a micron light-emitting diode (μLED) may shift depending on the amount of driving current. Therefore, when a light-emitting element such as a μLED is driven using a pulse amplitude modulation (PAM) method, a color shift phenomenon may occur, and the image displayed by the light-emitting element may be distorted.

[0004] Some embodiments provide a pixel of a display device capable of having improved image quality.

[0005] Some embodiments provide a display device capable of having improved image quality.

[0006] According to an embodiment, a pixel of a display device includes: a light-emitting element; a constant current generating circuit that generates a constant current; a pulse generating circuit that generates a pulse signal; and an emission transistor that provides the constant current to the light-emitting element in response to the pulse signal. In such an embodiment, the pulse generating circuit includes: a plurality of inverters connected in series, wherein the plurality of inverters output a pulse signal at a pulse output node based on a voltage at a first node; and a feedback capacitor including a first electrode connected to the first node and a second electrode connected to the pulse output node.

[0007] In an embodiment, the emission time of the light emitting element may be determined based on the pulse width of the pulse signal.

[0008] In an embodiment, the pulse generating circuit may further include: a first transistor applying a first power supply voltage to the first node in response to a voltage of the second node; and a second transistor applying a second power supply voltage to the first node in response to the scan signal.

[0009] In an embodiment, the first transistor may include a gate connected to the second node, a first terminal receiving a first power supply voltage, and a second terminal connected to the first node, and the second transistor may include a gate receiving a scan signal, a first terminal receiving the second power supply voltage, and a second terminal connected to the first node.

[0010] In an embodiment, the first power supply voltage may be a high power supply voltage, the second power supply voltage may be a low power supply voltage, the first transistor may be a P-type metal oxide semiconductor (PMOS) transistor, and the second transistor may be an N-type metal oxide semiconductor (NMOS) transistor.

[0011] In an embodiment, the first power supply voltage may be a low power supply voltage, the second power supply voltage may be a high power supply voltage, the first transistor may be an NMOS transistor, and the second transistor may be a PMOS transistor.

[0012] In an embodiment, the pulse generating circuit may further include a third transistor applying a data voltage to the second node in response to the scan signal.

[0013] In an embodiment, the pulse generating circuit may further include a fourth transistor applying the data voltage to the second node in response to the inverted scan signal.

[0014] In an embodiment, the pulse generating circuit may further include a third transistor applying a data voltage to the second node in response to a scan signal; and a fourth transistor applying the data voltage to the second node in response to an inverted scan signal.

[0015] In an embodiment, the third transistor may include a gate receiving a scan signal, a first terminal connected to the second node, and a second terminal receiving a data voltage, and the fourth transistor may include a gate receiving an inverted scan signal, a first terminal receiving the data voltage, and a second terminal connected to the second node.

[0016] In an embodiment, the third transistor may be a PMOS transistor, and the fourth transistor may be an NMOS transistor.

[0017] In an embodiment, the third transistor may be an NMOS transistor, and the fourth transistor may be a PMOS transistor.

[0018] In an embodiment, the pulse generating circuit may further include a storage capacitor including a first electrode receiving the swept frequency signal and a second electrode connected to the second node.

[0019] In an embodiment, the voltage level of the frequency sweep signal may be gradually reduced during the frequency sweep period.

[0020] In an embodiment, the voltage level of the frequency sweep signal may gradually increase during the frequency sweep period.

[0021] In an embodiment, the plurality of inverters may include a first inverter that inverts a voltage of the first node and outputs the inverted voltage to a third node, and a second inverter that inverts a voltage of the third node and outputs a pulse signal at a pulse output node.

[0022] In an embodiment, the first inverter may include: a fifth transistor including a gate connected to the first node, a first terminal receiving a first power supply voltage, and a second terminal connected to a third node; and a sixth transistor including a gate connected to the first node, a first terminal receiving a second power supply voltage, and a second terminal connected to the third node. In such an embodiment, the second inverter may include: a seventh transistor including a gate connected to the third node, a first terminal receiving the first power supply voltage, and a second terminal connected to a pulse output node; and an eighth transistor including a gate connected to the third node, a first terminal receiving the second power supply voltage, and a second terminal connected to the pulse output node.

[0023] In an embodiment, the fifth transistor and the seventh transistor may be PMOS transistors, and the sixth transistor and the eighth transistor may be NMOS transistors.

[0024] According to an embodiment, a pixel of a display device includes: a first transistor including a gate connected to a second node, a first terminal receiving a first power supply voltage, and a second terminal connected to the first node; a second transistor including a gate receiving a scan signal, a first terminal receiving a second power supply voltage, and a second terminal connected to the first node; a third transistor including a gate receiving a scan signal, a first terminal connected to the second node, and a second terminal receiving a data voltage; a fourth transistor including a gate receiving an inverted scan signal, a first terminal receiving a data voltage, and a second terminal connected to the second node; a storage capacitor including a first electrode receiving a scan signal and a second electrode connected to the second node; a fifth transistor including a gate connected to the first node, a first terminal receiving the first power supply voltage, and a second terminal connected to the third node; a sixth transistor including a gate connected to the first node, a first terminal receiving the first power supply voltage, and a second terminal connected to the third node. a seventh transistor including a gate connected to the third node, a first terminal receiving the first power supply voltage, and a second terminal connected to the pulse output node; an eighth transistor including a gate connected to the third node, a first terminal receiving the second power supply voltage, and a second terminal connected to the pulse output node; a feedback capacitor including a first electrode connected to the first node and a second electrode connected to the pulse output node; a ninth transistor including a gate receiving a bias voltage, a first terminal receiving the first power supply voltage, and a second terminal; a tenth transistor including a gate connected to the pulse output node, a first terminal connected to the second terminal of the ninth transistor, and a second terminal; and a light-emitting element including an anode connected to the second terminal of the tenth transistor and a cathode receiving the second power supply voltage.

[0025] According to an embodiment, a display device includes: a display panel including a plurality of pixels; a data driver providing a data voltage to each of the plurality of pixels; a scan driver providing a scan signal to each of the plurality of pixels; a sweep driver providing a sweep signal to each of the plurality of pixels; and a controller controlling the data driver, the scan driver, and the sweep driver. In such an embodiment, each of the plurality of pixels includes: a light-emitting element; a constant current generating circuit generating a constant current; a pulse generating circuit generating a pulse signal; and an emission transistor providing a constant current to the light-emitting element in response to the pulse signal. In such an embodiment, the pulse generating circuit includes: a plurality of inverters connected in series with each other, wherein the plurality of inverters output a pulse signal at a pulse output node based on a voltage at a first node; and a feedback capacitor including a first electrode connected to the first node and a second electrode connected to the pulse output node.

[0026] According to an embodiment, an electronic device includes: a processor configured to provide input image data; and a display device configured to receive the input image data and display an image based on the input image data. The display device includes: a display panel including a plurality of pixels; a data driver providing a data voltage to each of the plurality of pixels; a scan driver providing a scan signal to each of the plurality of pixels; a sweep driver providing a sweep signal to each of the plurality of pixels; and a controller controlling the data driver, the scan driver, and the sweep driver. Each of the plurality of pixels includes: a light-emitting element; a constant current generating circuit generating a constant current; a pulse generating circuit generating a pulse signal; and an emission transistor providing a constant current to the light-emitting element in response to the pulse signal. The pulse generating circuit includes: a plurality of inverters connected in series to each other, wherein the plurality of inverters output a pulse signal at a pulse output node based on a voltage of a first node; and a feedback capacitor including a first electrode connected to the first node and a second electrode connected to the pulse output node.

[0027] As described above, in a display device according to an embodiment, each pixel can drive a light-emitting element in a pulse width modulation (PWM) method based on a constant current with a constant current level. Therefore, the color shift phenomenon in the display device can be effectively prevented. In addition, in a pixel of a display device according to an embodiment, a pulse generating circuit may include a plurality of inverters connected in series with each other, and a feedback capacitor connected between the input node and the output node of the plurality of inverters. Therefore, the rise (and / or fall) time of the pulse signal can be improved, and the image quality of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0030] Figure 2 is a circuit diagram illustrating an example of a plurality of inverters included in a pixel according to an embodiment.

[0031] Figure 3 is a circuit diagram illustrating an example of a constant current generating circuit included in a pixel according to an embodiment.

[0032] Figure 4 is a timing chart for describing an example of the operation of a pixel according to an embodiment.

[0033] Figure 5 is a circuit diagram for describing an example of the operation of a pixel in a data writing period.

[0034] Figure 6 is a circuit diagram for describing an example of the operation of a pixel in the emission time within a sweep period.

[0035] Figure 7 is a circuit diagram for describing an example of the operation of a pixel in a non-emission time within a sweep period.

[0036] Figure 8 is a timing chart for describing an example of a rise time of a pulse signal generated in a pixel according to an embodiment.

[0037] Figure 9 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0038] Figure 10 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0039] Figure 11 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0040] Figure 12 is a timing chart for describing an example of the operation of a pixel according to an embodiment.

[0041] Figure 13 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0042] Figure 14 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0043] Figure 15 is a block diagram illustrating a display device according to an embodiment.

[0044] Figure 16 is a block diagram illustrating an electronic device including a display device according to an embodiment. DETAILED DESCRIPTION

[0045] The present invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Like reference numerals represent like elements throughout.

[0046] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present between them. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0047] It will be understood that, although the terms "first", "second", "third" etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as the second element, second component, second region, second layer or second part.

[0048] The terms used herein are only used to describe the purpose of specific embodiments and are not intended to be limiting. As used herein, "one", "a", "the" and "at least one" do not represent quantitative limitations and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. Therefore, in a claim, mentioning "one" element followed by "the" element includes one element and multiple elements. For example, "element" has the same meaning as "at least one element" unless the context clearly indicates otherwise. "At least one" is not interpreted as limiting "one" or "a kind of". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the term "includes" and / or "includes" or "contains" and / or "includes" specifies the presence of the features, regions, wholes, steps, operations, elements and / or components described, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0049] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device in one of the accompanying drawings is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, the term "lower" can include both "lower" and "upper" orientations, depending on the specific orientation of the accompanying drawings. Similarly, if the device in one of the accompanying drawings is turned over, the element described as being "below" or "beneath" the other elements will then be oriented to be "above" the other elements. Therefore, the term "lower" or "below" can include both "upper" and "lower" orientations.

[0050] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, in view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0052] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 is a circuit diagram showing a pixel of a display device according to an embodiment, Figure 2 is a circuit diagram illustrating an example of a plurality of inverters included in a pixel according to an embodiment, and Figure 3 is a circuit diagram illustrating an example of a constant current generating circuit included in a pixel according to an embodiment.

[0054] refer to Figure 1 According to an embodiment, the pixel 100 may include a light-emitting element EL, a constant current generating circuit CCGC that generates a constant current having a substantially constant current level, a pulse generating circuit PGC that generates a pulse signal SPWM, and an emission transistor T10 that provides a constant current to the light-emitting element EL in response to the pulse signal SPWM. The pulse generating circuit PGC may include a plurality of inverters INV1 and INV2 connected in series with each other, and a feedback capacitor CFB connected between an input node (or first node N1) and an output node (or pulse output node NPO) of the plurality of inverters INV1 and INV2. In some embodiments, the pulse generating circuit PGC may further include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a storage capacitor CST.

[0055] The third transistor T3 may apply the data voltage of the data line DL to the second node N2 in response to the scan signal SC[n], and the fourth transistor T4 may apply the data voltage of the data line DL to the second node N2 in response to the inverted scan signal SCB[n]. In some embodiments, the inverted scan signal SCB[n] may be a signal inverted to the scan signal SC[n], and each of the scan signal SC[n] and the inverted scan signal SCB[n] may be sequentially applied to the plurality of pixels 100 of the display device on a row-by-row basis. In some embodiments, as Figure 1 As shown in , the third transistor T3 may be an N-type metal oxide semiconductor (NMOS) transistor, and the fourth transistor T4 may be a P-type metal oxide semiconductor (PMOS) transistor. That is, the third transistor T3 and the fourth transistor T4 may be complementary metal oxide semiconductor (CMOS) transmission gates that transmit a data voltage in response to a scan signal SC[n] and an inverted scan signal SCB[n]. In addition, in some embodiments, the third transistor T3 may include a gate that receives the scan signal SC[n], a first terminal connected to the second node N2, and a second terminal that receives the data voltage, and the fourth transistor T4 may include a gate that receives the inverted scan signal SCB[n], a first terminal that receives the data voltage, and a second terminal that is connected to the second node N2.

[0056] The storage capacitor CST may receive the sweep signal SWEEP[n] and may be connected to the second node N2. In some embodiments, the storage capacitor CST may include a first electrode that receives the sweep signal SWEEP[n] and a second electrode that is connected to the second node N2. In some embodiments, the sweep signal SWEEP[n] may be sequentially applied to the plurality of pixels 100 of the display device on a row-by-row basis. In addition, in some embodiments, as Figure 4 As shown in , the voltage level of the sweep signal SWEEP[n] may gradually decrease during the sweep period SWP. Therefore, the voltage of the second node N2 may also gradually decrease from the data voltage during the sweep period SWP through the storage capacitor CST.

[0057] The first transistor T1 may apply the first power supply voltage VDD to the first node N1 in response to the voltage of the second node N2, and the second transistor T2 may apply the second power supply voltage VSS to the first node N1 in response to the scan signal SC[n]. Figure 4 and Figure 5 As described above, the second transistor T2 can apply the second power supply voltage VSS to the first node N1 during the data write period DWP. Figure 4 and Figure 7As described, during the sweep period SWP, when the voltage of the second node N2 becomes lower than the voltage VDD-|VTH| obtained by subtracting the absolute value |VTH| of the threshold voltage of the first transistor T1 from the first power supply voltage VDD, the first transistor T1 may apply the first power supply voltage VDD to the first node N1. In some embodiments, as Figure 1 As shown in , the first power supply voltage VDD may be a high power supply voltage, the second power supply voltage VSS may be a low power supply voltage, the first transistor T1 may be a PMOS transistor, and the second transistor T2 may be an NMOS transistor. In addition, in some embodiments, the first transistor T1 may include a gate connected to the second node N2, a first terminal receiving the first power supply voltage VDD, and a second terminal connected to the first node N1, and the second transistor T2 may include a gate receiving the scan signal SC[n], a first terminal receiving the second power supply voltage VSS, and a second terminal connected to the first node N1.

[0058] A plurality of inverters INV1 and INV2 may be connected in series between a first node N1 and a pulse output node NPO, and may output a pulse signal SPWM at the pulse output node NPO based on the voltage of the first node N1. Here, the pulse signal SPWM may be a signal having a pulse width adjusted or modulated based on the voltage level of the data voltage, and may therefore be referred to as a pulse width modulated (PWM) signal. The pulse generation circuit PGC may include an even number of inverters INV1 and INV2 between the first node N1 and the pulse output node NPO. Therefore, the even number of inverters INV1 and INV2 may generate the pulse signal SPWM having a logic level substantially the same as the logic level of the voltage of the first node N1 (e.g., a high level or a low level). In such an embodiment, since the voltage of the first node N1 is not directly used as the pulse signal SPWM, and the pulse signal SPWM is generated by the even number of inverters INV1 and INV2 based on the voltage of the first node N1, the rise time and / or fall time of the pulse signal SPWM may be improved or shortened.

[0059] In some embodiments, as Figure 1 As shown in FIG, the pulse generating circuit PGC may include two inverters INV1 and INV2 connected in series with each other as a plurality of inverters INV1 and INV2. That is, the pulse generating circuit PGC may include a first inverter INV1 and a second inverter INV2, the first inverter INV1 inverts the voltage of the first node N1 to output the inverted voltage to the third node N3, and the second inverter INV2 inverts the voltage of the third node N3 to output the pulse signal SPWM at the pulse output node NPO.

[0060] Furthermore, in some embodiments, each of the first inverter INV1 and the second inverter INV2 may be implemented as a CMOS inverter. Figure 2 As shown in , the first inverter INV1 may include a fifth transistor T5 and a sixth transistor T6 connected in series between a line transmitting a first power supply voltage VDD and a line transmitting a second power supply voltage VSS, and the second inverter INV2 may include a seventh transistor T7 and an eighth transistor T8 connected in series between the line transmitting the first power supply voltage VDD and the line transmitting the second power supply voltage VSS. In some embodiments, the fifth transistor T5 and the seventh transistor T7 may be PMOS transistors, and the sixth transistor T6 and the eighth transistor T8 may be NMOS transistors. In some embodiments, the fifth transistor T5 may include a gate connected to the first node N1, a first terminal receiving the first power supply voltage VDD, and a second terminal connected to the third node N3, and the sixth transistor T6 may include a gate connected to the first node N1, a first terminal receiving the second power supply voltage VSS, and a second terminal connected to the third node N3. In such an embodiment, the seventh transistor T7 may include a gate connected to the third node N3, a first terminal receiving the first power supply voltage VDD, and a second terminal connected to the pulse output node NPO, and the eighth transistor T8 may include a gate connected to the third node N3, a first terminal receiving the second power supply voltage VSS, and a second terminal connected to the pulse output node NPO.

[0061] The feedback capacitor CFB can be connected between a first node N1, which serves as an input node for the plurality of inverters INV1 and INV2, and a pulse output node NPO, which serves as an output node for the plurality of inverters INV1 and INV2. In some embodiments, the feedback capacitor CFB can include a first electrode connected to the first node N1 and a second electrode connected to the pulse output node NPO. When the pulse signal SPWM applied to the second electrode of the feedback capacitor CFB rises (or increases) from a low level to a high level, the voltage of the first electrode of the feedback capacitor CFB, or the voltage of the first node N1, can also rise (or increase). When the voltage of the first node N1 input to the plurality of inverters INV1 and INV2 rises, the pulse signal SPWM output from the plurality of inverters INV1 and INV2 can rise more rapidly. Therefore, by connecting the feedback capacitor CFB between the input node and the output node of the plurality of inverters INV1 and INV2, the rise time (and / or fall time) of the pulse signal SPWM can be further improved or shortened.

[0062] The constant current generating circuit CCGC may generate a constant current having a substantially constant current level. That is, the constant current generating circuit CCGC may be a constant current source that generates a constant current. In some embodiments, as Figure 3 As shown in , the constant current generating circuit CCGC can be implemented with a bias transistor. In an embodiment, for example, the constant current generating circuit CCGC may include a ninth transistor T9, which includes a gate receiving a bias voltage VBIAS, a first terminal receiving a first power supply voltage VDD, and a second terminal connected to an emission transistor (or tenth transistor) T10. In some embodiments, the ninth transistor T9 may be a PMOS transistor. In addition, in some embodiments, the ninth transistor T9 of all pixels 100 of the display device may receive the same bias voltage VBIAS, and the ninth transistor T9 of all pixels 100 may generate a constant current with substantially the same current level. In other embodiments, the display device may include red pixels, green pixels, and blue pixels, and the ninth transistor T9 of the red pixels may receive the same red bias voltage, the ninth transistor T9 of the green pixels may receive the same green bias voltage, and the ninth transistor T9 of the blue pixels may receive the same blue bias voltage, and the red bias voltage, the green bias voltage, and the blue bias voltage may have different voltage levels, respectively.

[0063] The emission transistor T10 may be a tenth transistor that provides a constant current generated by the ninth transistor T9 to the light-emitting element EL in response to the pulse signal SPWM. In some embodiments, the tenth transistor T10 may be a PMOS transistor. While the pulse signal SPWM is at a low level, the tenth transistor T10 may provide a constant current to the light-emitting element EL. That is, the duration of the constant current provided to the light-emitting element EL may be determined based on the pulse width of the low-level pulse signal SPWM. Furthermore, in some embodiments, the tenth transistor T10 may include a gate that receives the pulse signal SPWM, a first terminal connected to the second terminal of the ninth transistor T9, and a second terminal connected to the light-emitting element EL.

[0064] The light-emitting element EL can emit light based on the constant current provided by the tenth transistor T10. The time for which the constant current is provided to the light-emitting element EL or the emission time of the light-emitting element EL can be determined based on the pulse width of the pulse signal SPWM. In addition, since the pulse width of the pulse signal SPWM is determined based on (or in accordance with) the voltage level of the data voltage, and the emission time of the light-emitting element EL is determined based on the pulse width of the pulse signal SPWM, the emission time of the light-emitting element EL can be determined based on the voltage level of the data voltage. In some embodiments, the light-emitting element EL may include an anode connected to the second terminal of the tenth transistor T10 and a cathode receiving the second power supply voltage VSS. In some embodiments, the light-emitting element EL may be a micron light-emitting diode (μLED), but is not limited thereto. In other embodiments, the light-emitting element EL may be an organic light-emitting diode (OLED). In still other embodiments, the light-emitting element EL may be a nano-light-emitting diode (NLED), a quantum dot (QD) light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element.

[0065] In conventional display devices, the current supplied to the light-emitting element is adjusted based on the grayscale level indicated by the image data or the voltage level of the data voltage. However, depending on the amount of current supplied to the light-emitting element, the wavelength of light emitted by the light-emitting element, such as a μLED, is shifted. Therefore, if the current supplied to the light-emitting element changes, a color shift phenomenon may occur, and the image may be distorted. In the display device according to the embodiment, each pixel 100 can supply a constant current to the light-emitting element EL using a constant current generating circuit CCGC. Therefore, the color shift phenomenon can be effectively prevented in the display device according to the embodiment.

[0066] As described above, the pixel 100 according to the embodiment can drive the light-emitting element EL based on a constant current having a substantially constant current level. Therefore, the color shift phenomenon can be prevented in the display device including the pixel 100. In addition, in the pixel 100 according to the embodiment, the pulse generation circuit PGC can include a plurality of inverters INV1 and INV2 connected in series with each other, and a feedback capacitor CFB connected between the input nodes and output nodes of the plurality of inverters INV1 and INV2 (or between the first node N1 and the pulse output node NPO). Therefore, the rise time (and / or fall time) of the pulse signal SPWM generated by the pulse generation circuit PGC can be improved, and the image quality of the display device can be improved.

[0067] Figure 4 is a timing chart for describing an example of the operation of a pixel according to an embodiment, Figure 5 is a circuit diagram for describing an example of the operation of a pixel in a data writing period, Figure 6is a circuit diagram for describing an example of the operation of a pixel in an emission time within a sweep period, and Figure 7 is a circuit diagram for describing an example of the operation of a pixel in a non-emission time within a sweep period.

[0068] refer to Figure 1 and Figure 4 , the frame period FP of the pixel 100 may include a data writing period DWP and a sweeping period SWP.

[0069] In the data write period DWP, the scan signal SC[n] may have a high level, the inverted scan signal SCB[n] may have a low level, the data voltage VDAT may be applied to the second node N2, and the pulse signal SPWM may have the second power supply voltage VSS. In an embodiment, for example, Figure 5 As shown in FIG, the third transistor T3 may be turned on in response to a high-level scan signal SC[n], the fourth transistor T4 may be turned on in response to a low-level inverted scan signal SCB[n], and the third and fourth transistors T3 and T4 may transmit the data voltage VDAT of the data line DL to the second node N2. Thus, the voltage of the second node N2 may become the data voltage VDAT. Furthermore, the first transistor T1 may be turned off in response to the data voltage VDAT at the second node N2, and the second transistor T2 may be turned on in response to the high-level scan signal SC[n]. Thus, the second transistor T2 may transmit the second power supply voltage VSS to the first node N1, and the voltage of the first node N1 may become the second power supply voltage VSS. The sixth transistor T6 may be turned off in response to the second power supply voltage VSS at the first node N1, and the fifth transistor T5 may be turned on in response to the second power supply voltage VSS at the first node N1. Thus, the fifth transistor T5 may transmit the first power supply voltage VDD to the third node N3, and the voltage of the third node N3 may become the first power supply voltage VDD. Furthermore, the seventh transistor T7 can be turned off in response to the first power supply voltage VDD at the third node N3, and the eighth transistor T8 can be turned on in response to the first power supply voltage VDD at the third node N3. Therefore, the eighth transistor T8 can transmit the second power supply voltage VSS to the pulse output node NPO and can output the pulse signal SPWM having the second power supply voltage VSS at the pulse output node NPO. The ninth transistor T9 can generate a constant current ICC based on the bias voltage VBIAS, and the tenth transistor T10 can provide the constant current ICC to the light-emitting element EL in response to the pulse signal SPWM having the second power supply voltage VSS. Therefore, the light-emitting element EL can emit light based on the constant current ICC.

[0070] In the sweep period SWP, the scan signal SC[n] may have a low level, the inverted scan signal SCB[n] may have a high level, and the sweep signal SWEEP[n] may gradually decrease. In addition, while the first transistor T1 is turned off in the sweep period SWP, the light emitting element EL may emit light. In an embodiment, for example, in the emission time ET in the sweep period SWP, as shown in FIG. Figure 6 As shown in FIG, the third transistor T3 can be turned off in response to the scan signal SC[n] having a low level, and the fourth transistor T4 can be turned off in response to the inverted scan signal SCB[n] having a high level. Thus, the second node N2 can be floated. Furthermore, as the sweep signal SWEEP[n] applied to the first electrode of the storage capacitor CST gradually decreases, the voltage of the second node N2 connected to the second electrode of the storage capacitor CST may also gradually decrease. For example, when the sweep signal SWEEP[n] decreases by Δsweep voltage ΔSWEEP throughout the sweep period SWP, the voltage of the second node N2 may also decrease by Δsweep voltage ΔSWEEP throughout the sweep period SWP. The second transistor T2 can be turned off in response to the scan signal SC[n] having a low level. Furthermore, the first transistor T1 may also be turned off when the voltage of the second node N2 is higher than a voltage VDD-|VTH| obtained by subtracting the absolute value |VTH| of the threshold voltage of the first transistor T1 from the first power supply voltage VDD. Thus, the voltage of the first node N1 can be maintained at the second power supply voltage VSS applied during the data write period DWP. Furthermore, the fifth transistor T5 can be turned on in response to the second power supply voltage VSS at the first node N1, and the voltage of the third node N3 can be maintained at the first power supply voltage VDD. Furthermore, the eighth transistor T8 can be turned on in response to the first power supply voltage VDD at the third node N3, and the pulse signal SPWM can be maintained at the second power supply voltage VSS. Thus, the tenth transistor T10 can provide the constant current ICC generated by the ninth transistor T9 to the light-emitting element EL in response to the pulse signal SPWM having the second power supply voltage VSS, and the light-emitting element EL can emit light based on the constant current ICC.

[0071] In the sweep period SWP, when the voltage of the second node N2 decreases to a voltage VDD-|VTH| lower than the voltage VDD-|VTH| obtained by subtracting the absolute value |VTH| of the threshold voltage of the first transistor T1 from the first power supply voltage VDD, the first transistor T1 may be turned on, and the light emitting element EL may not emit light. In an embodiment, for example, in the non-emission time NET in the sweep period SWP, as shown in FIG. Figure 7As shown in FIG, when the voltage of the second node N2 decreases to below the voltage VDD-|VTH| obtained by subtracting the absolute value |VTH| of the threshold voltage of the first transistor T1 from the first power supply voltage VDD, the first transistor T1 may be turned on. When the first transistor T1 is turned on, the first transistor T1 may transmit the first power supply voltage VDD to the first node N1, and the voltage of the first node N1 may increase from the second power supply voltage VSS to the first power supply voltage VDD. The fifth transistor T5 may be turned off in response to the first power supply voltage VDD at the first node N1, and the sixth transistor T6 may be turned on in response to the first power supply voltage VDD at the first node N1. Therefore, the sixth transistor T6 may transmit the second power supply voltage VSS to the third node N3, and the voltage of the third node N3 may become the second power supply voltage VSS. In addition, the eighth transistor T8 may be turned off in response to the second power supply voltage VSS at the third node N3, and the seventh transistor T7 may be turned on in response to the second power supply voltage VSS at the third node N3. Therefore, the seventh transistor T7 may transfer the first power voltage VDD to the pulse output node NPO, and the pulse signal SPWM at the pulse output node NPO may increase or rise from the second power voltage VSS to the first power voltage VDD.

[0072] When the pulse signal SPWM applied to the second electrode of the feedback capacitor CFB rises from the second power supply voltage VSS to the first power supply voltage VDD, the speed at which the voltage of the first electrode of the feedback capacitor CFB or the voltage of the first node N1 rises from the second power supply voltage VSS to the first power supply voltage VDD can be increased. In addition, as the rising speed of the voltage of the first node N1 increases or increases, the rising speed of the pulse signal SPWM can also increase or increase through the sixth transistor T6 and the seventh transistor T7. For example, Figure 8 As shown in FIG, the rise time CRT of the pulse signal CSPWM of a conventional pixel without a feedback capacitor may be about 18.6 microseconds (μs), but the rise time RT of the pulse signal SPWM of the pixel 100 including the feedback capacitor CFB is improved or shortened to about 2.6 μs.

[0073] Return Reference Figure 4 and Figure 7 The tenth transistor T10 may be turned off in response to the pulse signal SPWM having the first power supply voltage VDD, and may not provide the constant current ICC to the light emitting element EL. Therefore, the light emitting element EL may not emit light.

[0074] In such an embodiment, as described above, while the pulse signal SPWM has a low level or the second power supply voltage VSS during the data write period DWP and a portion of the sweep period SWP, the light emitting element EL may emit light, and while the pulse signal SPWM has a high level or the first power supply voltage VDD during the remaining period of the sweep period SWP, the light emitting element EL may not emit light. That is, the emission time ET of the light emitting element EL may be determined based on the pulse width of the pulse signal SPWM having the second power supply voltage VSS, and the pulse width of the pulse signal SPWM may be determined based on the voltage level of the data voltage VDAT. In an embodiment, for example, as Figure 4 As shown in , when a data voltage VDAT' having a relatively high voltage level is applied to the pixel 100, a period during which the voltage of the second node N2 is higher than the voltage VDD-|VTH| obtained by subtracting the absolute value |VTH| of the threshold voltage of the first transistor T1 from the first power supply voltage VDD can be increased, and the pulse width of the pulse signal SPWM can be increased. When the pulse width of the pulse signal SPWM increases, the non-emission time NET' of the light emitting element EL can be reduced, the emission time ET' of the light emitting element EL can be increased, and the brightness of the pixel 100 can be increased within the frame period FP. That is, the brightness of the pixel 100 can be adjusted using a PWM method that adjusts the pulse width of the pulse signal SPWM.

[0075] Furthermore, as described above, in the pixel 100 according to the embodiment, the rising time RT (and / or falling time) of the pulse signal SPWM may be improved by the feedback capacitor CFB, and the image quality of the display device including the pixel 100 may be improved.

[0076] Figure 9 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0077] refer to Figure 9 , the pixel 200 according to the embodiment may include a first transistor T1, a second transistor T2, a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a storage capacitor CST, a feedback capacitor CFB and a light emitting element EL. Except for omitting Figure 1 In addition to the fourth transistor T4 shown in FIG. Figure 9 The pixel 200 may have Figures 1 to 3 The pixel 100 shown in FIG. 1 has substantially the same configuration and substantially the same operation.

[0078] In an embodiment, the pixel 200 may not include Figure 1The fourth transistor T4 is shown in FIG, and the data voltage of the data line DL may be transmitted to the second node N2 using the third transistor T3. The third transistor T3 may transmit the data voltage to the second node N2 in response to the scan signal SC[n].

[0079] Figure 10 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0080] refer to Figure 10 , the pixel 300 according to the embodiment may include a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a storage capacitor CST, a feedback capacitor CFB and a light emitting element EL. Except for omitting Figure 1 In addition to the third transistor T3 shown in FIG, Figure 10 The pixel 300 may have Figures 1 to 3 The pixel 100 shown in FIG. 1 has substantially the same configuration and substantially the same operation.

[0081] In an embodiment, the pixel 300 may not include the third transistor T3 and may transmit the data voltage of the data line DL to the second node N2 using the fourth transistor T4. The fourth transistor T4 may transmit the data voltage to the second node N2 in response to the inverse scan signal SCB[n].

[0082] Figure 11 is a circuit diagram showing a pixel of a display device according to an embodiment, and Figure 12 is a timing chart for describing an example of the operation of a pixel according to an embodiment.

[0083] refer to Figure 11 According to the embodiment, the pixel 400 may include a first transistor T1', a second transistor T2', a third transistor T3', a fourth transistor T4', a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9', a tenth transistor T10', a storage capacitor CST, a feedback capacitor CFB and a light emitting element EL. In addition to the pixel 400 being Figures 1 to 3 In addition to the pixel 100 shown in FIG. Figure 11 The pixel 400 may have Figures 1 to 3 1 and 2. The pixel 100 shown in FIG. 1 has a similar configuration and similar operation.

[0084] exist Figure 11In an embodiment of the pixel 400, the first transistor T1', the fourth transistor T4', the ninth transistor T9', and the tenth transistor T10' may be NMOS transistors, and the second transistor T2' and the third transistor T3' may be PMOS transistors. The first transistor T1' may apply the second power supply voltage VSS to the first node N1 in response to the voltage of the second node N2, and the second transistor T2' may apply the first power supply voltage VDD to the first node N1 in response to the scan signal SC[n]'.

[0085] In addition, if Figure 12 As shown in FIG, in the data write period DWP, the scan signal SC[n]' may have a low level, and the inverted scan signal SCB[n]' may have a high level. The third transistor T3' may be turned on in response to the scan signal SC[n]' having a low level, and the fourth transistor T4' may be turned on in response to the inverted scan signal SCB[n]' having a high level. The third transistor T3' and the fourth transistor T4' may transmit the data voltage VDAT to the second node N2.

[0086] Furthermore, during the sweep period SWP, the voltage level of the sweep signal SWEEP[n]' can gradually increase, and the voltage of the second node N2 can also gradually increase via the storage capacitor CST. When the voltage of the second node N2 is lower than the sum of the second power supply voltage VSS and the threshold voltage VTH of the first transistor T1', the pulse signal SPWM' can have the first power supply voltage VDD. When the pulse signal SPWM' has the first power supply voltage VDD, the tenth transistor T10' can be turned on, and the light-emitting element EL can emit light based on the constant current generated by the ninth transistor T9' in response to the bias voltage VBIAS'. Furthermore, the pulse width of the pulse signal SPWM' having the first power supply voltage VDD can be adjusted or modulated according to the voltage level of the data voltage VDAT, and the emission time ET of the light-emitting element EL can be adjusted based on the pulse width of the pulse signal SPWM' having the first power supply voltage VDD. Furthermore, in the pixel 400 according to the embodiment, the fall time of the pulse signal SPWM' from the first power supply voltage VDD to the second power supply voltage VSS can be improved or shortened via the feedback capacitor CFB, thereby improving the image quality of the display device.

[0087] Figure 13 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0088] refer to Figure 13, the pixel 500 according to the embodiment may include a first transistor T1', a second transistor T2', a third transistor T3', a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9', a tenth transistor T10', a storage capacitor CST, a feedback capacitor CFB and a light emitting element EL. Except for omitting Figure 11 In addition to the fourth transistor T4' shown in FIG. Figure 13 The pixel 500 may have Figure 11 The pixel 400 has substantially the same configuration and substantially the same operation.

[0089] In an embodiment, the pixel 500 may not include the fourth transistor T4' and may transmit the data voltage of the data line DL to the second node N2 using the third transistor T3'. The third transistor T3' may transmit the data voltage to the second node N2 in response to the scan signal SC[n]'.

[0090] Figure 14 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0091] refer to Figure 14 , the pixel 600 according to the embodiment may include a first transistor T1', a second transistor T2', a fourth transistor T4', a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9', a tenth transistor T10', a storage capacitor CST, a feedback capacitor CFB and a light emitting element EL. Except for omitting Figure 11 In addition to the third transistor T3' shown in FIG. Figure 14 The pixel 600 may have Figure 11 The pixel 400 has substantially the same configuration and substantially the same operation.

[0092] In an embodiment, the pixel 600 may not include the third transistor T3' and may transmit the data voltage of the data line DL to the second node N2 using the fourth transistor T4'. The fourth transistor T4' may transmit the data voltage to the second node N2 in response to the inverted scan signal SCB[n]'.

[0093] Figure 15 is a block diagram illustrating a display device according to an embodiment.

[0094] refer to Figure 15According to an embodiment, a display device 900 may include: a display panel 910 including a plurality of pixels PX; a data driver 930 providing a data voltage VDAT to the plurality of pixels PX; a scan driver 950 providing a scan signal SC[n] and / or an inverted scan signal SCB[n] to the plurality of pixels PX; a sweep driver 970 providing a sweep signal SWEEP[n] to the plurality of pixels PX; and a controller 990 controlling the data driver 930, the scan driver 950, and the sweep driver 970.

[0095] The display panel 910 may include a plurality of pixels PX. According to an embodiment, each pixel PX of the display panel 910 may be Figure 1 100 pixels, Figure 9 200 pixels, Figure 10 300 pixels, Figure 11 400 pixels, Figure 13 500 pixels or Figure 14 Pixel 600. In each pixel PX, the pulse generating circuit may include a plurality of inverters connected in series and a feedback capacitor connected between the input and output nodes of the plurality of inverters. Thus, the rise (and / or fall) time of the pulse signal can be improved, and the image quality of the display device 900 can be improved.

[0096] The data driver 930 can provide data voltages VDAT to a plurality of pixels PX based on a data control signal DCTRL and output image data ODAT received from the controller 990. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. In addition, in some embodiments, the data driver 930 and the controller 990 can be implemented as a single integrated circuit, and this single integrated circuit can be referred to as a timing controller embedded data driver (TED). In other embodiments, the data driver 930 and the controller 990 can be implemented as separate integrated circuits.

[0097] The scan driver 950 can sequentially provide scan signals SC[n] and / or inverted scan signals SCB[n] to a plurality of pixels PX on a row-by-row basis based on a scan control signal SCTRL received from the controller 990. In some embodiments, the scan control signal SCTRL can include, but is not limited to, a scan start signal and a scan clock signal. In some embodiments, the scan driver 950 can be integrated or formed in the display panel 910. In other embodiments, the scan driver 950 can be implemented as one or more integrated circuits.

[0098] The sweep driver 970 can sequentially provide a sweep signal SWEEP[n] to a plurality of pixels PX on a row-by-row basis based on a sweep control signal SWPCTRL received from the controller 990. In addition, the sweep signal SWEEP[n] can gradually decrease (or increase) during the sweep period. In some embodiments, the sweep control signal SWPCTRL can include, but is not limited to, a sweep clock signal. In addition, in some embodiments, the sweep driver 970 can be integrated or formed in the display panel 910. In other embodiments, the sweep driver 970 can be implemented in one or more integrated circuits.

[0099] The controller 990 (e.g., a timing controller) can receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a main clock signal. The controller 990 can generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and a sweep control signal SWPCTRL based on the input image data IDAT and the control signal CTRL. The controller 990 can control the data driver 930 by providing the output image data ODAT and the data control signal DCTRL, control the scan driver 950 by providing the scan control signal SCTRL, and control the sweep driver 970 by providing the sweep control signal SWPCTRL to the sweep driver 970.

[0100] In the display device 900 according to the embodiment, each pixel PX can drive the light-emitting element based on a constant current having a constant current level. Therefore, the color shift phenomenon in the display device 900 can be effectively prevented. Each pixel PX can include a feedback capacitor connected between the input node and the output node of the plurality of inverters that generate the pulse signal. Therefore, the rise (and / or fall) time of the pulse signal can be improved, and the image quality of the display device 900 can be improved.

[0101] Figure 16 is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0102] refer to Figure 16, an embodiment of the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0103] The processor 1110 can perform various computing functions or tasks. The processor 1110 can be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 can be connected to other components via an address bus, a control bus, a data bus, etc. In addition, in some embodiments, the processor 1110 can also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0104] The memory device 1120 may store data used for the operation of the electronic device 1100. In an embodiment, for example, the memory device 1120 may include at least one nonvolatile memory device and / or at least one volatile memory device, the at least one nonvolatile memory device being, for example, an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and the at least one volatile memory device being, for example, a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0105] The storage device 1130 may be a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 may provide power for the operation of the electronic device 1100. The display device 1160 may be coupled to other components via a bus or other communication link.

[0106] In an embodiment of the display device 1160, each pixel can drive a light-emitting element based on a constant current having a constant current level. Therefore, the color shift phenomenon in the display device 1160 can be effectively prevented. In addition, in the display device 1160, each pixel can include a feedback capacitor connected between the input node and the output node of the plurality of inverters that generate the pulse signal. Therefore, the rise (and / or fall) time of the pulse signal can be improved, and the image quality of the display device 1160 can be improved.

[0107] Embodiments of the present invention can be applied to any display device 1160 and any electronic device 1100 including the display device 1160, such as smart phones, wearable electronic devices, mobile phones, televisions (TVs) (e.g., digital TVs, three-dimensional (3D) TVs, etc.), personal computers (PCs) (e.g., tablet computers, laptop computers, etc.), home appliances, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0108] The present invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0109] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A pixel of a display device, the pixel comprising: Light-emitting element; A constant current generating circuit generates a constant current; A pulse generating circuit for generating a pulse signal; as well as an emission transistor, supplying the constant current to the light emitting element in response to the pulse signal, Wherein, the pulse generating circuit includes: a plurality of inverters connected in series with each other, wherein the plurality of inverters output the pulse signal at a pulse output node based on the voltage of the first node; and A feedback capacitor includes a first electrode connected to the first node and a second electrode connected to the pulse output node.

2. The pixel according to claim 1, wherein The emission time of the light emitting element is determined based on the pulse width of the pulse signal.

3. The pixel according to claim 1, wherein The pulse generating circuit further includes: a first transistor that applies a first power supply voltage to the first node in response to a voltage of a second node; and The second transistor applies a second power supply voltage to the first node in response to a scan signal.

4. The pixel according to claim 3, wherein The first transistor includes a gate connected to the second node, a first terminal receiving the first power supply voltage, and a second terminal connected to the first node, and The second transistor includes a gate receiving the scan signal, a first terminal receiving the second power supply voltage, and a second terminal connected to the first node.

5. The pixel according to claim 3, wherein The first power supply voltage is a high power supply voltage, wherein the second power supply voltage is a low power supply voltage, Wherein, the first transistor is a P-type metal oxide semiconductor transistor, and The second transistor is an N-type metal oxide semiconductor transistor.

6. The pixel according to claim 3, wherein the first power supply voltage is a low power supply voltage, wherein the second power supply voltage is a high power supply voltage, Wherein, the first transistor is an N-type metal oxide semiconductor transistor, and The second transistor is a P-type metal oxide semiconductor transistor.

7. The pixel according to claim 3, wherein: The pulse generating circuit further includes: The third transistor applies a data voltage to the second node in response to the scan signal.

8. The pixel according to claim 3, wherein: The pulse generating circuit further includes: The fourth transistor applies a data voltage to the second node in response to an inverted scan signal.

9. The pixel according to claim 3, wherein: The pulse generating circuit further includes: a third transistor applying a data voltage to the second node in response to the scan signal; and The fourth transistor applies the data voltage to the second node in response to an inverted scan signal.

10. The pixel according to claim 9, wherein: The third transistor includes a gate receiving the scan signal, a first terminal connected to the second node, and a second terminal receiving the data voltage, and The fourth transistor includes a gate receiving the inverse scan signal, a first terminal receiving the data voltage, and a second terminal connected to the second node.

11. The pixel according to claim 9, wherein The third transistor is a P-type metal oxide semiconductor transistor, and Wherein, the fourth transistor is an N-type metal oxide semiconductor transistor.

12. The pixel according to claim 9, wherein The third transistor is an N-type metal oxide semiconductor transistor, and Wherein, the fourth transistor is a P-type metal oxide semiconductor transistor.

13. The pixel according to claim 9, wherein: The pulse generating circuit further includes: The storage capacitor includes a first electrode receiving the sweep frequency signal and a second electrode connected to the second node.

14. The pixel according to claim 13, wherein: The voltage level of the frequency sweep signal gradually decreases during the frequency sweep period.

15. The pixel according to claim 13, wherein: The voltage level of the frequency sweep signal gradually increases during the frequency sweep period.

16. The pixel according to claim 13, wherein: The plurality of inverters include: a first inverter that inverts the voltage of the first node and outputs the inverted voltage to a third node; and The second inverter inverts the voltage of the third node and outputs the pulse signal at the pulse output node.

17. The pixel according to claim 16, wherein: The first inverter comprises: a fifth transistor including a gate connected to the first node, a first terminal receiving the first power supply voltage, and a second terminal connected to the third node; and a sixth transistor including a gate connected to the first node, a first terminal receiving the second power supply voltage, and a second terminal connected to the third node, and Wherein, the second inverter comprises: a seventh transistor including a gate connected to the third node, a first terminal receiving the first power supply voltage, and a second terminal connected to the pulse output node; and An eighth transistor includes a gate connected to the third node, a first terminal receiving the second power supply voltage, and a second terminal connected to the pulse output node.

18. The pixel according to claim 17, wherein: The fifth transistor and the seventh transistor are P-type metal oxide semiconductor transistors, and Wherein, the sixth transistor and the eighth transistor are N-type metal oxide semiconductor transistors.

19. A pixel of a display device, the pixel comprising: a first transistor including a gate connected to the second node, a first terminal receiving a first power supply voltage, and a second terminal connected to the first node; a second transistor including a gate receiving a scan signal, a first terminal receiving a second power supply voltage, and a second terminal connected to the first node; a third transistor including a gate receiving the scan signal, a first terminal connected to the second node, and a second terminal receiving a data voltage; a fourth transistor comprising a gate receiving an inverted scan signal, a first terminal receiving the data voltage, and a second terminal connected to the second node; a storage capacitor comprising a first electrode receiving the frequency sweep signal and a second electrode connected to the second node; a fifth transistor including a gate connected to the first node, a first terminal receiving the first power supply voltage, and a second terminal connected to a third node; a sixth transistor including a gate connected to the first node, a first terminal receiving the second power supply voltage, and a second terminal connected to the third node; a seventh transistor including a gate connected to the third node, a first terminal receiving the first power supply voltage, and a second terminal connected to a pulse output node; an eighth transistor including a gate connected to the third node, a first terminal receiving the second power supply voltage, and a second terminal connected to the pulse output node; a feedback capacitor comprising a first electrode connected to the first node and a second electrode connected to the pulse output node; a ninth transistor comprising a gate receiving a bias voltage, a first terminal receiving the first power supply voltage, and a second terminal; a tenth transistor comprising a gate connected to the pulse output node, a first terminal connected to the second terminal of the ninth transistor, and a second terminal; as well as The light emitting element includes an anode connected to the second terminal of the tenth transistor and a cathode receiving the second power supply voltage.

20. A display device comprising: a display panel comprising a plurality of pixels; a data driver that provides a data voltage to each of the plurality of pixels; a scan driver providing a scan signal to each of the plurality of pixels; a sweep frequency driver for providing a sweep frequency signal to each of the plurality of pixels; as well as a controller for controlling the data driver, the scan driver, and the frequency sweep driver, Wherein, each of the plurality of pixels comprises: Light-emitting element; A constant current generating circuit generates a constant current; a pulse generating circuit for generating a pulse signal; and an emission transistor that supplies the constant current to the light emitting element in response to the pulse signal, and Wherein, the pulse generating circuit includes: a plurality of inverters connected in series with each other, wherein the plurality of inverters output the pulse signal at a pulse output node based on the voltage of the first node; and A feedback capacitor includes a first electrode connected to the first node and a second electrode connected to the pulse output node.

Images