Display device

Abstract

The display device includes: a substrate; a polycrystalline semiconductor layer including a channel of the driving transistor and a channel of the seventh transistor; a gate electrode of the driving transistor overlapping with its channel; a gate electrode of the seventh transistor overlapping with its channel; an oxide semiconductor layer including a channel of the fourth transistor; a gate electrode of the fourth transistor overlapping with its channel; a first initialization voltage line connected to a first electrode of the fourth transistor, the first initialization voltage line and a gate electrode of the fourth transistor being on the same layer; and a second initialization voltage line connected to a second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being on different layers from each other.

Description

[0001] This application is a divisional application of patent application entitled "Display device" filed on February 24, 2021, with application number 202110208318.9.

[0002] Cross Reference to Related Applications

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0027043 filed in the Korean Intellectual Property Office on March 4, 2020, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0004] The present disclosure relates to a display device, and more particularly, to a display device including a transistor having a polysilicon semiconductor and a transistor having an oxide semiconductor. BACKGROUND

[0005] An organic light emitting device includes two electrodes and an organic emission layer disposed between the two electrodes, and an electron injected from one electrode and a hole injected from the other electrode combine in the organic emission layer to form an exciton. The exciton transitions from an excited state to a ground state to output energy and emit light.

[0006] An organic light emitting device includes a plurality of pixels including an organic light emitting diode which is a self-emitting device, and a plurality of transistors for driving the organic light emitting diode and at least one capacitor are formed on the respective pixels. The plurality of transistors include a switching transistor and a driving transistor.

[0007] As the number of pixels increases in order to improve the resolution of the organic light emitting device, and a high-speed driving process is performed in order to achieve stable video, the aperture ratio can decrease, the current density can increase, and the driving voltage can increase. Accordingly, a stain is generated, and the reliability of elements such as a transistor deteriorates.

[0008] The above information disclosed in the Background section is only for enhancing the understanding of the background of the technology, and therefore it can contain information that does not constitute prior art that is already known in this country to those of ordinary skill in the art. SUMMARY

[0009] The described technology is directed to driving a display device in a stable manner, improving reliability, and reducing power consumption.

[0010] According to an example embodiment of the present application, a display device includes: a substrate; a polycrystalline semiconductor layer over the substrate, the polycrystalline semiconductor layer including a channel, a first electrode, and a second electrode of a driver transistor and a channel, a first electrode, and a second electrode of a seventh transistor; a gate electrode of the driver transistor overlapping with the channel of the driver transistor; a gate electrode of the seventh transistor overlapping with the channel of the seventh transistor; an oxide semiconductor layer over the substrate, the oxide semiconductor layer including a channel, a first electrode, and a second electrode of a fourth transistor; a gate electrode of the fourth transistor overlapping with the channel of the fourth transistor; a first initialization voltage line connected to the first electrode of the fourth transistor, the first initialization voltage line and the gate electrode of the fourth transistor being on the same layer; and a second initialization voltage line connected to the second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being on different layers from each other.

[0011] The first initialization voltage line overlaps with the second initialization voltage line.

[0012] The display device further includes: a scan line overlapping with the first initialization voltage line and the second initialization voltage line; a data line overlapping with the first initialization voltage line and the second initialization voltage line; and a second transistor connected to the scan line and the data line.

[0013] The display device further includes a connection electrode for connecting the first initialization voltage line and the first electrode of the fourth transistor.

[0014] The display device further includes an insulating layer between the first initialization voltage line and the connection electrode and between the first electrode of the fourth transistor and the connection electrode, the insulating layer including a first opening exposing the first initialization voltage line and a second opening exposing the first electrode of the fourth transistor, the connection electrode being connected to the first initialization voltage line through the first opening and connected to the first electrode of the fourth transistor through the second opening.

[0015] The connection electrode and the data line are provided on the same layer, and the connection electrode overlaps with the first initialization voltage line and the first electrode of the fourth transistor.

[0016] The display device further includes a connection electrode for connecting the second initialization voltage line and the second electrode of the seventh transistor.

[0017] The display device further includes an insulating layer between the second initialization voltage line and the connection electrode and between the second electrode of the seventh transistor and the connection electrode, the insulating layer including a first opening exposing the second initialization voltage line and a second opening exposing the second electrode of the seventh transistor, the connection electrode being connected to the second initialization voltage line through the first opening and connected to the second electrode of the seventh transistor through the second opening.

[0018] The connection electrode and the data line are provided on the same layer, and the connection electrode overlaps the second initialization voltage line and the second electrode of the seventh transistor.

[0019] The first initialization voltage is applied to the first electrode of the fourth transistor via the first initialization voltage line, the second initialization voltage is applied to the second electrode of the seventh transistor via the second initialization voltage line, and the first initialization voltage can be different from the second initialization voltage.

[0020] The display device further includes a first storage electrode overlapping the gate electrode of the driving transistor, the second initialization voltage line and the first storage electrode are on the same layer, the oxide semiconductor layer further includes a channel, a first electrode, and a second electrode of the third transistor, and the channel of the third transistor and the channel of the fourth transistor are on the same layer.

[0021] The display device further includes a light-blocking layer of the fourth transistor overlapping the channel of the fourth transistor, the light-blocking layer of the fourth transistor and the first storage electrode are on the same layer.

[0022] The display device further includes a gate electrode of the third transistor overlapping the channel of the third transistor, a light-blocking layer of the third transistor overlaps the channel of the third transistor, the light-blocking layer of the third transistor and the first storage electrode are on the same layer, and the connection electrode connects the second electrode of the driving transistor and the first electrode of the third transistor.

[0023] The display device includes a plurality of pixels, each of the plurality of pixels includes a driving transistor, a fourth transistor, and a seventh transistor, and the plurality of pixels have the same shape as each other.

[0024] According to an exemplary embodiment of the present invention, a display device includes: a light emitting diode connected between a driving voltage line for applying a driving voltage to an anode of the light emitting diode and a common voltage line for applying a common voltage to a cathode of the light emitting diode; a driving transistor connected between the driving voltage line and the anode of the light emitting diode and configured to supply a driving current to the light emitting diode; a second transistor connected between a first electrode of the driving transistor connected to the driving voltage line and a data line to which a data voltage is applied; a third transistor connected between a second electrode of the driving transistor connected to the light emitting diode and a gate electrode of the driving transistor; a fourth transistor connected between the gate electrode of the driving transistor and a first initialization voltage line to which a first initialization voltage is applied; a seventh transistor connected between the anode of the light emitting diode and a second initialization voltage line to which a second initialization voltage is applied; and a storage capacitor connected between the driving voltage line and the gate electrode of the driving transistor. The driving transistor and the second transistor include a polycrystalline semiconductor layer, and the third transistor and the fourth transistor can include an oxide semiconductor layer.

[0025] The first initialization voltage line overlaps the second initialization voltage line.

[0026] The display device further includes a scan line connected to the second transistor and receiving a scan signal. The scan line overlaps the first initialization voltage line and the second initialization voltage line.

[0027] The display device further includes a first connection electrode connecting the first initialization voltage line and the fourth transistor, and a second connection electrode connecting the second initialization voltage line and the seventh transistor.

[0028] The driving transistor, the second transistor, and the seventh transistor are p-type transistors, and the third transistor and the fourth transistor are n-type transistors.

[0029] The display device further includes a fifth transistor connected between the driving voltage line and the first electrode of the driving transistor, and a sixth transistor connected between the second electrode of the driving transistor and the light emitting diode.

[0030] According to exemplary embodiments, a display device can be stably driven, reliability can be improved, and power consumption can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 A circuit diagram of a display device according to an exemplary embodiment is shown.

[0032] Figure 2 A top view of a display device according to an exemplary embodiment is shown.

[0033] Figure 3 A cross-sectional view taken along line III-III of Figure 2 is shown.

[0034] Figure 4 A cross-sectional view taken along line IV-IV of Figure 2 is shown.

[0035] Figure 5 A cross-sectional view taken along line V-V of Figure 2 is shown.

[0036] Figures 6 to 10 Top views according to a sequence for manufacturing a display device according to an exemplary embodiment are shown in sequence. DETAILED DESCRIPTION

[0037] The present application will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the application are shown. As those skilled in the art will appreciate, the described embodiments can be modified in various different ways without departing from the spirit or scope of the application.

[0038] The accompanying drawings and description are to be understood as being in essence illustrative and not restrictive, and throughout the specification like reference numerals indicate like elements.

[0039] For better understanding and ease of description, the size and thickness of each configuration shown in the drawings are arbitrarily shown, and the present application is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, and the like is exaggerated for clarity. For better understanding and ease of description, the thickness of some layers and regions is exaggerated.

[0040] It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. Further, in the specification, the word "on" or "above" means positioned on or below the object portion, and does not necessarily mean positioned on the upper side of the object portion based on the direction of gravity.

[0041] Unless otherwise described, the word "comprise" and variations such as "comprises" or "comprising" shall be understood to encompass the stated elements but not exclude any other elements.

[0042] The phrase "in plan view" means to observe the object portion from the top, and the phrase "in cross-sectional view" means to observe a cross-section of the object portion cut vertically from the side.

[0043] Reference will now be made to Figure 1 A pixel of a display device according to an exemplary embodiment is described.

[0044] Figure 1 A circuit diagram of a display device according to an exemplary embodiment is shown. One pixel PX of the display device according to an exemplary embodiment includes a storage capacitor Cst, a boost capacitor Cboost, a light emitting diode LED, and a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to various signal lines 127, 128, 151, 152, 153, 154, 155, 171, 172, and 741.

[0045] The display device includes a display area for displaying an image, and the pixels PX are arranged in various forms in the display area.

[0046] A plurality of signal lines 127, 128, 151, 152, 153, 154, 155, 171, 172, and 741 are connected to one pixel PX. The plurality of signal lines include a first initialization voltage line 127, a second initialization voltage line 128, a scan line 151, an inverted scan line 152, an initialization control line 153, a bypass control line 154, an emission control line 155, a data line 171, a driving voltage line 172, and a common voltage line 741.

[0047] The scan line 151 is connected to a gate driver (not shown) and transmits a scan signal GW to the second transistor T2. The inverted scan line 152 can receive a voltage having an opposite polarity from a voltage applied to the scan line 151 with the same timing as a signal of the scan line 151. For example, when a high voltage is applied to the scan line 151, a low voltage can be applied to the inverted scan line 152. The inverted scan line 152 transmits an inverted scan signal GC to the third transistor T3.

[0048] The initialization control line 153 transmits an initialization control signal GI to the fourth transistor T4 (i.e., a first initialization transistor). The bypass control line 154 transmits a bypass signal GB to the seventh transistor T7 (i.e., a second initialization transistor). The bypass control line 154 can be made of the scan line 151 at a rear end. The emission control line 155 transmits an emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0049] The data line 171 is a wiring for transmitting a data voltage DATA generated by a data driver (not shown), and brightness of light emitted by the light emitting diode LED is changed according to the data voltage DATA applied to the pixel PX.

[0050] The driving voltage line 172 applies a driving voltage ELVDD. For example, the driving voltage ELVDD is supplied to the pixel PX via the driving voltage line 172. The first initialization voltage line 127 transmits a first initialization voltage VINT, and the second initialization voltage line 128 transmits a second initialization voltage AINT. The common voltage line 741 applies a common voltage ELVSS to a cathode of the light emitting diode LED. In the present exemplary embodiment, the voltages applied to the driving voltage line 172, the first initialization voltage line 127, and the second initialization voltage line 128, and the common voltage line 741 can be constant voltages.

[0051] The configuration and connection relationship of the plurality of transistors will now be described in detail.

[0052] The driving transistor T1 (i.e., first transistor) can be a p-type transistor and can include a polycrystalline semiconductor (i.e., polycrystalline semiconductor layer). The driving transistor T1 controls the magnitude of the current output to the anode of the light emitting diode LED according to the data voltage DATA applied to the gate electrode of the driving transistor T1. The brightness of the light emitting diode LED is controlled by the magnitude of the driving current output to the anode of the light emitting diode LED, and thus the brightness of the light emitting diode LED can be controlled according to the data voltage DATA applied to the pixel PX. To this end, the first electrode of the driving transistor T1 receives the driving voltage ELVDD and is connected to the driving voltage line 172 through the fifth transistor T5. The first electrode of the driving transistor T1 is connected to the second electrode of the second transistor T2 to receive the data voltage DATA. The second electrode of the driving transistor T1 outputs the current to the light emitting diode LED and is connected to the anode of the light emitting diode LED through the sixth transistor T6. The second electrode of the driving transistor T1 transmits the data voltage DATA applied to the first electrode to the third transistor T3. The gate electrode of the driving transistor T1 is connected to one electrode (hereinafter, second storage electrode) of the storage capacitor Cst. The voltage at the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and the driving current output by the driving transistor T1 changes accordingly. The storage capacitor Cst also maintains the voltage at the gate electrode of the driving transistor T1 for one frame.

[0053] The second transistor T2 can be a p-type transistor and can include a polycrystalline semiconductor. The second transistor T2 receives the data voltage DATA to be supplied to the pixel PX. The gate electrode of the second transistor T2 is connected to the scan line 151 and the first electrode of the boost capacitor Cboost. The first electrode of the second transistor T2 is connected to the data line 171. The second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1. When the second transistor T2 is turned on by the low voltage in the scan signal GW transmitted through the scan line 151, the data voltage DATA transmitted through the data line 171 is transmitted to the first electrode of the driving transistor T1.

[0054] The third transistor T3 (i.e., an oxide semiconductor transistor) can be an n-type transistor and can include an oxide semiconductor (i.e., an oxide semiconductor layer). The third transistor T3 electrically connects the second electrode of the driver transistor T1 and the gate electrode of the driver transistor T1. As a result, the third transistor T3 transmits a compensation voltage, which is changed when a data voltage DATA passes through the driver transistor T1, to the second storage electrode of the storage capacitor Cst. The gate electrode of the third transistor T3 is connected to the inverted scan line 152, and the first electrode of the third transistor T3 is connected to the second electrode of the driver transistor T1. The second electrode of the third transistor T3 is connected to the second storage electrode of the storage capacitor Cst, the gate electrode of the driver transistor T1, and the second electrode of the boost capacitor Cboost. The third transistor T3 is turned on by a high voltage in the inverted scan signal GC transmitted through the inverted scan line 152 to connect the gate electrode of the driver transistor T1 and the second electrode of the driver transistor T1, and to transmit a voltage applied to the gate electrode of the driver transistor T1 to the second storage electrode of the storage capacitor Cst and store it in the storage capacitor Cst.

[0055] The fourth transistor T4 can be an n-type transistor and can include an oxide semiconductor (i.e., an oxide semiconductor layer). The fourth transistor T4 initializes the gate electrode of the driver transistor T1 and the second storage electrode of the storage capacitor Cst. The gate electrode of the fourth transistor T4 is connected to the initialization control line 153, and the first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127. The second electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, the second storage electrode of the storage capacitor Cst, the gate electrode of the driver transistor T1, and the second electrode of the boost capacitor Cboost. The fourth transistor T4 is turned on by a high voltage in the initialization control signal GI received through the initialization control line 153, and in response to the high voltage of the initialization control signal GI, the fourth transistor T4 transmits the first initialization voltage VINT to the gate electrode of the driver transistor T1 and the second storage electrode of the storage capacitor Cst. Accordingly, the voltage at the gate electrode of the driver transistor T1 and the storage capacitor Cst are initialized.

[0056] The fifth transistor T5 can be a p-type transistor and can include a polycrystalline semiconductor. The fifth transistor T5 transmits a driving voltage ELVDD to the driver transistor T1. The gate electrode of the fifth transistor T5 is connected to the emission control line 155, the first electrode of the fifth transistor T5 is connected to the driving voltage line 172, and the second electrode of the fifth transistor T5 is connected to the first electrode of the driver transistor T1.

[0057] The sixth transistor T6 can be a p-type transistor and can include a polycrystalline semiconductor. The sixth transistor T6 transmits a driving current output from the driving transistor T1 to the light emitting diode LED. A gate electrode of the sixth transistor T6 is connected to the emission control line 155, a first electrode of the sixth transistor T6 is connected to a second electrode of the driving transistor T1, and a second electrode of the sixth transistor T6 is connected to an anode of the light emitting diode LED.

[0058] The seventh transistor T7 (i.e., a second initialization transistor) can be a p-type transistor and can include a polycrystalline semiconductor. The seventh transistor T7 initializes an anode of the light emitting diode LED. A gate electrode of the seventh transistor T7 is connected to the bypass control line 154, a first electrode of the seventh transistor T7 is connected to the anode of the light emitting diode LED, and a second electrode of the seventh transistor T7 is connected to the second initialization voltage line 128. When the seventh transistor T7 is turned on by a low voltage in the bypass signal GB, the second initialization voltage AINT is applied to the anode of the light emitting diode LED to be initialized.

[0059] It has been described that one pixel includes seven transistors T1 to T7, one storage capacitor Cst, and one boost capacitor Cboost, but the present exemplary embodiment is not limited thereto, and the number of transistors, the number of capacitors, and their connection relationship can be modified in various ways.

[0060] In the present exemplary embodiment, the driving transistor T1 can include a polycrystalline semiconductor. The third transistor T3 and the fourth transistor T4 can include an oxide semiconductor. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can include a polycrystalline semiconductor. However, they are not limited thereto, and at least any one of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can include an oxide semiconductor. In the present exemplary embodiment, the third transistor T3 and the fourth transistor T4 include a different semiconductor material from the driving transistor T1, so their driving strength can be more stable and reliability can be improved.

[0061] As described above, when a high voltage is applied to the scan line 151, a low voltage is applied to the inverse scan line 152, and when a low voltage is applied to the scan line 151, a high voltage is applied to the inverse scan line 152. For example, the inverse scan signal GC applied to the inverse scan line 152 includes the scan signal GW applied to the scan line 151 and an inverse signal, thereby lowering the gate voltage of the drive transistor T1 after data is programmed. In contrast, the scan signal GW raises the gate voltage of the drive transistor T1 by the boost capacitor Cboost. Thus, when a black voltage is programmed, the black voltage can be reduced. In the present exemplary embodiment, by locating the boost capacitor Cboost between the scan line 151 for applying the scan signal GW and the gate electrode of the drive transistor T1, the gate voltage of the drive transistor T1 can be increased so that the drive transistor T1 stably outputs the black voltage. The gate voltage of the drive transistor T1 can be further increased as the capacitance of the boost capacitor Cboost increases. The gate voltage of the drive transistor T1 can be controlled by controlling the capacitance of the boost capacitor Cboost.

[0062] Reference will now be made to Figures 2 to 10 The planar and cross-sectional configurations of the drive transistor T1, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 will be described in more detail.

[0063] Figure 2 A plan view of a display device according to an exemplary embodiment is shown, Figure 3 A cross-sectional view with respect to line III-III of Figure 2 A cross-sectional view with respect to line IV-IV of Figure 4 A cross-sectional view with respect to line IV-IV of Figure 2 A cross-sectional view with respect to line V-V of Figure 5 A cross-sectional view with respect to line V-V of Figure 2 A cross-sectional view with respect to line V-V of Figures 6 to 10 Plan views in order of a sequence of manufacturing a display device according to an exemplary embodiment are shown. Figures 2 to 10 Two adjacent pixels that can substantially have the same shape as each other are shown. The display device can include a plurality of pixels that can be repeatedly arranged to form a display area.

[0064] As shown in Figures 2 to 10 A polycrystalline semiconductor (i.e., a polycrystalline semiconductor layer) can be located on the substrate 110. The polycrystalline semiconductor can include the channel 1132, the first electrode 1131, and the second electrode 1133 of the drive transistor T1 and the channel 7132, the first electrode 7131, and the second electrode 7133 of the seventh transistor T7. Figure 6 A polycrystalline semiconductor is shown. The polycrystalline semiconductor can further include the channels, the first electrodes, and the second electrodes of the second transistor T2, the fifth transistor T5, and the sixth transistor T6.

[0065] The channel 1132 of the driver transistor T1 can be curved in a plan view. The shape of the channel 1132 of the driver transistor T1 is not limited thereto, and can be modified in various ways. For example, the channel 1132 of the driver transistor T1 can be curved in another shape, and it can have a bar shape. The first electrode 1131 and the second electrode 1133 of the driver transistor T1 can be located on opposite sides of the channel 1132 of the driver transistor T1. In a plan view, the first electrode 1131 of the driver transistor T1 can extend to the top side and the bottom side, and the upwardly extending portion of the first electrode 1131 can be connected to the second electrode of the second transistor T2, while the downwardly extending portion of the first electrode 1131 can be connected to the second electrode of the fifth transistor T5. In a plan view, the second electrode 1133 of the driver transistor T1 can extend downward, and can be connected to the first electrode of the sixth transistor T6.

[0066] In a plan view, the channel 7132 of the seventh transistor T7 can have a bar shape. The shape of the channel 7132 of the seventh transistor T7 is not limited thereto, and can be modified in various ways. The first electrode 7131 and the second electrode 7133 of the seventh transistor T7 can be formed on opposite sides of the channel 7132 of the seventh transistor T7. In a plan view, the first electrode 7131 of the seventh transistor T7 can be formed on the upper side of the channel 7132. In a plan view, the first electrode 7131 of the seventh transistor T7 can extend on the upper side and can reach the second electrode of the sixth transistor T6. In a plan view, the second electrode 7133 of the seventh transistor T7 can be formed on the lower side of the channel 7132.

[0067] A buffer layer 111 can be formed between the substrate 110 and the polycrystalline semiconductor including the channel 1132, the first electrode 1131, and the second electrode 1133 of the driver transistor T1 and the channel 7132, the first electrode 7131, and the second electrode 7133 of the seventh transistor T7. The buffer layer 111 can have a single-layer or multi-layer structure. The buffer layer 111 can include an organic insulating material or an inorganic insulating material.

[0068] A first gate insulating layer 141 can be formed on the polycrystalline semiconductor including the channel 1132, the first electrode 1131, and the second electrode 1133 of the driver transistor T1 and the channel 7132, the first electrode 7131, and the second electrode 7133 of the seventh transistor T7. The first gate insulating layer 141 can include silicon nitride or silicon oxide.

[0069] A first gate conductor including the gate electrode 1151 of the driver transistor T1 and the gate electrode 7151 of the seventh transistor T7 can be formed on the first gate insulating layer 141. Figure 7 The polycrystalline semiconductor and the first gate conductor are illustrated.

[0070] The gate electrode 1151 of the driver transistor T1 can overlap the channel 1132 of the driver transistor T1. The channel 1132 of the driver transistor T1 is covered with the gate electrode 1151 of the driver transistor T1. The gate electrode 7151 of the seventh transistor T7 can overlap the channel 7132 of the seventh transistor T7. The channel 7132 of the seventh transistor T7 is covered with the gate electrode 7151 of the seventh transistor T7.

[0071] The first gate conductor can further include a scan line 151, an emission control line 155, and a bypass control line 154. The scan line 151, the emission control line 155, and the bypass control line 154 can extend substantially in a horizontal direction. In a plan view, the scan line 151 can extend downward to reach the gate electrode of the second transistor T2 and the first electrode of the boost capacitor Cboost. The gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 can be connected to the emission control line 155. The gate electrode 7151 of the seventh transistor T7 can be connected to the bypass control line 154. The bypass control line 154 can be a scan line of a next pixel.

[0072] The first gate conductor including the gate electrode 1151 of the driver transistor T1 and the gate electrode 7151 of the seventh transistor T7 can be formed, and then a doping process can be performed. The polycrystalline semiconductor covered with the first gate conductor can not be doped, and a portion of the polycrystalline semiconductor not covered with the first gate conductor can be doped so as to be conductive. For example, the doping process can be performed with a p-type dopant, and the driver transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 including the polycrystalline semiconductor can be p-type transistors.

[0073] The second gate insulating layer 142 can be formed on the first gate conductor including the gate electrode 1151 of the driver transistor T1 and the gate electrode 7151 of the seventh transistor T7 and the first gate insulating layer 141. The second gate insulating layer 142 can include silicon nitride or silicon oxide.

[0074] The second gate conductor including the first storage electrode 1153 of the storage capacitor Cst, the light-blocking layer 3155 of the third transistor T3, and the light-blocking layer 4155 of the fourth transistor T4 can be formed on the second gate insulating layer 142. Figure 8 A polycrystalline semiconductor, a first gate conductor, and a second gate conductor are illustrated.

[0075] The first storage electrode 1153 overlaps with the gate electrode 1151 of the driver transistor Tl to form a storage capacitor Cst. An opening 1152 is formed in the first storage electrode 1153 of the storage capacitor Cst. The opening 1152 of the first storage electrode 1153 of the storage capacitor Cst can overlap with the gate electrode 1151 of the driver transistor Tl. The light-blocking layer 3155 of the third transistor T3 can overlap with the channel 3137 and the gate electrode 3151 of the third transistor T3. The light-blocking layer 4155 of the fourth transistor T4 can overlap with the channel 4137 and the gate electrode 4151 of the fourth transistor T4.

[0076] The second gate conductor can further include a second initialization voltage line 128 and an inverted scan line 152. The second initialization voltage line 128 and the inverted scan line 152 can extend substantially in a horizontal direction. The second initialization voltage line 128 can overlap with the channel 7132 and the first electrode 7131 of the seventh transistor T7. The second initialization voltage line 128 can overlap with the gate electrode 7151 of the seventh transistor T7. The inverted scan line 152 can be connected to the light-blocking layer 3155 of the third transistor T3.

[0077] The first interlayer insulating layer 161 can be formed over the second gate conductor including the first storage electrode 1153 of the storage capacitor Cst, the light-blocking layer 3155 of the third transistor T3, and the light-blocking layer 4155 of the fourth transistor T4.

[0078] The first interlayer insulating layer 161 can include silicon nitride or silicon oxide.

[0079] An oxide semiconductor (i.e., an oxide semiconductor layer) including the channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3 and the channel 4137, the first electrode 4136, and the second electrode 4138 of the fourth transistor T4 can be formed over the first interlayer insulating layer 161. Figure 9 A polycrystalline semiconductor, a first gate conductor, and a second gate conductor, and an oxide semiconductor are shown.

[0080] The oxide semiconductor can include at least one of a monovalent metal oxide such as indium oxide (In), tin oxide (Sn), or zinc oxide (Zn); a binary metal oxide such as an In-Zn-based oxide, a Sn-Zn-based oxide, an Al-Zn-based oxide, a Zn-Mg-based oxide, a Sn-Mg-based oxide, an In-Mg-based oxide, or an In-Ga-based oxide; a ternary metal oxide such as an In-Ga-Zn-based oxide, an In-Al-Zn-based oxide, an In-Sn-Zn-based oxide, a Sn-Ga-Zn-based oxide, an Al-Ga-Zn-based oxide, a Sn-Al-Zn-based oxide, an In-Hf-Zn-based oxide, an In-La-Zn-based oxide, an In-Ce-Zn-based oxide, an In-Pr-Zn-based oxide, an In-Nd-Zn-based oxide, an In-Sm-Zn-based oxide, an In-Eu-Zn-based oxide, an In-Gd-Zn-based oxide, an In-Tb-Zn-based oxide, an In-Dy-Zn-based oxide, an In-Ho-Zn-based oxide, an In-Er-Zn-based oxide, an In-Tm-Zn-based oxide, an In-Yb-Zn-based oxide, or an In-Lu-Zn-based oxide; and a quaternary metal oxide such as an In-Sn-Ga-Zn-based oxide, an In-Hf-Ga-Zn-based oxide, an In-Al-Ga-Zn-based oxide, an In-Sn-Al-Zn-based oxide, an In-Sn-Hf-Zn-based oxide, or an In-Hf-Al-Zn-based oxide. For example, the oxide semiconductor can include indium-gallium-zinc oxide (IGZO) among the In-Ga-Zn-based oxides.

[0081] The channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3 and the channel 4137, the first electrode 4136, and the second electrode 4138 of the fourth transistor T4 can be connected to and can be integrally formed with each other. The first electrode 3136 and the second electrode 3138 of the third transistor T3 can be formed on opposite sides of the channel 3137 of the third transistor T3. The first electrode 4136 and the second electrode 4138 of the fourth transistor T4 can be formed on opposite sides of the channel 4137 of the fourth transistor T4. The second electrode 3138 of the third transistor T3 can be connected to the second electrode 4138 of the fourth transistor T4. The channel 3137 of the third transistor T3 can overlap with the light-blocking layer 3155. The channel 4137 of the fourth transistor T4 can overlap with the light-blocking layer 4155.

[0082] The oxide semiconductor can further include a second electrode of a boost capacitor Cboost. The second electrode of the boost capacitor Cboost can be connected to the second electrode 3138 of the third transistor T3. The second electrode of the boost capacitor Cboost can be connected to the second electrode 4138 of the fourth transistor T4. The second electrode of the boost capacitor Cboost can overlap the first electrode of the boost capacitor Cboost. The capacitance of the boost capacitor Cboost can be determined by the overlapping area of the first electrode and the second electrode of the boost capacitor Cboost and the thickness of the second gate insulating layer 142 and the first interlayer insulating layer 161 between the first electrode and the second electrode of the boost capacitor Cboost.

[0083] The third gate insulating layer 143 can be formed over the oxide semiconductor including the channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3 and the channel 4137, the first electrode 4136, and the second electrode 4138 of the fourth transistor T4. The third gate insulating layer 143 can be formed over the entire surface of the oxide semiconductor and the first interlayer insulating layer 161. Thus, the third gate insulating layer 143 can cover the top surface and side surfaces of the channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3 and the channel 4137, the first electrode 4136, and the second electrode 4138 of the fourth transistor T4. However, the present exemplary embodiment is not limited thereto, and the third gate insulating layer 143 can not be formed over the entire surface of the oxide semiconductor and the first interlayer insulating layer 161. For example, the third gate insulating layer 143 can overlap the channel 3137 of the third transistor T3 without overlapping the first electrode 3136 and the second electrode 3138. The third gate insulating layer 143 can overlap the channel 4137 of the fourth transistor T4 without overlapping the first electrode 4136 and the second electrode 4138.

[0084] The third gate conductor including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4 can be formed over the third gate insulating layer 143. Figure 10 A polycrystalline semiconductor, a first gate conductor, a second gate conductor, an oxide semiconductor, and a third gate conductor are illustrated.

[0085] The gate electrode 3151 of the third transistor T3 can overlap the channel 3137 of the third transistor T3. The gate electrode 3151 of the third transistor T3 can overlap at least one of the inverted scan line 152 and the light-blocking layer 3155 of the third transistor T3. The first interlayer insulating layer 161 and the third gate insulating layer 143 can be formed between the gate electrode 3151 of the third transistor T3 and the inverted scan line 152 and between the gate electrode 3151 of the third transistor T3 and the light-blocking layer 3155. The first opening 3145 can be formed in the third gate insulating layer 143 and the first interlayer insulating layer 161. The first opening 3145 can overlap (i.e., expose) at least a portion of at least one of the inverted scan line 152 and the light-blocking layer 3155 of the third transistor T3. The gate electrode 3151 of the third transistor T3 can be connected to at least one of the inverted scan line 152 and the light-blocking layer 3155 of the third transistor T3 through the first opening 3145. The gate electrode 3151 and the light-blocking layer 3155 of the third transistor T3 can receive the inverted scan signal GC through the inverted scan line 152.

[0086] The gate electrode 4151 of the fourth transistor T4 can overlap the channel 4137 of the fourth transistor T4. The third gate conductor can further include an initialization control line 153. The initialization control line 153 can extend substantially in a horizontal direction. The gate electrode 4151 of the fourth transistor T4 can be connected to the initialization control line 153. At least one of the gate electrode 4151 of the fourth transistor T4 and the initialization control line 153 can overlap the light-blocking layer 4155 of the fourth transistor T4. The first interlayer insulating layer 161 and the third gate insulating layer 143 can be formed between the gate electrode 4151 of the fourth transistor T4 and the light-blocking layer 4155 and between the initialization control line 153 and the light-blocking layer 4155 of the fourth transistor T4. The second opening 4145 can be formed in the third gate insulating layer 143 and the first interlayer insulating layer 161. The second opening 4145 can overlap (i.e., expose) at least a portion of the light-blocking layer 4155 of the fourth transistor T4. At least one of the gate electrode 4151 of the fourth transistor T4 and the initialization control line 153 can be connected to the light-blocking layer 4155 of the fourth transistor T4 through the second opening 4145. The gate electrode 4151 and the light-blocking layer 4155 of the fourth transistor T4 can receive the initialization control signal GI through the initialization control line 153.

[0087] The third gate conductor can further include a first initialization voltage line 127. The first initialization voltage line 127 can extend substantially in a horizontal direction. The first initialization voltage line 127 can extend in parallel with the initialization control line 153. The first initialization voltage line 127 can extend in parallel with the second initialization voltage line 128 and the scan line 151. The first initialization voltage line 127 can overlap the second initialization voltage line 128 and the scan line 151. The scan line 151 can be insulated from the second initialization voltage line 128 with the second gate insulating layer 142 therebetween. The second initialization voltage line 128 can be insulated from the first initialization voltage line 127 with the first interlayer insulating layer 161 and the third gate insulating layer 143 therebetween. In an example embodiment, the second initialization voltage line 128 and the first initialization voltage line 127 are located on different layers from each other. For example, the second initialization voltage line 128 can be provided on (or can contact) the second gate insulating layer 142, and the first initialization voltage line 127 can be provided on (or can contact) the third gate insulating layer 143 different from the second gate insulating layer 142.

[0088] A third gate conductor including a gate electrode 3151 of the third transistor T3 and a gate electrode 4151 of the fourth transistor T4 can be formed, and a doping process can be performed. A portion of the oxide semiconductor covered with the third gate conductor can not be doped, and a portion of the oxide semiconductor not covered with the third gate conductor can be doped so as to have the same characteristics as the conductor. The channel 3137 of the third transistor T3 can be located below the gate electrode 3151 so as to overlap the gate electrode 3151. The first electrode 3136 and the second electrode 3138 of the third transistor T3 can not overlap the gate electrode 3151. The channel 4137 of the fourth transistor T4 can be located below the gate electrode 4151 so as to overlap the gate electrode 4151. The first electrode 4136 and the second electrode 4138 of the fourth transistor T4 can not overlap the gate electrode 4151. The doping process of the oxide semiconductor can be performed using an n-type dopant, and the third transistor T3 and the fourth transistor T4 including the oxide semiconductor can have n-type transistor characteristics.

[0089] A second interlayer insulating layer 162 can be formed on the third gate conductor including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4. A third opening 1165, a fourth opening 3165, a fifth opening 3166, a sixth opening 4165, a seventh opening 4166, an eighth opening 7165, and a ninth opening 7166 can be formed in the second interlayer insulating layer 162.

[0090] The third opening 1165 can expose at least a portion of the gate electrode 1151 of the driving transistor T1. The third opening 1165 can be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, and the second gate insulating layer 142. The third opening 1165 can overlap the opening 1152 of the first storage electrode 1153. For example, in a plan view, the third opening 1165 can be disposed in the opening 1152. In an exemplary embodiment, the third opening 1165 can penetrate a portion of the second gate insulating layer 142 exposed by the opening 1152 and expose a portion of the gate electrode 1151 of the driving transistor T1. The third opening 1165 can be formed in the opening 1152 of the first storage electrode 1153. The fourth opening 3165 can overlap at least a portion of the second electrode 1133 of the driving transistor T1.

[0091] The fourth opening 3165 can be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, the second gate insulating layer 142, and the first gate insulating layer 141. The fifth opening 3166 can expose at least a portion of the first electrode 3136 of the third transistor T3. The fifth opening 3166 can be further formed in the third gate insulating layer 143.

[0092] The sixth opening 4165 can expose at least a portion of the first initialization voltage line 127. The seventh opening 4166 can expose at least a portion of the first electrode 4136 of the fourth transistor T4. The seventh opening 4166 can be further formed in the third gate insulating layer 143.

[0093] The eighth opening 7165 can expose at least a portion of the second initialization voltage line 128. The eighth opening 7165 can be further formed in the third gate insulating layer 143 and the first interlayer insulating layer 161. The ninth opening 7166 can expose at least a portion of the second electrode 7133 of the seventh transistor T7. The ninth opening 7166 can be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, the second gate insulating layer 142, and the first gate insulating layer 141.

[0094] The first connection electrode 1175, the second connection electrode 3175, the third connection electrode 4175, the fourth connection electrode 7175, the data line 171, and the driving voltage line 172 can be formed on the second interlayer insulating layer 162.

[0095] The first connection electrode 1175 can overlap the gate electrode 1151 of the driving transistor T1. The first connection electrode 1175 can be connected to the gate electrode 1151 of the driving transistor T1 through the third opening 1165 and the opening 1152 of the first storage electrode 1153. The first connection electrode 1175 can overlap the boost capacitor Cboost. The first connection electrode 1175 can be connected to the second electrode of the boost capacitor Cboost. Accordingly, the gate electrode 1151 of the driving transistor T1 can be connected to the second electrode of the boost capacitor Cboost through the first connection electrode 1175.

[0096] The second connection electrode 3175 can overlap the second electrode 1133 of the driving transistor T1. The second connection electrode 3175 can be connected to the second electrode 1133 of the driving transistor T1 through the fourth opening 3165. The second connection electrode 3175 can overlap the first electrode 3136 of the third transistor T3. The second connection electrode 3175 can be connected to the first electrode 3136 of the third transistor T3 through the fifth opening 3166. Accordingly, the second electrode 1133 of the driving transistor T1 can be connected to the first electrode 3136 of the third transistor T3 through the second connection electrode 3175.

[0097] The third connection electrode 4175 can overlap the first initialization voltage line 127. The third connection electrode 4175 can be connected to the first initialization voltage line 127 through the sixth opening 4165. The third connection electrode 4175 can overlap the first electrode 4136 of the fourth transistor T4. The third connection electrode 4175 can be connected to the first electrode 4136 of the fourth transistor T4 through the seventh opening 4166. Accordingly, the first initialization voltage line 127 can be connected to the first electrode 4136 of the fourth transistor T4 through the third connection electrode 4175.

[0098] The fourth connection electrode 7175 can overlap the second initialization voltage line 128. The fourth connection electrode 7175 can be connected to the second initialization voltage line 128 through the eighth opening 7165. The fourth connection electrode 7175 can overlap the second electrode 7133 of the seventh transistor T7. The fourth connection electrode 7175 can be connected to the second electrode 7133 of the seventh transistor T7 through the ninth opening 7166. Accordingly, the second initialization voltage line 128 can be connected to the second electrode 7133 of the seventh transistor T7 through the fourth connection electrode 7175.

[0099] The data line 171 and the driving voltage line 172 can extend substantially in a vertical direction. The data line 171 can be connected to the second transistor T2. The data line 171 can be connected to a first electrode of the second transistor T2. The driving voltage line 172 can be connected to the fifth transistor T5. The driving voltage line 172 can be connected to a first electrode of the fifth transistor T5. The driving voltage line 172 can be connected to the storage capacitor Cst. The driving voltage line 172 can be connected to a first storage electrode 1153 of the storage capacitor Cst. The first storage electrodes 1153 of the storage capacitors Cst of adjacent pixels are connected to each other, and they can extend substantially in a horizontal direction.

[0100] The third interlayer insulating layer 180 can be formed on the first connection electrode 1175, the second connection electrode 3175, the third connection electrode 4175, the fourth connection electrode 7175, the data line 171, and the driving voltage line 172.

[0101] Although not shown, an anode of the light emitting diode LED can be formed on the third interlayer insulating layer 180. The anode can be connected to the sixth transistor T6, and can receive an output current of the driving transistor T1. A partition wall can be formed on the anode. An opening is formed in the partition wall, and the opening in the partition wall can overlap the anode. A light emitting device layer can be formed in the opening of the partition wall. A cathode can be formed on the light emitting device layer and the partition wall. The anode, the light emitting device layer, and the cathode can constitute the light emitting diode LED.

[0102] With regard to the display device according to an exemplary embodiment, the driving transistor T1 can include a polycrystalline semiconductor, and the third transistor T3 and the fourth transistor T4 can include an oxide semiconductor. The third transistor T3 and the fourth transistor T4 include a different semiconductor material from the driving transistor T1, so their driving strength can be more stable and reliability can be improved.

[0103] Further, the third transistor T3 including the oxide semiconductor can include the light-blocking layer 3155, and the fourth transistor T4 can include the light-blocking layer 4155. The light-blocking layer 3155 of the third transistor T3 and the light-blocking layer 4155 of the fourth transistor T4 can be formed in the same layer (e.g., the second gate insulating layer 142) as the first storage electrode 1153 of the storage capacitor Cst, can be made of the same material, and can be formed using the same process. In an example embodiment, the light-blocking layer 3155 of the third transistor T3, the light-blocking layer 4155 of the fourth transistor T4, and the first storage electrode 1153 can be formed in the same layer, the second gate insulating layer 142. The light-blocking layer 3155 of the third transistor T3 and the light-blocking layer 4155 of the fourth transistor T4 can be formed in the same layer (e.g., the second gate insulating layer 142) as the second initialization voltage line 128, can be made of the same material, and can be formed using the same process. In an example embodiment, the light-blocking layer 3155 of the third transistor T3, the light-blocking layer 4155 of the fourth transistor T4, and the second initialization voltage line 128 can be formed in the same layer, the second gate insulating layer 142. The light-blocking layer 3155 of the third transistor T3 can receive the same signal as the gate electrode 3151, and the third transistor T3 can have a dual-gate structure. The light-blocking layer 4155 of the fourth transistor T4 can receive the same signal as the gate electrode 4151, and the fourth transistor T4 can have a dual-gate structure. As described above, the third transistor T3 and the fourth transistor T4 each have a configuration including the light-blocking layers 3155 and 4155 without requiring an additional process, thereby preventing leakage current from occurring in the third transistor T3 and the fourth transistor T4. Thus, device characteristics and reliability can be improved.

[0104] The fourth transistor T4 and the seventh transistor T7 are not connected to the same initialization voltage line, but are connected to different initialization voltage lines. The fourth transistor T4 can be connected to the first initialization voltage line 127, and can receive the first initialization voltage VINT. The seventh transistor T7 can be connected to the second initialization voltage line 128, and can receive the second initialization voltage AINT. When the fourth transistor T4 and the seventh transistor T7 are connected to the same initialization voltage line, the same initialization voltage is applied to the fourth transistor T4 and the seventh transistor T7. The organic light emitting device can be driven at a changed frequency. For example, a frequency of 120 Hz can be changed to 60 Hz, 30 Hz, or 1 Hz. When the organic light emitting device is driven at a changed frequency, a deviation of a variable refresh rate (VRR) characteristic can occur. For example, a greater deviation can occur in a region indicating a low gray scale. In the present exemplary embodiment, different initialization voltages can be applied to the fourth transistor T4 and the seventh transistor T7. Accordingly, by allowing the first initialization voltage VINT applied to the fourth transistor T4 to be different from the second initialization voltage AINT applied to the seventh transistor T7, a deviation of the VRR characteristic can be reduced in a low gray scale.

[0105] In the present exemplary embodiment, the first initialization voltage line 127 can overlap the second initialization voltage line 128. The fourth transistor T4 can be connected to the first initialization voltage line 127 through the third connection electrode 4175, and can receive the first initialization voltage VINT. The seventh transistor T7 can be connected to the second initialization voltage line 128 through the fourth connection electrode 7175, and can receive the second initialization voltage AINT.

[0106] While the disclosure has been described with respect to the exemplary embodiments currently perceived as the most practical and preferred, it is to be understood that the application is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements.

Claims

1. A display device comprising: a first transistor comprising a polycrystalline semiconductor layer; a second transistor including a polycrystalline semiconductor layer and connected to the first transistor; a third transistor including an oxide semiconductor layer and connected to the first transistor; a fourth transistor including an oxide semiconductor layer and connected to the first transistor and the third transistor, wherein the fourth transistor is connected to a gate electrode of the first transistor; a boosting capacitor comprising a first electrode and a second electrode overlapping the first electrode, wherein the first electrode is connected to the second transistor and the second electrode is connected to at least one of the third transistor and the fourth transistor; A light-emitting diode comprising an anode, a cathode and a light-emitting layer; a seventh transistor connected to the light emitting diode; a first initialization voltage line connected to the fourth transistor and transmitting a first initialization voltage; as well as A second initialization voltage line is connected to the seventh transistor and transmits a second initialization voltage different from the first initialization voltage, wherein the first initialization voltage line and the second initialization voltage line are provided on different layers from each other.

2. The display device according to claim 1, wherein The second electrode includes an oxide semiconductor.

3. The display device according to claim 1, wherein The first electrode is connected to a gate electrode of the second transistor, and the first electrode and the gate electrode of the second transistor are located on the same layer.

4. The display device according to claim 1, wherein The second electrode is connected to at least one of the oxide semiconductor layer of the third transistor and the oxide semiconductor layer of the fourth transistor, and the second electrode, the oxide semiconductor layer of the third transistor, and the oxide semiconductor layer of the fourth transistor are provided on the same layer.

5. The display device according to claim 1, further comprising: substrate; a first insulating layer, disposed between the substrate and the first electrode; a second insulating layer, disposed between the first electrode and the second electrode; a third insulating layer, disposed between the second insulating layer and the second electrode; as well as The fourth insulating layer is provided on the second electrode. The display device according to claim 5 , wherein: The polycrystalline semiconductor layer of the first transistor and the polycrystalline semiconductor layer of the second transistor are provided between the substrate and the first insulating layer.

7. The display device according to claim 5, wherein: The oxide semiconductor layer of the third transistor and the oxide semiconductor layer of the fourth transistor are provided between the third insulating layer and the fourth insulating layer.

8. The display device according to claim 5, wherein The gate electrode of the first transistor and the gate electrode of the second transistor are provided between the first insulating layer and the second insulating layer.

9. The display device according to claim 5, wherein: A gate electrode of the third transistor and a gate electrode of the fourth transistor are provided on the fourth insulating layer.

10. The display device according to claim 5, wherein The first initialization voltage line and the gate electrode of the fourth transistor are disposed on the same layer.

11. The display device according to claim 1 , further comprising: A driving voltage line, transmitting a driving voltage; a fifth transistor connected between the driving voltage line and the first transistor; as well as A sixth transistor is connected between the first transistor and the light emitting diode and is connected to the seventh transistor.

12. The display device according to claim 11, wherein Each of the fifth transistor, the sixth transistor, and the seventh transistor includes a polycrystalline semiconductor layer.

13. The display device according to claim 1, further comprising: a light-blocking layer overlapping the oxide semiconductor layer of the third transistor, Wherein, the light blocking layer and the second initialization voltage line are arranged on the same layer.

14. The display device according to claim 1, further comprising: a first scan line connected to the gate electrode of the second transistor and transmitting a scan signal; a second scan line connected to the gate electrode of the third transistor and transmitting an inverted scan signal; as well as a third scan line connected to the gate electrode of the fourth transistor and transmitting an initialization control signal; The boost capacitor is connected between the first scan line and the gate electrode of the first transistor.

15. A display device comprising: a first transistor comprising a polycrystalline semiconductor layer; a second transistor including a polycrystalline semiconductor layer and connected to the first transistor; a third transistor including an oxide semiconductor layer and connected to the first transistor; a fourth transistor including an oxide semiconductor layer and connected to the first transistor and the third transistor; a boosting capacitor comprising a first electrode and a second electrode overlapping the first electrode, wherein the first electrode is connected to the second transistor and the second electrode is connected to at least one of the third transistor and the fourth transistor; substrate; a first insulating layer, disposed between the substrate and the first electrode; a second insulating layer, disposed between the first electrode and the second electrode; a third insulating layer, disposed between the second insulating layer and the second electrode; a fourth insulating layer, disposed on the second electrode; a first initialization voltage line connected to the fourth transistor and transmitting a first initialization voltage; a fifth insulating layer, provided on the first initialization voltage line; as well as A first connection electrode is provided on the fifth insulating layer and electrically connects the first initialization voltage line and the oxide semiconductor layer of the fourth transistor.

16. The display device according to claim 15, further comprising: A second connection electrode is provided on the fifth insulating layer and electrically connects the polycrystalline semiconductor layer of the first transistor and the oxide semiconductor layer of the third transistor.

17. A display device comprising: a first transistor comprising a polycrystalline semiconductor layer; a second transistor including a polycrystalline semiconductor layer and connected to the first transistor; a third transistor including an oxide semiconductor layer and connected to the first transistor; a fourth transistor including an oxide semiconductor layer and connected to the first transistor and the third transistor; a boosting capacitor comprising a first electrode and a second electrode overlapping the first electrode, wherein the first electrode is connected to the second transistor and the second electrode is connected to at least one of the third transistor and the fourth transistor; A driving voltage line, transmitting a driving voltage; A light-emitting diode comprising an anode, a cathode and a light-emitting layer; a fifth transistor connected between the driving voltage line and the first transistor; a sixth transistor connected between the first transistor and the light emitting diode; a seventh transistor including a polycrystalline semiconductor layer and connected to the sixth transistor and the light emitting diode; a second initialization voltage line connected to the seventh transistor and transmitting a second initialization voltage; as well as A connecting electrode overlaps with the second initialization voltage line and electrically connects the second initialization voltage line and the polycrystalline semiconductor layer of the seventh transistor.

Images