Memory allocation method and electronic device

Abstract

The application discloses a memory allocation method and an electronic device, and relates to the technical field of computers, which comprises the following steps: identifying semantic information of an object, dynamically binding the semantic information with a cache area and a memory allocation strategy, improving the flexibility of cache replacement, and realizing differentiated management and control of cache resources. The selection of the memory access node is optimized by fusing remote delay, shared domain characteristics and the semantic information of the object. The management of the L3 cache area, the memory pool and the memory access node in the related art is in an independent optimization state. Through semantic-driven partition binding and cross-node decision-making, the cache hit rate is improved and the delay of cross-node memory access is reduced. The problems of low cache replacement flexibility, low cache utilization and high remote memory access delay are solved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to memory allocation methods and electronic devices. Background Technology

[0002] In high-performance computing systems with multi-core processors and non-uniform memory access (NUMA) architectures, system performance depends on cache utilization and memory access efficiency.

[0003] In related technologies, processor L3 cache, memory pool, and NUMA node management are all optimized independently. The L3 cache region does not incorporate memory-related information, resulting in a lack of targeted cache replacement strategies, and high-frequency data may be squeezed out by temporary data. Memory allocation does not consider cache physical characteristics (such as cache line alignment and associativity) and NUMA affinity, leading to low cache utilization. NUMA node selection does not coordinate locality, L3 cache shared domain characteristics, and cross-node latency, resulting in high remote access latency. Therefore, a memory allocation and optimization method is urgently needed to address the problems of low cache replacement flexibility, low cache utilization, and high access latency. Summary of the Invention

[0004] This application provides a memory allocation method and an electronic device to at least solve the problems of low cache replacement flexibility, low cache utilization, and high latency access in the related art.

[0005] This application provides a memory allocation method, including:

[0006] Obtain the memory allocation request, which includes the object information corresponding to the object requesting the memory, and the memory size;

[0007] Based on the semantic information corresponding to the memory allocation request, determine the target memory type of the object;

[0008] If the memory size is less than or equal to the size of the first remaining memory, then according to the target memory type, target memory is allocated for the object in the first memory, and a target cache area is allocated for the object in the cache area. The first memory is the memory under the first memory access node corresponding to the object, and the first remaining memory is the memory currently available in the first memory.

[0009] If the memory size is greater than the size of the first remaining memory, then a target memory access node is determined in at least one memory access node, and target memory is allocated for the object according to the target memory type and the second memory under the target memory access node, and a target cache area is allocated for the object in the cache area.

[0010] This application also provides a memory allocation device, including:

[0011] The acquisition module is used to acquire memory allocation requests. The memory allocation request includes object information corresponding to the object requesting memory, as well as the memory size.

[0012] The determination module is used to determine the target memory type of an object based on the semantic information corresponding to the memory allocation request;

[0013] The first processing module is used to allocate target memory for the object in the first memory and allocate target cache area for the object in the cache area according to the target memory type if the memory size is less than or equal to the size of the first remaining memory. The first memory is the memory under the first memory access node corresponding to the object, and the first remaining memory is the memory currently available in the first memory.

[0014] The second processing module is used to determine a target memory access node in at least one memory access node if the memory size is greater than the size of the first remaining memory, and to allocate target memory for the object according to the target memory type and the second memory under the target memory access node, and to allocate a target cache area for the object in the cache area.

[0015] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above memory allocation methods when executing the computer program.

[0016] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described memory allocation methods.

[0017] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described memory allocation methods.

[0018] This application improves cache replacement flexibility and enables differentiated management of cache resources by dynamically binding semantic information with cache regions and memory allocation strategies based on the semantic information of the identified objects. It integrates remote latency, shared domain characteristics, and object semantic information to optimize the selection of memory access nodes. This avoids the situation in related technologies where the management of L3 cache regions, memory pools, and memory access nodes are all independently optimized. Through semantically driven partition binding and cross-node decision-making, it improves cache hit rate and reduces cross-node memory access latency. It solves the problems of low cache replacement flexibility, low cache utilization, and high remote memory access latency. It achieves the technical effects of improving cache replacement flexibility, cache utilization, and reducing cross-node memory access latency. Attached Figure Description

[0019] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram illustrating the application scenarios provided in the embodiments of this application;

[0021] Figure 2 A flowchart illustrating the memory allocation method provided in the embodiments of this application. Figure 1 ;

[0022] Figure 3 A flowchart illustrating the memory allocation method provided in the embodiments of this application. Figure 2 ;

[0023] Figure 4 A schematic diagram illustrating the memory allocation process provided in this application embodiment;

[0024] Figure 5 This is a schematic diagram of the structure of the memory allocation device provided in the embodiments of this application;

[0025] Figure 6 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0027] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0028] By identifying the semantic information of objects and dynamically binding this information with cache regions and memory allocation strategies, the flexibility of cache replacement is improved, enabling differentiated management of cache resources. It integrates remote latency, shared domain characteristics, and object semantic information to optimize the selection of memory access nodes. This avoids the situation in related technologies where the management of L3 cache regions, memory pools, and memory access nodes are all optimized independently. Through semantically driven partition binding and cross-node decision-making, cache hit rate is improved and cross-node memory access latency is reduced. This addresses the problems of low cache replacement flexibility, low cache utilization, and high remote memory access latency. It achieves the technical effects of improving cache replacement flexibility, cache utilization, and reducing cross-node memory access latency.

[0029] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] This section describes the specific application environment architecture or hardware architecture upon which the memory allocation method depends. (References) Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario provided in an embodiment of this application. For example... Figure 1 As shown, the device includes an electronic device 101. The electronic device 101 has at least one memory access node, namely memory access node 1, memory access node 2, ..., memory access node N. Each memory access node corresponds to a sub-memory in the memory of the electronic device 101. The memory access node can be a NUMA node. The electronic device 101 also has a central processing unit (CPU) and a cache area. The CPU of the electronic device 101 includes at least one processing core, and the cache area of ​​the electronic device 101 is an L3 cache area. When the application program of the electronic device 101 runs, it can request memory according to the running information. The application program of the electronic device 101 accesses memory through the CPU to implement the corresponding functions.

[0031] Figure 2 A flowchart illustrating the memory allocation method provided in the embodiments of this application. Figure 1 ,like Figure 2 As shown, embodiments of this application provide a memory allocation method, which is described in detail below:

[0032] S201: Obtain memory allocation request.

[0033] The execution entity in this application embodiment can be an electronic device or a memory allocation device disposed in an electronic device. The memory allocation device can be implemented by software or by a combination of software and hardware.

[0034] A memory allocation request includes the object information corresponding to the object requesting the memory, as well as the memory size.

[0035] When an application on an electronic device is running, or when the system needs to access memory, it can generate a memory allocation request based on relevant application information or system information.

[0036] For example, when application A on an electronic device needs to perform read / write operations during runtime, it can generate a memory allocation request based on application A's process identity, context information, and resource limitations. The memory allocation request includes the object information corresponding to application A and the memory size of 4 bytes. The object information corresponding to application A includes the application's suggested address for the requested memory, the purpose of the memory call, the application A's call instruction, process identifier, user identifier, and expected access frequency. The application A's call instruction indicates whether file or physical memory needs to be mapped, whether memory modifications should be shared with other processes, or whether physical memory needs to be allocated and mapped immediately.

[0037] For example, when an electronic device's system needs to access memory, it can generate a memory allocation request based on system status information, resource limit information, etc. The memory allocation request includes the system's corresponding object information and the memory size of 4 bytes. The system's corresponding object information includes the suggested address for the requested memory, the purpose of the memory access, the system call instruction, the process identifier, and the expected access frequency. The system call instruction indicates the required mapping type. The mapping type can be whether to map a file or physical memory, whether memory modifications need to be shared with other processes, whether physical memory needs to be allocated and mapped immediately, or whether it needs to be locked in memory.

[0038] S202: Determine the target memory type of the object based on the semantic information corresponding to the memory allocation request.

[0039] The semantic information corresponding to a memory allocation request can be determined based on at least one first field corresponding to the object information and the memory size. This semantic information describes information related to the object's runtime memory access.

[0040] The target memory type can be a high-frequency type, a temporary type, or a large object type.

[0041] The target memory type of an object can be determined based on the semantic information corresponding to the memory allocation request in the following way: obtain at least one preset field, which is used to describe the relevant information of the object's memory access at runtime; determine at least one first field corresponding to the semantic information; for any first field, if there is a preset field that matches the first field, then the preset field is determined as a candidate field, the memory type corresponding to the candidate field is determined, and the target memory type of the object is determined as the memory type corresponding to the candidate field.

[0042] Based on the field type and field identifier, the corresponding preset field can be determined. The field type can be a semantic type or a numeric type. If the first field is a semantic type, and its semantic features match the corresponding preset field, then the first field is determined to match the preset field. If the first field is a numeric type, and its corresponding value is within the range of the corresponding preset field, then the first field is determined to match the preset field.

[0043] For example, suppose at least one first field includes the object's purpose and expected access frequency. The electronic device determines the object's semantics based on the object's purpose and expected access frequency. The object's purpose field is a semantic type, and the expected access frequency field is a numeric type. Preset fields can be specifically shown in Table 1:

[0044] Table 1

[0045]

[0046] If the object's purpose is data indexing or global configuration, and / or the expected access frequency is greater than the preset frequency, then according to Table 1, the first field matches the corresponding preset field. Therefore, the electronic device determines that the target memory type corresponding to the object is a high-frequency type. If the object's purpose is to calculate a local variable of a function or an intermediate calculation result, and / or the expected access frequency is less than or equal to the preset frequency, then according to Table 1, the first field matches the corresponding preset field. Therefore, the electronic device determines that the target memory type corresponding to the object is a temporary type.

[0047] For example, suppose the first field includes memory size, and the field type for memory size is numeric. If the memory size is greater than or equal to the candidate memory size, then according to Table 1, the first field matches the corresponding preset field. Therefore, the electronic device determines that the target memory type corresponding to the object is a large object type. The candidate memory size can be the capacity of the cache area in the electronic device, and the cache area is the L3 cache area.

[0048] S203: If the memory size is less than or equal to the size of the first remaining memory, then according to the target memory type, allocate target memory for the object in the first memory and allocate target cache area for the object in the cache area.

[0049] The first memory refers to the memory under the first memory access node corresponding to the object. The first remaining memory is the currently available memory in the first memory.

[0050] Memory access nodes can be NUMA nodes. The initial remaining memory can be determined based on a memory free list.

[0051] At least one processing core of the CPU in an electronic device can be bound to a memory access node. If a processing core of the CPU accesses memory under a bound memory access node, it indicates that the CPU is performing local access, with the lowest access latency. If a processing core of the CPU accesses memory under an unbound memory access node, it indicates that the CPU is not performing local access, and the access latency is determined based on the local memory access latency, the basic latency of the interconnect links between memory access nodes, and the system topology.

[0052] If the memory size is less than or equal to the size of the first remaining memory, it indicates that memory can be allocated for objects under the memory access node bound to the CPU processing core of the electronic device. This allows the CPU processing core to access the memory with minimal access latency.

[0053] The first memory area is divided into three sub-memory areas based on memory type. The first sub-memory area is for high-frequency data, the second sub-memory area is for temporary data, and the third sub-memory area is for large objects. Specifically, the first sub-memory area stores frequently used objects, the second sub-memory area stores less frequently used temporary data, and the third sub-memory area stores large amounts of data. The memory size occupied by large amounts of data is larger than the size of the L3 cache area.

[0054] The cache area is divided into three sub-cache areas, with each sub-memory region associated with one sub-cache area. These three sub-cache areas are: a high-priority replacement sub-cache area, a low-priority replacement sub-cache area, and an independent sub-cache area. When cache release and replacement are required, the cache in the high-priority replacement sub-cache area is released first, and the new data is cached in the high-priority replacement sub-cache area. If the cache in the high-priority replacement sub-cache area cannot be released, then the cache in the low-priority replacement sub-cache area is released, and the new data is cached in the low-priority replacement sub-cache area.

[0055] For example, suppose the CPU of an electronic device includes 6 processing cores. The memory access node corresponding to each processing core and the memory under the memory access node can be specifically shown in Table 2:

[0056] Table 2

[0057]

[0058] Based on the example above, the object is identified as application A, with a memory size of 4 bytes. Assuming the electronic device runs application A as shown in the example via processing core 1, Table 2 indicates that the first memory access node is memory access node 1, and the first memory is memory 1 under memory access node 1. Assume the semantic information corresponding to application A includes object purpose and expected access frequency. The electronic device determines that the field information corresponding to object purpose is a local variable of a computational function, and the field information corresponding to expected access frequency is less than a preset frequency. Based on the preset fields shown in Table 1, the electronic device can determine that object purpose matches preset field 3, and preset access frequency matches preset field 6. The electronic device determines that the memory type corresponding to preset fields 3 and 6 is temporary. Therefore, the electronic device determines that the target memory type corresponding to application A is temporary. The target memory allocated by the electronic device for application A is the sub-memory of memory 1 with a temporary memory type. The electronic device determines that the cache region associated with the temporary sub-memory is the sub-cache region with the highest replacement priority in the L3 cache region of the electronic device. Therefore, the target cache region allocated by the electronic device for application A is the sub-cache region with the highest replacement priority in the L3 cache region.

[0059] S204: If the memory size is greater than the size of the first remaining memory, then determine the target memory access node in at least one memory access node, allocate target memory for the object according to the target memory type and the second memory under the target memory access node, and allocate the target cache area for the object in the cache area.

[0060] If the memory size is less than or equal to the size of the first memory, it indicates that memory cannot be allocated for the object under the memory access node bound to the CPU processing core of the electronic device. To minimize the latency of accessing non-local memory, the target memory access node can be determined based on the access latency of accessing non-first memory access nodes.

[0061] Real-time access latency can be statistically analyzed through CPU hardware events within a preset processing cycle, and the node-level average latency can be determined based on the real-time access latency.

[0062] The target memory access node can be determined in at least one memory access node as follows: Among the at least one memory access node, at least one second memory access node is determined, which is in the same shared domain as the first memory access node; among the at least one second memory access node, the target memory access node is determined, which has the lowest access latency, and the size of the second remaining memory corresponding to the target memory access node is greater than or equal to the memory size.

[0063] The physical topology of memory access nodes can be obtained through resource association tables or system location information tables, thereby identifying the second memory access node that is in the same shared domain as the first memory access node, and the third memory access node that is not in the same shared domain as the first memory access node.

[0064] The second remaining memory corresponding to the target memory access node is the currently available memory in the memory under the target memory access node.

[0065] Memory access nodes within the same shared domain can reduce cache miss rates for cross-node access, resulting in higher overall benefits. Therefore, it is preferable to identify the target memory access node from at least one secondary memory access node.

[0066] For example, as shown in Table 2 above, the electronic device includes three memory access nodes. The first memory access node is memory access node 1. The electronic device determines the second memory access node to be memory access node 2 and the third memory access node to be memory access node 3 based on the resource association table. As illustrated in the example above, the memory size is determined to be 4 bytes. Assume that the first remaining memory size of memory access node 1 is 0. Since the only second memory access node in the same shared domain as the first memory access node is memory access node 2, and it can be determined that the second remaining memory size of 64 bytes is greater than the memory size of 4 bytes, the electronic device determines the target access node to be memory access node 2.

[0067] Based on the example above, the target memory type is determined to be temporary. Therefore, the electronic device identifies a temporary sub-memory in the second memory under memory access node 2. The target memory allocated for application A is this temporary sub-memory identified in the second memory under memory access node 2. The cache region associated with this temporary sub-memory is the high-priority replacement sub-cache region in the electronic device's L3 cache region. Therefore, the target cache region allocated for application A by the electronic device is the high-priority replacement sub-cache region in the L3 cache region.

[0068] Optionally, if the target memory access node is not present in at least one second memory access node, then at least one third access node is determined among the at least one memory access node; the target memory access node is determined among the at least one third memory access node, wherein the access latency of the target memory access node is the minimum, and the size of the second remaining memory is greater than or equal to the memory size, and the third memory access node and the first memory access node are not in the same shared domain.

[0069] If the size of the second remaining memory corresponding to each second memory access node is less than the memory size, it indicates that there is no target memory access node among at least one second memory access node. In this case, among at least one memory access node that is not in the same shared domain as the first memory access node, the memory access node with the lowest access latency and a second remaining memory size greater than or equal to the memory size can be identified as the target memory access node.

[0070] The memory allocation method provided in this application determines the corresponding target memory type based on semantic information. High-frequency objects can reside in the cache long-term, temporary objects are replaced first, and large objects are managed independently to reduce cache pollution. High-frequency objects are preferentially allocated to low-latency nodes in the same shared domain to reduce cross-node cache misses and lower remote access latency.

[0071] Figure 3 A flowchart illustrating the memory allocation method provided in the embodiments of this application. Figure 2 ,like Figure 3 As shown, embodiments of this application provide a memory allocation method, which is described in detail below:

[0072] S301, Obtain memory allocation request.

[0073] Before receiving a memory allocation request, the electronic device can configure the memory under each memory access node to partition the memory according to memory type. The partitioned memory is then associated with a cache region. This allows for differentiated management of high-frequency objects, temporary objects, and large objects.

[0074] The memory under a memory access node can be configured as follows: The first memory is divided according to at least one memory type to obtain sub-memory corresponding to each memory type. The memory identifier of the sub-memory is stored in the header area of ​​the sub-memory. The memory type is either high-frequency, temporary, or large object. The high-frequency sub-memory is associated with a sub-cache region in the cache region with a lower replacement priority. The temporary sub-memory is associated with a sub-cache region in the cache region with a higher replacement priority. The large object sub-memory is associated with an independent sub-cache region in the cache region, thus obtaining the sub-cache region corresponding to each sub-memory.

[0075] By isolating large object cache areas through independent partitions, their interference with shared cache is reduced, and the cache areas of high-frequency or temporary objects are avoided, thereby improving overall cache efficiency.

[0076] Resource Director Technology (RDT) can be used to set Class of Service (COS) partitions, resulting in sub-memory for each memory type. By configuring hardware registers, the cache region can be divided into at least one independent sub-cache region.

[0077] COS partitioning can divide shared hardware resources (such as last-level cache and memory bandwidth) into multiple "service levels" and assign different applications or tasks to these levels, thereby achieving isolation, protection and control of shared resources.

[0078] The memory size of each sub-memory and the memory size of the cache area can be determined according to user settings and specific use cases; this application does not impose any restrictions.

[0079] The memory identifier of the sub-memory is stored in the header area of ​​the sub-memory, and the memory identifier occupies a memory size of 1~2B.

[0080] For example, suppose the CPU of an electronic device has 6 processing cores. The memory access nodes corresponding to each processing core, and the memory under each memory access node, can be specifically shown in Table 2. Before allocating memory, the electronic device divides memory 1 under memory access node 1 into 3 sub-memories: sub-memory 11, sub-memory 12, and sub-memory 13. The electronic device also divides the cache region into 3 sub-cache regions: sub-cache region 11, sub-cache region 12, and sub-cache region 13. The electronic device associates the sub-memories and sub-cache regions to obtain the memory type of each sub-memory and the associated sub-cache region, as shown in Table 3.

[0081] Table 3

[0082]

[0083] The electronic device sets an identifier for high-frequency types as identifier 1 in the header area of ​​sub-memory 11, an identifier for temporary types as identifier 2 in the header area of ​​sub-memory 12, and an identifier for large object types as identifier 3 in the header area of ​​sub-memory 13. Accordingly, the electronic device can partition memory 2 and memory 3 and associate them with sub-cache areas.

[0084] Optionally, for read-only objects or copy-on-write objects, the memory type and its corresponding memory identifier can be extended to bind the read-only object or copy-on-write object to a new sub-memory in the first memory and associate it with an independent sub-cache partition in the cache region. By extending semantic tags, cache resource management can be further refined, improving caching efficiency for specific object types.

[0085] For example, the first memory can be further divided into sub-memory 11, sub-memory 12, sub-memory 13, and sub-memory 14. Sub-memory 11, sub-memory 12, and sub-memory 13 can be as shown in Table 3 above. Sub-memory 14 has a read-only memory type and its memory identifier is identifier 4. The cache area is divided into sub-cache area 11, sub-cache area 12, sub-cache area 13, and sub-cache area 14. The association between sub-memory 14 and sub-cache area 14 is then performed.

[0086] For example, the first memory can be further divided into sub-memory 11, sub-memory 12, sub-memory 13, and sub-memory 15. Sub-memory 11, sub-memory 12, and sub-memory 13 can be as shown in Table 3 above. Sub-memory 15 has a copy type memory and a memory identifier of identifier 5. The cache area is divided into sub-cache area 11, sub-cache area 12, sub-cache area 13, and sub-cache area 15. Association processing is then performed between sub-memory 15 and sub-cache area 15.

[0087] In this embodiment, the dynamic binding of sub-memory and memory object semantics is achieved through the memory identifier corresponding to the memory type, so that high-frequency data resides in the cache for a long time and temporary data is replaced first, which significantly improves the cache hit rate and reduces the cache pollution rate.

[0088] S302. Determine the target memory type of the object based on the semantic information corresponding to the memory allocation request.

[0089] For example, suppose a memory allocation request includes object information for object B and a memory size of 10B. Assuming the electronic device runs object B through processing core 1, then according to Table 2 above, the first memory access node can be determined to be memory access node 1, and the first memory is memory 1 under memory access node 1. Assume the semantic information corresponding to application object B includes object purpose and expected access frequency. The electronic device determines that the field information corresponding to object purpose is a data index, and the field information corresponding to expected access frequency is greater than a preset frequency.

[0090] Based on the preset fields shown in Table 1 above, the electronic device can determine that the object's purpose matches preset field 1, and the preset access frequency matches preset field 5. The electronic device determines that the memory type corresponding to preset fields 1 and 5 is a high-frequency type. Therefore, the electronic device determines that the target memory type corresponding to object B is a high-frequency type.

[0091] S303. If the memory size is less than or equal to the size of the first remaining memory, allocate target memory for the object in the first memory and allocate target cache area for the object in the cache area, according to the target memory type.

[0092] The target memory for an object in the first memory and the target cache region for the object in the cache region can be allocated in the following manner, based on the target memory type: At least one sub-memory is determined in the first memory, and the memory identifier of each sub-memory is obtained from the header storage region of each sub-memory; the target memory identifier corresponding to the target memory type is determined; candidate sub-memories are determined in at least one sub-memory of the first memory, and the memory identifier of the candidate sub-memory matches the target memory identifier; if the memory size is less than or equal to a preset memory size, the target memory is allocated for the object in the candidate sub-memory, and the target memory is a cache line in the candidate sub-memory, with the starting address of the target memory aligned with the boundary of the cache line; if the memory size is greater than the preset memory size, the target memory is allocated for the object in the candidate sub-memory, and the target memory is a contiguous storage region in the candidate sub-memory; in the cache region, the target cache region allocated for the object is determined to be the sub-cache region associated with the target memory.

[0093] The default memory size is the memory size corresponding to one cache line in the sub-memory. The default memory size can be 64B. The default memory size can be set in advance and stored in the default storage space of the electronic device.

[0094] For example, as illustrated above, the target memory type corresponding to object B is determined to be a high-frequency type, and the target memory identifier corresponding to the target memory type is identified as identifier 1. Among at least one sub-memory shown in Table 3 above, the electronic device identifies sub-memory 11 as the candidate sub-memory, and the identifier of sub-memory 11 matches the target memory identifier. Since the memory size in the memory allocation request is 10B, which is less than the preset memory size, target memory is allocated for object B in sub-memory 11. The target memory is cache line 1 in sub-memory 11, and the starting address of the target memory is aligned with the boundary of cache line 1. Based on Table 3 above, the electronic device determines that the cache region associated with the high-frequency type sub-memory is sub-cache region 11 of the electronic device. Therefore, the target cache region allocated by the electronic device for object B is sub-cache region 11.

[0095] In this embodiment of the application, cache line alignment reduces cache conflicts and fragmentation, improves cache line utilization, and reduces the miss rate.

[0096] When allocating target cache regions, electronic devices use cache prefetching technology to load data from main memory into the cache region in advance, thereby reducing the pause time for the processor to access data and improving the processor's performance.

[0097] After prefetching and releasing the cache, electronic devices can monitor the access efficiency of the target cache region according to a preset processing cycle. This allows for adjustments to the prefetch memory allocated to the pre-allocated cache region based on access efficiency, improving the flexibility and accuracy of prefetching.

[0098] The prefetch memory can be adjusted as follows: Obtain the target access efficiency corresponding to the target cache region, where the target access efficiency is the ratio between the prefetch memory and the actual access memory; if the target access efficiency is greater than a first preset value, then the target prefetch memory is determined to be the memory requested by the object, and the target prefetch memory is the memory size for the next cache prefetch processing; if the target access efficiency is less than or equal to the first preset value and greater than or equal to the second preset value, then the target prefetch memory is determined to be the prefetch memory; if the target access efficiency is less than the second preset value, then the target prefetch memory is determined to be the product of the prefetch memory and the third preset value.

[0099] The first, second, and third preset values ​​can be set in advance and stored in the preset storage space of the electronic device.

[0100] The first preset value can be 0.9, the second preset value can be 0.6, and the third preset value can be 1.5.

[0101] If the target access efficiency is greater than the first preset value, it indicates that the prefetched memory and the actual accessed memory highly overlap, and no adjustment to the prefetched memory is needed; the next prefetch will be the memory requested by the object. If the target access efficiency is less than or equal to the first preset value, but greater than or equal to the second preset value, it indicates that there is a certain difference between the prefetched memory and the actual accessed memory; the next prefetch can maintain the current prefetched memory. If the target access efficiency is less than the second preset value, it indicates that the difference between the prefetched memory and the actual accessed memory is significant, and the prefetched memory needs to be increased to improve access efficiency.

[0102] Optionally, when monitoring target access efficiency, the memory prefetch instruction can be updated based on the target access efficiency. If the target access efficiency is greater than a first preset value, the prefetch instruction is updated to load the prefetch cache into the L1 / L2 / L3 cache. If the target access efficiency is less than or equal to the first preset value, but greater than or equal to a second preset value, the prefetch instruction is not updated. If the target access efficiency is less than the second preset value, the prefetch instruction is updated to load the prefetch cache into the L3 cache area to reduce cache pollution.

[0103] By monitoring access efficiency in real time, we can dynamically optimize prefetch memory and instruction types, improve prefetch hit rate, and reduce cache pollution caused by invalid prefetches.

[0104] S304. If the memory size is greater than the size of the first remaining memory, then determine the target memory access node in at least one memory access node.

[0105] For each object, the method for selecting the target memory access node can be further determined based on the target memory type.

[0106] If the target memory type corresponding to the object is a high-frequency type, then among at least one second memory access node, the memory access node with an access latency less than or equal to a preset latency and a second remaining memory greater than or equal to the memory size is determined as the target memory access node. If there is no target memory access node among at least one second memory access node, then among at least one third memory access node, the memory access node with an access latency less than or equal to a preset latency and a second remaining memory greater than or equal to the memory size is determined as the target memory access node.

[0107] Optionally, if the target memory access node corresponding to the object is not in the same shared domain as the first memory access node, the object is marked as "remote access". When releasing the cache, the object is replaced with a priority lower than local high-frequency objects and higher than temporary objects to ensure that hot data resides for as long as possible.

[0108] If the target memory type corresponding to the object is a temporary type, then among at least one second memory access node, the memory access node with an access latency less than or equal to a preset latency and a second remaining memory greater than or equal to the memory size is determined as the target memory access node. If there is no target memory access node among at least one second memory access node, then among at least one third memory access node, the memory access node with an access latency less than or equal to a preset latency and a second remaining memory greater than or equal to the memory size is determined as the target memory access node.

[0109] Optionally, for objects of temporary types, priority can be given to memory access nodes that have an access latency less than or equal to the preset latency, the lowest access latency, and a second remaining memory greater than or equal to the memory size.

[0110] For objects of high-frequency and temporary types, the cache miss rate of cross-node access is reduced and remote access latency is decreased by prioritizing low-latency nodes within the shared domain.

[0111] If the target memory type corresponding to the object is a large object type, then in at least one second memory access node, the memory access node with the second remaining memory greater than or equal to the memory size is determined as the target memory access node.

[0112] Large object types suffer from high overhead when accessing shared domain caches, leading to performance degradation. Therefore, we only consider nodes within the shared domain to reduce cross-shared domain access latency and improve the efficiency of large object processing.

[0113] For example, as illustrated above, the target memory type corresponding to object B is determined to be a high-frequency type, and the target memory is memory 1. Assuming the first remaining memory of memory 1 is 0, it can be determined that the first remaining memory is less than the memory size 10B. The electronic device determines the second memory access node as memory access node 2 and the third memory access node as memory access node 3 based on the resource association table. Since the only second memory access node in the same shared domain as the first memory access node is memory access node 2, the electronic device determines that the access latency of memory access node 2 is less than a preset latency, and therefore determines that the target memory access node is memory access node 2.

[0114] For example, as illustrated above, the target memory type corresponding to object B is determined to be a high-frequency type, and the target memory is memory 1. Assuming the first remaining memory of memory 1 is 0, it can be determined that the first remaining memory is less than the memory size 10B. The electronic device determines the second memory access node as memory access node 2 and the third memory access node as memory access node 3 based on the resource association table. Since memory access node 2 is the only second memory access node in the same shared domain as the first memory access node, the electronic device determines that the access latency of memory access node 2 is greater than a preset latency. Therefore, the electronic device further determines that the access latency of memory access node 3 is less than the preset latency. Thus, the electronic device determines the target memory access node as memory access node 3.

[0115] Optionally, memory bandwidth utilization can also be considered as one of the decision factors when determining the target memory access node. By comprehensively considering memory bandwidth utilization, node selection can be optimized, avoiding performance degradation caused by bandwidth bottlenecks.

[0116] S305. Allocate target memory for the object based on the target memory type and the second memory under the target memory access node, and allocate target cache area for the object in the cache area.

[0117] For example, as illustrated above, the target memory access node is determined to be memory access node 2. The second memory under memory access node 2 is memory 2. The electronic device determines the sub-memory corresponding to the high-frequency type in memory 2 as sub-memory 21. Therefore, the target memory allocated by the electronic device for object B is sub-memory 21. Since the sub-cache region associated with sub-memory 21 is sub-cache region 11, the target cache region allocated for object B can be determined to be sub-cache region 11.

[0118] When allocating memory for objects, electronic devices can also release memory in cache areas to promptly delete unused data and provide cache areas for new data.

[0119] The cache area can be released in the following way: If the target cache area is a high-frequency type of sub-memory associated sub-cache area, then if the object accesses the sub-cache area twice consecutively, and the interval between the two accesses is greater than or equal to the first preset duration, the cache accessed by the object will be released in the target cache area.

[0120] If the target cache region is a temporary type of sub-memory associated sub-cache region, then obtain the cache queue of the target cache region. If the duration of the first data in the cache queue is greater than or equal to the second preset duration, release the cache corresponding to the first data in the target cache region through a preset instruction.

[0121] If the target cache region is a sub-cache region associated with a large object type, then determine the second data with the longest cache duration in the cache region, and release the cache corresponding to the second data in the target cache region.

[0122] The first preset duration can be set in advance and stored in the preset storage space of the electronic device.

[0123] Optionally, if the target cache region is a high-frequency type of sub-memory associated sub-cache region, the Least Recently Used (LRU)-2 algorithm and the method provided in the embodiments of this application can be combined to determine whether to release the cache accessed by the object. When it is determined for the first time that the cache needs to be released, the cache state can be modified to reusable without forcibly clearing the cache lines. In this way, by extending the lifespan of high-frequency data, the frequency of its replacement is reduced, the cache residence time is increased, and the latency of repeated loading is reduced.

[0124] Optionally, if the target cache region is a temporary sub-memory associated sub-cache region, the First-In-First-Out (FIFO) strategy and the method provided in the embodiments of this application can be combined to determine whether to release the cache accessed by the object. Furthermore, if it is determined that the data in the cache accessed by the object is invalid, the cache corresponding to the invalid data can be released directly.

[0125] Optionally, if the target cache region is a temporary type sub-memory associated sub-cache region, at least one second data with a cache duration greater than or equal to a second preset duration is identified in the cache region, and the cache occupied by the second data is released sequentially according to the release priority corresponding to the at least one second data. The release priority corresponding to the second data can be determined based on the data type.

[0126] When global memory is scarce, cache release is performed according to priority, effectively curbing the phenomenon of large objects crowding out shared cache resources.

[0127] After releasing the cached word, the electronic device can adjust the memory size of the target cache region according to the target access efficiency to improve the utilization of the cache region.

[0128] The memory size of the target cache region can be adjusted in the following ways: In response to the cache release command, obtain the target access efficiency corresponding to the target cache region; if the target cache region is a sub-cache region associated with a high-frequency type of sub-memory, and the target access efficiency is less than the fourth preset value, then increase the memory size of the sub-cache region according to the preset ratio; if the target cache region is a sub-cache region associated with a temporary type of sub-memory, and the target access efficiency is less than the fifth preset value, then decrease the memory size of the sub-cache region according to the preset ratio.

[0129] The fourth preset value, the fifth preset value, and the preset ratio can be set in advance. These preset values ​​and the preset ratio are then stored in the electronic device's preset storage space. The fourth preset value can be 0.8, and the fifth preset value can be 0.7.

[0130] For example, as illustrated above, the target cache region is determined to be sub-cache region 11, which is a sub-cache region associated with high-frequency type sub-memory. In response to a cache release instruction, the electronic device obtains the target access efficiency corresponding to sub-cache region 11 as 0.5. If the electronic device determines that the target access efficiency is less than the fourth preset value of 0.8, then according to a preset ratio of 1.5, the electronic device increases the memory size of the sub-cache region from 4MB to 6MB.

[0131] For example, suppose the target cache region is a temporary sub-memory associated sub-cache region. In response to a cache release instruction, the electronic device obtains a target access efficiency of 0.5 for the target cache region. If the electronic device determines that the target access efficiency is less than a fifth preset value of 0.7, then, according to a preset ratio of 1.5, the electronic device reduces the memory size of the sub-cache region from 6MB to 4MB.

[0132] By dynamically adjusting partition quotas, the resource allocation for high-frequency / temporary objects is balanced, thereby improving cache resource utilization.

[0133] The memory allocation method provided in this application constructs a dynamic closed loop across the entire chain of "semantic tagging, partition binding, prefetch optimization, release, and adjustment," adjusting strategies and related parameters through real-time metric feedback. This adapts to diverse load scenarios, reduces performance fluctuations, and improves system stability.

[0134] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0135] Based on any of the above embodiments, the following, in conjunction with Figure 4 The process of memory allocation will be explained.

[0136] Figure 4 A schematic diagram of the memory allocation process provided in the embodiments of this application is shown below. Figure 4 As shown, the device includes electronic device 401. Electronic device 401 includes a CPU, a cache region, first memory, and at least one memory access node. The CPU includes three processing cores, and the first memory is the memory under memory access node 2. Before memory allocation, electronic device 401 divides the first memory under memory access node 2 into three sub-memories: sub-memory 1, sub-memory 2, and sub-memory 3. The electronic device also divides the cache region into three sub-cache regions: sub-cache region 1, sub-cache region 2, and sub-cache region 3. The electronic device associates the sub-memories and sub-cache regions to obtain the memory type of each sub-memory and the associated sub-cache regions, as shown in Table 4.

[0137] Table 4

[0138]

[0139] Electronic device 401 sets an identifier for high-frequency types as identifier 1 in the header area of ​​sub-memory 1, sets an identifier for temporary types as identifier 2 in the header area of ​​sub-memory 2, and sets an identifier for large object types as identifier 3 in the header area of ​​sub-memory 3. Electronic device 401 obtains a memory allocation request, which includes object information corresponding to object C and a memory size of 5B. Electronic device 401 determines that processing core 2 runs object C. Therefore, electronic device 401 determines that the first memory access node is memory access node 2, and the first memory is the memory under memory access node 2.

[0140] Electronic device 401 determines semantic information based on the object information corresponding to object C, and determines that at least one first field corresponding to the semantic information includes the object's purpose and expected access frequency. Electronic device 401 determines that the field information corresponding to the object's purpose is a data index, and the field information corresponding to the expected access frequency is greater than a preset frequency. Electronic device 401 can determine that the object's purpose matches preset field 1, and the preset access frequency matches preset field 5. Electronic device 401 determines that the memory type corresponding to preset field 1 and preset field 5 is a high-frequency type. Therefore, electronic device 401 determines that the target memory type corresponding to object C is a high-frequency type.

[0141] Electronic device 401 determines that the memory size of 5B is less than the size of the first remaining memory. Therefore, based on the high-frequency type, it determines the target memory as sub-memory 1 within the first memory. Since the memory allocation request contains a memory size of 5B, which is less than the preset memory size, electronic device 401 allocates target memory for object C within sub-memory 1. The target memory is cache line 1 within sub-memory 1, and the starting address of the target memory is aligned with the boundary of cache line 1. Electronic device 401 determines that the target cache region is sub-cache region 1 associated with the high-frequency type sub-memory; therefore, the target cache region allocated by electronic device 401 for object C is sub-cache region 1.

[0142] Since the target cache region is sub-cache region 1 associated with a high-frequency type of sub-memory, electronic device 401 determines that if object B accesses the sub-cache region twice consecutively, and the interval between the two accesses is longer than a first preset duration, then it releases the cache accessed by object A in the target cache region. Within a preset processing cycle, electronic device 401 responds to the cache release instruction and obtains a target access efficiency of 0.8.

[0143] Electronic device 401 determines that the prefetch memory is 32B. Since the target access efficiency is less than the first preset value of 0.9 and greater than the second preset value of 0.6, electronic device 401 determines the target prefetch memory to be 32B. Because the target cache region is sub-cache region 1 associated with high-frequency type sub-memory, and the target access efficiency is less than the fourth preset value of 0.9, electronic device 401 increases the memory size of sub-cache region 1 from 3MB to 4.5MB according to a preset ratio of 1.5.

[0144] The memory allocation process provided in this application constructs a dynamic closed loop across the entire chain, encompassing semantic tagging, partition binding, prefetch optimization, release, and adjustment. It adjusts strategies and related parameters through real-time metric feedback. This adapts to diverse load scenarios, reduces performance fluctuations, and improves system stability.

[0145] Figure 5 This is a schematic diagram of the structure of a memory allocation device provided in an embodiment of this application. Figure 5 As shown, embodiments of this application also provide a memory allocation device, the memory allocation device 500 comprising:

[0146] The acquisition module 501 is used to acquire memory allocation requests. The memory allocation request includes object information corresponding to the object requesting memory, as well as the memory size.

[0147] The determination module 502 is used to determine the target memory type of the object based on the semantic information corresponding to the memory allocation request;

[0148] The first processing module 503 is used to allocate target memory for the object in the first memory and allocate a target cache area for the object in the cache area according to the target memory type if the memory size is less than or equal to the size of the first remaining memory. The first memory is the memory under the first memory access node corresponding to the object, and the first remaining memory is the memory currently available in the first memory.

[0149] The second processing module 504 is used to determine a target memory access node in at least one memory access node if the memory size is greater than the size of the first remaining memory, and to allocate target memory for the object according to the target memory type and the second memory under the target memory access node, and to allocate a target cache area for the object in the cache area.

[0150] In one possible implementation, the determining module 502 is specifically used for:

[0151] Obtain at least one preset field, which is used to describe information related to the object's runtime memory access;

[0152] Determine at least one first field corresponding to the semantic information;

[0153] For any first field, if there exists a preset field that matches the first field, then the preset field is determined as the candidate field, the memory type corresponding to the candidate field is determined, and the target memory type of the object is determined to be the memory type corresponding to the candidate field.

[0154] In one possible implementation, the first processing module 503 is specifically used for:

[0155] In the first memory, at least one sub-memory is identified, and the memory identifier of each sub-memory is obtained in the header storage area of ​​each sub-memory;

[0156] Determine the target memory identifier corresponding to the target memory type;

[0157] In at least one sub-memory of the first memory, a candidate sub-memory is determined, and the memory identifier of the candidate sub-memory matches the target memory identifier;

[0158] If the memory size is less than or equal to the preset memory size, then the target memory is allocated for the object in the candidate sub-memory. The target memory is the cache line in the candidate sub-memory, and the starting address of the target memory is aligned with the boundary of the cache line.

[0159] If the memory size is greater than the preset memory size, then the target memory is allocated for the object in the candidate sub-memory. The target memory is a contiguous storage area in the candidate sub-memory.

[0160] Within the cache region, the target cache region allocated for an object is determined to be a sub-cache region associated with the target memory.

[0161] In one possible implementation, the second processing module 504 is specifically used for:

[0162] In at least one memory access node, at least one second memory access node is determined, the second memory access node being in the same shared domain as the first memory access node;

[0163] A target memory access node is determined among at least one second memory access node, the target memory access node has the minimum access latency, and the size of the second remaining memory corresponding to the target memory access node is greater than or equal to the memory size.

[0164] In one possible implementation, the second processing module 504 is further configured to:

[0165] If the target memory access node is not present in at least one second memory access node, then at least one third access node is determined in at least one memory access node.

[0166] A target memory access node is determined among at least one third memory access node, the target memory access node has the minimum access latency, the size of the second remaining memory is greater than or equal to the memory size, and the third memory access node and the first memory access node are not in the same shared domain.

[0167] In one possible implementation, the first processing module 503 is further configured to:

[0168] The first memory is divided according to at least one memory type to obtain sub-memory corresponding to each memory type. The memory identifier of the sub-memory is stored in the header area of ​​the sub-memory. The memory type is high-frequency type, temporary type, or large object type.

[0169] The high-frequency type sub-memory is associated with the sub-cache region with low replacement priority in the cache region, the temporary type sub-memory is associated with the sub-cache region with high replacement priority in the cache region, and the large object type sub-memory is associated with the independent sub-cache region in the cache region, thus obtaining the sub-cache region corresponding to each sub-memory.

[0170] In one possible implementation, the first processing module 503 is further configured to:

[0171] If the target cache region is a high-frequency type of sub-memory associated sub-cache region, then if an object accesses the sub-cache region twice consecutively, and the interval between the two accesses is greater than or equal to the first preset duration, the cache accessed by the object will be released in the target cache region.

[0172] If the target cache region is a temporary type of sub-memory associated sub-cache region, then obtain the cache queue of the target cache region. If the duration of the first data in the cache queue is greater than or equal to the second preset duration, release the cache corresponding to the first data in the target cache region through a preset instruction.

[0173] If the target cache region is a sub-cache region associated with a large object type, then determine the second data with the longest cache duration in the cache region, and release the cache corresponding to the second data in the target cache region.

[0174] In one possible implementation, the first processing module 503 is further configured to:

[0175] Obtain the target access efficiency corresponding to the target cache region. The target access efficiency is the ratio of prefetched memory to actual accessed memory.

[0176] If the target access efficiency is greater than the first preset value, then the target prefetch memory is determined to be the memory requested by the object, and the target prefetch memory is the memory size for the next cache prefetch process;

[0177] If the target access efficiency is less than or equal to the first preset value and greater than or equal to the second preset value, then the target prefetch memory is determined to be prefetch memory.

[0178] If the target access efficiency is less than the second preset value, then the target prefetch memory is determined to be the product of the prefetch memory and the third preset value.

[0179] In one possible implementation, the first processing module 503 is further configured to:

[0180] In response to a cache release command, obtain the target access efficiency corresponding to the target cache region;

[0181] If the target cache region is a high-frequency type of sub-memory associated sub-cache region, and the target access efficiency is less than the fourth preset value, then the memory size of the sub-cache region will be increased according to the preset ratio.

[0182] If the target cache region is a temporary type of sub-memory associated sub-cache region, and the target access efficiency is less than the fifth preset value, then the memory size of the sub-cache region will be reduced according to the preset ratio.

[0183] For a description of the features in the embodiment corresponding to the memory allocation device, please refer to the relevant description in the embodiment corresponding to the memory allocation method, which will not be repeated here.

[0184] Figure 6 A schematic diagram of the structure of the electronic device provided in this application. Figure 6As shown, the electronic device 600 provided in this embodiment includes at least one processor 601 and a memory 602. Optionally, the electronic device 600 further includes a communication component 603. The processor 601, memory 602, and communication component 603 are connected via a bus.

[0185] In a specific implementation, at least one processor 601 executes computer execution instructions stored in memory 602, causing at least one processor 601 to execute the memory allocation method embodiment described above.

[0186] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0187] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0188] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0189] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0190] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described memory allocation method embodiments at runtime.

[0191] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0192] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described memory allocation method embodiments.

[0193] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described memory allocation method embodiments.

[0194] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0195] The foregoing has provided a detailed description of a memory allocation and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A memory allocation method, characterized in that, include: Obtain a memory allocation request, wherein the memory allocation request includes object information corresponding to the object requesting memory, and the memory size; Based on the semantic information corresponding to the memory allocation request, determine the target memory type corresponding to the object; If the memory size is less than or equal to the size of the first remaining memory, then according to the target memory type, target memory is allocated for the object in the first memory, and a target cache area is allocated for the object in the cache area. The first memory is the memory under the first memory access node corresponding to the object, and the first remaining memory is the memory currently available in the first memory. If the memory size is greater than the size of the first remaining memory, then a target memory access node is determined in at least one memory access node, and the target memory is allocated to the object according to the target memory type and the second memory under the target memory access node, and the target cache area is allocated to the object in the cache area; Determining the target memory access node in at least one memory access node includes: Among the at least one memory access node, at least one second memory access node is determined, the second memory access node being in the same shared domain as the first memory access node; The target memory access node is determined among the at least one second memory access node, the target memory access node has the lowest access latency, and the size of the second remaining memory corresponding to the target memory access node is greater than or equal to the memory size.

2. The memory allocation method according to claim 1, characterized in that, Based on the semantic information corresponding to the memory allocation request, the target memory type corresponding to the object is determined, including: Obtain at least one preset field, which is used to describe information related to the object's runtime memory access; Determine at least one first field corresponding to the semantic information; For any first field, if there exists a preset field that matches the first field, then the preset field is determined as a candidate field, the memory type corresponding to the candidate field is determined, and the target memory type corresponding to the object is determined as the memory type corresponding to the candidate field.

3. The memory allocation method according to claim 2, characterized in that, Based on the target memory type, allocating target memory for the object in the first memory and allocating a target cache area for the object in the cache area includes: In the first memory, at least one sub-memory is determined, and the memory identifier of each sub-memory is obtained in the header storage area of ​​each sub-memory; Determine the target memory identifier corresponding to the target memory type; In at least one sub-memory of the first memory, a candidate sub-memory is determined, wherein the memory identifier of the candidate sub-memory matches the target memory identifier; If the memory size is less than or equal to the preset memory size, then the target memory is allocated for the object in the candidate sub-memory. The target memory is a cache line in the candidate sub-memory, and the starting address of the target memory is aligned with the boundary of the cache line. If the memory size is greater than the preset memory size, then the target memory is allocated for the object in the candidate sub-memory, and the target memory is a contiguous storage area in the candidate sub-memory; Within the cache region, the target cache region allocated to the object is determined to be the sub-cache region associated with the target memory.

4. The memory allocation method according to claim 1, characterized in that, The method further includes: If the target memory access node is not present among the at least one second memory access node, then at least one third access node is determined among the at least one memory access node; The target memory access node is determined among the at least one third memory access node, the target memory access node has the lowest access latency, and the size of the second remaining memory is greater than or equal to the memory size, and the third memory access node and the first memory access node are not in the same shared domain.

5. The memory allocation method according to any one of claims 1-4, characterized in that, The method further includes: The first memory is divided according to at least one memory type to obtain sub-memory corresponding to each memory type. The memory identifier of the sub-memory is stored in the header area of ​​the sub-memory. The memory type is a high-frequency type, a temporary type, or a large object type. The high-frequency type sub-memory is associated with the sub-cache region with low replacement priority in the cache region, the temporary type sub-memory is associated with the sub-cache region with high replacement priority in the cache region, and the large object type sub-memory is associated with the independent sub-cache region in the cache region, thus obtaining the sub-cache region corresponding to each sub-memory.

6. The memory allocation method according to any one of claims 1-4, characterized in that, The method further includes: If the target cache region is a high-frequency type sub-memory associated sub-cache region, then if the object accesses the sub-cache region twice consecutively, and the interval between the two accesses is greater than or equal to a first preset duration, the cache accessed by the object is released in the target cache region. If the target cache region is a temporary type of sub-memory associated sub-cache region, then obtain the cache queue of the target cache region. If the duration of the first data in the cache queue is greater than or equal to the second preset duration, release the cache corresponding to the first data in the target cache region through a preset instruction. If the target cache region is a sub-cache region associated with a sub-memory of a large object type, then the second data with the longest cache duration is determined in the cache region, and the cache corresponding to the second data is released in the target cache region.

7. The memory allocation method according to any one of claims 1-4, characterized in that, The method further includes: Obtain the target access efficiency corresponding to the target cache region, where the target access efficiency is the ratio between prefetched memory and actual accessed memory. If the target access efficiency is greater than the first preset value, then the target prefetch memory is determined to be the memory requested by the object, and the target prefetch memory is the memory size for the next cache prefetch process; If the target access efficiency is less than or equal to the first preset value and greater than or equal to the second preset value, then the target prefetch memory is determined to be the prefetch memory; If the target access efficiency is less than the second preset value, then the target prefetch memory is determined to be the product of the prefetch memory and the third preset value.

8. The memory allocation method according to any one of claims 1-4, characterized in that, The method further includes: In response to a cache release command, obtain the target access efficiency corresponding to the target cache region; If the target cache region is a high-frequency type of sub-memory associated sub-cache region, and the target access efficiency is less than a fourth preset value, then the memory size of the sub-cache region is increased according to a preset ratio. If the target cache region is a temporary type of sub-memory associated sub-cache region, and the target access efficiency is less than a fifth preset value, then the memory size of the sub-cache region is reduced according to the preset ratio.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for implementing the steps of the memory allocation method as described in any one of claims 1 to 8 when executing the computer program.

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