Silicon photomultiplier and preparation method thereof

Abstract

The invention discloses a silicon photomultiplier and a preparation method thereof, belongs to the technical field of semiconductor device processing, and aims to solve the problems of lattice damage, channel effect, interface defects and the like caused by single-time high-dose ion implantation in the traditional process. Through the innovative processes of dose grading ion implantation, stepped cooling annealing, Gepre-amorphization processing, atomic layer deposition passivation and the like, the dark counting rate of the device is remarkably reduced, and the photon detection efficiency and the avalanche gain stability are improved. The prepared silicon photomultiplier comprises an optimally designed doped region and an Al2O3 / SiNx composite passivation layer, has excellent detection performance in a blue-violet light band, and can be widely applied to high-sensitivity detection fields such as biomedical imaging, nuclear radiation detection and laser radar.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device processing technology, specifically relating to a silicon photomultiplier tube and its preparation method. Background Technology

[0002] Silicon photomultiplier tubes (SiPMs) are a novel type of solid-state photon detector characterized by high gain, high sensitivity, low bias voltage, insensitivity to magnetic fields, and compact structure. They are widely used in biomedical imaging, nuclear radiation detection, lidar, quantum communication, and other fields. In blue-violet light detection scenarios, such as water quality monitoring and biofluorescence detection, extremely high dark count performance is required for SiPMs.

[0003] The basic structure of a conventional silicon photomultiplier tube (SiPM) includes a substrate made of N-type low-resistivity silicon, an epitaxial layer formed on the substrate surface made of N-type high-resistivity silicon, and a photoanode and photocathode formed by P-type ion implantation and N-type ion implantation, respectively. In existing manufacturing processes, ion implantation of the photocathode or photoanode is performed using a single high-dose implantation method. This method easily leads to lattice damage in the silicon material, and even with subsequent annealing, such lattice damage is difficult to completely repair, thus affecting the performance of the SiPM. At the same time, traditional processes lack effective means to solve the channeling effect and defect cluster problem during photoanode formation, and the interface between the implanted region and the sidewalls is not effectively passivated, making it difficult to meet the performance requirements of low dark count SiPMs, leaving room for process optimization.

[0004] In existing technologies, the photoanode and photocathode of silicon photomultiplier tubes (SMTs) are typically formed using a single high-dose ion implantation process. However, during high-dose ion implantation, high-energy ions collide violently with silicon lattice atoms, causing lattice atoms to detach from their original positions and forming numerous vacancies, interstitial atoms, and other lattice defects. Although subsequent annealing processes attempt to repair the lattice damage, the defect density generated by high-dose implantation is extremely high, making it difficult to completely eliminate residual defects after annealing. These residual defects become recombination or generation centers for charge carriers, significantly increasing the dark current of the device and consequently leading to an increase in the dark count, which fails to meet the application requirements for low dark counts in the blue-violet light band. Furthermore, in traditional ion implantation processes, ions tend to generate channeling effects along specific crystal orientations of the silicon crystal, causing the implanted ion distribution to deviate from the design target, further affecting the photoelectric conversion efficiency and uniformity of the device, thus limiting the application of silicon photomultiplier tubes in low dark count scenarios in the blue-violet light band. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a silicon photomultiplier tube and its fabrication method. This invention solves the technical problems in the prior art, such as the difficulty in repairing lattice damage caused by a single high-dose ion implantation, the formation of ion implantation channel effects and defect clusters, and the poor interfacial electric field characteristics and excessively high dark count caused by the lack of effective passivation of the implantation region and interface. This invention enables the fabrication of a silicon photomultiplier tube with low dark count characteristics in the blue-violet light band.

[0006] The present invention adopts the following technical solution: A method for fabricating a silicon photomultiplier tube includes the following steps: S1. A first doped type substrate with a specific doping concentration is provided, the substrate comprising an epitaxial layer; S2. Multiple ion implantations of the first doping type are performed on the epitaxial layer by dose distribution to form well doped ion implantation and heavily doped ion implantation of the first doping type region for cathode contact hole contact. S3. Perform stepped cooling annealing on the implanted doped ions in the well region to obtain ion activation and defect repair; S4. Perform multiple ion implantations of the first doping type on the epitaxial layer through dose distribution to form a first avalanche region of the first doping type for avalanche; perform stepped cooling annealing on the ion implantation of the first avalanche region to obtain ion activation and defect repair. S5. Pre-amorphization ion implantation is performed in the second avalanche region above the first avalanche region to form an amorphous layer. Multiple ion implantations of the second doping type are performed in the second avalanche region through dose distribution to form a second avalanche region of the second doping type for avalanche. Stepped cooling annealing is performed on the ion implantation of the second avalanche region to obtain ion activation and defect repair. S6. Perform atomic layer deposition above the second avalanche region to suppress interface state defects of the silicon photomultiplier tube through surface passivation.

[0007] Preferably, in step S1, the first doped substrate is made of N-type low-resistivity silicon, and the epitaxial layer is formed on the surface of the substrate by epitaxial growth technology.

[0008] Preferably, in step S2, multiple ion implantations of the first doping type are performed on the epitaxial layer by dose distribution to form a well region doped with ion implantations for the first doping type of cathode contact hole contact, specifically including: Phosphorus ions were injected at a dose of 1-2e13cm. -2 The energy is 380-420 keV; Phosphate ions were injected at a dose of 4-6e12cm. -2The energy is 130-150 keV; Arsenic ions were injected at a dose of 0.8-1.2e12cm. -2 The energy is 110-130 keV; Multiple ion implantations of the first doping type are performed on the epitaxial layer through dose allocation to form a heavily doped ion implantation region of the first doping type, including: Arsenic ions were injected at a dose of 6-7e15cm. -2 The energy is 38-42 keV; Phosphate ions were injected at a dose of 1.8-2.2e14cm. -2 The energy is 23-27 keV; Among them, the heavy doping ion implantation is compatible with the source and drain ion implantation of silicon photomultiplier tubes.

[0009] Preferably, in step S3, the temperature of the stepped cooling annealing is reduced from 1020-1050°C to 580-620°C, and the stepped cooling annealing is carried out in an inert gas atmosphere and is a gradient cooling.

[0010] Preferably, in step S4, multiple ion implantations of the epitaxial layer of the first doping type are performed by dose allocation to form a first avalanche region of the first doping type for avalanche formation, specifically including: The multiple ion implantations consist of four phosphorus ion implantations, with a total dose of 1.8-2.2e12cm. -2 The energy of each ion implantation was 230-250 keV; the dose distribution of the four ion implantations was equal-dose split, meaning the dose of each ion implantation was 4.5-5.5e11cm. -2 Alternatively, the doses of the four ion implantations can be divided into gradient doses, with the single dose ratio increasing in an incremental relationship, wherein the single dose ratio is 1:1.5:2:2.5; The temperature for the ion implantation in the first avalanche region is reduced from 1010-1020°C to 440-460°C using a stepped cooling annealing method.

[0011] Preferably, in step S5, the parameters for the pre-amorphized ion implantation are: Injecting Ge + Ions, Ge + The ion implantation dose was 0.8-1.2e14cm. -2 Ge + The ion implantation energy is 8-12 keV.

[0012] Preferably, in step S5, multiple ion implantations of the second doping type are performed on the second avalanche region through dose distribution to form a second doped type second avalanche region for avalanche formation, specifically including: The multiple ion implantations consist of four boron ion implantations, with each implantation using the following parameters: dose 2.0-3.0e14cm. -2 The energy was 5-7 keV; the total dose of the four boron ion implantations was 0.9-1.1e15cm. -2 ; The temperature for the ion implantation in the second avalanche region was reduced from 1010-1020°C to 440-460°C using a stepped cooling annealing method.

[0013] Preferably, in step S6, an Al2O3 layer of 5-10 nm is deposited above the second avalanche region by atomic layer deposition, and a SiNx layer of 70-90 nm is formed above the Al2O3 layer by enhanced chemical vapor deposition, and the negative fixed charge of the Al2O3 layer is activated by annealing at 440-460°C.

[0014] Preferably, after step S6 is completed, the dielectric layer of all avalanche regions in the silicon photomultiplier array is completely etched away using a dedicated mask and etching process, leaving only the dielectric layer structure of other functional areas of the chip, including the driving circuit area and PAD interconnect.

[0015] Another technical solution of the present invention is a silicon photomultiplier tube, the silicon photomultiplier tube comprising a substrate of a first doping type, wherein an epitaxial layer of the same type as the substrate is covered on the substrate; a well region and a heavily doped ion region are formed on the epitaxial layer by ion implantation; a first avalanche region of the first doping type is disposed above the epitaxial layer, an amorphous layer and a second avalanche region of the second doping type are disposed above the first avalanche region, an Al2O3 layer is disposed above the second avalanche region, and a SiNx layer is disposed above the Al2O3 layer; wherein the well region and the heavily doped ion region are formed by multiple ion implantations, the first avalanche region is formed by multiple ion implantations, and the second avalanche region is formed by multiple ion implantations.

[0016] Compared with the prior art, the present invention has at least the following beneficial effects: A method for fabricating silicon photomultiplier tubes (PMTs) replaces traditional single high-dose implantation with multiple ion implantations, combined with stepped cooling annealing and pre-amorphization treatment, forming a closed-loop technology of damage reduction, defect repair, and interface optimization. Multiple ion implantations reduce the impact of a single implantation on the silicon lattice, minimizing initial lattice damage; stepped annealing enables ion activation and defect repair in stages, avoiding secondary damage caused by thermal stress; pre-amorphization and surface passivation address channel effects and interface state defects, respectively. The overall approach effectively improves device performance, particularly suitable for low-darkness counting requirements in the blue-violet light band, providing a basic framework for subsequent parameter optimization while balancing process feasibility and performance stability.

[0017] Furthermore, it is explicitly stated that the first doped substrate is N-type low-resistivity silicon, and the epitaxial layer is formed through epitaxial growth. This limitation lays the foundation for device performance. N-type low-resistivity silicon substrates possess excellent conductivity, reducing signal loss caused by substrate resistance and ensuring efficient carrier transport. Epitaxial growth technology allows for precise control of the crystal structure, doping concentration, and thickness of the epitaxial layer, ensuring its uniformity and avoiding impurity interference. Compared to ordinary substrates and deposition methods, this reduces interface defects between the substrate and the epitaxial layer, improving the device's electrical stability. Simultaneously, it provides a uniform doped substrate for subsequent ion implantation, resulting in a more precise concentration distribution in the doped region, indirectly optimizing the avalanche multiplication effect and meeting the high requirements of silicon photomultiplier tubes for substrate materials.

[0018] Furthermore, multiple implantations using a mixture of phosphorus and arsenic ions were employed, with clearly defined dose and energy ranges. In mixed ion implantation, phosphorus ions, being lightweight and having a moderate diffusion coefficient, are suitable for forming deep, low-concentration regions; arsenic ions, being heavy and having a low diffusion coefficient, are beneficial for stabilizing high-concentration regions on the surface. An energy gradient design (380-420 keV to 110-130 keV) creates a gradient concentration distribution from deep to middle to surface layers, which can suppress lateral carrier diffusion and reduce edge leakage caused by photolithography alignment errors. The heavily doped ion implantation parameters are matched to the source and drain to ensure low contact resistance and reduce signal transmission loss. This scheme, through precise matching of ion type, dose, and energy, reduces lattice defect density, improves doping activation rate, and simultaneously ensures process compatibility, providing a guarantee for stable operation of the cathode contact region.

[0019] Furthermore, the stepped cooling annealing employs a gradient cooling process within the temperature range of 1020-1050°C to 580-620°C, solving the problem that traditional isothermal annealing cannot simultaneously achieve ion activation and thermal stress control. The high-temperature range of 1035°C ensures that the N-type ion activation rate reaches over 90%, while the gradient cooling process reduces the risk of lattice microcracks caused by thermal stress by 70%. Annealing in an inert gas atmosphere avoids silicon surface oxidation and impurity reactions, ensuring the purity and electrical stability of the doped region.

[0020] Furthermore, splitting the single high-dose phosphorus implantation into four medium- and low-dose implantations significantly reduced the local lattice damage density. Equal-dose splitting ensured doping uniformity, while gradient-dose splitting (1:1.5:2:2.5) naturally created a gradient doping distribution, optimizing the electric field distribution in the avalanche region. This design improved avalanche gain uniformity to over 95%, reduced dark count rate by 30%, and the stepped annealing from 1010-1020°C to 440-460°C further repaired implantation defects, improving device reliability.

[0021] Furthermore, Ge + Pre-amorphization implantation completely eliminates the channeling effect in traditional single-crystal implantation by forming an amorphous layer. Low-energy implantation of 8-12 keV ensures precise matching of the amorphous layer depth with subsequent doping regions (0.8-1.2e14cm). -2 The moderate dosage ensures the amorphization effect while avoiding excessive surface damage. The ordered reconstruction of the amorphous layer during annealing provides regular occupancy paths for boron ions, resulting in a doping concentration uniformity of 96% and reducing the number of defect clusters to 1 / 5 of that in traditional processes.

[0022] Furthermore, the boron implantation in the second avalanche region was divided into four stages. Each implantation resulted in a significantly reduced defect density and a more dispersed spatial distribution, facilitating subsequent annealing repair. The low-energy implantation of 5-7 keV primarily affected the surface layer, reducing surface roughness caused by ion sputtering. This multi-step implantation strategy reduced surface roughness by 40% and improved photon absorption efficiency by 15%-25%, with a particularly significant improvement in detection sensitivity in the ultraviolet to blue light band.

[0023] Furthermore, the innovative combination of Al2O3 / SiNx composite passivation layers achieves the dual functions of interface passivation and optical optimization. The 5-10nm Al2O3 layer modulates the interface electric field through negative fixed charge, reducing the interface state density to 10-1. 11 cm -2 ·eV -1 The 70-90nm SiNx layer reduces the blue-violet light reflectivity to 5%-8% through optical interference. Annealing at 440-460°C activates the negative fixed charge of Al2O3, while the dense structure of SiNx prevents hydrogen atom escape and oxygen vacancy migration, thus improving the field-effect passivation effect by 50%.

[0024] Furthermore, by selectively etching away the dielectric layer in the avalanche region, precise optimization of the device structure was achieved. This step simplifies the incident light interface from multiple dielectric layers to a single air-silicon interface, increasing the photon absorption efficiency in the blue-violet light band from 70% to over 92%. Simultaneously, the removal of the dielectric layer effectively releases wafer stress, avoiding device reliability issues caused by stress accumulation and improving the long-term stability of the device by 30%.

[0025] In summary, this invention significantly reduces the dark count rate (40-85Hz) of silicon photomultiplier tubes and improves photon detection efficiency (60%-80%) and avalanche gain stability through innovative processes such as dose-graded injection, stepped annealing, pre-amorphization, and atomic layer deposition passivation. The device exhibits excellent performance in the blue-violet light band, demonstrates good process repeatability, and is suitable for high-sensitivity detection scenarios, solving key technical challenges such as lattice damage, channeling effects, and interface defects in traditional processes.

[0026] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the following description of the relative embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic flowchart of the silicon photomultiplier tube fabrication method of the present invention; Figure 2 is a cross-sectional schematic diagram of the silicon photomultiplier tube during the preparation process of the present invention, wherein (a) is a schematic diagram of the substrate and epitaxy, (b) is a schematic diagram of N-trap ion implantation, (c) is a schematic diagram of cathode ion implantation, (d) is a schematic diagram of anode ion implantation, and (e) is a schematic diagram of passivation and anti-reflection layer film coating. Figure 3 This is a cross-sectional schematic diagram of a silicon photomultiplier tube according to this application; Figure 4 This is a schematic diagram of a silicon photomultiplier tube chip according to this application.

[0029] Figure 5 This is a schematic diagram of the chip with the etching dielectric layer of this application.

[0030] Wherein: 201. Substrate; 202. Epitaxial layer; 203. N-well; 204. N++. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "one side," "one end," and "one side," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0033] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0034] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0035] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0036] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0037] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0038] This invention provides a silicon photomultiplier tube and its fabrication method. The method involves dose-stage implantation in both the photocathode and photoanode regions of the silicon photomultiplier tube, breaking down the existing single high-dose ion implantation into multiple medium- and low-dose implantations to reduce local lattice damage. During the formation of the photoanode, the photoanode region is first subjected to Ge... + Pre-amorphization treatment is used to reduce the channeling effect of ion implantation and reduce the formation of defect clusters. An Al2O3 layer is formed by atomic layer deposition to cover the implantation area and sidewalls. The negative charge of Al2O3 is used to adjust the interface electric field to achieve interface passivation, thereby achieving low dark count characteristics with peak wavelength at blue-violet light wavelength, which meets the performance requirements of SiPM for specific application scenarios.

[0039] Please see Figure 1 The present invention discloses a method for fabricating a silicon photomultiplier tube, comprising the following steps: S1. A first doped type substrate with a specific doping concentration is provided, the substrate comprising an epitaxial layer; Referring to Figure 2(a), in the semiconductor manufacturing process, a substrate 201 with a first doping type and a specific doping concentration is first provided. This substrate serves as the foundation of the entire device, and its doping type is determined according to requirements, such as P-type or N-type, depending on the functional requirements of the subsequent device. Based on this, the substrate further includes an epitaxial layer 202, which is formed on the substrate surface using epitaxial growth technology. Its crystal structure, composition, and thickness are precisely controlled to meet specific performance requirements.

[0040] Specifically, in the silicon photomultiplier tube fabrication method of this embodiment, the first doped substrate is made of N-type low-resistivity silicon.

[0041] S2. Multiple ion implantations of the first doping type are performed on the epitaxial layer by dose distribution to form well doped ion implantation and heavily doped ion implantation of the first doping type region for cathode contact hole contact. Over-doping is performed on the epitaxial layer using multiple ion implantations of the first doping type to form a well region doped with ion implantations for the first doping type of cathode contact hole contact, including: Phosphorus ions were injected at a dose of 1-2e13cm. -2 The energy is 380-420 keV; Phosphate ions were injected at a dose of 4-6e12cm. -2 The energy is 130-150 keV; Arsenic ions were injected at a dose of 0.8-1.2e12cm. -2 The energy is 110-130 keV.

[0042] Multiple ion implantations of the first doping type are performed on the epitaxial layer through dose allocation to form a heavily doped ion implantation region of the first doping type, including: Arsenic ions were injected at a dose of 6-7e15cm. -2 The energy is 38-42 keV; Phosphate ions were injected at a dose of 1.8-2.2e14cm. -2 The energy is 23-27 keV; Among them, the heavy doping ion implantation is compatible with the source and drain ion implantation of silicon photomultiplier tubes.

[0043] Please refer to Figure 2(b). The N-type region for cathode contact hole contact is formed by implanting N-type (first doping type) ions to form the N-type region N-well 203 doped ion implantation and N++204 implantation. N++ ion implantation is used to adapt the source and drain ions for the silicon photomultiplier tube. The ion implantation example menu is as follows, and the multiple ion implantation parameters for N-well 203 are as follows: implantPhosphorusdose= 1.5e13 cm -2 energy = 400 <kev> implantPhosphorusdose= 5.0e12 cm -2 energy= 140 <kev> ImplantArsenicdose= 1.0e12 cm -2 energy= 120 <kev> The parameters for multiple ion implantation of N++204 are as follows: implant Arsenicdose = 6.5e15 cm -2 energy=40 <kev> implantPhosphorusdose=2.0e14 cm -2 energy=25 <kev> First, the N-well 203 employs a mixed phosphorus (P) and arsenic (As) implantation with a gradient implantation energy design (400 keV → 140 keV → 120 keV). High-energy (400 keV) phosphorus implantation forms a deep, low-concentration N-type region, medium-energy (140 keV) phosphorus implantation forms a mid-layer transition region, and low-energy (120 keV) arsenic implantation forms a shallow surface junction region. This gradient concentration distribution (lower dose in the deep layer and slightly higher dose in the surface layer) forms a lateral barrier. When there are small alignment deviations at the edge of the cathode contact hole, the gradient distribution can suppress the lateral diffusion of charge carriers into the substrate, unexpectedly reducing edge leakage current caused by photolithography alignment errors.

[0044] Phosphorus ions are relatively light and easily form lattice defects during high-energy implantation, while arsenic ions are heavier and mainly generate interstitial atom defects during low-energy implantation. These two defect types can annihilate each other during subsequent annealing (vacancy and interstitial atom recombination), reducing the total defect density compared to single ion implantation. This increases the doping activation rate of the N-well and indirectly improves the carrier concentration stability in the cathode contact region.

[0045] In addition, N++204 uses a high dose of arsenic (6.5e15cm). -2 40 keV) and low doses of phosphorus (2.0 e14 cm⁻¹) -2 Ion implantation at 25 keV.

[0046] Arsenic has a large atomic weight and a low diffusion coefficient. After high-dose implantation, it will form a high-concentration and stable N-type layer on the surface, ensuring low contact resistance between the source / drain of the silicon photomultiplier tube and the metal. Low-energy phosphorus implantation (25keV) will fill the gaps between arsenic ions, forming a mixed doping of arsenic and phosphorus. The small atomic radius of phosphorus can reduce the electrical neutrality defects of arsenic ions, making the surface carrier concentration higher than that of single arsenic implantation. At the same time, due to the shallow junction characteristics of phosphorus, it will not affect the PN junction depth, further reducing the contact resistance without increasing junction leakage current.

[0047] Furthermore, the highest energy of N++204 ion implantation is only 40 keV (far lower than the 400 keV of N-wells), and the implantation damage is mainly concentrated on the surface layer. Moreover, the damage layer formed by the mixed implantation of arsenic and phosphorus is more porous. Subsequent low-temperature annealing (since N++ ion implantation is the last step) can more thoroughly repair the surface damage and reduce the roughness of the wafer surface. This smooth surface can enhance the adhesion of the metal layer and reduce the risk of metal peeling.

[0048] The aforementioned ion implantation dose and energy values, through the combination of ion species matching, energy gradient, and dose level difference, achieve additional effects such as reduced leakage current, improved reliability, and expanded process compatibility.

[0049] S3. Perform stepped cooling annealing on the implanted doped ions in the well region to obtain ion activation and defect repair; After ion implantation into the N-well region, a thermal diffusion annealing process is performed, which involves stepped cooling annealing from 1020-1050°C to 580-620°C to reduce thermal stress. The high temperature is used for ion activation, and the low temperature is used for defect repair.

[0050] Specifically, if the injected N-type ions remain in the interstitial positions of the silicon lattice, they cannot participate in electrical conduction. The core function of the high-temperature section is to provide sufficient thermal energy for the ions to break through the lattice barrier and migrate to the substitutional positions of silicon atoms (i.e., occupy the original lattice nodes of silicon atoms), becoming freely moving charge carriers (free electrons). This process is called ion activation.

[0051] Among them, 1035°C is the optimal temperature range for N-type ion activation of silicon-based devices. Below 1000°C, the thermal kinetic energy of ions is insufficient, the substitution migration probability is low, and the activation rate can only reach 50%-60%, resulting in insufficient carrier concentration in the doped region, which cannot meet the electrical requirements of devices (such as the N-type cathode of SiPM). Above 1050°C, the silicon lattice is prone to thermal melting, and the implanted ions may cause the boundary of the doped region to become blurred due to excessive diffusion, which will destroy the doping accuracy of the device design.

[0052] In addition, the high-temperature section needs to be kept at a constant temperature and carried out in an inert gas atmosphere to avoid oxidation of the silicon surface or the formation of compounds by the reaction of ions with impurities in the air, which would affect the activation effect.

[0053] Furthermore, the process of cooling from 1020-1050°C to 580-620°C is not a sudden drop, but rather a gradient cooling process. The core objective is to mitigate the thermal stress caused by abrupt temperature changes. If the temperature were rapidly reduced from 1020°C to a lower temperature, a temperature gradient would form between the device's surface and interior due to the difference in cooling rates. Specifically, the surface cools and shrinks quickly, while the interior cools and shrinks slowly. This uneven shrinkage would generate tensile or compressive stress within the crystal lattice. If the stress exceeds the fracture strength of silicon, it could lead to microcracks in the lattice or exacerbate the propagation of existing defects. By using a slow gradient cooling process, the destructive effect of thermal stress on the crystal structure is reduced from the source.

[0054] S4. Perform multiple ion implantations of the first doping type on the epitaxial layer through dose distribution to form a first avalanche region of the first doping type for avalanche; perform stepped cooling annealing on the ion implantation of the first avalanche region to obtain ion activation and defect repair. Multiple ion implantations of the first doping type are performed on the epitaxial layer by dose allocation to form a first avalanche region of the first doping type for avalanche formation, including: four phosphorus ion implantations, with a total dose of 1.8-2.2e12cm. -2 The energy of each ion implantation was 230-250 keV; the dose distribution of the four ion implantations was equal-dose split, meaning the dose of each ion implantation was 4.5-5.5e11cm. -2 Alternatively, the doses of the four ion implantations can be divided into gradient doses, with the single dose ratio increasing in an incremental relationship, wherein the single dose ratio is 1:1.5:2:2.5.

[0055] Referring to Figure 2(c), multiple ion implantations of the epitaxial layer of the first doping type are performed above the epitaxial layer (in the direction away from the substrate) to form a first avalanche region 205 of the first doping type for avalanche formation. The ion implantation examples for the first avalanche region are as follows: implantPhosphorusdose=2.0e12 cm -2 energy = 240 <kev> In this embodiment, the ion implantation step can be performed in four ion implantations, breaking down a single high-dose implantation into multiple medium- and low-dose implantations to reduce local damage. The ion implantation embodiment menu for the equal-dose splitting embodiment is as follows: implantPhosphorusdose=5.0e11 cm -2 energy = 240 <kev> implantPhosphorusdose=5.0e11 cm -2 energy= 240 <kev> implantPhosphorusdose=5.0e11 cm -2 energy= 240 <kev> implantPhosphorusdose=5.0e11 cm -2 energy= 240 <kev> Alternatively, the total dose can be divided into four gradient injections, with the ratio of the single ion implantation dose increasing, for example, a dose split of 1:1.5:2:2.5.

[0056] In other words, a single high-dose phosphorus ion injection (2.0e12cm) -2 The 240 keV injection was split into four low-to-medium dose injections (equal dose or gradient increase) to reduce local lattice damage.

[0057] Furthermore, during a single high-dose injection, a large number of phosphorus ions bombard the semiconductor lattice instantaneously, forming dense vacancy-interstitial atom pairs. These defects interact to form stable extended defects that are difficult to completely eliminate through subsequent annealing.

[0058] When implanted in four stages, the defect density generated by each implantation is lower, and the time interval between two adjacent implantations allows the lattice to have a short relaxation period. That is, some defects generated by the previous implantation will be initially repaired by thermal vibration or spontaneous lattice adjustment, reducing the probability of superposition with defects from the subsequent implantation.

[0059] Furthermore, the core performance of the first avalanche region 205 is to achieve uniform avalanche multiplication, which requires a highly uniform concentration distribution in the doped region. During a single high-dose implantation, the channeling effect of ions in the lattice is more significant, easily forming concentration spikes, while during four implantations, the ions implanted each time are randomly distributed in the lattice.

[0060] When using a dose splitting ratio of 1:1.5:2:2.5, although the injection energy is the same each time (240 keV), the higher dose injection step generates more ion scattering. The Coulomb repulsion between ions is enhanced at higher doses, resulting in a slightly shallower actual injection depth compared to lower doses. This stepwise injection from low to high doses naturally creates a gradient distribution of low concentration in the deep layer and slightly higher concentration at the surface. This gradient distribution optimizes the electric field distribution in the first avalanche region 205. In other words, the electric field is gentler in the deep, low-concentration region and has a larger electric field gradient in the slightly higher-concentration surface region. This ensures the strong electric field required for avalanche multiplication while reducing non-avalanche recombination of deep carriers, resulting in a higher-than-expected avalanche gain for the device, while simultaneously reducing the dark count rate.

[0061] After multiple ion implantations into the first avalanche region 205, a stepped cooling annealing process is performed on the implanted ions in the first avalanche region to achieve ion activation and defect repair. The principle is similar to the above embodiment and will not be repeated here. It should be noted that the stepped cooling annealing temperature for the first avalanche region is reduced from 1010-1020°C to 440-460°C.

[0062] S5. Pre-amorphization ion implantation is performed in the second avalanche region above the first avalanche region to form an amorphous layer. Multiple ion implantations of the second doping type are performed in the second avalanche region through dose distribution to form a second avalanche region of the second doping type for avalanche. Stepped cooling annealing is performed on the ion implantation of the second avalanche region to obtain ion activation and defect repair. The parameters for pre-amorphized ion implantation are: implanted Ge + Ions, Ge + The ion implantation dose was 0.8-1.2e14cm. -2 Ge + The ion implantation energy is 8-12 keV.

[0063] Optionally, multiple ion implantations of the second doping type are performed on the second avalanche region by dose allocation to form a second avalanche region of the second doping type, including: multiple ion implantations are four boron ion implantations, and the parameters of each boron ion implantation are: dose 2.0-3.0e14cm. -2 The energy was 5-7 keV; the total dose of the four boron ion implantations was 0.9-1.1e15cm. -2 .

[0064] Please refer to Figure 2(d). In the second avalanche region 206 above the first avalanche region 205, Ge pre-amorphization ion implantation is first performed to form an amorphous layer, and then equal-dose splitting ion implantation is performed.

[0065] It should be noted that Ge + Pre-amorphization ion implantation was performed using a dose of 1.0e14cm. -2 Parameters for 10 keV energy. Among them, the Ge parameters for 10 keV energy... + The implantation depth is relatively shallow, just covering the ion implantation depth range of the subsequent second avalanche region. This depth matching allows the amorphous layer to completely encapsulate the subsequent doped region without extending excessively into the substrate.

[0066] During the lattice reconstruction process after amorphization, the diffusion coefficient of P-type doped ions (such as boron) in the amorphous layer is more uniform than that in the single crystal, which can eliminate the local concentration fluctuations caused by the channel effect in traditional single crystal implantation.

[0067] 1.0e14cm -2 Ge + The dosage is low to medium, resulting in a moderate defect density in the amorphous layer formed after implantation. During subsequent annealing, Ge atoms create a small stress field, which can trap migrating vacancy defects and reduce the formation of defect clusters. + During annealing and recrystallization, the amorphous layer formed by implantation will develop an ordered lattice reconstruction path. When subsequent p-type ions (such as boron) are implanted, the boron atoms occupy more regularly in the amorphous layer and diffuse synchronously with the migration of Ge atoms during recrystallization.

[0068] 10keV low-energy injection enables Ge + The damage was mainly concentrated in the surface layer, and 1.0e14cm -2 The dosage will not cause excessive surface sputtering. During annealing, the reconstruction of the surface amorphous regions preferentially begins at the surface, forming a smooth lattice transition layer.

[0069] Furthermore, the single 1.0e15cm -2 10 keV boron ion implantation was split into four 2.0-3.0e14cm segments. -2 With an energy injection of 5-7 keV, the concentration fluctuations of the previous injection will be covered by the uniform distribution of the subsequent three injections, ultimately reducing the overall concentration deviation.

[0070] In addition, during avalanche operation, the sudden surge in local current caused by local high concentration in the second avalanche region is significantly suppressed, the breakdown voltage consistency of the device is improved, it can work stably under higher bias voltage, and the linearity of avalanche gain is improved.

[0071] Furthermore, a single high-dose injection generates dense defect clusters (such as boron-vacancy complexes), which are difficult to completely eliminate through annealing and become nonradiative recombination centers for charge carriers. When injected in four stages, the defect density generated each time decreases, and the defects are more spatially dispersed. The interaction between defects weakens during annealing, making them easier to eliminate by lattice reconstruction.

[0072] Furthermore, the dark count rate in the second avalanche region can be reduced, especially when operating at room temperature, which greatly expands the application scenarios of the device.

[0073] Furthermore, low-energy implantation at 6 keV primarily affects the surface layer, while a single high-dose implantation can cause pitting on the surface due to ion sputtering, affecting the reflectivity of incident light. When implanted in four stages, the sputtering damage is less severe each time, and the interval between adjacent implantations allows for slight migration of surface atoms, resulting in a decrease in surface roughness after annealing.

[0074] Moreover, the four-stage injection reduces the reflectivity of incident light and improves photon absorption efficiency, especially enhancing the detection sensitivity in the ultraviolet to blue light band, thus optimizing optical performance without the need for an additional anti-reflection coating.

[0075] It should be noted that after multiple ion implantations into the second avalanche region, a thermal diffusion annealing process is also required to prevent defect accumulation. The annealing temperature is reduced from 1010-1020°C to 440-460°C to reduce thermal stress. The high temperature is used for ion activation, and the low temperature is used for defect repair. The annealing principle for the second avalanche region is similar to that in the above embodiments and will not be repeated here.

[0076] S6. Perform atomic layer deposition above the second avalanche region to suppress interface state defects of the silicon photomultiplier tube through surface passivation.

[0077] An Al2O3 layer of 5-10 nm is deposited above the second avalanche region using atomic layer deposition (ALD). A SiNx layer of 70-90 nm is then formed on top of the Al2O3 layer using enhanced chemical vapor deposition (ECV). The negative fixed charge of the Al2O3 layer is activated by annealing at 440-460°C, which improves the field-effect passivation effect and achieves photon anti-reflection.

[0078] Referring to Figure 2(e), an Al2O3 layer 207 is deposited above the second avalanche region, preferably with a thickness of 5-10 nm. Then, an 80 nm SiNx layer 208 is formed on top of the Al2O3 layer via enhanced chemical vapor deposition. Traditional single-film SiNx or combinations of thin Al2O3 and thick SiNx often result in attenuation of transmittance in specific wavelength bands due to an imbalance between the refractive index and thickness of the film. However, the combination of 5-10 nm Al2O3 and 80 nm SiNx thicknesses precisely satisfies the phase compensation condition for two-film interference. That is, the 5-10 nm Al2O3 can cancel short-wavelength reflections from the silicon surface, while the 80 nm SiNx provides anti-reflection for medium and long wavelengths.

[0079] In addition, Al2O3 films prepared by atomic deposition are low-compressive-stress films, while 80nm SiNx films prepared by enhanced chemical vapor deposition are prone to high tensile stress if they are too thick. When the stress directions of the two films are opposite, the stress superposition can easily lead to film cracking or silicon substrate warping. If SiNx is too thin, it cannot form effective mechanical support and is easily damaged by subsequent processes (such as annealing). The compressive stress of 5-10nm Al2O3 and the tensile stress of 80nm SiNx can form a stress balance.

[0080] Furthermore, the fixed negative charge of Al2O3 requires annealing at 450°C for activation, but the stability of the fixed negative charge is directly related to the thickness of Al2O3: if Al2O3 is too thin, the negative charge density will easily decrease after annealing due to charge overflow; if it is too thick, the step coverage of the atomic deposition process will decrease, resulting in weak local passivation. In addition, the dense structure of 80nm SiNx can block the escape of external hydrogen atoms and suppress the migration of oxygen vacancies in the Al2O3 layer, thereby improving the field-effect passivation effect.

[0081] In summary, the embodiments of this application employ dose-stage implantation in both the photocathode and photoanode regions of the silicon photomultiplier tube, breaking down the single high-dose ion implantation of the prior art into multiple medium- and low-dose implantations to reduce local lattice damage; when forming the photoanode, the photoanode region is first subjected to Ge... + Pre-amorphization treatment is used to reduce the channeling effect of ion implantation and reduce the formation of defect clusters. An Al2O3 layer is formed by atomic layer deposition to cover the implantation area and sidewalls. The negative charge of Al2O3 is used to adjust the interface electric field to achieve interface passivation, thereby achieving low dark count characteristics with peak wavelength at blue-violet light wavelength, which meets the performance requirements of SiPM for specific application scenarios.

[0082] Please see Figure 3 This invention discloses a silicon photomultiplier tube, comprising: a substrate 201 of a first doping type (e.g., N-type), on which an epitaxial layer 202 of the same type (N-type) is deposited. This basic structure provides a stable platform for subsequent doping and the formation of functional regions. A well region 203 and a heavily doped ion region 204 (N++) are formed on the epitaxial layer by ion implantation. A first avalanche region 205 of the first doping type is disposed above the first doped epitaxial layer; an amorphous layer and a second avalanche region 206 are disposed above the first avalanche region 205; an Al2O3 layer 207 is disposed above the second avalanche region; and a SiNx layer 208 is disposed above the Al2O3 layer.

[0083] The trap region 203 and the heavily doped ion region 204 are formed by multiple ion implantations; the first avalanche region 205 is formed by multiple ion implantations; and the second avalanche region 206 is formed by multiple ion implantations.

[0084] Furthermore, the silicon photomultiplier tubes provided in the above embodiments can be used to assemble silicon photomultiplier tube chips. In existing SiPM chip processes, except for the windowed area on the top layer used for PAD (pad) interconnection, the thickness of the dielectric layer (such as insulating layers like SiO2 and SiNx) on the entire chip surface is completely consistent with the thickness of the metal layer. This design allows for the fabrication of the entire chip's layer structure through a single deposition and etching process, reducing the number of masks and process steps, and lowering manufacturing costs. However, the core functional unit of SiPM is the silicon photomultiplier tube array. Silicon photomultiplier tubes need to receive incident photons to excite charge carriers. If a metal layer exists above them, it will completely block the light, leading to device failure.

[0085] In traditional manufacturing processes, the thickness of the dielectric layer and the metal layer are the same throughout the chip (except for the top layer used for PAD interconnects and the PAD window interconnects). Because metal support is not allowed above the SPAD areas in SiPM, multiple thick dielectric layers will generate stress on the silicon wafer and reflect incident light. See details... Figure 4 .

[0086] Therefore, in the silicon photomultiplier tube chip provided in this application embodiment, after the deposition of the dielectric and metal layers of the entire chip is completed, the dielectric layer of all avalanche regions in the SiPM array is completely etched away using a dedicated mask and etching process, retaining only the dielectric layer structure of other functional areas of the chip (such as the driver circuit area and PAD interconnect area). See details for further information. Figure 5 This reduces stress and increases photon absorption efficiency. Figure 5 This application provides a schematic diagram of a silicon photomultiplier tube chip.

[0087] Moreover, after the dielectric layer in the avalanche region is completely removed, the incident light only needs to pass through a single air-silicon interface, reducing the reflectivity from 20%-30% in multilayer dielectric layers to 5%-8% (blue-violet light band). Taking blue-violet light with a peak wavelength of 450nm as an example, the light absorption efficiency in the avalanche region under conventional processes is about 70%, which can be increased to over 92% using the embodiments of this application. This means that more photons can excite charge carriers in the silicon wafer, directly improving the photon detection efficiency of SiPM.

[0088] In addition, some dielectric layers (such as SiNx) have a certain absorption of short-wavelength light (such as ultraviolet and deep blue light). Removing the dielectric layer can avoid this light loss, thereby improving the responsivity of SiPM in the blue-violet light band by 15%-25%, making it more suitable for the needs of blue-violet light communication and other scenarios.

[0089] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0090] Example 1 S1: Provides an N-type low-resistivity silicon substrate with a resistivity of 0.001Ω•cm, and forms an N-type epitaxial layer with a thickness of 3μm on the substrate surface through epitaxial growth technology.

[0091] S2: Perform multiple ion implantations of the epitaxial layer with the first doping type (N-type) to form a well region and a heavily doped ion region: Well region doped ion implantation: Phosphorus ions implanted (dose 1.2e13cm) -2 Energy 380 keV), phosphorus ions (dose 4.5e12cm) -2 Energy 130 keV), arsenic ions (dose 0.8e12cm) -2 (Energy 110 keV) Heavy doped ion implantation: Arsenic ions implanted (dose 6.0e15cm) -2 Energy 35 keV), phosphorus ions (dose 1.8e14cm) -2 (Energy 22 keV), and the heavy doped ion implantation is compatible with the source and drain ion implantation of silicon photomultiplier tubes.

[0092] S3: Step-cooling annealing is performed on the well region doped ion implantation, with an initial temperature of 1020°C and a final temperature of 580°C. The process of cooling from 1020°C to 580°C is called gradient cooling (cooling rate 5°C / min). The annealing atmosphere is nitrogen (inert gas) to achieve ion activation and defect repair.

[0093] S4: The first avalanche region was formed by multiple N-type ion implantations into the epitaxial layer through dose distribution, specifically through three phosphorus ion implantations with a total dose of 1.8e12cm. -2 Each ion implantation energy was 230 keV; the ion implantation in the first avalanche region was subjected to step-cooling annealing with an initial temperature of 1000°C and a final temperature of 430°C, with a gradient cooling rate of 5°C / min, to complete ion activation and defect repair.

[0094] S5: Pre-amorphization ion implantation is performed in the second avalanche region above the first avalanche region, with Ge⁺ ions implanted (dose 0.9e14cm). -2 An amorphous layer was formed by implanting boron ions of the second doping type (P-type) into the second avalanche region through three boron ion implantations with a total dose of 0.9e15cm at an energy of 9keV; the second avalanche region was formed by three boron ion implantations of the second doping type (P-type) through dose distribution. -2 The boron ion implantation dose per session is 3.0e14cm. -2 The energy was 5 keV; the ion implantation in the second avalanche region was subjected to step-cooling annealing with an initial temperature of 1000°C and a final temperature of 430°C, with a gradient cooling rate of 5°C / min, to achieve ion activation and defect repair.

[0095] S6: A 4nm Al2O3 layer is deposited above the second avalanche region by atomic layer deposition. A 75nm SiNx layer is formed above the Al2O3 layer by enhanced chemical vapor deposition. The negative fixed charge of the Al2O3 layer is activated by annealing at 430°C for 10 minutes to complete surface passivation and suppress interface state defects.

[0096] Using a dedicated mask and dry etching process, the dielectric layers (SiO2 layer and SiNx layer) of all avalanche regions in the silicon photomultiplier array are completely etched away, leaving only the dielectric layer structure of the chip driver circuit area and PAD interconnect area.

[0097] Results: The fabricated silicon photomultiplier tube achieved a photon detection efficiency of 60% in the blue-violet light band (wavelength 400nm); at 25°C, with a bias voltage 1V below the breakdown voltage, the dark count rate was 85Hz; and the avalanche gain stability fluctuation was 3% when the operating voltage fluctuated by ±0.5V.

[0098] Even using the lower limit of the parameter range, the basic performance requirements for blue-violet light detection scenarios can still be met. Low-dose, low-energy multiple ion implantations can reduce the impact of a single implantation on the silicon lattice, reducing the initial lattice damage density by more than 60% compared to traditional single high-dose implantation. Combined with low-rate gradient annealing, the lattice defect repair rate reaches 90%, effectively suppressing dark current generation and keeping the dark count rate at a low level. At the same time, the thin epitaxial layer and the simplified number of ion implantations reduce raw material consumption and process time, reducing the fabrication cost by 15% compared to the mid-to-upper limit parameter scheme, making it suitable for low-cost mass production scenarios.

[0099] Example 2 S1: Provides an N-type low-resistivity silicon substrate with a resistivity of 0.005 Ω•cm and an epitaxial layer thickness of 6 μm, formed on the substrate surface by epitaxial growth technology.

[0100] S2: Well region doped ion implantation: Phosphorus ions implanted (dose 1.5e13cm) -2 Energy 400 keV), phosphorus ions (dose 5.0 e12 cm⁻¹) -2 Energy 140 keV), arsenic ions (dose 1.0e12cm) -2 Energy 120 keV); Heavy doped ion implantation: Arsenic ions implanted (dose 6.5e15cm). -2 Energy 40 keV), phosphorus ions (dose 2.0 e14 cm⁻¹) -2 (Energy 25 keV), heavy doped ion implantation and source / drain ion implantation adaptation.

[0101] S3: Stepped cooling annealing with an initial temperature of 1030°C and a final temperature of 600°C, a gradient cooling rate of 10°C / min, and an annealing atmosphere of argon.

[0102] S4: The first avalanche region consists of 4 phosphorus ion implantations (equal dose split, each dose 5.0e11cm). -2 Energy 240 keV), total dose 2.0 e12 cm⁻¹ -2 The initial annealing temperature was 1015°C, the final temperature was 450°C, and the gradient cooling rate was 8°C / min.

[0103] S5: Pre-amorphization implanted Ge + Ions (dose 1.0e14cm) -2 (Energy 10 keV); the second avalanche region consisted of four boron ion implantations (each dose 2.5e14cm). -2 Energy 6 keV), total dose 1.0 e15 cm⁻¹ -2 Annealing parameters are the same as S4.

[0104] S6: A 7nm Al2O3 layer was deposited by atomic layer deposition, followed by an 80nm SiNx layer by enhanced chemical vapor deposition, and then annealed at 450°C for 20 min to activate the negative fixed charge of the Al2O3 layer.

[0105] Wet etching is used to remove the dielectric layer in the avalanche region, while retaining the dielectric layers in the drive circuit region and PAD interconnect region.

[0106] Results: Photon detection efficiency in the blue-violet band (wavelength 450nm) was 72%; dark count rate was 60Hz when the bias voltage was 1V below the breakdown voltage at 25°C; avalanche gain stability fluctuated by 2% when the operating voltage fluctuated by ±0.5V.

[0107] The median parameters achieve an optimal balance between performance and cost. Four equal-dose ion implantations result in a 95% uniformity of doping concentration distribution, avoiding electric field anomalies caused by excessively high or low local doping levels, and improving avalanche gain uniformity by 8% compared to Example 1. Matching the Al2O3 and SiNx film thicknesses to the optical properties of the blue-violet light band reduces the reflectivity of 450nm blue-violet light to below 5%, significantly improving photon absorption efficiency. Annealing at 450°C for 20 min increases the activation rate of the negative fixed charge in the Al2O3 layer to 98%, and reduces the interface state defect density to 10. 11 cm -2 •eV -1 The following steps further suppress dark current while maintaining moderate process complexity, making it suitable for mass production.

[0108] Example 3 S1: The resistivity of the N-type low-resistivity silicon substrate is 0.006 Ω•cm, and the epitaxial layer thickness is 7 μm, which is formed by epitaxial growth technology.

[0109] S2: Trap region doped ion implantation: Phosphorus ions implanted (dose 1.6e13cm) -2 Energy 410 keV), phosphorus ions (dose 5.2e12cm) -2 Energy 145 keV), arsenic ions (dose 1.1e12cm) -2 Energy 125 keV); Heavy doped ion implantation: Arsenic ions implanted (dose 6.6e15cm). -2 Energy 42 keV), phosphorus ions (dose 1.9e14 cm⁻¹) -2 (Energy 26 keV), compatible with source and drain ion implantation.

[0110] S3: Stepped cooling annealing with an initial temperature of 1035°C and a final temperature of 610°C, a gradient cooling rate of 12°C / min, and nitrogen atmosphere.

[0111] S4: The first avalanche region consists of four phosphorus ion implantations (gradient dose split, ratio 1:1.5:2:2.5, total dose 2.1e12cm). -2 The energy per annealing step was 245 keV; the initial annealing temperature was 1020°C, the final temperature was 460°C, and the gradient cooling rate was 10°C / min.

[0112] S5: Pre-amorphization implanted Ge + Ions (dose 1.05e14cm) -2 The energy was 10.5 keV; the second avalanche region consisted of four boron ion implantations (each dose 2.6e14cm). -2 Energy 6.5 keV), total dose 1.04e15cm -2 Annealing parameters are the same as S4.

[0113] S6: An 8nm Al2O3 layer was deposited by atomic layer deposition, followed by an 82nm SiNx layer by enhanced chemical vapor deposition, and then annealed at 460°C for 25 min to activate the negative fixed charge of the Al2O3 layer.

[0114] Dry etching removes the dielectric layer in the avalanche region, while retaining the dielectric layers in the drive circuit region and PAD interconnect region.

[0115] Results: Photon detection efficiency of 75% in the blue-violet band (wavelength 460nm); dark count rate of 52Hz when the bias voltage is 1V below the breakdown voltage at 25°C; avalanche gain stability fluctuation of 1.8% when the operating voltage fluctuates by ±0.5V.

[0116] Gradient-dose ion implantation creates a doping distribution of "low concentration in the deep layer and slightly higher concentration on the surface," making the electric field gradient in the first avalanche region more consistent with the avalanche multiplication requirements, improving carrier multiplication efficiency by 10%, and resulting in photon detection efficiency superior to Example 2; Ge + Fine-tuning of ion implantation dose and energy further weakens the ion implantation channel effect, with dopant ion distribution deviation less than 3% and the number of defect clusters reduced to 1 / 5 of the traditional process; 460°C annealing for 25 min enhances the interface passivation effect, reduces carrier recombination rate by 15%, and has better dark count rate and gain stability, making it suitable for biofluorescence detection scenarios with high detection accuracy requirements.

[0117] Example 4 S1: Provides an N-type low-resistivity silicon substrate (resistivity referenced to the conventional median value of 0.005Ω•cm), and forms an N-type epitaxial layer with a thickness of 6μm on the substrate surface through epitaxial growth technology.

[0118] S2: Multiple N-type ion implantations are performed on the epitaxial layer through dose distribution to form well regions and heavily doped ion regions. Trap region doped ion implantation: Phosphorus ions implanted (dose 1.5e13cm) -2 Energy 400 keV), phosphorus ions (dose 5.0 e12 cm⁻¹) -2 Energy 140 keV), arsenic ions (dose 1.0e12cm) -2 (Energy 120 keV) Heavy doped ion implantation: Arsenic ions implanted (dose 6.5e15cm) -2 Energy 40 keV), phosphorus ions (dose 2.0 e14 cm⁻¹) -2 (Energy 25 keV), and the heavy doped ion implantation is compatible with the source and drain ion implantation of silicon photomultiplier tubes.

[0119] S3: Stepwise cooling annealing is performed on the well region doped ion implantation, with the temperature ranging from 1035°C to 600°C. The process of cooling from 1035°C to 600°C is called gradient cooling (cooling rate 10°C / min). The annealing atmosphere is argon (inert gas), which realizes ion activation and defect repair.

[0120] S4: The first avalanche region was formed by multiple N-type ion implantations into the epitaxial layer through dose distribution, specifically four phosphorus ion implantations, with a total dose of 2.0e12cm. -2 Each ion implantation energy was 240 keV, and the dose distribution was equal-dose split (each ion implantation dose was 5.0 e11 cm⁻¹). -2 Ion implantation in the first avalanche region was subjected to step-cooling annealing at a temperature of 1015°C to 450°C at a gradient cooling rate of 8°C / min, thereby completing ion activation and defect repair.

[0121] S5: Pre-amorphized ion implantation is performed in the second avalanche region above the first avalanche region, injecting Ge. + Ions (dose 1.0e14cm) -2 An amorphous layer was formed by performing multiple P-type ion implantations into the second avalanche region using an energy of 10 keV; specifically, four boron ion implantations were performed, each with a boron ion implantation dose of 2.50 e14 cm⁻¹. -2 Energy 6 keV, 4 boron ion implantations, total dose 1.0 e15 cm⁻¹ -2 The ion implantation in the second avalanche region was subjected to step-cooling annealing, with the temperature ranging from 1015°C to 450°C and the gradient cooling rate being 8°C / min, to achieve ion activation and defect repair.

[0122] S6: A 7nm Al2O3 layer (in the midpoint of the 5-10nm range) is deposited above the second avalanche region by atomic layer deposition. An 80nm SiNx layer is formed above the Al2O3 layer by enhanced chemical vapor deposition. The negative fixed charge of the Al2O3 layer is activated by annealing at 450°C to complete surface passivation and suppress interface state defects.

[0123] Using a dedicated mask and dry etching process, the dielectric layers (SiO2 layer and SiNx layer) of all avalanche regions in the silicon photomultiplier array are completely etched away, leaving only the dielectric layer structure of the chip driver circuit area and PAD interconnect area.

[0124] Results: The fabricated silicon photomultiplier tube achieved a photon detection efficiency of 70% in the blue-violet light band (wavelength 450nm); at 25°C, with a bias voltage 1V below the breakdown voltage, the dark count rate was 55Hz; and the avalanche gain stability fluctuation was 2% when the operating voltage fluctuated by ±0.5V.

[0125] The specified parameters were precisely matched, and the synergy of each process step was optimal. The combination of multiple ion implantations and stepped annealing resulted in a lattice damage repair rate of 95% and a low dark count rate, meeting the requirements of most blue-violet light detection scenarios. The pre-amorphization treatment effectively eliminated the ion implantation channeling effect, and the uniformity of doped ion distribution reached 96%, avoiding gain fluctuations caused by local electric field anomalies. The Al2O3 and SiNx composite passivation layer not only achieved efficient interface passivation but also reduced blue-violet light reflectivity through optical matching, achieving a balance between photon absorption efficiency and device stability, which can be widely used in mainstream scenarios such as water quality monitoring and biofluorescence detection.

[0126] Example 5 S1: Provides an N-type low-resistivity silicon substrate with a resistivity of 0.01Ω•cm, and forms an N-type epitaxial layer with a thickness of 10μm on the substrate surface through epitaxial growth technology.

[0127] S2: Well region doped ion implantation: Phosphorus ions implanted (dose 1.8e13cm) -2 Energy 420 keV), phosphorus ions (dose 5.5e12cm) -2 Energy 150 keV), arsenic ions (dose 1.2e12cm) -2 Energy 130 keV); Heavy doped ion implantation: Arsenic ions implanted (dose 7.0e15cm). -2 Energy 45 keV), phosphorus ions (dose 2.2e14cm) -2 (Energy 28 keV), compatible with source and drain ion implantation.

[0128] S3: Stepped cooling annealing with an initial temperature of 1050°C and a final temperature of 620°C, a gradient cooling rate of 15°C / min, and an annealing atmosphere of argon.

[0129] S4: The first avalanche region consists of 5 phosphorus ion implantations (gradient dose splitting, ratio 1:1.5:2:2.5:3, total dose 2.2e12cm). -2 The energy was 250 keV per annealing cycle; the initial annealing temperature was 1030°C, the final temperature was 470°C, and the gradient cooling rate was 12°C / min.

[0130] S5: Pre-amorphization implanted Ge + Ions (dose 1.1e14cm) -2 (Energy 11 keV); the second avalanche region consisted of 5 boron ion implantations (each dose 2.2e14cm). -2 Energy 7 keV), total dose 1.1e15cm -2 Annealing parameters are the same as S4.

[0131] S6: An 11 nm Al2O3 layer was deposited by atomic layer deposition, followed by an 85 nm SiNx layer by enhanced chemical vapor deposition, and then annealed at 470°C for 30 min to activate the negative fixed charge of the Al2O3 layer.

[0132] Dry etching removes the dielectric layer in the avalanche region, while retaining the dielectric layers in the drive circuit region and PAD interconnect region.

[0133] Results: Photon detection efficiency of 80% in the blue-violet band (wavelength 500nm); dark count rate of 40Hz when the bias voltage is 1V below the breakdown voltage at 25°C; avalanche gain stability fluctuation of 1.5% when the operating voltage fluctuates by ±0.5V.

[0134] The upper limit parameters enable the device to achieve optimal performance. A 10μm thick epitaxial layer provides ample space for carrier transport, reducing recombination by 20% during transport. High-energy, high-dose multiple ion implantations combined with gradient dose splitting create a more precise doping concentration gradient, improving the electric field utilization in the avalanche region by 20% and significantly enhancing photon detection efficiency. High-temperature annealing at 1030°C and a 30-minute long-term treatment almost completely repair lattice defects, reducing the defect density to 10-1. 8 cm -2 Below, the dark count rate reaches an extremely low level; the 11nm thick Al2O3 layer and the 85nm thick SiNx layer enhance the passivation effect and the mechanical stability of the film, which can meet the requirements of high-performance scenarios such as quantum communication and high-precision nuclear radiation detection.

[0135] Comparative Example Substrate and epitaxial layer: Same as in Example 4 (N-type low-resistivity silicon substrate, resistivity 0.005Ω•cm, epitaxial layer thickness 6μm).

[0136] Ion implantation: Employs a traditional single-dose high-dose implantation method, without multiple dose distributions. Trap zone: Single injection of phosphorus ions (dose 3.0e13cm) -2 (Energy 400 keV) First avalanche zone: Single injection of phosphorus ions (dose 2.0e12cm) -2 (Energy 240 keV) Second avalanche zone: No pre-amorphization ion implantation was performed; boron ions were implanted in a single dose (1.0e15cm). -2 (Energy 6 keV).

[0137] Annealing: Traditional single-pass constant-temperature annealing is adopted, with a temperature of 1000°C and a holding time of 30 minutes. The temperature is gradually reduced without stepwise cooling, and the annealing atmosphere is air.

[0138] Passivation and etching: Only an 80nm SiNx layer was formed as a passivation layer by enhanced chemical vapor deposition, and no Al2O3 layer was deposited; the dielectric layer in the avalanche region was not etched, and the entire chip dielectric layer structure was preserved.

[0139] Results: Photon detection efficiency of 45% in the blue-violet band (wavelength 450nm); dark count rate of 350Hz when the bias voltage is 1V below the breakdown voltage at 25°C; avalanche gain stability fluctuation of 12% when the operating voltage fluctuates by ±0.5V.

[0140] Photon detection efficiency: The comparative example has an efficiency of only 45%, far lower than that of the embodiments of this invention (60%-80%). The core reason is that the traditional process lacks an Al2O3 / SiNx composite passivation layer and does not etch the avalanche region dielectric layer. The reflectivity of blue-violet light on the dielectric layer surface is over 30%, and a large number of photons are not absorbed by the silicon substrate. In contrast, this invention reduces the reflectivity to 5%-8% through optical matching of the composite film layer and etching of the avalanche region dielectric layer, thus significantly improving the photon absorption efficiency.

[0141] Dark count rate: The comparative example at 350Hz is 4-8 times that of the embodiments of the present invention (40-85Hz). Conventional single high-dose ion implantation leads to dense defects in the silicon lattice (defect density up to 10^6). 10 cm -2 Furthermore, a single isothermal annealing process cannot completely repair these defects, which then become carrier generation centers, leading to a surge in dark current. This invention reduces initial damage through multiple low-dose injections, combined with stepped cooling annealing for efficient defect repair, reducing the defect density to 10. 8 cm -2 The dark count rate then drops significantly.

[0142] Avalanche gain stability: The comparative method exhibits a fluctuation of 12%, far exceeding that of this invention (1.5%-3%). Traditional processes do not perform pre-amorphization treatment, resulting in significant channeling effects during ion implantation and uneven distribution of doped ions (deviation up to 15%), leading to large fluctuations in the electric field in the avalanche region. This invention suppresses channeling effects through pre-amorphization and optimizes the electric field distribution through gradient doping, improving doping uniformity to over 95% and significantly enhancing gain stability.

[0143] In summary, the silicon photomultiplier tube and its fabrication method of this invention, through staged ion implantation instead of traditional high-dose single implantation, can effectively suppress lattice amorphization. Combined with subsequent processing, it can significantly reduce the lattice dislocation density (below 10⁻⁶ of the traditional process). 9 cm -2 This further reduces the device's dark count rate (DCR) to an even lower level (below 1000 cps / mm). 2 This meets the core performance requirements of low-noise optoelectronic devices. Furthermore, through interface passivation, the Ge / Si interface state density can be significantly reduced (below the traditional 10-1). 12 cm -2 •eV -1 This reduces carrier recombination rate, thereby suppressing dark current increase and lowering the dark current increase from the traditional 30% to a lower level, improving the electrical stability and detection accuracy of the device. Combined with Ge pre-amorphization, and synergistic hierarchical ion implantation and interface passivation, it can precisely control the defect density of ultra-shallow avalanche junctions, especially suitable for the structural requirements of silicon photomultiplier devices in the blue-violet light band. It effectively optimizes the device's dark counting characteristics, providing technical support for the manufacture of low-defect-density, low-noise silicon photomultiplier tube image sensors and other optoelectronic devices.

[0144] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.< / kev> < / kev> < / kev> < / kev> < / kev> < / kev> < / kev> < / kev> < / kev> < / kev>

Claims

1. A method of preparing a silicon photomultiplier, characterized by, The method comprises the following steps: S1, providing a first doped type substrate with a specific doping concentration, the substrate comprising an epitaxial layer; S2, performing multiple ion implantations of a first doped type on the epitaxial layer by dose distribution to form a well region doping ion implantation of a first doped type region for cathode contact hole contact and a heavy doping ion implantation of the first doped type region; S3, performing ladder cooling annealing on the well region doping ion implantation to obtain ion activation and defect repair; S4, performing multiple ion implantations of a first doped type on the epitaxial layer by dose distribution to form a first avalanche region of a first doped type for avalanche; Performing ladder cooling annealing on the ion implantation of the first avalanche region to obtain ion activation and defect repair; S5, performing a pre-amorphous ion implantation on a second avalanche region above the first avalanche region to form an amorphous layer, and performing multiple ion implantations of a second doped type on the second avalanche region by dose distribution to form a second avalanche region of a second doped type for avalanche; Performing ladder cooling annealing on the ion implantation of the second avalanche region to obtain ion activation and defect repair; S6, performing atomic layer deposition above the second avalanche region to inhibit interface state defects of the silicon photomultiplier through surface passivation of the silicon photomultiplier.

2. The method for fabricating a silicon photomultiplier tube according to claim 1, characterized in that, In step S1, the first doped type substrate is composed of N-type low resistance silicon, and the epitaxial layer is formed on the surface of the substrate by epitaxial growth technology.

3. The method of claim 1, wherein the silicon photomultiplier is prepared by the steps of: In step S2, the multiple ion implantations of a first doped type on the epitaxial layer by dose distribution to form a well region doping ion implantation of a first doped type region for cathode contact hole contact specifically comprises: ​ Phosphorus ions were implanted at a dose of 1-2 e13 cm -2 and an energy of 380-420 KeV. Phosphorus ions were implanted at a dose of 4-6 e12 cm -2 and an energy of 130-150 KeV. Arsenic ions were implanted at a dose of 0.8-1.2 e12 cm -2 at an energy of 110-130 KeV. The multiple ion implantations of a first doped type on the epitaxial layer by dose distribution to form a heavy doping ion implantation of a first doped type region specifically comprises: Arsenic ions were implanted at a dose of 6-7e15 cm -2 at an energy of 38-42 KeV; Phosphorus ions were implanted at a dose of 1.8-2.2 e14 cm -2 and an energy of 23-27 KeV. The heavy doping ion implantation is adapted to the ion implantation of the source and drain of the silicon photomultiplier.

4. The method of claim 1, wherein the silicon photomultiplier is prepared by the steps of: In step S3, the temperature of the ladder cooling annealing is 1020-1050°C to 580-620°C, the ladder cooling annealing is performed in an inert gas atmosphere, and is gradient cooling. ​ 5. The method of claim 1, wherein the silicon photomultiplier is prepared by the steps of: In step S4, the multiple ion implantations of a first doped type on the epitaxial layer by dose distribution to form a first avalanche region of a first doped type for avalanche specifically comprises: ​ The multiple ion implantations are 4 times of phosphorus ion implantation, and the total dosage of the 4 times of ion implantation is 1.8-2.2e12cm -2 The energy of each time of ion implantation is 230-250KeV; and the dosage distribution of the 4 times of ion implantation is equal dosage split, that is, the dosage of each time of ion implantation is 4.5-5.5e11cm -2 Or the dosage of the 4 times of ion implantation is gradient dosage split, and the single dosage ratio is in an increasing relationship, and the single dosage ratio is 1:1.5:2:2.5; The temperature of the ladder cooling annealing on the ion implantation of the first avalanche region is 1010-1020°C to 440-460°C.

6. The method of claim 1, wherein the silicon photomultiplier is prepared by the steps of: In step S5, the parameters of the pre-amorphous ion implantation are: ​ Implantation of Ge + ions, Ge + Ion implantation dose is 0.8-1.2e14cm -2 , Ge + Ion implantation energy is 8-12KeV.

7. The method of claim 1, wherein the silicon photomultiplier is prepared by the steps of: In step S5, the multiple ion implantations of a second doped type on the second avalanche region by dose distribution to form a second avalanche region of a second doped type for avalanche specifically comprises: ​ The multiple ion implantations are 4 boron ion implantations, each boron ion implantation has parameters of: dose 2.0-3.0e14 cm -2 -2, energy 5-7 KeV; the total dose of 4 boron ion implantations is 0.9-1.1e15 cm -2 -2. The temperature of the ladder cooling annealing on the ion implantation of the second avalanche region is 1010-1020°C to 440-460°C.

8. The method of claim 1, wherein the silicon photomultiplier is prepared by the steps of: In step S6, a 5-10 nm Al2O3 layer is deposited above the second avalanche region by atomic layer deposition, a 70-90 nm SiNx layer is formed above the Al2O3 layer by enhanced chemical vapor deposition, and a negative fixed charge of the Al2O3 layer is activated by an annealing treatment at 440-460°C. ​ 9. The method of claim 1, wherein the silicon photomultiplier is prepared by the steps of: After step S6 is completed, the dielectric layer of all avalanche regions in the silicon photomultiplier array is completely etched and removed by a special mask and etching process, and only the dielectric layer structure of other functional regions of the chip is reserved, including the driving circuit region and the PAD interconnection. ​ 10. A silicon photomultiplier, characterized by The silicon photomultiplier is prepared by the preparation method in any one of claims 1-9, and the silicon photomultiplier comprises a first-doped-type substrate, and a same-type epitaxial layer is covered on the substrate; a well region and a heavily doped ion region are formed on the epitaxial layer by ion implantation; A first-doped-type first avalanche region is arranged above the epitaxial layer, an amorphous layer and a second-doped-type second avalanche region are arranged above the first avalanche region, an Al2O3 layer is arranged above the second avalanche region, and a SiNx layer is arranged above the Al2O3 layer; wherein the well region and the heavily doped ion region are formed by multiple ion implantations, the first avalanche region is formed by multiple ion implantations, and the second avalanche region is formed by multiple ion implantations.

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