Server intelligent integrated hierarchical storage system and method based on U.2 interface

Abstract

The invention discloses a U.2 interface-based server intelligent integrated hierarchical storage system and method, relates to the technical field of computer server storage, and is used for solving the problem of optimization of multi-type SSD data access efficiency and storage resource utilization rate. Firstly, a multi-protocol parallel channel is established by redefining U.2 interface reserved pins, signal integrity parameters are monitored in real time and fused with equipment I / O access features, and an I / O feature sequence of physical layer state information is generated; then, based on a time sequence convolutional neural network, extracting access mode multi-scale features, calculating a data block access heat probability, mapping and determining a target storage hierarchy, and generating a scheduling instruction containing a source physical address, the target hierarchy and a migration priority; the migration execution module realizes zero-copy migration of the data block between the shared DRAM pool and the SSD according to the instruction; and the resource coordination module monitors system load in real time, dynamically adjusts migration concurrency and an I / O sampling strategy, and realizes self-adaptive optimization of storage performance and resource utilization.

Description

Technical Field

[0001] This invention relates to the field of computer server storage technology, specifically to a server intelligent integrated hierarchical storage system and method based on the U.2 interface. Background Technology

[0002] With the rapid development of applications such as cloud computing, big data, and artificial intelligence, servers in enterprise data centers and high-performance computing environments undertake the tasks of massive data storage and high-speed processing. Faced with diverse business needs, it is necessary to meet the high-performance requirements of mission-critical tasks while also ensuring cost-effective storage of large volumes of data. To this end, tiered storage systems have gradually become the mainstream solution, achieving a balance between performance and cost by grading and migrating data between different types of storage media. However, with the diversification of SSD interface protocols and the increasing complexity of application access patterns, traditional storage architectures face challenges in terms of resource utilization and intelligent data scheduling.

[0003] Existing tiered storage methods have some substantial drawbacks in practical applications: On the one hand, different interfaces and protocols often rely on independent controllers and channels, leading to fragmented hardware resources. The system requires additional bridging devices to support multiple protocols in parallel, resulting in architectural redundancy and increased energy consumption. On the other hand, traditional data heat identification mainly relies on historical access statistics of the file system or logical layer, which is difficult to reflect the dynamic changes in the underlying physical link status and I / O characteristics. This can easily lead to delayed or even erroneous hot data identification, resulting in inaccurate migration decisions. In addition, existing migration scheduling is usually executed with fixed task concurrency and data block granularity, which cannot be adjusted in real time according to system load. As a result, it is easy to aggravate link congestion and reduce overall throughput in high-load scenarios, while causing resource idleness in low-load scenarios, which seriously affects the operating efficiency and reliability of the tiered storage system. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a server-integrated intelligent hierarchical storage system and method based on the U.2 interface, which solves the problems mentioned in the background.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a server intelligent integrated hierarchical storage system based on a U.2 interface, comprising the following modules: a state awareness module, used to establish a multi-protocol parallel channel by redefining the reserved pins of the U.2 interface, monitor the signal integrity parameters of each channel in real time, fuse the signal integrity parameters with device I / O access characteristics, and generate an I / O feature sequence of physical layer state information; a heat prediction module, used to receive the I / O feature sequence of physical layer state information, extract multi-scale features of access patterns through a temporal convolutional neural network, calculate the access heat probability of each data block, and determine the target storage level of each data block based on the high and low access heat probabilities, thereby generating a system containing the source physical address, The system includes a data migration scheduling instruction with target level identifier and migration priority; a migration execution module, which receives the data migration scheduling instruction, reads data blocks from the corresponding SSD flash memory according to the source physical address in the instruction, allocates an isolation buffer of the corresponding level in the shared DRAM pool according to the migration priority in the instruction, writes the data blocks to the corresponding SSD flash memory according to the target level identifier in the instruction, and realizes zero-copy migration of data blocks through the DMA engine; and a resource coordination module, which monitors the PCIe link utilization and SSD controller queue depth of the migration execution module in real time, dynamically adjusts the concurrency and data block granularity of the migration task according to the system load threshold and migration priority, and feeds back to the status awareness module to adjust the sampling frequency and feature dimension of the I / O feature sequence.

[0006] Furthermore, the specific process of establishing a multi-protocol parallel channel by redefining the reserved pins of the U.2 interface is as follows: Identify the reserved signal pin groups in the U.2 interface that are preset for the SAS protocol, redefine the first group of SAS signal pins as PCIe x1 links to establish an independent data transmission channel with the M.2 NVMe SSD, redefine the second group of SAS signal pins as SATA x1 links to establish an independent data transmission channel with the M.2 SATA SSD, and retain the native PCIe x4 link in the U.2 interface as a high-speed data channel with the U.2 NVMe SSD; configure independent device presence detection signals for each redefined link, and identify the insertion status of each SSD by combining the level states of the detection pins.

[0007] Furthermore, the specific process of real-time monitoring of signal integrity parameters of each channel and fusing these parameters with device I / O access characteristics to generate a physical layer status information I / O feature sequence is as follows: The signal quality monitoring unit built into the interface controller periodically collects signal integrity parameters of each data channel, including bit error rate, timing jitter amplitude, and eye diagram opening. A mapping model from signal integrity parameters to link health is established, converting the original signal parameters into a standardized link quality score. I / O requests passing through each channel are captured in parallel, extracting logical block addresses, operation types, data sizes, and timestamp information from the requests. The link quality score is then timestamped and features are concatenated with real-time I / O features to form a hybrid feature vector. The hybrid feature vector is then serialized and normalized using a sliding time window to generate a physical layer status information I / O feature sequence.

[0008] Furthermore, the specific process for calculating the access heat probability of each data block by extracting multi-scale features of access patterns from the I / O feature sequence that receives physical layer state information and using a temporal convolutional neural network is as follows: The input I / O feature sequence undergoes time-dimensional standardization preprocessing; access pattern features at different time scales are extracted using a temporal convolutional neural network with causal dilated convolutions; a multi-head self-attention mechanism is introduced at each layer of the convolutional network to adaptively assign weights to key time steps and feature channels in the feature maps; cross-layer connections and feature fusion are performed on feature maps from different layers; the fused high-dimensional features are mapped to the access heat probability value of each data block in the current time window through a fully connected layer; and the heat probability sequence is exponentially weighted and smoothed based on a sliding time window mechanism to reduce the impact of instantaneous fluctuations on prediction stability.

[0009] Furthermore, the specific process of determining the target storage level for each data block based on the access popularity probability, thereby generating a data migration scheduling instruction containing the source physical address, target level identifier, and migration priority, is as follows: A dynamically adjusted popularity probability interval division mechanism is established to map the access popularity probability of data blocks to the corresponding storage level. The high popularity interval corresponds to U.2 NVMe SSD, the medium popularity interval to M.2 NVMe SSD, and the low popularity interval to M.2 SATA SSD. The remaining capacity distribution of each storage level is monitored in real time. When the remaining capacity of the target level is lower than a set threshold, the boundary value of the popularity probability interval is dynamically adjusted, and some data blocks are reallocated to the available space of adjacent levels. Based on the determined target storage level, a structured migration scheduling instruction is constructed. This instruction includes the source physical address of the data block, the target level identifier, and the migration priority based on the popularity probability change rate and data block size. The generated scheduling instruction undergoes resource availability verification to ensure that the target level has sufficient receiving capacity and performance margin. Simultaneously, conflict detection is performed on the ongoing migration tasks to avoid address overlap and resource contention.

[0010] Furthermore, the migration execution module includes the following steps: Dividing the shared DRAM pool into isolated buffers with different access permissions according to migration priorities, where high-priority migration tasks are allocated exclusive buffers and low-priority migration tasks use shared buffers; establishing a direct read channel from the source SSD flash memory to the shared DRAM pool buffer using the DMA engine, transferring data blocks from the source SSD flash memory to the allocated isolated buffer; after data transfer is complete, establishing a direct write channel from the shared DRAM pool buffer to the target SSD flash memory using the DMA engine, writing data blocks from the buffer to the specified physical address of the target SSD; during data transfer, performing real-time verification of the transmitted data using a cyclic redundancy check mechanism, generating a checksum during the source SSD read phase and verifying the checksum during the target SSD write phase.

[0011] Furthermore, the specific process of dynamically adjusting the concurrency and data block granularity of migration tasks based on system load thresholds and migration priorities by real-time monitoring of PCIe link utilization and SSD controller queue depth of the migration execution module is as follows: The bandwidth utilization of each PCIe link and the command queue depth of each SSD controller are collected in real time using performance counters to calculate the current comprehensive load index of the system; a load evaluation function based on a sliding window is established to smooth and predict the trend of the collected load data; when the system load exceeds the threshold, migration tasks are scheduled in stages according to migration priorities to reduce the number of concurrent executions of low-priority migration tasks and decrease the data block granularity to reduce the impact of a single migration on system performance.

[0012] Furthermore, the specific process for adjusting the sampling frequency and feature dimensions of the I / O feature sequence is as follows: Establish a mapping relationship between system load status and sampling parameters; dynamically adjust the sampling frequency of the I / O feature sequence according to the load level, reducing the sampling frequency under high load and increasing the sampling frequency under low load; configure the feature dimension combination of the I / O feature sequence based on system load characteristics, retaining the core feature dimensions under high load and enabling extended feature dimensions under low load, and sending the configuration parameters to the status awareness module in real time.

[0013] A server-based intelligent integrated hierarchical storage method based on the U.2 interface includes the following steps: S1. Establishing a multi-protocol parallel channel by redefining the reserved pins of the U.2 interface, monitoring the signal integrity parameters of each channel in real time, fusing the signal integrity parameters with device I / O access characteristics, and generating an I / O feature sequence of physical layer status information; S2. Receiving the I / O feature sequence of physical layer status information, extracting multi-scale features of access patterns through a temporal convolutional neural network, calculating the access heat probability of each data block, and determining the target storage level of each data block based on the high and low access heat probabilities, thereby generating a storage layer containing the source physical address, target level identifier, and migration priority. S3. Receive the data migration scheduling instruction, read the data block from the corresponding SSD flash memory according to the source physical address in the instruction, allocate the corresponding level of isolation buffer in the shared DRAM pool according to the migration priority in the instruction, write the data block to the corresponding SSD flash memory according to the target level identifier in the instruction, and realize zero-copy migration of data blocks through the DMA engine; S4. Monitor the PCIe link utilization and SSD controller queue depth of the migration execution module in real time, dynamically adjust the concurrency and data block granularity of the migration task according to the system load threshold and migration priority, and feed back to the status awareness module to adjust the sampling frequency and feature dimension of the I / O feature sequence.

[0014] The present invention has the following beneficial effects:

[0015] (1) A server intelligent integrated hierarchical storage system based on the U.2 interface redefines the reserved pins of the U.2 interface through the status awareness module, breaking through the mutual exclusion limitation of the existing U.2 interface in multi-protocol support, realizing the concurrent access and identification of multiple SSDs with different protocols on a single physical port, effectively improving the server storage density and economy. At the same time, combined with the I / O feature sequence generated by real-time signal integrity parameters and device I / O access characteristics, the heat prediction module uses a temporal convolutional neural network to perform multi-scale feature extraction, which can more accurately predict the data access heat and automatically complete the mapping of data blocks to target storage levels, avoiding the resource waste caused by traditional hierarchical storage relying on fixed rules or manual strategies, thereby reducing the total cost of ownership while ensuring access performance.

[0016] (2) A server-integrated intelligent tiered storage method based on the U.2 interface achieves zero-copy migration of data blocks through a shared DRAM pool and DMA engine, avoiding the occupation of host CPU and memory resources by traditional software scheduling-based migration methods, reducing migration latency and system overhead, and ensuring rapid data transfer between different tiers of storage devices. At the same time, it senses the PCIe link utilization and SSD controller queue depth in real time, dynamically adjusts the migration concurrency and data block granularity, and feeds back to the status sensing module to form a closed-loop optimization, so that the system can maintain data integrity and consistency during the migration process under high load scenarios, and realizes adaptive optimization allocation of storage system resources.

[0017] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0018] Figure 1 This is a flowchart of a server intelligent integrated hierarchical storage system based on the U.2 interface according to the present invention.

[0019] Figure 2 This is a flowchart of a server intelligent integrated hierarchical storage method based on the U.2 interface according to the present invention. Detailed Implementation

[0020] This application provides a server-based intelligent integrated hierarchical storage system and method based on the U.2 interface, which solves the problems of poor interface compatibility, rigid hierarchical division, and low data migration efficiency in existing hierarchical storage systems.

[0021] The overall concept of the solution in this application embodiment is as follows:

[0022] First, the reserved pins of the U.2 interface are redefined using the state-aware module to establish a multi-protocol parallel channel, enabling concurrent access of SSDs with different protocols, and generating physical layer state information by combining signal integrity parameters and I / O characteristics. Second, the I / O feature sequence is analyzed by deep learning through the heat prediction module to obtain the data block access heat probability and automatically complete the hierarchical mapping. Then, the migration execution module realizes zero-copy migration of data blocks based on the shared DRAM pool and DMA engine, reducing resource consumption during the migration process. Finally, the resource coordination module dynamically adjusts the migration concurrency and data block granularity according to the system load, forming a feedback loop to the state-aware module to achieve adaptive optimization of the overall system.

[0023] Please see Figure 1This invention provides a technical solution: a server intelligent integrated hierarchical storage system based on a U.2 interface, comprising the following modules: a state awareness module, used to establish a multi-protocol parallel channel by redefining the reserved pins of the U.2 interface, monitor the signal integrity parameters of each channel in real time, fuse the signal integrity parameters with device I / O access characteristics, and generate an I / O feature sequence of physical layer state information; and a heat prediction module, used to receive the I / O feature sequence of physical layer state information, extract multi-scale features of access patterns through a temporal convolutional neural network, calculate the access heat probability of each data block, and determine the target storage level of each data block based on the high and low access heat probabilities, thereby generating a system containing the source physical address and target level. The system includes: a data migration scheduling instruction with identifiers and migration priorities; a migration execution module, which receives the data migration scheduling instruction, reads data blocks from the corresponding SSD flash memory according to the source physical address in the instruction, allocates an isolation buffer of the corresponding level in the shared DRAM pool according to the migration priority in the instruction, writes the data blocks to the corresponding SSD flash memory according to the target level identifier in the instruction, and realizes zero-copy migration of data blocks through the DMA engine; and a resource coordination module, which monitors the PCIe link utilization and SSD controller queue depth of the migration execution module in real time, dynamically adjusts the concurrency and data block granularity of the migration task according to the system load threshold and migration priority, and feeds back to the status awareness module to adjust the sampling frequency and feature dimension of the I / O feature sequence.

[0024] In this implementation scheme, the system consists of four cooperating modules. The data flow of each module is as follows: the state awareness module collects physical signals and I / O information and outputs a physical layer state I / O feature sequence → the heat prediction module predicts the heat of data blocks based on this sequence and outputs migration scheduling instructions → the migration execution module performs zero-copy migration between shared DRAM and each SSD according to the instructions → the resource coordination module monitors the migration running status and adjusts the migration parameters, and then feeds the adjustment results back to the state awareness module to adjust the sampling / feature strategy, forming a closed-loop optimization. The state awareness module merges the running status of the physical link layer and the I / O access behavior of the upper layer into a feature sequence that can be used for machine learning, providing physically aware input for subsequent heat prediction. The main inputs are: physical signals on the U.2 interface channel (such as differential pair waveforms, clock / synchronization information, error counts, etc.) and I / O request streams from the host (including logical block addresses, operation types, data sizes, timestamps, etc.). On the redefined U.2 channel, signal integrity metrics (see terminology description) are sampled and recorded in real time. Device presence detection signals are periodically read and verified to confirm the online status of each SSD. I / O request metadata (LBA, read / write, length, timestamp) is captured in parallel and preprocessed (denoising, normalization). Physical signal metrics are mapped to link health scores (e.g., converting bit error rate, jitter, eye diagram, etc., into a unified quality score), and these are aligned with the I / O metadata by timestamp, concatenating them into a hybrid feature vector for each time step. A sliding time window is used to serialize the continuous hybrid feature vectors (generating a time series), and normalization / denoising is performed to output a physical layer state I / O feature sequence (this sequence is the input to the subsequent ML model). Output: Physical layer state I / O feature sequence (time series format, each time step includes a link quality score and corresponding I / O metadata). U.2 interface: Standard 2.5-inch SSD physical / electrical interface, capable of supporting protocols such as PCIe / NVMe or SATA / SAS. Signal integrity parameters, such as bit error rate, timing jitter, and eye diagram opening, reflect the quality of high-speed differential signals. LBA (Logical Block Address): An address identifier in block storage. Sliding time window: A common method for segmenting time series for timing analysis. Popularity prediction module: Based on the time series output by the state-aware module, it identifies the "popularity" (probability / intensity of access) of each data block and determines which storage level (hot / warm / cold) the data block should be migrated to, while generating executable migration scheduling instructions. Main input: Physical layer state I / O feature sequence (time series, each step is a mixed feature vector).The input sequence is standardized in the time domain and missing values ​​are handled to ensure the consistency of the temporal model's input. A temporal convolutional neural network (TCN) is used for multi-scale feature extraction: the TCN captures short-term / medium-term / long-term access patterns at different time scales through causal and dilated convolutions. Multi-head self-attention is introduced on the feature maps extracted by convolution to weight key signals from different time steps or channels, enhancing the model's response to sudden hotspots or important signals. The fused high-dimensional features are mapped to the access popularity probability (classification or regression form) of each data block, and the popularity probability sequence is smoothed (e.g., exponentially weighted average) to reduce misjudgments due to instantaneous fluctuations. Based on the popularity probability and the current available capacity / performance status of each level, the target level is determined, and a data migration scheduling instruction is generated. This instruction structure includes: source physical address, target level identifier, initial migration priority, and instruction generation timestamp. Before the instruction is issued, resource availability verification (ensuring sufficient space / IOPS in the target level) and conflict detection (avoiding duplicate address migrations) can be performed. Output: A structured set of data migration scheduling instructions (which can be directly parsed and executed by the migration execution module). Temporal Convolutional Neural Network (TCN): A neural network structure for sequence modeling, featuring causal convolution and dilated convolution to capture long-term dependencies. Self-Attention Mechanism: Used to assign learnable weights to different positions in a sequence, highlighting important time steps or channels. Exponentially Weighted Smoothing: A smoothing method that assigns higher weights to recent observations, reducing the impact of random jitter. Migration Execution Module: Executes scheduling instructions issued by the heat prediction module to efficiently and securely complete cross-layer data block migrations on physical devices, minimizing host intervention and additional copying. Main Input: Migration scheduling instructions (including source physical address, target level, migration priority, etc.). The system locates the source SSD (within the module's U.2 or M.2) based on the source physical address in the instruction and requests a read operation. It allocates isolation buffers in the shared DRAM pool according to migration priority: high-priority tasks are allocated exclusive areas or buffers with higher QoS, while low-priority tasks share the buffer to save resources. It configures the DMA (Direct Memory Access) engine to establish a direct read path from the source SSD to the shared DRAM buffer, completing zero-copy data block reading (zero-copy: data is transferred directly between the device and DRAM, avoiding intermediate copying by the CPU). After the buffer is ready, it configures the DMA write path to write the data directly from the buffer to the physical location specified on the target SSD. During transmission, it performs data integrity checks (e.g., CRC checks), generating checksums during the read phase and verifying them during the write phase. After writing is complete, it atomically updates relevant metadata (e.g., the FTL mapping table) and returns the migration completion / failure status to the upper-layer management. Output: migration completion / failure status, migration time / bandwidth usage, and other runtime metrics (for collection by the resource coordination module).DMA (Direct Memory Access): A mechanism that allows peripherals to exchange data directly with memory without occupying the CPU. Shared DRAM Pool: A physical DRAM block within the module, logically divided into multiple virtual isolated regions by the controller for different purposes (FTL mapping, caching, migration channels). FTL (Flash Translation Layer): The management layer used by the SSD controller to map logical addresses to physical flash pages. Zero Copy: A method where data is copied multiple times during transmission without passing through the CPU buffer, reducing latency and CPU load. Resource Coordination Module (Runtime Monitoring and Adaptive Adjustment): During migration execution, it continuously monitors the system's internal resource utilization (such as PCIe link utilization and SSD controller queue depth), and adjusts migration parameters (concurrency, single migration block size) in real time based on these runtime metrics and migration priorities to achieve a dynamic balance between migration efficiency and business I / O response; simultaneously, it feeds the adjustment results back to the status-aware module to optimize subsequent sampling / feature strategies. Key inputs include real-time performance metrics from the migration execution module (PCIe bandwidth utilization, command queue depth for each SSD controller, number of migration tasks, current block size, etc.); it also receives system-preset load thresholds and priority policies. The system periodically samples PCIe link bandwidth utilization and queue depth for each SSD using performance counters or controller registers, calculating short-term moving averages and trend indicators. The sampled results are compared to preset thresholds (using hysteresis / intervals to avoid frequent jitter), and adjustments are determined based on the priority of each migration task: if the link is near saturation or the queue has significantly increased → reduce migration concurrency or decrease the block size per migration to reduce instantaneous load; if the link is idle and the queue is shallow → appropriately increase concurrency or block size to improve migration throughput; for high-priority tasks, relaxed restrictions or priority tokens can be used to ensure their execution. The adjusted migration parameters (e.g., number of concurrent tasks C, block size B) are sent to the migration execution module, and the adjusted runtime observations are recorded simultaneously. The records or parameter summaries are then fed back to the state-aware module. Based on this, the state-aware module can adaptively adjust the sampling frequency (reducing the sampling frequency under high load to reduce additional monitoring overhead, and increasing sampling to capture details under low load) and feature dimensions (retaining only core features under high load, and enabling extended features under low load) when generating the next round of I / O feature sequences. Output: The adjusted migration parameters are sent, and a feedback vector / summary for the state-aware module. Performance counters: Hardware or firmware-provided counting / measuring registers used to statistically analyze metrics such as bandwidth, frame errors, and queue depth. Queue depth: The number of commands queued for execution within the SSD controller, reflecting instantaneous load and response pressure. Concurrency: The number of migration tasks running simultaneously; data block granularity refers to the size of the data migrated each time (affecting the number of I / O requests and single bandwidth usage).

[0025] Specifically, the process of establishing a multi-protocol parallel channel by redefining the reserved pins of the U.2 interface is as follows: Identify the reserved signal pin groups in the U.2 interface that are preset for the SAS protocol, redefine the first group of SAS signal pins as PCIe x1 links to establish an independent data transmission channel with the M.2 NVMe SSD, redefine the second group of SAS signal pins as SATAx1 links to establish an independent data transmission channel with the M.2 SATA SSD, and retain the native PCIe x4 link in the U.2 interface as a high-speed data channel with the U.2 NVMe SSD; configure independent device presence detection signals for each redefined link, and identify the insertion status of each SSD by combining the level states of the detection pins.

[0026] In this implementation, firstly, the signal pin groups in the U.2 interface originally pre-configured for SAS (Serial Attached SCSI, a serial-attached SCSI storage protocol) are identified. In this embodiment, these pins are not actually used for the SAS protocol, so they can be redefined as reserved resources. The first group of SAS signal pins is redefined as a PCIe (Peripheral Component Interconnect Express) x1 link, i.e., a single-channel PCIe high-speed data transmission channel, used to establish an independent data path with the M.2 NVMe SSD (a solid-state drive supporting the PCIe-based non-volatile memory standard). The second group of SAS signal pins is then redefined as a SATA (Serial ATA, Serial Advanced Technology Attachment) x1 link, used to establish an independent data path with the M.2 SATA SSD (a solid-state drive based on the SATA protocol). Meanwhile, the U.2 interface's native PCIe x4 link is retained, used as a high-speed data transmission channel with the U.2 NVMe SSD. To ensure manageability and device identification capabilities for each redefined link, this embodiment further configures an independent device presence detection signal for each link (i.e., confirming device insertion by detecting the level state of a specific pin), and distinguishes the insertion status of different types of SSDs through level combination modes. In this way, the system can achieve plug-and-play management of SSDs with different protocols without the need for an additional external controller.

[0027] Specifically, the process of real-time monitoring of signal integrity parameters for each channel, fusing these parameters with device I / O access characteristics to generate a physical layer status information I / O feature sequence is as follows: The signal quality monitoring unit built into the interface controller periodically collects signal integrity parameters for each data channel, including bit error rate, timing jitter amplitude, and eye diagram opening. A mapping model from signal integrity parameters to link health is established, converting the original signal parameters into a standardized link quality score. I / O requests passing through each channel are captured in parallel, extracting logical block addresses, operation types, data sizes, and timestamp information from the requests. The link quality score is then timestamped and features are concatenated with real-time I / O characteristics to form a hybrid feature vector. This hybrid feature vector is then serialized and normalized using a sliding time window to generate a physical layer status information I / O feature sequence.

[0028] In this implementation scheme, firstly, the signal quality monitoring unit built into the interface controller periodically collects signal integrity parameters for each data channel, including: bit error rate (BER) parameter (denoted as...). ), representing the ratio of the number of erroneous bits to the total number of bits in the transmitted data at the k-th sampling; jitter amplitude parameter (denoted as ), representing the offset range of the clock edge position at the k-th sampling time; eye diagram opening parameter (denoted as ), representing the stable voltage range of the signal waveform at the k-th sampling. Subsequently, a mapping model from signal integrity parameters to link health is established. Specifically, the link quality score at the k-th sampling is calculated. The formula is as follows: ;in: : Link quality score of the kth sampling; : The bit error rate parameter of the k-th sample; : The jitter amplitude parameter of the kth sample; : Eye opening parameter of the k-th sample; : Refer to the maximum eye opening; Weighting coefficients are used to balance the contributions of different metrics to link quality. Specifically, the weighting coefficients... The determination method is as follows: During the system factory calibration phase, based on multiple sets of actual measurement data, the score is calculated using least squares regression by minimizing the error between the predicted score and the actual link failure probability. While collecting link quality parameters, I / O requests transmitted through each channel are captured in parallel, and their characteristic information is extracted, including: logical block address (denoted as...). This indicates the logical storage location corresponding to the I / O request; the operation type (denoted as...) ), use 0 / 1 variables to distinguish between read and write operations; data size (denoted as ), ), indicating the amount of data to be transmitted in this request; timestamp (denoted as Record the arrival time of the request. Then, assign a link quality score. With corresponding I / O features Perform time alignment and feature concatenation to obtain the k-th mixed feature vector: The mixed feature vector sequence is then organized using a sliding time window. Let the window length be L, then the feature sequence within the m-th window is represented as: Finally, for the sequence The features of each dimension are normalized to fall into a uniform numerical range, forming a standardized physical layer state information I / O feature sequence, which serves as the input for the subsequent heat prediction module.

[0029] Specifically, the process of receiving I / O feature sequences containing physical layer state information, extracting multi-scale features of access patterns through a temporal convolutional neural network, and calculating the access heat probability of each data block is as follows: The input I / O feature sequences undergo time-dimensional standardization preprocessing; access pattern features at different time scales are extracted using a temporal convolutional neural network with causal dilated convolutions; a multi-head self-attention mechanism is introduced at each layer of the convolutional network to adaptively assign weights to key time steps and feature channels in the feature maps; cross-layer connections and feature fusion are performed on feature maps from different layers; the fused high-dimensional features are mapped to the access heat probability value of each data block in the current time window through a fully connected layer; and the heat probability sequence is exponentially weighted and smoothed based on a sliding time window mechanism to reduce the impact of instantaneous fluctuations on prediction stability.

[0030] In this implementation scheme, specifically, the process of receiving the I / O feature sequence of physical layer state information, extracting multi-scale features of access patterns through a temporal convolutional neural network, and calculating the access frequency probability of each data block is as follows: Sequence normalization preprocessing of the input I / O feature sequence Temporal standardization is performed by subtracting the mean and dividing by the standard deviation for each feature dimension to reduce the impact of dimensional differences on network training. Standardization ensures balanced responses of the convolutional network across different feature dimensions, improving training stability. Temporal convolutional neural network feature extraction uses a temporal convolutional neural network (TCN) with causal dilated convolutions to extract multi-scale access pattern features. For the ... The first layer of convolutional networks Each output feature channel has an output representation as follows: ;in: : No. Layer Each channel at time step The output characteristics; : Input sequence at time step eigenvalues; : Kernel length, i.e., the number of historical time steps considered in each convolution; Dilation factor: controls the expansion of the receptive field; Convolution weights; Convolution bias; Activation functions, such as ReLU, are used to introduce non-linearity. Weight determination methods: Network weights. The algorithm is optimized using training data, employing backpropagation and a loss function that minimizes prediction error. A multi-head self-attention mechanism is introduced at each layer of the convolutional network, adaptively weighting the feature maps at different time steps and feature channels. For each time step... and feature channels Calculate the attention-weighted features: ;in: Attention-weighted features; : Convolutional layer Channel at time step The output characteristics; : No. Channel 1 Time step corresponds to the first The attention weights at each time step are calculated using the softmax function: ; Attention scoring function, typically calculated using dot product scoring or a small feedforward network; weights are determined automatically through network training, with the training objective being to minimize the error in predicting popularity probability. Cross-layer feature fusion involves connecting and fusing feature maps from different layers to obtain fused high-dimensional features. : ;in: Total number of convolutional layers; Feature channel splicing operation; Time step The fused feature vector. The high-dimensional feature mapping is converted into a heat probability, which will then be used to fuse the features. The input fully connected layer is mapped to the access frequency probability of each data block. : ;in: Time step The probability of data block access popularity; : Weight matrix of fully connected layers; : Bias vector; : Activation function, mapping the output to the range [0,1]; weights With bias Optimized using training data. Exponentially weighted smoothing is applied to the heat probability sequence. Perform exponentially weighted smoothing using a sliding window to reduce the impact of instantaneous fluctuations: ;in: : Smoothed heat probability; : Smoothing coefficient, with a value range of [0,1]; Smoothing coefficient determination: set according to system experience, usually adjusted according to I / O access volatility, so that short-term fluctuations do not significantly affect the stability of prediction.

[0031] Specifically, the process of determining the target storage level for each data block based on the access popularity probability, and generating data migration scheduling instructions containing the source physical address, target level identifier, and migration priority, is as follows: A dynamically adjusted popularity probability interval division mechanism is established to map the access popularity probability of data blocks to the corresponding storage level. The high popularity interval corresponds to U.2 NVMe SSD, the medium popularity interval to M.2 NVMe SSD, and the low popularity interval to M.2 SATA SSD. The remaining capacity distribution of each storage level is monitored in real time. When the remaining capacity of the target level is lower than a set threshold, the boundary values ​​of the popularity probability interval are dynamically adjusted, and some data blocks are reallocated to the available space of adjacent levels. Based on the determined target storage level, a structured migration scheduling instruction is constructed. The instruction includes the source physical address of the data block, the target level identifier, and the migration priority based on the popularity probability change rate and data block size. The generated scheduling instruction undergoes resource availability verification to ensure that the target level has sufficient receiving capacity and performance margin. Simultaneously, conflict detection is performed on the ongoing migration tasks to avoid address overlap and resource contention.

[0032] In this implementation plan, a dynamically adjustable heat probability interval is established. , data block Access popularity probability Mapped to the corresponding storage level: ;in: : data block Target storage tier identifier; : data block The probability of being accessed based on popularity; High-intensity zone, used for mapping to U.2 NVMe SSD; Medium heat range, used for mapping to M.2 NVMe SSD; Low-heat zone, used for mapping to M.2 SATA SSDs; zone dynamic adjustment: by monitoring the remaining capacity of each storage tier in real time, when the remaining capacity falls below a threshold... Adjust as appropriate The boundary ensures a balanced distribution of heat across the available space. Threshold Determination: Based on storage layer capacity statistics, a trigger threshold of 10%-15% of the remaining capacity is typically used. Migration priority calculation is performed for each data block. According to the probability change rate of heat With data block size Calculate migration priority : ;in: : data block The migration priority, with a larger value indicating a higher migration priority; Rate of change of heat probability This is the value predicted last time; : data block Size; Weighting coefficients are used to adjust the impact of changes in access popularity and data block size on migration priority. The weighting coefficients are determined based on historical access fluctuations and system I / O performance statistics, such as normalization based on the ratio of average access popularity change to average data block size. Structured migration scheduling instructions are generated based on the determined target storage tier. and migration priority Generate migration scheduling instructions : ;in: Data block Migration scheduling instructions; Data block The source physical address; Target storage tier identifier; Migration Priority. Before generating instructions, the system verifies the availability of the target tier's capacity and performance margin to ensure that instruction execution does not exceed storage capacity. For ongoing migration tasks, address conflict detection is also performed to prevent two migration tasks from pointing to the same physical space or competing for the same buffer resource. Dynamic Adjustment and Conflict Control: By monitoring the remaining capacity of each tier and the migration task queue depth in real time, the system dynamically adjusts the hot zone boundaries and migration priority calculation strategies to ensure a balanced distribution of migration tasks and prevent performance bottlenecks or resource contention. Hot Zone Boundaries The adjustments can be made using the following strategies: ; ; Current remaining capacity of U.2 NVMe SSD and M.2 SATA SSD; Adjustment coefficient, publicly determined: set according to the proportion of total remaining capacity, such as 0.05~0.1; when the remaining capacity of a certain layer is lower than the threshold, the corresponding interval boundary shrinks or expands, and the data block is dynamically migrated to the available space.

[0033] Specifically, the migration execution module includes the following steps: First, it divides the shared DRAM pool into isolated buffers with different access permissions based on migration priority, where high-priority migration tasks are allocated exclusive buffers, and low-priority migration tasks use shared buffers. Second, it establishes a direct read channel from the source SSD flash memory to the shared DRAM pool buffer using the DMA engine, transferring data blocks from the source SSD flash memory to the allocated isolated buffer. Third, after data transfer is complete, it establishes a direct write channel from the shared DRAM pool buffer to the target SSD flash memory using the DMA engine, writing data blocks from the buffer to the specified physical address of the target SSD. Fourth, during data transfer, it performs real-time verification of the transmitted data using a cyclic redundancy check mechanism, generating a checksum during the source SSD read phase and verifying the checksum during the target SSD write phase.

[0034] In this implementation scheme, the isolation buffer is partitioned as follows: The system partitions isolation buffers within the shared DRAM pool based on the priority of migration tasks. High-priority migration tasks are allocated exclusive buffers to ensure uninterrupted bandwidth and response time during data transfer; low-priority migration tasks use shared buffers, allowing concurrent access by multiple tasks while maintaining overall resource utilization. This approach enables dynamic resource isolation and priority scheduling for migration tasks, improving the timeliness of high-volume data block migration and overall system efficiency. Data is read from the source SSD to the buffer: A direct memory access channel is established using the DMA engine to transfer data blocks directly from the source SSD flash memory to the allocated DRAM isolation buffer. The DMA mechanism bypasses the CPU for high-speed transfer, reducing CPU load and data copying overhead, achieving zero-copy, high-efficiency migration. This improves data block migration speed while ensuring data integrity. Data is written from the buffer to the target SSD: After the data blocks are ready in the buffer, the DMA engine establishes another direct write channel from the DRAM buffer to the target SSD, writing the data to the specified physical address. In this way, data blocks can be accurately migrated according to the target level and physical location specified by the scheduling instructions, achieving intelligent tiered storage management. Data transmission verification: During data transmission, a Cyclic Redundancy Check (CRC) mechanism is used to verify the data in real time. A checksum is generated during the source SSD read phase and verified during the target SSD write phase to ensure that no data errors or corruption occur during the migration process. This step ensures the reliability of the migration, prevents data loss or corruption during transmission, and thus guarantees the data integrity and security of the storage system.

[0035] Specifically, the process of dynamically adjusting the concurrency and data block granularity of migration tasks based on system load thresholds and migration priorities by real-time monitoring of PCIe link utilization and SSD controller queue depth of the migration execution module is as follows: The bandwidth utilization of each PCIe link and the command queue depth of each SSD controller are collected in real time using performance counters to calculate the current comprehensive load index of the system; a load evaluation function based on a sliding window is established to smooth and predict the trend of the collected load data; when the system load exceeds the threshold, migration tasks are scheduled in stages according to migration priorities to reduce the number of concurrent executions of low-priority migration tasks and decrease the data block granularity to reduce the impact of a single migration on system performance.

[0036] In this implementation scheme, the performance acquisition and load metric calculation system collects the bandwidth utilization of each PCIe link in real time through a built-in performance counter. and the command queue depth of each SSD controller ,in Indicates the link number. This indicates the controller number. Based on this collected data, the current overall load index of the system is calculated. : ;in: The overall system load metric measures the overall pressure exerted on the system by the current migration task. : No. Bandwidth utilization of each PCIe link; : No. Command queue depth of each SSD controller; PCIe link weight coefficient, used to reflect the importance of different links. The determination method can be based on the link bandwidth ratio initialization and dynamically adjusted according to the operating status. SSD controller weight coefficient, used to reflect the degree of impact of the controller on system performance, can be set according to the historical distribution of controller queue length; Total number of PCIe links; Total number of SSD controllers. Explanation: This is a comprehensive load metric obtained by combining link bandwidth utilization and controller queue depth using a weighted average method. This can reflect the real-time stress status of the entire migration system. Load smoothing and trend prediction, to reduce the impact of instantaneous fluctuations on decision-making, employ a sliding window mechanism to adjust load indicators. Perform smoothing and trend forecasting: ;in: : Smoothed system load metrics; : The real-time load metrics currently being collected; The smoothed load metric for the previous time window; The smoothing coefficient controls the impact of historical data on current load forecasting. It is determined empirically by initializing it to a range of 0.3 to 0.5 and can be dynamically adjusted based on system response time. Explanation: Smoothed load metrics reflect short-term system trends, preventing instability in migration tasks caused by instantaneous fluctuations. Dynamically adjusting migration task concurrency and data block granularity based on smoothed load metrics... Exceeding the set system load threshold At that time, the system will determine the priority of the migration task. Migration tasks are scheduled in a tiered manner: high-priority tasks maintain high concurrency and larger data block granularity; low-priority tasks reduce concurrent execution and divide data blocks into smaller granularities to minimize the instantaneous impact on system performance. Explanation: This dynamic adjustment strategy enables adaptive control of system load, ensuring the timeliness of high-priority data migration while preventing low-priority migration tasks from causing PCIe link congestion or SSD controller queue accumulation. Resource feedback and loop optimization adjustment results are fed back to the state-aware module to adjust the sampling frequency and feature dimension of the / / O feature sequence, thus forming a closed-loop control mechanism to achieve dynamic matching between migration tasks and system resources.

[0037] Specifically, the process of adjusting the sampling frequency and feature dimensions of the I / O feature sequence is as follows: establish a mapping relationship between system load status and sampling parameters, dynamically adjust the sampling frequency of the I / O feature sequence according to the load level, reduce the sampling frequency under high load and increase the sampling frequency under low load; configure the feature dimension combination of the I / O feature sequence based on system load characteristics, retain the core feature dimensions under high load and enable the extended feature dimensions under low load, and send the configuration parameters to the status awareness module in real time.

[0038] In this implementation scheme, the sampling frequency is dynamically adjusted: The system first establishes a mapping relationship between system load status and I / O sampling parameters, that is, the sampling frequency is determined based on the current system load level. When the system load is high, the sampling frequency of the I / O feature sequence is reduced to reduce performance overhead and interference with migration tasks, thereby alleviating the real-time monitoring pressure on the interface controller and storage devices; when the system load is low, the sampling frequency is increased to obtain more refined I / O behavior information, facilitating more accurate decision-making by the heat prediction module and migration scheduling module. Feature dimension adaptive configuration: The system selects the combination of feature dimensions to be retained or enabled in the I / O feature sequence based on load characteristics. Under high load conditions, only core feature dimensions (such as link quality score, key I / O operation type, hot logical block address, etc.) are retained to reduce data processing volume and transmission overhead; under low load conditions, extended feature dimensions (such as time-related features, multi-level cache hit rate, queue wait time, etc.) are enabled to obtain richer I / O status information, thereby improving the accuracy of heat prediction and migration decisions. Real-time parameter delivery and closed-loop control: The adjusted sampling frequency and feature dimension configuration parameters are delivered to the state awareness module in real time, enabling the state awareness module to collect I / O features according to the new sampling strategy and form closed-loop control. This mechanism ensures a dynamic balance between I / O monitoring and system resource utilization, achieving adaptive optimization of system stability under high load and data monitoring accuracy under low load.

[0039] Please see Figure 2 A server-based intelligent integrated hierarchical storage method based on the U.2 interface includes the following steps: S1. Establishing a multi-protocol parallel channel by redefining the reserved pins of the U.2 interface, monitoring the signal integrity parameters of each channel in real time, fusing the signal integrity parameters with device I / O access characteristics, and generating an I / O feature sequence of physical layer status information; S2. Receiving the I / O feature sequence of physical layer status information, extracting multi-scale features of access patterns through a temporal convolutional neural network, calculating the access heat probability of each data block, and determining the target storage level of each data block based on the high and low access heat probabilities, thereby generating a storage sequence containing the source physical address, target level identifier, and migration priority. S3. Receive data migration scheduling instructions, read data blocks from the corresponding SSD flash memory according to the source physical address in the instructions, allocate isolation buffers of the corresponding level in the shared DRAM pool according to the migration priority in the instructions, write data blocks to the corresponding SSD flash memory according to the target level identifier in the instructions, and realize zero-copy migration of data blocks through the DMA engine; S4. Monitor the PCIe link utilization and SSD controller queue depth of the migration execution module in real time, dynamically adjust the concurrency and data block granularity of the migration task according to the system load threshold and migration priority, and feed back to the status awareness module to adjust the sampling frequency and feature dimension of the I / O feature sequence.

[0040] In this implementation scheme, step S1: By redefining the reserved pins of the U.2 interface, the signal pins originally used for the SAS protocol are reassigned to PCIe x1 links or SATA x1 links, establishing independent data transmission channels with M.2 NVMe SSDs and M.2 SATA SSDs respectively, while retaining the native PCIe x4 link of the U.2 interface for high-speed NVMe SSD communication. By detecting signals through independent devices, the insertion status of each SSD can be identified, thus supporting the simultaneous operation of multiple SSD types. Using the signal quality monitoring unit built into the interface controller, signal integrity parameters (such as bit error rate, timing jitter amplitude, and eye diagram opening) of each channel are periodically collected and standardized into a link health score. Simultaneously, I / O requests through each channel are captured in parallel, extracting information such as logical block address, operation type, data size, and timestamp. The link health score and I / O features are aligned and concatenated to form a hybrid feature vector, and then processed through sliding window serialization and normalization to generate an I / O feature sequence of physical layer status information. This provides a unified description of the system's real-time physical layer state and I / O behavior, offering foundational data for subsequent heat prediction and migration decisions. Step S2: After time-normalizing the I / O feature sequence, access pattern features at different time scales are extracted using a temporal convolutional neural network with causal dilated convolutions, capturing short-term and long-term access trends. A multi-head self-attention mechanism is introduced into each layer of the convolutional network to adaptively weight key time steps and feature channels, enhancing the ability to express important information. Feature maps from different levels are connected and fused across layers, mapping the access heat probability of each data block through a fully connected layer. The probability sequence is then smoothed using a sliding window exponential weighting to reduce the impact of instantaneous fluctuations. Storage tiers are dynamically partitioned based on heat probability, allocating high-heat data to U.2 NVMe SSDs, medium-heat data to M.2 NVMe SSDs, and low-heat data to M.2 SATA SSDs. When the target tier capacity is insufficient, boundary values ​​are dynamically adjusted to ensure available space; simultaneously, structured migration scheduling instructions are generated, including the source physical address, target tier identifier, and migration priority. This system intelligently predicts the access frequency of each data block and generates executable migration instructions, enabling dynamic optimization of the storage tier. Step S3: Based on migration priority, buffers with different access permissions are allocated in the shared DRAM pool. High-priority tasks use exclusive buffers, while low-priority tasks use shared buffers. A direct read channel from the source SSD to the buffer is established through the DMA engine, and a direct write channel from the buffer to the target SSD is established after the transfer is complete, achieving zero-copy migration and reducing CPU load. During the transfer process, a cyclic redundancy check mechanism is used to verify the data in real time to ensure data integrity. This system efficiently and securely completes the migration of data blocks from the source SSD to the target SSD, supporting dynamic data scheduling between different storage tiers.Step S4: Real-time collection of PCIe link bandwidth utilization and SSD controller command queue depth to establish comprehensive load metrics. Load trends are then smoothed and predicted using a sliding window. When system load exceeds a threshold, the concurrency of low-priority migration tasks and data block granularity are reduced to mitigate the impact on system performance. Load information is fed back to the status awareness module, which adjusts the sampling frequency and feature dimensions of I / O feature sequences based on the load. Under high load, the sampling frequency is reduced while retaining core feature dimensions; under low load, the sampling frequency is increased and extended feature dimensions are enabled. This achieves a dynamic balance between migration tasks and system load, ensuring the stability of the data migration process while maintaining high-precision I / O monitoring.

[0041] In summary, this application has at least the following effects:

[0042] This application provides a server-based intelligent integrated tiered storage system based on the U.2 interface. It establishes multi-protocol parallel channels by redefining reserved pins of the U.2 interface and monitors the signal integrity parameters of each channel in real time. These signal integrity parameters are fused with device I / O access characteristics to generate an I / O feature sequence of physical layer status information. This enables precise description of the status and I / O behavior of different storage devices, providing a reliable basis for subsequent access frequency prediction and data migration. By receiving the I / O feature sequence of physical layer status information, a temporal convolutional neural network is used to extract multi-scale features of access patterns, calculate the access frequency probability of each data block, and dynamically map the target storage level of the data block based on the access frequency probability. A data migration scheduling instruction containing the source physical address, target level identifier, and migration priority is generated, enabling intelligent scheduling of data blocks between different storage levels and optimizing storage resource utilization and access performance. Furthermore, a migration execution module enables zero-copy migration of data blocks between the shared DRAM pool buffer and the SSD. Combined with an isolation buffer strategy and a cyclic redundancy check mechanism, the efficiency and data integrity of the migration task are ensured. The resource coordination module monitors system load and migration task status in real time, dynamically adjusts migration task concurrency and data block granularity, and adaptively adjusts the sampling frequency and feature dimension of I / O feature sequences to achieve dynamic balance between migration process and system load, thereby improving system stability and storage scheduling accuracy.

[0043] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0044] This invention is described with reference to flowchart illustrations and / or block diagrams of systems, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0045] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0046] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0047] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0048] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A server-integrated intelligent hierarchical storage system based on a U.2 interface, characterized in that, Includes the following modules: The state awareness module is used to establish a multi-protocol parallel channel by redefining the reserved pins of the U.2 interface, monitor the signal integrity parameters of each channel in real time, and fuse the signal integrity parameters with the device I / O access characteristics to generate an I / O feature sequence of physical layer state information. The heat prediction module is used to receive the I / O feature sequence of physical layer status information, extract multi-scale features of access patterns through a temporal convolutional neural network, calculate the access heat probability of each data block, and determine the target storage level of each data block based on the high and low access heat probabilities, thereby generating a data migration scheduling instruction containing the source physical address, target level identifier and migration priority. The migration execution module is used to receive data migration scheduling instructions, read data blocks from the corresponding SSD flash memory according to the source physical address in the instructions, allocate the corresponding level of isolation buffer in the shared DRAM pool according to the migration priority in the instructions, write the data blocks to the corresponding SSD flash memory according to the target level identifier in the instructions, and realize zero-copy migration of data blocks through the DMA engine. The resource coordination module is used to monitor the PCIe link utilization and SSD controller queue depth of the migration execution module in real time. It dynamically adjusts the concurrency and data block granularity of migration tasks according to the system load threshold and migration priority, and feeds back to the status awareness module to adjust the sampling frequency and feature dimension of I / O feature sequences.

2. The server intelligent integrated hierarchical storage system based on the U.2 interface according to claim 1, characterized in that: The specific process of establishing a multi-protocol parallel channel by redefining the reserved pins of the U.2 interface is as follows: Identify the reserved signal pin groups in the U.2 interface that are preset for the SAS protocol, redefine the first group of SAS signal pins as PCIe x1 links to establish an independent data transmission channel with the M.2 NVMe SSD, redefine the second group of SAS signal pins as SATA x1 links to establish an independent data transmission channel with the M.2 SATA SSD, and retain the native PCIe x4 link in the U.2 interface as a high-speed data channel with the U.2 NVMe SSD; Each redefined link is configured with an independent device presence detection signal, and the insertion status of each SSD is identified by the combination of the level states of the detection pins.

3. The server intelligent integrated hierarchical storage system based on the U.2 interface according to claim 2, characterized in that: The specific process of real-time monitoring of signal integrity parameters for each channel, fusing these parameters with device I / O access characteristics, and generating an I / O feature sequence of physical layer status information is as follows: By using the signal quality monitoring unit built into the interface controller, the signal integrity parameters of each data channel are periodically collected, including the signal bit error rate, timing jitter amplitude and eye diagram opening. A mapping model from signal integrity parameters to link health is established, and the original signal parameters are converted into standardized link quality scores. Parallel capture of I / O requests through each channel, extract logical block address, operation type, data size and timestamp information from the requests, and align link quality score with real-time I / O features by timestamp and feature concatenation to form a hybrid feature vector; By using a sliding time window, the hybrid feature vectors are serialized and normalized to generate a physical layer state information I / O feature sequence.

4. The server intelligent integrated hierarchical storage system based on the U.2 interface according to claim 1, characterized in that: The specific process of receiving I / O feature sequences of physical layer state information, extracting multi-scale features of access patterns through a temporal convolutional neural network, and calculating the access frequency probability of each data block is as follows: The input I / O feature sequence is preprocessed with time-dimensional standardization, and access pattern features at different time scales are extracted by a temporal convolutional neural network with causal dilated convolution. A multi-head self-attention mechanism is introduced at each layer of the convolutional network to adaptively allocate weights to key time steps and feature channels in the feature map. The feature maps of different levels are connected across layers and feature fusion is performed. The fused high-dimensional features are mapped to the access popularity probability value of each data block in the current time window through a fully connected layer. The popularity probability sequence is exponentially weighted and smoothed based on the sliding time window mechanism to reduce the impact of instantaneous fluctuations on prediction stability.

5. The server intelligent integrated hierarchical storage system based on the U.2 interface according to claim 4, characterized in that: The specific process of determining the target storage level of each data block based on the probability of access popularity, and thus generating a data migration scheduling instruction containing the source physical address, target level identifier, and migration priority, is as follows: A dynamic hot probability interval division mechanism is established to map the access hot probability of data blocks to the corresponding storage level. The high hot interval corresponds to U.2 NVMe SSD, the medium hot interval corresponds to M.2 NVMe SSD, and the low hot interval corresponds to M.2 SATA SSD. The remaining capacity distribution of each storage level is monitored in real time. When the remaining capacity of the target level is lower than the set threshold, the boundary value of the hot probability interval is dynamically adjusted to reallocate some data blocks to the available space of adjacent levels. Based on the determined target storage level, a structured migration scheduling instruction is constructed. The instruction includes the source physical address of the data block, the target level identifier, and the migration priority based on the probability change rate of heat and the data block size. The generated scheduling instruction is verified for resource availability to ensure that the target level has sufficient receiving capacity and performance margin. At the same time, conflict detection is performed on the migration task being executed to avoid address overlap and resource contention.

6. The server intelligent integrated hierarchical storage system based on the U.2 interface according to claim 1, characterized in that: The migration execution module includes the following steps: Based on migration priority, isolated buffers with different access permissions are divided in the shared DRAM pool, where high-priority migration tasks are allocated exclusive buffers and low-priority migration tasks use shared buffers. A direct read channel from the source SSD flash memory to the shared DRAM pool buffer is established through the DMA engine, transferring data blocks from the source SSD flash memory to the allocated isolation buffer; After the data transfer is completed, a direct write channel from the shared DRAM pool buffer to the target SSD flash memory is established through the DMA engine, and the data block is written from the buffer to the specified physical address of the target SSD. During data transmission, a cyclic redundancy check mechanism is used to verify the transmitted data in real time. A checksum is generated during the source SSD read phase and verified during the target SSD write phase.

7. The server intelligent integrated hierarchical storage system based on the U.2 interface according to claim 1, characterized in that: The specific process of dynamically adjusting the concurrency and data block granularity of migration tasks based on system load thresholds and migration priorities, while monitoring the PCIe link utilization and SSD controller queue depth of the migration execution module in real time, is as follows: The bandwidth utilization of each PCIe link and the command queue depth of each SSD controller are collected in real time by performance counters to calculate the current comprehensive load index of the system. A sliding window-based load assessment function is established to smooth and predict the trend of the collected load data. When the system load exceeds the threshold, the migration tasks are scheduled in a hierarchical manner according to the migration priority to reduce the number of concurrent executions of low-priority migration tasks and reduce the data block granularity to reduce the impact of a single migration on system performance.

8. The server intelligent integrated hierarchical storage system based on the U.2 interface according to claim 7, characterized in that: The specific process for adjusting the sampling frequency and feature dimension of the I / O feature sequence is as follows: Establish a mapping relationship between system load status and sampling parameters, and dynamically adjust the sampling frequency of I / O characteristic sequences according to the load level, reducing the sampling frequency under high load and increasing the sampling frequency under low load. The configuration of I / O feature sequence feature dimension combination is based on system load characteristics. Core feature dimensions are retained under high load, and extended feature dimensions are enabled under low load. The configuration parameters are sent to the status awareness module in real time.

9. A server intelligent integrated hierarchical storage method based on a U.2 interface, applied to the server intelligent integrated hierarchical storage system based on a U.2 interface as described in any one of claims 1-8, characterized in that, Includes the following steps: S1. By redefining the reserved pins of the U.2 interface, a multi-protocol parallel channel is established, the signal integrity parameters of each channel are monitored in real time, and the signal integrity parameters are fused with the device I / O access characteristics to generate the I / O feature sequence of physical layer status information; S2. Receive the I / O feature sequence of physical layer status information, extract multi-scale features of access patterns through a temporal convolutional neural network, calculate the access hotness probability of each data block, and determine the target storage level of each data block based on the high and low access hotness probability, thereby generating a data migration scheduling instruction containing the source physical address, target level identifier and migration priority. S3. Receive data migration scheduling instructions, read data blocks from the corresponding SSD flash memory according to the source physical address in the instructions, allocate isolation buffers of the corresponding level in the shared DRAM pool according to the migration priority in the instructions, write data blocks to the corresponding SSD flash memory according to the target level identifier in the instructions, and realize zero-copy migration of data blocks through the DMA engine. S4. Monitor the PCIe link utilization and SSD controller queue depth of the migration execution module in real time, dynamically adjust the concurrency and data block granularity of the migration task according to the system load threshold and migration priority, and feed back to the status awareness module to adjust the sampling frequency and feature dimension of the I / O feature sequence.

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