A method and system for generating test patterns for curve layout based on machine learning

By generating curve layout test graphics through machine learning, the problem of balancing detection accuracy and efficiency is solved, and efficient and accurate curve layout detection is achieved.

CN121482049BActive Publication Date: 2026-05-01YIXIN TECH (HANGZHOU) CO LTD
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Patent Information

Application Number
CN202610023907.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-01-09
Publication Date
2026-05-01
Estimated Expiration
2046-01-09

AI Technical Summary

Technical Problem

Existing technologies for curve layout inspection suffer from a tradeoff between accuracy and efficiency. Traditional methods are inefficient and prone to missing detections, while automatically generated test patterns cannot accurately extract the geometric features and defect correlation features of the curve layout, resulting in insufficient targeting of the test patterns.

Method used

A machine learning-based approach is adopted, which involves data cleaning and completion, precise feature extraction, correlation analysis and dimensionality reduction, combined with K-means clustering and silhouette coefficient correction to generate optimized test graphs. A model validation and iteration mechanism is introduced to dynamically adjust the model and test graphs to adapt to the needs of complex curve pattern detection.

Benefits of technology

It improves the accuracy of defect pattern recognition, reduces the risk of missed detection, shortens the testing time, achieves a balance between detection accuracy and efficiency, and enhances the applicability and reliability of test patterns.

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Abstract

The present application relates to the technical field of integrated circuit layout detection, and particularly relates to a curve layout test pattern generation method and system based on machine learning, comprising: obtaining historical curve layout data and preprocessing to obtain an effective data set; extracting geometric and defect correlation features, and obtaining a feature matrix through correlation analysis and dimension reduction; generating a defect mode label by K-means clustering combined with contour coefficient correction clustering number; inputting the feature matrix and the label into a classification model to output parameters to generate an initial test pattern, and obtaining an optimized test pattern through redundancy and coverage optimization; importing a test system for verification, and if the verification does not meet the standard, the model is retrained, and if the verification meets the standard, the final pattern is output. The present application realizes accurate identification of defect modes with the aid of machine learning, balances detection accuracy and efficiency, improves the applicability of test patterns, and is suitable for integrated circuit curve layout detection.
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