Reference voltage easy drive analog-to-digital converter

By combining fine and coarse SAR ADCs and using passive charge redistribution DACs and LSB DACs, the problems of complex capacitor arrangement and noise effects in high-precision SAR ADCs are solved, realizing a high-precision and easy-to-manufacture analog-to-digital converter design.

CN121618974BActive Publication Date: 2026-05-01XIDIAN UNIV
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Patent Information

Application Number
CN202610140638.8
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-02-02
Publication Date
2026-05-01
Estimated Expiration
2046-02-02

AI Technical Summary

Technical Problem

In existing technologies, high-precision SARADCs require large sampling capacitors and complex capacitor arrangements, which leads to high manufacturing difficulty, high area overhead, and severe noise (kT/C). They are also sensitive to parasitic capacitances in the DAC section, affecting accuracy and practicality.

Method used

By combining a fine SAR ADC and a coarse SAR ADC with a passive charge redistribution DAC and an LSB DAC, the capacitor connections and charge redistribution are controlled by a clock signal to generate residual voltage, avoiding the use of CREF,i, maintaining binary weights and simplifying capacitor arrangement.

Benefits of technology

This solves the trade-off between CREF,i area and noise, avoids errors and complex adjustments introduced by parasitic capacitance, and improves the manufacturability and practicality of analog-to-digital converters.

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Abstract

This invention relates to a reference voltage-driven analog-to-digital converter (ADC), belonging to the field of integrated circuits. The ADC includes a fine SAR ADC and a coarse SAR ADC. When φ... SA φ S and φ D When the voltage is high, connect the top plate of the DAC bit capacitor to V. CM Terminal and base plate are connected to the input signal terminal, φ SA and φ S The signal is successively lowered to a low level to complete the sampling of the input signal; at φ C When the signal is high, the first 5 bits of the input signal are obtained by coarse SAR ADC quantization. Based on this digital code, the bit capacitor base plate of the passive charge redistribution DAC in the fine SAR ADC is connected to V. REFP End or V REFN end, at φ C The connection is disconnected when the voltage drops to a low level, and when φ D Drop to low level, φ R After rising to a high level, the base plate of some capacitors in the passive charge redistribution DAC is shorted, causing charge redistribution to generate a residual voltage. This invention improves manufacturability and practicality.
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