A method, apparatus, device, and medium for predicting flash memory erase / write cycles.

Abstract

This application discloses a method, apparatus, device, and medium for predicting the number of erase / write cycles of flash memory. The method includes: performing a limited number of cycles of room temperature and high temperature testing on selected flash memory chips to obtain pre-test characteristic parameters, and determining bad block judgment parameters based on the pre-test characteristic parameters; determining logical bad blocks on the selected flash memory chips based on the bad block judgment parameters to obtain the number of logical bad blocks with a limited number of cycles at room temperature and the number of logical bad blocks with a limited number of cycles at high temperature; performing a high temperature cycle test on the selected flash memory chips and determining physical bad blocks to obtain the number of high temperature cycle erase / write cycles; performing the same room temperature and high temperature tests on the pre-test flash memory chips to obtain the number of pre-test logical bad blocks with a limited number of cycles at room temperature and the number of pre-test logical bad blocks with a limited number of cycles at high temperature; and determining the target number of erase / write cycles for the pre-test flash memory chips based on the obtained data. This technical solution achieves accurate evaluation of the number of erase / write cycles of flash memory chips, reduces losses, and improves efficiency.

Description

Technical Field

[0001] This application belongs to the field of electronic digital data processing technology, specifically relating to a method, apparatus, device, and medium for predicting the number of times a flash memory can be erased and written. Background Technology

[0002] Flash memory is a non-volatile storage medium widely used due to its advantages such as high density, low power consumption, and data retention even when power is off. The number of erase / write cycles is a core indicator of flash memory lifespan, directly representing its reliability and data security.

[0003] Currently, mainstream erase / write cycle testing uses a high-temperature cycling method until failure. This requires continuous erasing and writing of the flash memory chip until a preset bad block threshold is reached to obtain accurate erase / write cycle data. This type of failure testing is destructive; the testing process completely consumes the lifespan of the flash memory chip, rendering it unusable in finished products. Therefore, in mass production, only sampling inspection can be used. The overall performance of the entire batch of products can be inferred from the test results of a small sample, making it impossible to perform full testing on every single flash memory chip. This can easily lead to the omission of individual flash memory chip reliability defects, thus affecting the overall quality and reliability of the entire batch. Summary of the Invention

[0004] This application provides a method, apparatus, device, and medium for predicting the number of erase / write cycles of flash memory, aiming to support accurate evaluation of the number of erase / write cycles of all flash memory chips in mass production scenarios, reduce production testing losses, and improve the efficiency of erase / write cycle detection.

[0005] In a first aspect, embodiments of this application provide a method for predicting flash memory erase / write cycles, the method comprising:

[0006] Flash memory chips are extracted from the pre-test flash memory chips, and the extracted flash memory chips are subjected to room temperature testing and high temperature testing with a limited number of cycles to obtain the corresponding pre-test characteristic parameters; wherein, the pre-test characteristic parameters include the number of flash page rereads and / or the number of flash page error bits, and the limited number of cycles is at least one;

[0007] Based on the pre-test feature parameters, bad block judgment parameters are determined, and based on the bad block judgment parameters, logical bad blocks are judged on the extracted flash memory chips to obtain the number of room temperature finite cycle logical bad blocks and the number of high temperature finite cycle logical bad blocks of the extracted flash memory chips.

[0008] The extracted flash memory chips are subjected to high-temperature cycling tests, and physical bad blocks are determined during the high-temperature cycling tests to obtain the number of physical bad blocks. The high-temperature cycling tests are stopped when the number of physical bad blocks reaches a preset number, and the number of high-temperature cycle erase / write cycles of the extracted flash memory chips is obtained.

[0009] For the pre-test flash memory chip, perform the same room temperature test and high temperature test as the extracted flash memory chip to obtain the number of pre-test room temperature finite cycle logic bad blocks and the number of pre-test high temperature finite cycle logic bad blocks for the pre-test flash memory chip;

[0010] Based on the number of room-temperature finite-cycle bad blocks, the number of high-temperature finite-cycle bad blocks, and the number of high-temperature erase / write cycles of the extracted flash memory chips, and based on the number of pre-test room-temperature finite-cycle bad blocks and the number of pre-test high-temperature finite-cycle bad blocks of the pre-test flash memory chips, the target number of erase / write cycles of the pre-test flash memory chips is determined.

[0011] Furthermore, determining the bad block evaluation parameters based on the pre-test feature parameters includes:

[0012] Determine the maximum value among the pre-test feature parameters, and determine the bad block evaluation parameters based on the maximum value among the pre-test feature parameters.

[0013] Furthermore, determining the bad block evaluation parameters based on the maximum value among the pre-test feature parameters includes:

[0014] The spatial influence coefficient is determined based on the pre-test feature parameters and the flash page positions corresponding to the pre-test feature parameters.

[0015] Multiply the spatial influence coefficient by the maximum value among the pre-test feature parameters to obtain the bad block evaluation parameters.

[0016] Furthermore, determining the spatial influence coefficient based on the pre-test feature parameters and the corresponding flash page positions includes:

[0017] The flash memory page locations where the pre-test feature parameters exceed a preset threshold are identified as bad page locations, and cluster analysis is performed on the bad page locations to obtain each cluster and the coverage radius of each cluster.

[0018] Calculate the ratio of the maximum value of the coverage radius of each cluster to the total number of flash pages of the pre-test flash memory chip, and calculate the difference between the maximum value and the average value of the pre-test feature parameters;

[0019] The spatial influence coefficient is calculated based on the ratio and the difference.

[0020] Furthermore, determining the spatial influence coefficient based on the pre-test feature parameters and the corresponding flash page positions includes:

[0021] The flash memory page locations where the pre-test feature parameters exceed a preset threshold are identified as bad page locations, and the shortest distance between each bad page location and other bad page locations is calculated.

[0022] The average value of each of the shortest distances is calculated as the first average value, and the average value of the pre-test feature parameters is calculated as the second average value;

[0023] The spatial influence coefficient is calculated based on the first average value and the second average value.

[0024] Furthermore, determining the bad block evaluation parameters based on the pre-test feature parameters includes:

[0025] Obtain the flash memory type information and stacking layer number information of the pre-tested flash memory chip, and determine the feature adaptation coefficient based on the flash memory type information and the stacking layer number information;

[0026] The mean and standard deviation of the pre-test characteristic parameters are statistically analyzed;

[0027] Multiply the standard deviation by the characteristic fitting coefficient to obtain an intermediate calculation result, and add the intermediate calculation result to the average value to obtain the bad block evaluation parameters.

[0028] Furthermore, determining the target number of erase / write cycles for the pre-test flash memory chip based on the number of room-temperature finite-cycle bad blocks, the number of high-temperature finite-cycle bad blocks, and the number of high-temperature erase / write cycles of the extracted flash memory chip, and based on the number of pre-test room-temperature finite-cycle bad blocks and the number of pre-test high-temperature finite-cycle bad blocks of the pre-test flash memory chip, includes:

[0029] The difference between the number of pre-test high-temperature finite cycle logic bad blocks of the pre-test flash memory chip and the number of high-temperature finite cycle logic bad blocks of the extracted flash memory chip is calculated as the first difference value corresponding to the extracted flash memory chip, and the extracted flash memory chip corresponding to the minimum value of the first difference value is determined as the target flash memory chip.

[0030] When the number of target flash memory chips is one, the number of high-temperature cycle erase / write cycles of the target flash memory chip is determined as the target number of erase / write cycles of the pre-test flash memory chip;

[0031] When the number of target flash memory chips is not one, the difference between the number of pre-test room temperature finite cycle bad blocks of the pre-test flash memory chip and the number of room temperature finite cycle bad blocks of the target flash memory chip is calculated as the second difference corresponding to the target flash memory chip, and the number of high temperature cycle erase / write cycles of the target flash memory chip corresponding to the minimum value of the second difference is determined as the target erasure / write cycle of the pre-test flash memory chip.

[0032] Secondly, embodiments of this application provide a flash memory erase / write cycle prediction device, the device comprising:

[0033] The feature parameter acquisition module is used to extract flash memory chips from the pre-test flash memory chips and perform room temperature and high temperature tests on the extracted flash memory chips for a limited number of cycles to obtain the corresponding pre-test feature parameters; wherein, the pre-test feature parameters include the number of flash page rereads and / or the number of flash page error bits, and the limited number of cycles is at least one;

[0034] The bad block quantity determination module is used to determine bad block evaluation parameters based on the pre-test feature parameters, and to perform logical bad block determination on the extracted flash memory chips based on the bad block evaluation parameters, so as to obtain the number of room temperature finite cycle logical bad blocks and the number of high temperature finite cycle logical bad blocks of the extracted flash memory chips.

[0035] The high-temperature cycle test module is used to perform high-temperature cycle tests on the extracted flash memory chips, and to determine the number of physical bad blocks during the high-temperature cycle test. When the number of physical bad blocks reaches a preset number, the high-temperature cycle test is stopped, and the number of high-temperature cycle erase / write cycles of the extracted flash memory chips is obtained.

[0036] The pre-test bad block determination module is used to perform the same room temperature test and high temperature test on the pre-test flash memory chip as the extracted flash memory chip, and obtain the number of pre-test room temperature finite cycle logic bad blocks and the number of pre-test high temperature finite cycle logic bad blocks of the pre-test flash memory chip.

[0037] The erasable write count determination module is used to determine the target erasable write count of the pre-test flash memory chip based on the number of room temperature finite cycle logical bad blocks, the number of high temperature finite cycle logical bad blocks, and the number of high temperature cycle erase / write cycles of the extracted flash memory chip, as well as based on the number of pre-test room temperature finite cycle logical bad blocks and the number of pre-test high temperature finite cycle logical bad blocks of the pre-test flash memory chip.

[0038] Furthermore, the bad block count determination module is specifically used for:

[0039] Determine the maximum value among the pre-test feature parameters, and determine the bad block evaluation parameters based on the maximum value among the pre-test feature parameters.

[0040] Furthermore, the bad block count determination module is specifically used for:

[0041] The spatial influence coefficient is determined based on the pre-test feature parameters and the flash page positions corresponding to the pre-test feature parameters.

[0042] Multiply the spatial influence coefficient by the maximum value among the pre-test feature parameters to obtain the bad block evaluation parameters.

[0043] Furthermore, the bad block count determination module is specifically used for:

[0044] The flash memory page locations where the pre-test feature parameters exceed a preset threshold are identified as bad page locations, and cluster analysis is performed on the bad page locations to obtain each cluster and the coverage radius of each cluster.

[0045] Calculate the ratio of the maximum value of the coverage radius of each cluster to the total number of flash pages of the pre-test flash memory chip, and calculate the difference between the maximum value and the average value of the pre-test feature parameters;

[0046] The spatial influence coefficient is calculated based on the ratio and the difference.

[0047] Furthermore, the bad block count determination module is specifically used for:

[0048] The flash memory page locations where the pre-test feature parameters exceed a preset threshold are identified as bad page locations, and the shortest distance between each bad page location and other bad page locations is calculated.

[0049] The average value of each of the shortest distances is calculated as the first average value, and the average value of the pre-test feature parameters is calculated as the second average value;

[0050] The spatial influence coefficient is calculated based on the first average value and the second average value.

[0051] Furthermore, the bad block count determination module is specifically used for:

[0052] Obtain the flash memory type information and stacking layer number information of the pre-tested flash memory chip, and determine the feature adaptation coefficient based on the flash memory type information and the stacking layer number information;

[0053] The mean and standard deviation of the pre-test characteristic parameters are statistically analyzed;

[0054] Multiply the standard deviation by the characteristic fitting coefficient to obtain an intermediate calculation result, and add the intermediate calculation result to the average value to obtain the bad block evaluation parameters.

[0055] Furthermore, the erase / write cycle determination module is specifically used for:

[0056] The difference between the number of pre-test high-temperature finite cycle logic bad blocks of the pre-test flash memory chip and the number of high-temperature finite cycle logic bad blocks of the extracted flash memory chip is calculated as the first difference value corresponding to the extracted flash memory chip, and the extracted flash memory chip corresponding to the minimum value of the first difference value is determined as the target flash memory chip.

[0057] When the number of target flash memory chips is one, the number of high-temperature cycle erase / write cycles of the target flash memory chip is determined as the target number of erase / write cycles of the pre-test flash memory chip;

[0058] When the number of target flash memory chips is not one, the difference between the number of pre-test room temperature finite cycle bad blocks of the pre-test flash memory chip and the number of room temperature finite cycle bad blocks of the target flash memory chip is calculated as the second difference corresponding to the target flash memory chip, and the number of high temperature cycle erase / write cycles of the target flash memory chip corresponding to the minimum value of the second difference is determined as the target erasure / write cycle of the pre-test flash memory chip.

[0059] Thirdly, embodiments of this application provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the method described in the first aspect.

[0060] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the method described in the first aspect.

[0061] In this embodiment, flash memory chips are extracted from pre-test flash memory chips, and the extracted flash memory chips are subjected to room temperature and high temperature tests with a limited number of cycles to obtain corresponding pre-test characteristic parameters. The pre-test characteristic parameters include the number of flash page rereads and / or the number of flash page error bits, and the limited number of cycles is at least one. Bad block judgment parameters are determined based on the pre-test characteristic parameters, and logical bad block determination is performed on the extracted flash memory chips based on the bad block judgment parameters to obtain the number of room temperature limited-cycle logical bad blocks and the number of high temperature limited-cycle logical bad blocks for the extracted flash memory chips. The extracted flash memory chips are subjected to high-temperature cycling tests, and physical bad blocks are determined during the high-temperature cycling tests to obtain physical bad blocks. The high-temperature cycle test is stopped when the number of physical bad blocks reaches a preset number, thus obtaining the high-temperature cycle erase / write count of the extracted flash memory chips. For the pre-test flash memory chips, the same room-temperature and high-temperature tests are performed as on the extracted flash memory chips to obtain the number of pre-test room-temperature finite-cycle logical bad blocks and the number of pre-test high-temperature finite-cycle logical bad blocks for the pre-test flash memory chips. Based on the number of room-temperature finite-cycle logical bad blocks, the number of high-temperature finite-cycle logical bad blocks, and the number of high-temperature cycle erase / write counts of the extracted flash memory chips, and based on the number of pre-test room-temperature finite-cycle logical bad blocks and the number of pre-test high-temperature finite-cycle logical bad blocks for the pre-test flash memory chips, the target erasure / write count of the pre-test flash memory chips is determined. This flash memory erasure / write count prediction method supports accurate evaluation of the erasure / write count of all flash memory chips in batch production scenarios, reducing production testing losses and improving erasure / write count detection efficiency. Attached Figure Description

[0062] Figure 1 This is a flowchart illustrating a flash memory erase / write cycle prediction method provided in an embodiment of this application;

[0063] Figure 2 This is a flowchart illustrating another flash memory erase / write cycle prediction method provided in an embodiment of this application;

[0064] Figure 3 This is a flowchart illustrating another flash memory erase / write cycle prediction method provided in the embodiments of this application;

[0065] Figure 4 This is a schematic diagram of the structure of a flash memory erase / write cycle prediction device provided in an embodiment of this application;

[0066] Figure 5 This is a schematic diagram of the structure of an electronic device provided in Embodiment 5 of this application. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. It should also be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but may also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0068] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0069] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0070] The flash memory erase / write cycle prediction method, apparatus, device, and medium provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0071] First, this application is applicable to scenarios involving flash memory chip lifetime prediction and reliability assessment. Based on the above application scenarios, it can be understood that the implementing entity of this application can be a smart terminal device with computing capabilities, such as a computer, server, or embedded controller, without further limitations.

[0072] Figure 1 This is a flowchart illustrating a flash memory erase / write cycle prediction method provided in an embodiment of this application. Figure 1 As shown, the specific steps include the following:

[0073] S101, extract flash memory chips from the pre-test flash memory chips, and perform room temperature test and high temperature test on the extracted flash memory chips for a limited number of cycles to obtain the corresponding pre-test characteristic parameters; wherein, the pre-test characteristic parameters include the number of flash page rereads and / or the number of flash page error bits, and the limited number of cycles is at least one.

[0074] Among them, flash memory chips can be semiconductor chip units that can still retain data after power failure and can be erased and written multiple times; pre-test flash memory chips can be flash memory chips from the same production batch; the extracted flash memory chips can be sample flash memory chips randomly selected from the pre-test flash memory chips for pre-destructive or long-cycle testing.

[0075] In one embodiment, the flash memory chips are selected from the pre-test flash memory chips by means of simple random sampling or systematic sampling, selecting a predetermined number of flash memory chips. For example, each pre-test flash memory chip is numbered and then selected using a random number table, or selected at fixed intervals. The predetermined number can be a sample size determined according to statistical significance requirements, such as 0.5% of the total number of pre-test flash memory chips.

[0076] The room temperature test involves performing a limited number of erase / write cycles on the flash memory chip under normal operating conditions to simulate the wear and tear process. The high temperature test involves performing a limited number of erase / write cycles on the flash memory chip under high temperature conditions to accelerate the exposure of its durability defects. Specifically, the room temperature can be 25°C, and the high temperature can be 85°C; the limited number of cycles can be preset, and the limited number of cycles can be at least one.

[0077] Among them, the pre-test characteristic parameters can be quantitative indicators that reflect the wear degree of flash memory chips and are collected during the test. These can include the number of flash page rereads and / or the number of flash page error bits.

[0078] Specifically, a flash page can be the smallest read / write unit in a flash memory chip. Correspondingly, the flash page reread count can be the number of times a flash page needs to be reread due to an error during the read operation; the flash page error bit count can be the number of bits that are erroneous during the read operation of a flash page.

[0079] In one embodiment, the method of performing a limited number of cycles of room temperature and high temperature testing on the extracted flash memory chips to obtain the corresponding pre-test characteristic parameters can be achieved by reading each flash page of each extracted flash memory chip after each erase / write cycle in both room temperature and high temperature tests, recording the number of flash page rereads and / or the number of flash page error bits at each read, until the number of cycles reaches the preset limited number of cycles.

[0080] S102, bad block evaluation parameters are determined based on the pre-test feature parameters, and logical bad blocks are determined on the extracted flash memory chips based on the bad block evaluation parameters to obtain the number of room temperature finite cycle logical bad blocks and the number of high temperature finite cycle logical bad blocks of the extracted flash memory chips.

[0081] The bad block assessment parameter can be a comprehensive indicator used to quantify the health of a flash memory block, logically determining whether the block has become worn to the point of being unusable. Specifically, a flash memory block can be the smallest unit of an erase operation, consisting of multiple flash pages. The bad block assessment parameter is calculated independently for each flash memory block; one bad block assessment parameter corresponds to each flash memory block after each erase / write cycle.

[0082] In one embodiment, the method for determining bad block evaluation parameters based on pre-test feature parameters can be as follows: after each erase / write cycle, for each flash block, calculate the average number of rereads of each flash page in the flash block as the bad block evaluation parameter corresponding to the flash block after that erase / write cycle; or after each erase / write cycle, for each flash block, calculate the average number of error bits of each flash page in the flash block as the bad block evaluation parameter corresponding to the flash block after that erase / write cycle; or after each erase / write cycle, for each flash block, calculate the average of the normalized weighted sum of the number of flash page rereads and the number of flash page error bits of each flash page in the flash block as the bad block evaluation parameter corresponding to the flash block after that erase / write cycle.

[0083] In one embodiment, determining the bad block evaluation parameters based on the pre-test feature parameters includes: acquiring flash memory type information and stacking layer number information of the pre-test flash memory chip, and determining the feature adaptation coefficient based on the flash memory type information and the stacking layer number information; calculating the average value and standard deviation of the pre-test feature parameters; multiplying the standard deviation by the feature adaptation coefficient to obtain an intermediate calculation result, and adding the intermediate calculation result to the average value to obtain the bad block evaluation parameters.

[0084] The flash memory type information can be the bit type of the flash memory chip storage cell, such as SLC (single-level cell), MLC (multi-level cell), TLC (triple-level cell), or QLC (quadruple-level cell); the stacking layer information can refer to the number of layers in which the storage cells are stacked vertically, such as 64 layers, 96 layers, 128 layers, 176 layers, or 232 layers.

[0085] In one embodiment, the flash memory type information and stacking layer number information of the pre-test flash memory chip can be obtained by reading the production specification information of the pre-test flash memory chip.

[0086] Among them, the feature adaptation coefficient can be an empirical weighting coefficient related to flash memory type information and stacking layer information, used to adjust the influence of the standard deviation of the pre-test feature parameters on the bad block evaluation parameters.

[0087] In one embodiment, the method for determining the feature adaptation coefficient based on flash memory type information and stacking layer number information can be achieved by pre-constructing a mapping table between flash memory type information, stacking layer number information, and feature adaptation coefficients. The feature adaptation coefficient corresponding to the current flash memory type information and stacking layer number information can be obtained by querying this mapping table. As an example, the mapping table for flash memory type information, stacking layer number information, and feature adaptation coefficients can be as follows: if the flash memory type information is TLC and the stacking layer number is 64, the corresponding feature adaptation coefficient is 2.0; if the flash memory type information is TLC and the stacking layer number is 128, the corresponding feature adaptation coefficient is 2.5; if the flash memory type information is QLC and the stacking layer number is 128, the corresponding feature adaptation coefficient is 3.0; and if the flash memory type information is QLC and the stacking layer number is 176, the corresponding feature adaptation coefficient is 3.0.

[0088] In one embodiment, the method for calculating the average and standard deviation of the pre-test characteristic parameters can be as follows: after each erase / write cycle, for each flash block, calculate the average and standard deviation of the pre-test characteristic parameters (number of flash page rereads or number of flash page error bits or the normalized weighted sum of the number of flash page rereads and the number of flash page error bits, the same below) of each flash page in the flash block as the average and standard deviation of the pre-test characteristic parameters of the flash block after that erase / write cycle.

[0089] The formula for calculating the bad block evaluation parameters is as follows: The intermediate calculation result is obtained by multiplying the standard deviation by the characteristic fitting coefficient, and then the intermediate calculation result is added to the average value. .

[0090] The advantage of this scheme is that it makes the calculated bad block evaluation parameters more consistent with the actual wear distribution and avoids misjudgment or omission due to ignoring differences in flash memory technology.

[0091] The number of finite-cycle bad blocks at room temperature can be the number of newly identified bad blocks from the extracted flash memory chips during room temperature testing; the number of finite-cycle bad blocks at high temperature can be the number of newly identified bad blocks from the extracted flash memory chips during high-temperature testing. It can be understood that each extracted flash memory chip corresponds to one finite-cycle bad block count at room temperature and one finite-cycle bad block count at high temperature.

[0092] In one embodiment, the process of determining logical bad blocks in the extracted flash memory chips based on bad block evaluation parameters to obtain the number of room-temperature finite-cycle logical bad blocks and the number of high-temperature finite-cycle logical bad blocks in the extracted flash memory chips may include: if the bad block evaluation parameters corresponding to a flash block in the extracted flash memory chips exceed a preset bad block evaluation threshold after one erase / write cycle, then the flash block is logically determined to be a logical bad block; the number of logical bad blocks newly added in the room-temperature test of the extracted flash memory chips is counted as the number of room-temperature finite-cycle logical bad blocks of the extracted flash memory chips; and the number of logical bad blocks newly added in the high-temperature test of the extracted flash memory chips is counted as the number of high-temperature finite-cycle logical bad blocks of the extracted flash memory chips.

[0093] Specifically, if the bad block evaluation parameter value is determined solely based on the number of flash page rereads, the corresponding preset bad block evaluation threshold can be the upper limit of the allowed number of flash page rereads, such as 10 times; if the bad block evaluation parameter value is determined solely based on the number of flash page error bits, the corresponding preset bad block evaluation threshold can be the upper limit of the allowed number of flash page error bits, such as 32 bits; if the bad block evaluation parameter value is determined based on both the number of flash page rereads and the number of flash page error bits, the corresponding preset bad block evaluation threshold can be the upper limit of the normalized weighted sum of the number of flash page rereads and the number of flash page error bits, such as 0.8.

[0094] S103, perform a high-temperature cycle test on the extracted flash memory chip, and determine the number of physical bad blocks in the high-temperature cycle test. Stop the high-temperature cycle test when the number of physical bad blocks reaches a preset number, and obtain the number of high-temperature cycle erase / write cycles of the extracted flash memory chip.

[0095] The high-temperature cycling test involves continuously performing erase and write cycles on the extracted flash memory chips under high-temperature conditions until the number of physical bad blocks in the extracted flash memory chips reaches a preset number (i.e., they are judged as failed). Specifically, the number of physical bad blocks can be the number of newly added physical bad blocks that are physically judged as physical bad blocks in the extracted flash memory chips during the high-temperature cycling test; the preset number can be set according to the total number of flash memory blocks of the flash memory chips to be tested.

[0096] Here, the erase / write count can be the cumulative number of erase and write operations that a flash memory chip undergoes. Correspondingly, the high-temperature cycle erase / write count can be the total number of erase / write operations that each extracted flash memory chip undergoes from the start to failure in a high-temperature cycle test.

[0097] In one embodiment, a high-temperature cycling test is performed on the extracted flash memory chips, and the number of physical bad blocks is determined during the high-temperature cycling test. The high-temperature cycling test is stopped when the number of physical bad blocks reaches a preset number, and the number of high-temperature cycle erase / write cycles of the extracted flash memory chips is obtained. This can be achieved by continuously performing erase / write cycles on each extracted flash memory chip under high-temperature conditions, detecting the number of physical bad blocks of each extracted flash memory chip after each cycle, stopping the high-temperature cycling test when the cumulative number of physical bad blocks reaches a preset number, and recording the current cycle number as the number of high-temperature cycle erase / write cycles of the extracted flash memory chips.

[0098] In one embodiment, the method for determining physical bad blocks in the extracted flash memory chips can be as follows: if the erase operation returns a failure state, or the programming operation returns a failure state, or an uncorrectable ECC (Error Correcting Code) error occurs during reading, then the flash memory block is physically determined to be a physical bad block.

[0099] S104, Perform the same room temperature test and high temperature test as the extracted flash memory chip on the pre-test flash memory chip to obtain the number of pre-test room temperature finite cycle logic bad blocks and the number of pre-test high temperature finite cycle logic bad blocks on the pre-test flash memory chip.

[0100] Among them, the same room temperature test and high temperature test as the extracted flash memory chip can refer to the room temperature test and high temperature test using the same temperature and the same limited number of cycles as the extracted flash memory chip.

[0101] The number of pre-tested room temperature finite cycle logic bad blocks can be the number of logic bad blocks newly added to the flash memory chip during the room temperature test; the number of pre-tested high temperature finite cycle logic bad blocks can be the number of logic bad blocks newly added to the flash memory chip during the high temperature test.

[0102] In one embodiment, the process of performing the same room temperature test and high temperature test as the extracted flash memory chip on the pre-test flash memory chip to obtain the number of pre-test room temperature finite cycle logical bad blocks and the number of pre-test high temperature finite cycle logical bad blocks of the pre-test flash memory chip may include: if the bad block evaluation parameter corresponding to a flash block in the pre-test flash memory chip exceeds a preset bad block evaluation threshold after one erase / write cycle, then the flash block is logically determined to be a logical bad block; the number of logical bad blocks newly added in the room temperature test of the pre-test flash memory chip is counted as the number of pre-test room temperature finite cycle logical bad blocks of the pre-test flash memory chip; and the number of logical bad blocks newly added in the high temperature test of the pre-test flash memory chip is counted as the number of pre-test high temperature finite cycle logical bad blocks of the pre-test flash memory chip.

[0103] S105, based on the number of room-temperature finite-cycle bad blocks, the number of high-temperature finite-cycle bad blocks, and the number of high-temperature erase / write cycles of the extracted flash memory chip, and based on the number of pre-test room-temperature finite-cycle bad blocks and the number of pre-test high-temperature finite-cycle bad blocks of the pre-test flash memory chip, determine the target number of erase / write cycles of the pre-test flash memory chip.

[0104] The target number of erase / write cycles can be the predicted maximum number of erase / write cycles of the pre-tested flash memory chip under normal usage conditions.

[0105] In one embodiment, the target erasure count of a pre-tested flash memory chip is determined based on the number of room-temperature finite-cycle bad blocks, the number of high-temperature finite-cycle bad blocks, and the number of high-temperature erase / write cycles of the extracted flash memory chips, as well as the number of pre-test room-temperature finite-cycle bad blocks and the number of pre-test high-temperature finite-cycle bad blocks of the pre-tested flash memory chips. This can be achieved by using the number of room-temperature finite-cycle bad blocks, the number of high-temperature finite-cycle bad blocks, and the number of high-temperature erase / write cycles of each extracted flash memory chip as a three-dimensional coordinate point. The three-dimensional coordinate points corresponding to each extracted flash memory chip are fitted into a smooth curve. The corresponding three-dimensional coordinate point is located on the smooth curve based on the number of pre-test room-temperature finite-cycle bad blocks and the number of pre-test high-temperature finite-cycle bad blocks of a pre-tested flash memory chip. The number of high-temperature erase / write cycles at this three-dimensional coordinate point is read as the target erasure count of the pre-tested flash memory chip.

[0106] In this embodiment, flash memory chips are extracted from pre-test flash memory chips, and the extracted flash memory chips are subjected to room temperature and high temperature tests with a limited number of cycles to obtain corresponding pre-test characteristic parameters. The pre-test characteristic parameters include the number of flash page rereads and / or the number of flash page error bits, and the limited number of cycles is at least one. Bad block judgment parameters are determined based on the pre-test characteristic parameters, and logical bad block determination is performed on the extracted flash memory chips based on the bad block judgment parameters to obtain the number of room temperature limited-cycle logical bad blocks and the number of high temperature limited-cycle logical bad blocks for the extracted flash memory chips. High temperature cycling tests are performed on the extracted flash memory chips, and physical bad block determination is performed during the high temperature cycling tests to obtain the number of physical bad blocks. The high temperature cycling tests are stopped when the number of physical bad blocks reaches a preset number, to obtain the number of high temperature cycle erase / write cycles for the extracted flash memory chips. The same room temperature and high temperature tests as the extracted flash memory chips are performed on the pre-test flash memory chips to obtain the number of pre-test room temperature limited-cycle logical bad blocks and the number of pre-test high temperature limited-cycle logical bad blocks for the pre-test flash memory chips. The above-mentioned flash memory erase / write cycle prediction method supports accurate assessment of the erase / write cycles of all flash memory chips in mass production scenarios, reducing production testing losses and improving erase / write cycle detection efficiency.

[0107] Figure 2 This is a flowchart illustrating another flash memory erase / write cycle prediction method provided in an embodiment of this application. Figure 2 As shown, the specific steps include the following:

[0108] S201, extract flash memory chips from the pre-test flash memory chips, and perform room temperature testing and high temperature testing on the extracted flash memory chips for a limited number of cycles to obtain the corresponding pre-test characteristic parameters; wherein, the pre-test characteristic parameters include the number of flash page rereads and / or the number of flash page error bits, and the limited number of cycles is at least one.

[0109] S202, determine the maximum value among the pre-test feature parameters, and determine the bad block evaluation parameters based on the maximum value among the pre-test feature parameters.

[0110] The maximum value in the pre-test characteristic parameters can refer to the maximum value of the pre-test characteristic parameters of each flash page in each flash block after each erase / write cycle.

[0111] In one embodiment, the method of determining bad block evaluation parameters based on the maximum value among the pre-test feature parameters can be as follows: after each erase / write cycle, for each flash memory block, compare the pre-test feature parameters of each flash page in the flash memory block, and directly determine the maximum value among the pre-test feature parameters of each flash page as the bad block evaluation parameter corresponding to the flash memory block after that erase / write cycle.

[0112] In one embodiment, determining the bad block judgment parameter based on the maximum value among the pre-test feature parameters includes: determining a spatial influence coefficient based on the pre-test feature parameters and the flash memory page location corresponding to the pre-test feature parameters; and multiplying the spatial influence coefficient by the maximum value among the pre-test feature parameters to obtain the bad block judgment parameter.

[0113] The flash page location can be the physical sequence number or offset address of the flash page within its respective flash block.

[0114] Among them, the spatial influence coefficient can be a coefficient used to correct the impact of uneven wear distribution on the evaluation of bad block assessment parameters. The value range of the spatial influence coefficient is 0~1.

[0115] In one embodiment, the method of determining the spatial influence coefficient based on the pre-test feature parameters and the flash page positions corresponding to the pre-test feature parameters can be achieved by determining the wear centroid position for each flash block after each erase / write cycle, based on the flash page positions of each flash page in the flash block and the pre-test feature parameters, and then normalizing the deviation between the wear centroid position and the center position within the block to determine the spatial influence coefficient of the flash block after that erase / write cycle.

[0116] In one embodiment, the method for determining the wear centroid location based on the flash page location of each flash page in the flash memory block and the pre-test feature parameters can be to use the pre-test feature parameters of each flash page as weights to perform a weighted summation of the flash page locations of each flash page, and then divide by the sum of all pre-test feature parameters to obtain the wear centroid location.

[0117] In one embodiment, the method of multiplying the spatial influence coefficient by the maximum value in the pre-test characteristic parameters to obtain the bad block evaluation parameters can be achieved by multiplying the spatial influence coefficient of the flash memory block by the maximum value in the pre-test characteristic parameters after each erase / write cycle for each flash memory block to obtain the bad block evaluation parameters corresponding to that flash memory block after that erase / write cycle.

[0118] In one embodiment, determining the spatial influence coefficient based on the pre-test feature parameters and the corresponding flash memory page locations includes: identifying flash memory page locations where the pre-test feature parameters exceed a preset threshold as bad page locations, performing cluster analysis on the bad page locations to obtain each cluster and the coverage radius of each cluster; calculating the ratio of the maximum value among the coverage radii of each cluster to the total number of flash memory pages in the pre-test flash memory chip, and calculating the difference between the maximum value and the average value of the pre-test feature parameters; and calculating the spatial influence coefficient based on the ratio and the difference.

[0119] The preset threshold can be a critical value used to determine whether a flash memory page has abnormal wear or abnormal errors. The value of the preset threshold can be the same as the value of the preset bad block judgment threshold mentioned above.

[0120] The bad page location can be the location of a flash page in a flash block whose pre-test characteristic parameters are abnormal (i.e., there is obvious wear or error). If the pre-test characteristic parameters exceed a preset threshold, it means that the flash page has experienced significant abnormal wear or data errors, and its reliability has decreased significantly. Therefore, the corresponding flash page location can be identified as the bad page location.

[0121] Here, a cluster can be a set of bad page locations that are geographically close and concentrated; the coverage radius can be the maximum distance between all bad page locations within a cluster and the cluster center.

[0122] In one embodiment, clustering analysis of bad page locations to obtain each cluster and its coverage radius can be performed using a density-based clustering algorithm. This algorithm can determine the cluster center of each cluster and calculate the maximum distance from each bad page location within a cluster to the cluster center as the coverage radius of the corresponding cluster.

[0123] The total number of flash pages in the pre-test flash memory chip can refer to the total number of flash pages included in a flash block within the pre-test flash memory chip.

[0124] The ratio of the maximum coverage radius of each cluster to the total number of flash pages in the pre-test flash memory chip can be used to characterize the concentration and spatial spread of bad pages within the flash memory block. The difference between the maximum and average values ​​of the pre-test characteristic parameters can be used to characterize the impact of the most abnormal page on the overall evaluation.

[0125] In one embodiment, the spatial influence coefficient can be calculated by weighting and summing the ratio and the difference and then normalizing the result to obtain the spatial influence coefficient.

[0126] The advantage of this scheme is that it can dynamically correct the evaluation results by combining the spatial distribution concentration of bad pages with the degree of parameter anomaly, reducing the interference of local concentrated anomalies or single-point extreme anomalies on the judgment of logic bad blocks, and improving the rationality and stability of bad block evaluation.

[0127] In one embodiment, determining the spatial influence coefficient based on the pre-test feature parameters and the flash page positions corresponding to the pre-test feature parameters includes: identifying flash page positions where the pre-test feature parameters exceed a preset threshold as bad page positions, and calculating the shortest distance between each bad page position and other bad page positions; calculating the average of each shortest distance as a first average, and calculating the average of the pre-test feature parameters as a second average; and calculating the spatial influence coefficient based on the first average and the second average.

[0128] The shortest distance between each bad page location and other bad page locations can be the distance between the bad page location and its nearest neighbor bad page location.

[0129] The average value of each shortest distance (first average value) can be used to characterize the spatial density of bad pages within a flash memory block; the average value of the pre-test characteristic parameters (second average value) can be used to characterize the overall wear or error level of bad pages.

[0130] In one embodiment, the spatial influence coefficient can be calculated by weighting and summing the first and second average values ​​and then normalizing the result to obtain the spatial influence coefficient.

[0131] The advantage of this scheme is that it can simultaneously combine the spatial distribution characteristics of bad pages with the overall anomaly level to achieve adaptive adjustment of the spatial influence coefficient, more accurately reflect the actual impact of wear distribution on the determination of logical bad blocks, and improve the reliability and stability of bad block identification.

[0132] The advantage of this scheme is that it can dynamically adjust the spatial influence coefficient according to the spatial distribution of wear. When the wear centroid deviates from the center, the bad block evaluation parameter is appropriately reduced to avoid misjudgment caused by the bad block evaluation parameter being too large due to local abnormal wear, thereby improving the accuracy and stability of bad block identification.

[0133] S203, based on the bad block evaluation parameters, the extracted flash memory chips are judged for logical bad blocks to obtain the number of room temperature finite cycle logical bad blocks and the number of high temperature finite cycle logical bad blocks of the extracted flash memory chips.

[0134] S204, perform a high-temperature cycle test on the extracted flash memory chip, and determine the number of physical bad blocks during the high-temperature cycle test. Stop the high-temperature cycle test when the number of physical bad blocks reaches a preset number, and obtain the number of high-temperature cycle erase / write cycles of the extracted flash memory chip.

[0135] S205, perform the same room temperature test and high temperature test as the extracted flash memory chip on the pre-test flash memory chip to obtain the number of pre-test room temperature finite cycle logic bad blocks and the number of pre-test high temperature finite cycle logic bad blocks on the pre-test flash memory chip.

[0136] S206, based on the number of room-temperature finite-cycle bad blocks, the number of high-temperature finite-cycle bad blocks, and the number of high-temperature erase / write cycles of the extracted flash memory chip, and based on the number of pre-test room-temperature finite-cycle bad blocks and the number of pre-test high-temperature finite-cycle bad blocks of the pre-test flash memory chip, determine the target number of erase / write cycles of the pre-test flash memory chip.

[0137] The advantage of this scheme is that by directly taking the maximum value of the pre-test characteristic parameters of each flash page in the flash block as the bad block judgment parameter, it can capture the wear state of the worst page in the flash block with the most stringent standard, thereby improving the sensitivity of logic bad block judgment.

[0138] Figure 3 This is a flowchart illustrating another flash memory erase / write cycle prediction method provided in an embodiment of this application. Figure 3 As shown, the specific steps include the following:

[0139] S301, extract flash memory chips from the pre-test flash memory chips, and perform room temperature test and high temperature test on the extracted flash memory chips for a limited number of cycles to obtain the corresponding pre-test characteristic parameters; wherein, the pre-test characteristic parameters include the number of flash page rereads and / or the number of flash page error bits, and the limited number of cycles is at least one.

[0140] S302, bad block evaluation parameters are determined based on the pre-test feature parameters, and logical bad blocks are determined on the extracted flash memory chips based on the bad block evaluation parameters to obtain the number of room temperature finite cycle logical bad blocks and the number of high temperature finite cycle logical bad blocks of the extracted flash memory chips.

[0141] S303, perform a high-temperature cycle test on the extracted flash memory chip, and determine the number of physical bad blocks during the high-temperature cycle test. Stop the high-temperature cycle test when the number of physical bad blocks reaches a preset number, and obtain the number of high-temperature cycle erase / write cycles of the extracted flash memory chip.

[0142] S304, Perform the same room temperature test and high temperature test as the extracted flash memory chip on the pre-test flash memory chip to obtain the number of pre-test room temperature finite cycle logic bad blocks and the number of pre-test high temperature finite cycle logic bad blocks on the pre-test flash memory chip.

[0143] S305, calculate the difference between the number of pre-test high-temperature finite-cycle bad blocks of the pre-test flash memory chip and the number of high-temperature finite-cycle bad blocks of the extracted flash memory chip as the first difference value corresponding to the extracted flash memory chip, and determine the extracted flash memory chip corresponding to the minimum value of the first difference value as the target flash memory chip.

[0144] The difference between the number of pre-tested high-temperature finite-cycle bad blocks in a pre-tested flash memory chip and the number of high-temperature finite-cycle bad blocks in the extracted flash memory chips (the first difference for each extracted flash memory chip for the pre-tested flash memory chip) can be used to characterize the similarity of the wear degree of the pre-tested flash memory chip and each extracted flash memory chip under high-temperature conditions. Understandably, the smaller the first difference, the closer the high-temperature wear characteristics of the two are.

[0145] The target flash memory chip can be the extracted flash memory chip that is most similar to the high-temperature wear characteristics of the pre-test flash memory chip, and its high-temperature cycle erase / write count can be used as the core reference for the erase / write life of the pre-test flash memory chip.

[0146] Among them, the flash memory chip corresponding to the minimum value in the first difference is determined as the target flash memory chip, that is, the reference sample that best matches the high temperature wear characteristics of the chip to be tested is selected.

[0147] S306, when the number of target flash memory chips is one, the number of high-temperature cycle erase / write cycles of the target flash memory chip is determined as the target number of erase / write cycles of the pre-test flash memory chip.

[0148] The target flash memory chip is one, indicating that there is a unique flash memory chip that best matches the high-temperature wear characteristics of the pre-test flash memory chip. The reliability performance of the two chips in high-temperature environments is highly consistent. Therefore, the number of high-temperature cycle erase / write cycles of the target flash memory chip can be directly determined as the target erase / write cycles of the pre-test flash memory chip.

[0149] S307, when the number of target flash memory chips is not one, calculate the difference between the number of pre-test room temperature finite cycle bad blocks of the pre-test flash memory chip and the number of room temperature finite cycle bad blocks of the target flash memory chip as the second difference corresponding to the target flash memory chip, and determine the high temperature cycle erase / write count of the target flash memory chip corresponding to the minimum value of the second difference as the target erase / write count of the pre-test flash memory chip.

[0150] The number of target flash memory chips is not one, indicating that there are multiple extracted flash memory chips with similar high-temperature wear characteristics to the pre-test flash memory chips. The number of high-temperature bad blocks alone cannot uniquely identify the best matching sample, so room-temperature wear characteristics need to be introduced as a secondary screening dimension.

[0151] The difference between the number of pre-tested room-temperature finite-cycle bad blocks in a pre-test flash memory chip and the number of room-temperature finite-cycle bad blocks in a target flash memory chip (the second difference for each target flash memory chip for the pre-tested flash memory chip) can be used to characterize the similarity of the wear degree between the pre-tested flash memory chip and each target flash memory chip under room-temperature conditions. Understandably, the smaller the second difference, the higher the consistency of their room-temperature wear characteristics.

[0152] Specifically, the number of high-temperature cycle erase / write cycles of the target flash memory chip corresponding to the minimum value in the second difference is determined as the target erasure / write count of the pre-test flash memory chip. That is, the reference sample that best matches the room-temperature wear characteristics of the chip to be tested is uniquely locked in the target flash memory chip, and the number of high-temperature cycle erase / write cycles of the reference sample is directly transferred as the target erasure / write count of the pre-test flash memory chip.

[0153] This solution first selects high-temperature wear characteristics as the primary matching dimension. The core reason is that high temperature is a key factor in accelerating the wear and reliability degradation of flash memory chips. The number of new bad blocks under high-temperature conditions can more directly reflect the inherent lifespan potential of flash memory chips. Using this as the priority matching standard can quickly identify the reference sample that is closest to the core lifespan characteristics of the flash memory chip to be tested, laying the foundation for accurate prediction. When there are multiple samples that match the high-temperature wear characteristics, room-temperature wear characteristics are further introduced for secondary screening. This is because room temperature is the normal operating scenario for flash memory chips, and its wear characteristics can reflect the stability differences of flash memory chips in daily use. Through the two-layer matching logic of high-temperature priority matching and room-temperature secondary screening, the matching efficiency and the reliability of the prediction results can be improved.

[0154] Figure 4 This is a schematic diagram of a flash memory erase / write cycle prediction device provided in an embodiment of this application. Figure 4 As shown, the device includes:

[0155] The feature parameter acquisition module 410 is used to extract flash memory chips from the pre-test flash memory chips and perform room temperature and high temperature tests on the extracted flash memory chips for a limited number of cycles to obtain the corresponding pre-test feature parameters; wherein, the pre-test feature parameters include the number of flash page rereads and / or the number of flash page error bits, and the limited number of cycles is at least one;

[0156] The bad block quantity determination module 420 is used to determine bad block evaluation parameters based on the pre-test feature parameters, and to perform logical bad block determination on the extracted flash memory chips based on the bad block evaluation parameters, so as to obtain the number of room temperature finite cycle logical bad blocks and the number of high temperature finite cycle logical bad blocks of the extracted flash memory chips.

[0157] The high-temperature cycle test module 430 is used to perform a high-temperature cycle test on the extracted flash memory chip, and to determine the number of physical bad blocks in the high-temperature cycle test. When the number of physical bad blocks reaches a preset number, the high-temperature cycle test is stopped, and the number of high-temperature cycle erase and write cycles of the extracted flash memory chip is obtained.

[0158] The pre-test bad block determination module 440 is used to perform the same room temperature test and high temperature test as the extracted flash memory chip on the pre-test flash memory chip to obtain the number of pre-test room temperature finite cycle logic bad blocks and the number of pre-test high temperature finite cycle logic bad blocks of the pre-test flash memory chip.

[0159] The erasable write count determination module 450 is used to determine the target erasable write count of the pre-test flash memory chip based on the number of room temperature finite cycle logical bad blocks, the number of high temperature finite cycle logical bad blocks, and the number of high temperature cycle erase / write cycles of the extracted flash memory chip, as well as based on the number of pre-test room temperature finite cycle logical bad blocks and the number of pre-test high temperature finite cycle logical bad blocks of the pre-test flash memory chip.

[0160] Furthermore, the bad block count determination module 420 is specifically used for:

[0161] Determine the maximum value among the pre-test feature parameters, and determine the bad block evaluation parameters based on the maximum value among the pre-test feature parameters.

[0162] Furthermore, the bad block count determination module 420 is specifically used for:

[0163] The spatial influence coefficient is determined based on the pre-test feature parameters and the flash page positions corresponding to the pre-test feature parameters.

[0164] Multiply the spatial influence coefficient by the maximum value among the pre-test feature parameters to obtain the bad block evaluation parameters.

[0165] Furthermore, the bad block count determination module 420 is specifically used for:

[0166] The flash memory page locations where the pre-test feature parameters exceed a preset threshold are identified as bad page locations, and cluster analysis is performed on the bad page locations to obtain each cluster and the coverage radius of each cluster.

[0167] Calculate the ratio of the maximum value of the coverage radius of each cluster to the total number of flash pages of the pre-test flash memory chip, and calculate the difference between the maximum value and the average value of the pre-test feature parameters;

[0168] The spatial influence coefficient is calculated based on the ratio and the difference.

[0169] Furthermore, the bad block count determination module 420 is specifically used for:

[0170] The flash memory page locations where the pre-test feature parameters exceed a preset threshold are identified as bad page locations, and the shortest distance between each bad page location and other bad page locations is calculated.

[0171] The average value of each of the shortest distances is calculated as the first average value, and the average value of the pre-test feature parameters is calculated as the second average value;

[0172] The spatial influence coefficient is calculated based on the first average value and the second average value.

[0173] Furthermore, the bad block count determination module 420 is specifically used for:

[0174] Obtain the flash memory type information and stacking layer number information of the pre-tested flash memory chip, and determine the feature adaptation coefficient based on the flash memory type information and the stacking layer number information;

[0175] The mean and standard deviation of the pre-test characteristic parameters are statistically analyzed;

[0176] Multiply the standard deviation by the characteristic fitting coefficient to obtain an intermediate calculation result, and add the intermediate calculation result to the average value to obtain the bad block evaluation parameters.

[0177] Furthermore, the erasable / rewrite count determination module 450 is specifically used for:

[0178] The difference between the number of pre-test high-temperature finite cycle logic bad blocks of the pre-test flash memory chip and the number of high-temperature finite cycle logic bad blocks of the extracted flash memory chip is calculated as the first difference value corresponding to the extracted flash memory chip, and the extracted flash memory chip corresponding to the minimum value of the first difference value is determined as the target flash memory chip.

[0179] When the number of target flash memory chips is one, the number of high-temperature cycle erase / write cycles of the target flash memory chip is determined as the target number of erase / write cycles of the pre-test flash memory chip;

[0180] When the number of target flash memory chips is not one, the difference between the number of pre-test room temperature finite cycle bad blocks of the pre-test flash memory chip and the number of room temperature finite cycle bad blocks of the target flash memory chip is calculated as the second difference corresponding to the target flash memory chip, and the number of high temperature cycle erase / write cycles of the target flash memory chip corresponding to the minimum value of the second difference is determined as the target erasure / write cycle of the pre-test flash memory chip.

[0181] In this embodiment, a feature parameter acquisition module is used to extract flash memory chips from the pre-test flash memory chips and perform room temperature and high temperature tests on the extracted flash memory chips with a limited number of cycles to obtain corresponding pre-test feature parameters; wherein, the pre-test feature parameters include the number of flash page rereads and / or the number of flash page error bits, and the limited number of cycles is at least one; a bad block quantity determination module is used to determine bad block judgment parameters based on the pre-test feature parameters, and perform logical bad block judgment on the extracted flash memory chips based on the bad block judgment parameters to obtain the number of room temperature limited cycle logical bad blocks and the number of high temperature limited cycle logical bad blocks of the extracted flash memory chips; a high temperature cycle test module is used to perform high temperature cycle tests on the extracted flash memory chips, and perform physical bad block judgment in the high temperature cycle test to obtain The high-temperature cycle test is stopped when the number of physical bad blocks reaches a preset number, thus obtaining the high-temperature cycle erase / write count of the extracted flash memory chip. A pre-test bad block determination module is used to perform the same room-temperature and high-temperature tests on the pre-test flash memory chip as on the extracted flash memory chip, obtaining the pre-test room-temperature finite cycle logical bad block count and the pre-test high-temperature finite cycle logical bad block count of the pre-test flash memory chip. An erasable write count determination module is used to determine the target erasable write count of the pre-test flash memory chip based on the room-temperature finite cycle logical bad block count, the high-temperature finite cycle logical bad block count, and the high-temperature cycle erase / write count of the extracted flash memory chip, as well as based on the pre-test room-temperature finite cycle logical bad block count and the pre-test high-temperature finite cycle logical bad block count of the pre-test flash memory chip. The above flash memory erase / write count prediction device supports accurate evaluation of the erase / write count of all flash memory chips in mass production scenarios, reducing production testing losses and improving erase / write count detection efficiency.

[0182] The flash memory erase / write cycle prediction device in this application embodiment can be a device, or a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. For example, mobile electronic devices can be mobile phones, tablets, laptops, PDAs, in-vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc., while non-mobile electronic devices can be servers, network attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This application embodiment does not impose specific limitations.

[0183] The flash memory erase / write cycle prediction device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit it.

[0184] The flash memory erase / write cycle prediction device provided in this application embodiment can realize the various processes implemented in the above embodiments. To avoid repetition, it will not be described again here.

[0185] Figure 5 This is a schematic diagram of the structure of an electronic device provided in Embodiment 5 of this application. Figure 5 As shown, this application embodiment also provides an electronic device 500, including a processor 501, a memory 502, and a program or instructions stored in the memory 502 and executable on the processor 501. When the program or instructions are executed by the processor 501, they implement the various processes of the above-described flash memory erase / write cycle prediction embodiment and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0186] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0187] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described flash memory erase / write cycle prediction embodiment and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0188] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0189] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0190] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0191] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0192] The above description is merely a preferred embodiment and the technical principles employed in this application. This application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions that can be made by those skilled in the art will not depart from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the claims.

Claims

1. A method for predicting the number of erase / write cycles of a flash memory, characterized in that, The method includes: Flash memory chips are extracted from the pre-test flash memory chips, and the extracted flash memory chips are subjected to room temperature testing and high temperature testing with a limited number of cycles to obtain the corresponding pre-test characteristic parameters; wherein, the pre-test characteristic parameters include the number of flash page rereads and / or the number of flash page error bits, and the limited number of cycles is at least one; Based on the pre-test feature parameters, bad block judgment parameters are determined, and based on the bad block judgment parameters, logical bad blocks are judged on the extracted flash memory chips to obtain the number of room temperature finite cycle logical bad blocks and the number of high temperature finite cycle logical bad blocks of the extracted flash memory chips. The extracted flash memory chips are subjected to high-temperature cycling tests, and physical bad blocks are determined during the high-temperature cycling tests to obtain the number of physical bad blocks. The high-temperature cycling tests are stopped when the number of physical bad blocks reaches a preset number, and the number of high-temperature cycle erase / write cycles of the extracted flash memory chips is obtained. For the pre-test flash memory chip, perform the same room temperature test and high temperature test as the extracted flash memory chip to obtain the number of pre-test room temperature finite cycle logic bad blocks and the number of pre-test high temperature finite cycle logic bad blocks for the pre-test flash memory chip; Based on the number of room-temperature finite-cycle bad blocks, the number of high-temperature finite-cycle bad blocks, and the number of high-temperature erase / write cycles of the extracted flash memory chips, and based on the number of pre-test room-temperature finite-cycle bad blocks and the number of pre-test high-temperature finite-cycle bad blocks of the pre-test flash memory chips, the target number of erase / write cycles for the pre-test flash memory chips is determined, including: calculating the difference between the number of pre-test high-temperature finite-cycle bad blocks of the pre-test flash memory chips and the number of high-temperature finite-cycle bad blocks of the extracted flash memory chips as the first difference corresponding to the extracted flash memory chips, and assigning the minimum value of the first difference to the extracted flash memory chips. The target flash memory chip is identified as one; if there is only one target flash memory chip, the number of high-temperature cycle erase / write cycles of the target flash memory chip is determined as the target erasure / write count of the pre-test flash memory chip; if there is more than one target flash memory chip, the difference between the number of pre-test room-temperature finite cycle logic bad blocks of the pre-test flash memory chip and the number of room-temperature finite cycle logic bad blocks of the target flash memory chip is calculated as the second difference corresponding to the target flash memory chip, and the number of high-temperature cycle erase / write cycles of the target flash memory chip corresponding to the minimum value of the second difference is determined as the target erasure / write count of the pre-test flash memory chip.

2. The flash memory erase / write cycle prediction method according to claim 1, characterized in that, The step of determining bad block evaluation parameters based on the pre-test feature parameters includes: Determine the maximum value among the pre-test feature parameters, and determine the bad block evaluation parameters based on the maximum value among the pre-test feature parameters.

3. The flash memory erase / write cycle prediction method according to claim 2, characterized in that, The step of determining the bad block evaluation parameters based on the maximum value among the pre-test feature parameters includes: The spatial influence coefficient is determined based on the pre-test feature parameters and the flash page positions corresponding to the pre-test feature parameters. Multiply the spatial influence coefficient by the maximum value among the pre-test feature parameters to obtain the bad block evaluation parameters.

4. The flash memory erase / write cycle prediction method according to claim 3, characterized in that, The determination of the spatial influence coefficient based on the pre-test feature parameters and the corresponding flash page positions includes: The flash memory page locations where the pre-test feature parameters exceed a preset threshold are identified as bad page locations, and cluster analysis is performed on the bad page locations to obtain each cluster and the coverage radius of each cluster. Calculate the ratio of the maximum value of the coverage radius of each cluster to the total number of flash pages of the pre-test flash memory chip, and calculate the difference between the maximum value and the average value of the pre-test feature parameters; The spatial influence coefficient is calculated based on the ratio and the difference.

5. The flash memory erase / write cycle prediction method according to claim 3, characterized in that, The determination of the spatial influence coefficient based on the pre-test feature parameters and the corresponding flash page positions includes: The flash memory page locations where the pre-test feature parameters exceed a preset threshold are identified as bad page locations, and the shortest distance between each bad page location and other bad page locations is calculated. The average value of each of the shortest distances is calculated as the first average value, and the average value of the pre-test feature parameters is calculated as the second average value; The spatial influence coefficient is calculated based on the first average value and the second average value.

6. The flash memory erase / write cycle prediction method according to claim 1, characterized in that, The step of determining bad block evaluation parameters based on the pre-test feature parameters includes: Obtain the flash memory type information and stacking layer number information of the pre-tested flash memory chip, and determine the feature adaptation coefficient based on the flash memory type information and the stacking layer number information; The mean and standard deviation of the pre-test characteristic parameters are statistically analyzed; Multiply the standard deviation by the characteristic fitting coefficient to obtain an intermediate calculation result, and add the intermediate calculation result to the average value to obtain the bad block evaluation parameters.

7. A flash memory erase / write cycle prediction device, characterized in that, The device includes: The feature parameter acquisition module is used to extract flash memory chips from the pre-test flash memory chips and perform room temperature and high temperature tests on the extracted flash memory chips for a limited number of cycles to obtain the corresponding pre-test feature parameters; wherein, the pre-test feature parameters include the number of flash page rereads and / or the number of flash page error bits, and the limited number of cycles is at least one; The bad block quantity determination module is used to determine bad block evaluation parameters based on the pre-test feature parameters, and to perform logical bad block determination on the extracted flash memory chips based on the bad block evaluation parameters, so as to obtain the number of room temperature finite cycle logical bad blocks and the number of high temperature finite cycle logical bad blocks of the extracted flash memory chips. The high-temperature cycle test module is used to perform high-temperature cycle tests on the extracted flash memory chips, and to determine the number of physical bad blocks during the high-temperature cycle test. When the number of physical bad blocks reaches a preset number, the high-temperature cycle test is stopped, and the number of high-temperature cycle erase / write cycles of the extracted flash memory chips is obtained. The pre-test bad block determination module is used to perform the same room temperature test and high temperature test on the pre-test flash memory chip as the extracted flash memory chip, and obtain the number of pre-test room temperature finite cycle logic bad blocks and the number of pre-test high temperature finite cycle logic bad blocks of the pre-test flash memory chip. The erasable write count determination module is used to determine the target erasable write count of the pre-test flash memory chip based on the number of room temperature finite cycle logical bad blocks, the number of high temperature finite cycle logical bad blocks, and the number of high temperature cycle erase and write counts of the extracted flash memory chip, as well as based on the number of pre-test room temperature finite cycle logical bad blocks and the number of pre-test high temperature finite cycle logical bad blocks of the pre-test flash memory chip. The erase / write count determination module is specifically used for: calculating the difference between the number of pre-test high-temperature finite-cycle bad blocks of the pre-test flash memory chip and the number of high-temperature finite-cycle bad blocks of the extracted flash memory chip as the first difference value corresponding to the extracted flash memory chip, and determining the extracted flash memory chip corresponding to the minimum value of the first difference value as the target flash memory chip; when the number of target flash memory chips is one, determining the high-temperature cycle erase / write count of the target flash memory chip as the target erase / write count of the pre-test flash memory chip; when the number of target flash memory chips is not one, calculating the difference between the number of pre-test room-temperature finite-cycle bad blocks of the pre-test flash memory chip and the number of room-temperature finite-cycle bad blocks of the target flash memory chip as the second difference value corresponding to the target flash memory chip, and determining the high-temperature cycle erase / write count of the target flash memory chip corresponding to the minimum value of the second difference value as the target erase / write count of the pre-test flash memory chip.

8. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the flash memory erase / write cycle prediction method as described in any one of claims 1-6.

9. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions, which, when executed by a processor, implement the flash memory erase / write cycle prediction method as described in any one of claims 1-6.

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