Image sensor, electronic equipment and method

Abstract

The invention provides an image sensor, an electronic device and a method, the image sensor comprises a pixel, a comparator, a digital-to-analog converter, a digital processing circuit, a correction module and a first controller, the first controller is used for responding to a received black level correction signal output by the digital processing circuit and controlling the correction module to output a correction signal, a first signal output by the digital-to-analog converter is combined with the correction signal and then is output to a first input end of the comparator; the correction signal is a decimal multiple of the first signal. Therefore, as the signals input to the comparator comprise the first signal and the correction signal, and the correction signal is decimal times of the first signal, the comparator can perform decimal bit correction on the black level, so that the digital processing circuit only needs to perform integer bit correction on the black level, and on the basis of realizing high-precision decimal bit correction, the correction efficiency of the black level is improved. And the operand and the power consumption increment of the digital processing circuit are reduced.

Description

Technical Field

[0001] This application relates to the field of image processing technology, and in particular to an image sensor, electronic device and method. Background Technology

[0002] Image sensors are widely used in electronic devices such as digital cameras and mobile phones to form digital images. A traditional image sensor includes a pixel array and a readout circuit. The pixel array includes multiple pixels arranged in an array. Each pixel includes a photoelectric device and a pixel circuit. The photoelectric device is used to convert the sensed light signal into an electrical signal, and the pixel circuit is used to output a voltage related to the electrical signal. The readout circuit includes an analog-to-digital converter circuit and a digital processing circuit. The voltage output by the pixel circuit is sequentially fed into the analog-to-digital converter circuit and the digital processing circuit to realize image construction.

[0003] However, due to the dark current characteristics of optoelectronic devices, the analog-to-digital converter outputs a non-zero signal to the digital processor circuit without exposure, resulting in an image that is not perfectly black, affecting imaging accuracy. To avoid the influence of dark current, black level correction is usually performed in the digital processing circuit. However, when performing decimal-level black level correction, in order to improve the correction accuracy, the amount of data processing often increases significantly, leading to an increase in the computational load and power consumption of the digital processing circuit. Summary of the Invention

[0004] This application provides an image sensor, electronic device, and method for reducing the computational load and power consumption of digital processing circuits while achieving high-precision decimal correction.

[0005] In a first aspect, embodiments of this application provide an image processor. The image sensor includes: pixels, a comparator, a digital-to-analog converter (DAC), and a digital processing circuit. The DAC is connected to a first input terminal of the comparator, the pixels are connected to a second input terminal of the comparator, and the output terminal of the comparator is connected to the digital processing circuit. The image sensor further includes a calibration module and a first controller. The calibration module is connected to the first controller and the first input terminal of the comparator, respectively. The first controller is also connected to the digital processing circuit. The first controller is configured to: in response to receiving a black-level calibration signal output by the digital processing circuit, control the calibration module to output a calibration signal. The first signal output by the DAC and the calibration signal are combined and output to the first input terminal of the comparator. The calibration signal is a fractional multiple of the first signal.

[0006] Thus, since the input to the first terminal of the comparator is the combined signal, i.e., the reference signal, this reference signal includes both the first signal and the correction signal. When the comparator outputs a signal to the digital processing circuit based on this reference signal and the second signal output by the pixel, because the correction signal is a fractional multiple of the first signal, the comparator can perform fractional-level correction on the black level. This allows the digital processing circuit to perform integer-level correction only on the black level, thereby achieving fractional-level correction on the analog side and integer-level correction on the digital side. This avoids the increased computational load and power consumption caused by performing fractional-level correction on the digital side, reducing the computational load and power consumption of the digital processing circuit while achieving high-precision fractional-level correction. It should be understood that the analog side refers to the entire assembly consisting of the comparator, digital-to-analog converter, correction module, and first controller, while the digital side refers to the digital processing circuit.

[0007] Optionally, the first controller is specifically configured to: in response to receiving a black level correction signal output by the digital processing circuit, control the correction module to output a correction signal corresponding to the gear position signal according to the gear position signal output by the digital processing circuit. This ensures that the correction signal output by the correction module meets the correction requirements, thereby further improving the imaging effect.

[0008] Optionally, the calibration module includes multiple calibration branches arranged in parallel, each connected to a connection node and a first controller. The first controller is specifically used to: in response to receiving a black-level calibration signal, control at least a portion of the multiple calibration branches to inject a first current into the connection node; wherein, the connection node is the node formed by connecting the first input terminals of the calibration module, the digital-to-analog converter, and the comparator, and the calibration signal is determined based on the first current. Thus, the first controller can determine the calibration branches to be controlled as needed, and when entering the black-level calibration stage upon receiving a black-level calibration signal, one or more calibration branches controlled by the first controller can inject a first current into the connection node; if one calibration branch outputs a first current under the control of the first controller, the calibration signal can be determined based on this first current; if multiple calibration branches output a first current under the control of the first controller, these first currents will converge at the connection node to form a calibration signal, so the calibration signal is determined based on the sum of these first currents; thereby, the function of the calibration module is achieved through multiple calibration branches.

[0009] Furthermore, the first current injected into the connection node differs among the various correction branches. This allows for combinations of multiple correction branches, resulting in more diverse and refined values ​​for the output first current, thus enabling more precise decimal correction.

[0010] Furthermore, the first current injected into the connection node by each correction branch is (1 / m) of the current value of the first signal.n The formula is: m > 1, n is a positive integer. This allows the first current to be a fractional multiple of the first signal's current value, and thus the correction signal to be a fractional multiple of the first signal, achieving fractional-level correction of the black level.

[0011] Optionally, each correction branch includes a first current source and a first switch. The first switch is connected between the first current source and the connection node, and is also connected to a first controller. Specifically, the first controller is used to: in response to receiving a black-level correction signal, control at least a portion of the first switches to connect the corresponding first current source and the first input terminal of the comparator. Thus, when the first switch is closed under the control of the first controller, it connects the corresponding first current source and the connection node. The current provided by the corresponding first current source can be transmitted to the connection node as a first current, thereby injecting a first current into the connection node through the correction branch, thus realizing the function of the correction module.

[0012] Optionally, the digital-to-analog converter includes: a resistor and multiple current branches connected in parallel, each current branch being connected to a first end of the resistor and a connection node, the first end of the resistor also being connected to the connection node, and a second end of the resistor being connected to a first voltage terminal; the image sensor also includes a second controller, which is connected to the multiple current branches and a digital processing circuit, respectively. The second controller is used to: in response to receiving a black level correction signal, control the multiple current branches to inject a second current into the connection node; wherein, the first signal is determined based on the second current. Thus, when a black level correction signal is received, it indicates that black level correction is required, at least some correction branches output the first current, and all current branches output the second current; under the action of the resistor, the first current and the second current converge at the connection node and are converted into a corresponding voltage signal. This voltage signal can be regarded as a signal combining the first signal and the correction signal, thereby achieving decimal point correction.

[0013] Furthermore, the second controller is also used to control multiple current branches according to the first control signal; wherein, within any period of the first control signal, when the first control signal is at its first rising edge, the multiple current branches are controlled to inject a second current into the connection node; when the first control signal is at its first falling edge and its second falling edge, the multiple current branches are controlled to sequentially stop injecting the second current into the connection node; when all the multiple current branches have stopped injecting the second current, some of the multiple current branches are controlled to inject the second current into the connection node; the time period from the moment when the first control signal is at its first falling edge to the moment when the black level correction signal is received is the first quantization stage; the time period from the moment when the first control signal is at its second falling edge to the moment when all the multiple current branches have stopped injecting the second current is the second quantization stage; the pixel includes a photoelectric device and a pixel circuit, the pixel circuit being connected to the second input terminal of the photoelectric device and the comparator respectively; in the first quantization stage, the photoelectric device is disconnected from the second input terminal of the comparator under the control of the pixel circuit; in the second quantization stage, the photoelectric device is connected to the second input terminal of the comparator under the control of the pixel circuit.

[0014] In this way, all current branches are activated twice, realizing two quantization processes. The first quantization process can be regarded as the quantization of interference factors in the pixel, and the second quantization process can be regarded as the quantization of interference factors in the pixel and the second signal output by the pixel. The quantized values ​​obtained from these two quantization processes can be output to the digital processing circuit through the comparator. After obtaining the quantized values ​​from the two quantization processes, the digital processing circuit subtracts the quantized value obtained from the first quantization process from the quantized value obtained from the second quantization process, which is the quantized value of the second signal output by the pixel. This increases the accuracy of the quantization value, avoids the influence of interference factors, and thus helps to improve the imaging effect.

[0015] Secondly, embodiments of this application also provide a method for black level decimal correction, applied to an image processor. The image processor includes: pixels, a comparator, a digital-to-analog converter (DAC), and a digital processing circuit. The DAC is connected to a first input terminal of the comparator, the pixels are connected to a second input terminal of the comparator, and the output terminal of the comparator is connected to the digital processing circuit. The image sensor also includes a correction module and a first controller. The correction module is connected to the first controller and the first input terminal of the comparator, respectively. The first controller is also connected to the digital processing circuit. The method includes: in response to receiving a black level correction signal output by the digital processing circuit, controlling the correction module to output a correction signal; combining a first signal output by the DAC with the correction signal and outputting it to the first input terminal of the comparator; the correction signal is a decimal multiple of the first signal.

[0016] It should be understood that since the principle of this method in solving the problem is similar to that of the aforementioned image sensor, the implementation and technical effects of this method can be found in the aforementioned image sensor implementation and technical effects, and the repetition will not be repeated.

[0017] Thirdly, embodiments of this application also provide an electronic device, which includes: an image signal processor and an image sensor as described in the first aspect and any of the embodiments of the first aspect above, wherein the image sensor is connected to the image signal processor; the image sensor is configured to: output a digital quantization value of each pixel to the image signal processor; and the image signal processor is configured to: generate an image based on the digital quantization value of each pixel.

[0018] It should be understood that since the principle by which this electronic device solves the problem is similar to that of the aforementioned image sensor, the implementation and technical effects of this electronic device can be found in the implementation and technical effects of the aforementioned image sensor, and the repetition will not be repeated. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0020] Figure 2 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of the structure of an image sensor provided in an embodiment of this application;

[0022] Figure 4 A schematic diagram of a specific structure of the digital-to-analog converter and correction module provided in an embodiment of this application;

[0023] Figure 5a A timing diagram provided for an embodiment of this application;

[0024] Figure 5b Another timing diagram provided for an embodiment of this application;

[0025] Figure 6 This is another specific structural diagram of the digital-to-analog converter and correction module provided in the embodiments of this application.

[0026] Figure label:

[0027] 1-Housing, 2-Image sensor, 3-Main board, 100-Pixel array, 200-Readout circuit, 300-Image signal processor, 10-Comparator, 20-Digital-to-analog converter, 21-Current branch, 30-Digital processing circuit, 40-Correction module, 41-Correction branch, 50-First controller, 60-Second controller, VSL-Readout line, PX-Pixel, y1-First current source, y2-Second current source, y3-Third current source, k1-First switch, k2-Second switch, EN-Enable signal, Ck-Gear signal, P0-Connection node, S0-Correction signal, S1-First signal, Vref-Reference signal, R0-Resistor, S11-First control signal, S12-Second control signal. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0029] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0030] It should be noted that, in this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0031] In the embodiments of this application, the terms "first," "second," etc., do not limit the quantity or order. The term "connection" is used to indicate an electrical connection, including direct connection via wires or terminals or indirect connection via other devices.

[0032] To facilitate understanding of the technical solutions provided in the embodiments of this application, their application scenarios are first described below. The image sensor provided in the embodiments of this application can be applied to electronic devices, including but not limited to common devices with photographic functions such as digital cameras, mobile phones, tablets, and wearable devices. Of course, the image sensor provided in the embodiments of this application can also be applied to other types of electronic devices with shooting functions.

[0033] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. (Refer to...) Figure 1 As shown, the electronic device may include: a housing 1, an image sensor 2, and a motherboard 3. The image sensor 2 and the motherboard 3 are disposed within the housing 1, and the image sensor 2 is disposed on the motherboard 3 and electrically connected to the motherboard 3. Exemplarily, the motherboard 3 may include, but is not limited to, a printed circuit board (PCB).

[0034] Figure 2 This is another structural schematic diagram of the electronic device provided in an embodiment of this application. (Refer to...) Figure 2 The electronic device may include an image sensor and an image signal processor (ISP) 300. The image sensor includes a pixel array 100 and readout circuits 200. Each readout circuit 200 is connected to the image signal processor 300. The pixel array 100 includes multiple pixels PX arranged in an array and multiple readout lines VSL. Each readout line VSL is connected to a readout circuit 200 in a one-to-one correspondence. For example, the multiple pixels PX can be arranged in multiple rows and columns, and a column of pixels PX can be connected to one or more readout lines VSL. Furthermore, each pixel PX has a photodiode (PD) and a pixel circuit composed of transistors. The pixel circuit is connected to the negative terminal of the photodiode and is also connected to a readout line VSL. The readout circuit 200 generally includes an analog-to-digital converter (ADC) circuit. Figure 2 (not shown in the image) and digital processing circuits ( Figure 2 (Not shown in the image), the analog-to-digital converter (ADC) is connected between the digital processing circuit and the corresponding readout line VSL. The digital processing circuit is connected to the image signal processor 300. In practical applications, light from the target object enters the PD of the image sensor. The PD converts the light signal into an electrical signal. The pixel circuit processes the electrical signal converted by the PD into a voltage signal and transmits it to the readout line VSL. The ADC quantizes the voltage signal on the readout line VSL and converts it into a corresponding digital signal, which is then transmitted to the digital processing circuit. The digital processing circuit processes the signal output by the ADC to obtain a digital quantized value and transmits the digital quantized value to the image signal processor 300. The image signal processor 300 performs image synthesis based on the received digital quantized value.

[0035] Due to factors such as manufacturing process and usage environment, even if a pixel is not exposed, the presence of dark current causes the analog-to-digital converter (ADC) to output a non-zero signal to the digital processing circuit. This results in the image not appearing absolutely black even when completely dark. The output level of the PD in this completely dark environment can be referred to as the black level. During normal imaging, black level correction can be performed in the digital processing circuit to obtain a corrected signal. The image signal processor 300 then uses this corrected signal to synthesize the image, thereby improving the imaging effect and enhancing the realism and quality of the image.

[0036] However, when performing black level correction in digital processing circuits, the following problem arises: Black level correction can include integer bit correction and decimal bit correction, and decimal bit correction is processed using powers of 1 / 2, for example, 1 bit of decimal corresponds to a correction precision of 0.5. 1 The correction precision corresponding to 2 decimal places is 0.5. 2 The correction precision corresponding to 3 decimal places is 0.5. 3 The correction precision corresponding to the n-bit decimal places is 0.5. n To achieve a correction accuracy of 0.1 times, at least 4 bits need to be added. Therefore, the higher the correction accuracy, the more bits need to be added. This leads to a significant increase in the amount of data processing during decimal correction, which in turn increases the computational load and power consumption of the digital processing circuit.

[0037] Based on this, embodiments of this application provide an image processor for reducing the computational load and power consumption increment of the digital processing circuit while achieving high-precision decimal point correction. Exemplarily, the image processor may include: pixels, a comparator, a digital-to-analog converter (DAC), and a digital processing circuit; the DAC is connected to a first input terminal of the comparator, the pixels are connected to a second input terminal of the comparator, and the output terminal of the comparator is connected to the digital processing circuit; the image sensor further includes a correction module and a first controller, the correction module being connected to both the first controller and the first input terminal of the comparator, and the first controller also being connected to the digital processing circuit; the first controller is configured to: in response to receiving a black-level correction signal output by the digital processing circuit, control the correction module to output a correction signal, and combine the first signal output by the DAC with the correction signal before outputting it to the first input terminal of the comparator; the correction signal is a decimal multiple of the first signal. Thus, since the input to the first terminal of the comparator is the combined signal, i.e., the reference signal, this reference signal includes both the first signal and the correction signal. When the comparator outputs a signal to the digital processing circuit based on this reference signal and the second signal output by the pixel, because the correction signal is a fractional multiple of the first signal, the comparator can perform fractional-level correction on the black level. This allows the digital processing circuit to perform integer-level correction only on the black level, thereby achieving fractional-level correction on the analog side and integer-level correction on the digital side. This avoids the increased computational load and power consumption caused by performing fractional-level correction on the digital side, reducing the computational load and power consumption of the digital processing circuit while achieving high-precision fractional-level correction. It should be understood that the analog side refers to the entire assembly consisting of the comparator, digital-to-analog converter, correction module, and first controller, while the digital side refers to the digital processing circuit.

[0038] The specific structure of the image sensor is described below.

[0039] Figure 3 An exemplary schematic diagram of an image sensor provided in an embodiment of this application is shown, with reference to... Figure 3 As shown, the image sensor may include a pixel array and a readout circuit 200. The pixel array includes multiple pixels PX arranged in an array and multiple readout lines VSL. Each readout line VSL is connected to a portion of the pixels PX, and different readout lines VSL are connected to different pixels PX. Multiple readout circuits 200 are provided, and the number of readout circuits 200 is the same as the number of readout lines VSL, and they are connected in a one-to-one correspondence. To avoid... Figure 3 Too complicated Figure 3The image only shows one pixel PX, one readout line VSL, and one readout circuit 200. However, this does not mean that the image sensor only includes one pixel PX, one readout line VSL, and one readout circuit 200. The number of pixels PX, readout line VSL, and readout circuit 200 can be set according to actual needs, and no specific limitation is made here. The structures of pixel PX and readout circuit 200 are described below.

[0040] I. Pixels (PX)

[0041] For example, a pixel PX includes an optoelectronic device and a pixel circuit. One end of the optoelectronic device is connected to the pixel circuit, and the other end of the optoelectronic device is connected to a ground terminal. The pixel circuit is also connected to a readout line VSL. The optoelectronic device is used to sense light signals and convert the sensed light signals into electrical signals, which are then output to the pixel circuit. The pixel circuit is used to process the electrical signals output by the optoelectronic device. The processed electrical signals are then output to the second input terminal of the comparator 10 in the readout circuit 200 via the readout line VSL, thereby realizing the sensing and processing of light signals for imaging processing.

[0042] Among them, the optoelectronic device can be any device with photoelectric effect, such as but not limited to photodiodes, etc. The specific settings can be set according to actual needs, and no specific limitations are made here.

[0043] The pixel circuit may include: a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, and a third current source y3. The first terminal of the first transistor Q1 is connected to the optoelectronic device. The second terminal of the first transistor Q1 is connected to the first terminal of the second transistor Q2 and the control terminal of the third transistor Q3, respectively. The control terminal of the first transistor Q1 is connected to the signal terminal for providing the tx signal. The first terminal of the second transistor Q2 is also connected to the control terminal of the third transistor Q3. The second terminal of the second transistor Q2 is connected to the signal terminal for providing the first constant voltage signal VDD. The control terminal of the second transistor Q2 is connected to the signal terminal for providing the rst signal. The first terminal of the third transistor Q3 is connected to the second terminal of the fourth transistor Q4, respectively. The second terminal of the third transistor Q3 is connected to the signal terminal for providing the first constant voltage signal VDD. The first terminal of the fourth transistor Q4 is connected to the third current source y3 and the second input terminal of the comparator 10, respectively. The control terminal of the fourth transistor Q4 is connected to the signal terminal for providing the SEL signal. The third current source y3 is also connected to the ground terminal GND and the second input terminal of the comparator 10, respectively. The third current source y3 is used to provide the operating current for the fourth transistor Q4. The tx, rst, and SEL signals can be provided by a controller used to control the operation of the pixel circuit. This controller may be different from the first controller 50 and the second controller 60 mentioned later, or it may be either the first controller 50 or the second controller 60 mentioned later. The specific configuration can be determined according to actual needs and is not specifically limited here. Furthermore, the tx, rst, and SEL signals are three different signals used to control the first transistor Q1, the second transistor Q2, and the fourth transistor Q4, respectively. The specific forms of the tx, rst, and SEL signals can be determined according to actual needs and are not specifically limited here.

[0044] In the first quantization stage, transistors Q2, Q3, and Q4 are turned on, while transistor Q1 is turned off. This disconnects the connection between the photoelectric device and comparator 10, allowing interference factors in the pixel circuit to be quantized during the first quantization stage. In the second quantization stage, transistors Q1, Q3, and Q4 are turned on, while transistor Q2 is turned off. This connects the photoelectric device and comparator 10, allowing interference factors in the pixel circuit and the output electrical signal of the photoelectric device to be quantized during the second quantization stage. The first and second quantization stages will be described later.

[0045] Of course, in actual implementation, the structure of the pixel circuit is not limited to... Figure 3 As shown, other structures can also be set according to actual needs. As long as the structure can realize the pixel circuit function, it is within the protection scope of the embodiments of this application.

[0046] II. Reading circuit 200.

[0047] For example, the reading circuit 200 may include: a comparator 10, a digital-to-analog converter 20, a digital processing circuit 30, a correction module 40, and a first controller 50. The first input terminal of the comparator 10 is connected to the digital-to-analog converter 20 and the correction module 40, respectively. The second input terminal of the comparator 10 is connected to the pixel circuit, and the output terminal of the comparator 10 is connected to the digital processing circuit 30. The first controller 50 is connected to the correction module 40 and the digital processing circuit 30, respectively. The first controller 50 is used to: control the correction module 40 to output a correction signal S0 in response to the black level correction signal output by the digital processing circuit 30. The first signal S1 output by the digital-to-analog converter 20 is combined with the correction signal S0 and output as a reference signal Vref to the first input terminal of the comparator 10. The correction signal S0 is a fractional multiple of the first signal S1. The combination of the first signal S1 and the correction signal S0 can be understood as the superposition of the first signal S1 and the correction signal S0.

[0048] The digital processing circuit 30 can output an enable signal EN to the first controller 50. The enable signal EN can be a pulse signal. When the enable signal EN is at the first level, it indicates that the digital processing circuit 30 outputs a black level correction signal to the first controller 50. When the enable signal EN is at the second level, it indicates that the digital processing circuit 30 does not output a black level correction signal to the first controller 50. When the first level is high, the second level is low; or, when the first level is low, the second level is high.

[0049] Thus, since the input to the first terminal of comparator 10 is the combined reference signal Vref, this reference signal Vref includes the first signal S1 and the correction signal S0. When comparator 10 outputs a signal to digital processing circuit 30 based on the reference signal Vref and the second signal S2 output by the pixel, because the correction signal S0 is a fractional multiple of the first signal S1, comparator 10 can perform fractional correction on the black level. This allows digital processing circuit 30 to perform integer correction only on the black level, thereby achieving fractional correction on the analog side and integer correction on the digital side. This avoids the problem of increased computational load and power consumption caused by performing fractional correction on the digital side, reducing the computational load and power consumption of digital processing circuit 30 while achieving high-precision fractional correction. Furthermore, compared to performing fractional correction on the digital side, performing fractional correction on the analog side results in smaller area and hardware resource overhead.

[0050] 2.1. Calibration module 40.

[0051] Reference Figure 4As shown, the correction module 40 includes multiple correction branches 41 arranged in parallel, which are respectively connected to the connection node P0 and the first controller 50. The connection node P0 is a node formed by connecting the first input terminals of the correction module 40, the digital-to-analog converter 20, and the comparator 10. The first controller 50 is specifically used to: in response to receiving a black level correction signal, control at least a portion of the correction branches 41 to inject a first current into the connection node P0; wherein the correction signal S0 is determined based on the first current.

[0052] It should be understood that, in order to avoid overly complex accompanying diagrams, Figure 4 The example shown is that the calibration module 40 includes three calibration branches 41. However, this does not mean that the calibration module 40 only includes three calibration branches 41. The number of calibration branches 41 included in the calibration module 40 is not specifically limited here and can be set according to actual needs.

[0053] Thus, the first controller 50 can determine the correction branch 41 to be controlled as needed. When a black level correction signal is received and the black level correction stage is entered, one or more correction branches 41 controlled by the first controller 50 can inject a first current into the connection node P0. If one of the correction branches 41 outputs a first current under the control of the first controller 50, the correction signal S0 can be determined based on the first current. If multiple correction branches 41 output a first current under the control of the first controller 50, these first currents will converge at the connection node P0 to form the correction signal S0. Therefore, the correction signal S0 is determined based on the sum of these first currents. Thus, the function of the correction module 40 is realized through multiple correction branches 41.

[0054] If a resistor R0 is provided at connection node P0, the first current injected into connection node P0 can form a corresponding voltage at connection node P0 under the action of resistor R0. This voltage can be regarded as a correction signal S0. The resistor R0 can be located within the digital-to-analog converter 20; in other words, resistor R0 is a device within the digital-to-analog converter 20. In this case, even if the correction branch 41 only injects the first current into connection node P0, the corresponding correction signal S0 can still be formed under the action of resistor R0 within the digital-to-analog converter 20, thereby realizing the function of the correction module 40. Alternatively, the resistor R0 can be located within the correction module 40; in other words, resistor R0 is a device within the correction module 40. Thus, the first current injected into connection node P0 by the correction branch 41 can also form a corresponding correction signal S0 under the action of resistor R0, thereby also enabling the function of the correction module 40.

[0055] For example, the first current injected into the connection node P0 by each correction branch 41 is (1 / m) of the current value of the first signal S1. nThe formula is: m > 1, n is a positive integer; thus, the first current can be a fractional multiple of the current value of the first signal S1, and the correction signal S0 can be a fractional multiple of the first signal S1, achieving fractional-level correction of the black level. Furthermore, in all correction branches 41, the first current injected into the connection node P0 is different for each branch, allowing for combinations of multiple correction branches 41. This results in more diverse and refined values ​​of the output first current, enabling more precise fractional-level correction. Alternatively, in all correction branches 41, some branches inject different first currents into the connection node P0, further diversifying and refining the value of the output first current to a certain extent, thus achieving precise fractional-level correction.

[0056] Wherein, the first current output by any correction branch 41 is I i This means that when the current value of the first signal S1 is represented by I0, the relationship between the first current and the current value of the first signal S1 can be expressed by Equation 1, that is, Equation 1 is: I i =I0×(1 / m) n For each correction branch 41 with different first current outputs, the value of n in equation 1 will be different. For example, combined with... Figure 4 As shown, the three correction branches 41 are first numbered from left to right: the leftmost correction branch 41 is denoted as correction branch 1, the middle correction branch 41 is denoted as correction branch 2, and the rightmost correction branch 41 is denoted as correction branch 3. The first current injected by correction branch 1 into the connecting node P0 is denoted as I1. When n is 1, I1 = I0 × (1 / m) 1 The first current injected into the connecting node P0 by the correction branch 2 is denoted by I2. When n is 2, I2 = I0 × (1 / m) 2 The first current injected into the connecting node P0 by the correction branch 3 is denoted by I3. When n is 3, I3 = I0 × (1 / m) 3 Of course, the value of n is not limited to 1, 2, or 3; it can be other values ​​as well. This is just an example for illustration. The value of m can be, but is not limited to, 2, 3, 4, 5, or 6, or other integers or decimals. It can be set according to actual needs and is not specifically limited here. For example, when m is 2, and the correction module 40 includes w correction branches 41, and the first current injected into the connection node P0 by different correction branches 41 is different, 1 / 2 can be achieved. w Decimal place correction accuracy.

[0057] Continue to refer to Figure 4As shown, each correction branch 41 may include a first current source y1 and a first switch k1. The first switch k1 is connected between the first current source y1 and the connection node P0, and the first switch k1 is also connected to the first controller 50. The second current source y2 is also connected to a signal terminal for providing a first constant voltage signal VDD. The first controller 50 is specifically used to: in response to receiving a black level correction signal, control at least a portion of the first switches k1 to connect the corresponding first current source y1 and the first input terminal of the comparator 10. Thus, when the first switch k1 is closed under the control of the first controller 50, it connects the corresponding first current source y1 and the connection node P0. The current provided by the corresponding first current source y1 can be transmitted to the connection node P0 as the first current, realizing the injection of the first current into the connection node P0 by the correction branch 41, thereby realizing the function of the correction module 40.

[0058] The first current source y1 may include a transistor, and the type of transistor may be a P-type transistor. To avoid making the attached diagram too complex, in Figure 4 The transistor in the first current source y1 is not shown in the diagram. The first switch k1 may be, but is not limited to, a transistor or a switching circuit, etc., and can be set according to actual needs. No specific limitation is made here.

[0059] Furthermore, in addition to outputting an enable signal EN to the first controller 50, the digital processing circuit 30 can also output a level signal Ck. This level signal Ck can be used to indicate the magnitude of the correction signal S0 that the correction module 40 needs to output; that is, different level signals Ck correspond to different magnitudes of correction signals S0. Based on this, the first controller 50 is specifically used to: respond to receiving the black level correction signal output by the digital processing circuit 30, and control the correction module 40 to output the correction signal S0 corresponding to the level signal Ck, according to the level signal Ck output by the digital processing circuit 30. This ensures that the correction signal S0 output by the correction module 40 can meet the correction requirements, thereby further improving the imaging effect. For example, when the correction branch 41 includes a first current source y1 and a first switch k1, the gear position signal Ck can carry the identifier of the first switch k1. When the first controller 50 receives the black level correction signal and the gear position signal Ck, it can control the corresponding first switch k1 to close according to the identifier of the first switch k1 carried in the gear position signal Ck, so that the correction module 40 outputs the correction signal S0 corresponding to the gear position signal Ck.

[0060] It should be understood that the digital processing circuit 30 may be configured with a mapping relationship between the first current that can be output by each correction branch 41 and the first switch k1 in each correction branch 41, or the digital processing circuit 30 may be configured with a mapping relationship between the correction signal S0 output by the correction module 40 and the first switch k1 in each correction branch 41. When the digital processing circuit 30 determines the correction accuracy that needs to be met when performing decimal correction, the digital processing circuit 30 can determine the first current or the correction signal S0 that the correction module 40 needs to output when performing decimal correction, and then determine which first switches k1 need to be closed. The identifiers of these first switches k1 that need to be closed are carried in the gear position signal Ck and sent to the first controller 50 so that the correction signal S0 output by the correction module 40 meets the correction accuracy.

[0061] The method for determining the correction accuracy includes: before performing black level correction, the pixel outputs a second signal S2 to the comparator 10 through the corresponding readout line VSL. The first controller 50 controls the correction module 40 not to output a correction signal S0. Therefore, the first signal S1 output by the digital-to-analog converter 20 is transmitted to the comparator 10 as a reference signal Vref. The comparator 10 outputs a corresponding digital signal to the digital processing circuit 30 based on the reference signal Vref and the second signal S2. The digital processing circuit 30 processes the input digital signal to obtain a digital quantization value and transmits it to the image signal processor 300, where it is processed. In this process, because black level correction is not performed, the actual imaging effect differs from the ideal imaging effect due to the dark current characteristics of the photoelectric device. The image signal processor 300 can determine the correction accuracy corresponding to this difference and then transmit the determined correction accuracy to the digital processing circuit 30. Alternatively, an additional processor can determine the correction accuracy corresponding to this difference and then transmit the determined correction accuracy to the digital processing circuit 30. This additional processor can be any processor different from the image signal processor 300, without specific limitations. Furthermore, the correction accuracy and black level correction can be determined before each image sensor imaging, enabling dynamic adjustment of the correction accuracy and real-time black level correction. This ensures that the image sensor can accurately perform black level correction each time it operates, meeting actual correction requirements and thus improving the imaging effect.

[0062] Alternatively, the calibration accuracy can be pre-configured based on experience, so the calibration accuracy is fixed. Although dynamic adjustment is not possible, this reduces the computational load of the image sensor, lowers the power consumption of the image sensor, and can also improve the imaging effect to some extent.

[0063] 2.2 Digital-to-analog converter 20.

[0064] Reference Figure 4 As shown, the digital-to-analog converter 20 may include: a resistor R0 and multiple current branches 21 connected in parallel, the multiple current branches 21 being connected to the first end of the resistor R0 and the connection node P0 respectively, the first end of the resistor R0 being connected to the connection node P0, and the second end of the resistor R0 being connected to the ground terminal; the image sensor also includes a second controller 60, the second controller 60 being connected to the multiple current branches 21 and the digital processing circuit 30 respectively, the second controller 60 being used to: in response to receiving a black level correction signal, control all current branches 21 to inject a second current into the connection node P0; wherein, the first signal S1 is determined based on the second current.

[0065] It should be understood that, in order to avoid overly complex accompanying diagrams, Figure 4 The example shown is a digital-to-analog converter 20 with two current branches 21. However, this does not mean that the digital-to-analog converter 20 only includes two current branches 21. The number of current branches 21 included in the digital-to-analog converter 20 is not specifically limited here and can be set according to actual needs.

[0066] The second current injected into the connection node P0 by the current branch 21, under the action of resistor R0, can form a corresponding first signal S1 at the connection node P0. At this time, the first signal S1 is the first voltage. Therefore, when the first signal S1 is determined according to the second current, it can be understood that the first voltage is the product of the second current and the resistance value of resistor R0. Thus, when a black level correction signal is received, it indicates that black level correction is required. At least part of the correction branch 41 outputs the first current, and all current branches 21 output the second current. Under the action of resistor R0, the first current and the second current are converted into a corresponding voltage signal after converging at the connection node P0. This voltage signal can be regarded as the signal after the combination of the first signal S1 and the correction signal S0, thereby realizing decimal point correction.

[0067] Furthermore, if the first control signal S11 cannot individually control each current branch 21, the second controller 60 can also control whether each current branch 21 injects a second current into the connection node P0 according to the first control signal S11 and the second control signal S12. For example, when the periods of the first control signal S11 and the second control signal S12 are basically the same, in any period, when the second control signal S12 is at the rising edge, the second controller 60 controls all current branches 21 to inject a second current into the connection node P0; when all current branches 21 finish injecting the second current, it controls some current branches 21 to inject a second current into the connection node P0; when the first control signal S11 is at the falling edge for the first time and at the falling edge for the second time, it controls all current branches 21 to sequentially stop injecting the second current into the connection node P0.

[0068] Alternatively, if the first control signal S11 can independently control each current branch 21, the second controller 60 can control whether each current branch 21 injects a second current into the connection node P0 according to the first control signal S11. For example, during any period of the first control signal S11, when the first control signal S11 is at its rising edge for the first time, the second controller 60 controls all current branches 21 to inject a second current into the connection node P0; when all current branches 21 finish injecting the second current, the second controller controls some current branches 21 to inject a second current into the connection node P0; when the first control signal S11 is at its falling edge for the first time and at its falling edge for the second time, the second controller controls all current branches 21 to sequentially stop injecting the second current into the connection node P0.

[0069] Whether the current branches 21 are controlled according to the first control signal S11 or according to the first control signal S11 and the second control signal S12, the time period from the moment the first control signal S11 first falls to the moment the black level correction signal is received is the first quantization stage, and the time period from the moment the first control signal S11 second falls to the moment when all current branches 21 stop injecting the second current is the second quantization stage. In the first quantization stage, the photoelectric device is disconnected from the second input terminal of the comparator 10 under the control of the pixel circuit; in the second quantization stage, the photoelectric device is connected to the second input terminal of the comparator 10 under the control of the pixel circuit.

[0070] In this way, all current branches 21 are activated twice, realizing two quantization processes. The first quantization process can be regarded as the quantization of interference factors in the pixel, and the second quantization process can be regarded as the quantization of interference factors in the pixel and the second signal S2 output by the pixel. The quantized values ​​obtained from these two quantization processes can be output to the digital processing circuit 30 through the comparator 10. After obtaining the quantized values ​​of the two quantization processes, the digital processing circuit 30 subtracts the quantized value obtained from the first quantization process from the quantized value obtained from the second quantization process, which is the quantized value of the second signal S2 output by the pixel. This increases the accuracy of the quantization value, avoids the influence of interference factors, and thus helps to improve the imaging effect.

[0071] For example, each current branch 21 may include: a second current source y2 and a second switch k2. The second switch k2 is connected between the second current source y2 and the connection node P0, and the second switch k2 is also connected to the second controller 60. The second current source y2 is also connected to a signal terminal for providing a first constant voltage signal VDD. When any second switch k2 is closed under the control of the second controller 60, the corresponding second current source y2 is connected to the connection node P0, so that the current provided by the corresponding second current source y2 is injected into the connection node P0 as a second current. When the second switch k2 is opened under the control of the second controller 60, the connection between the corresponding second current source y2 and the connection node P0 is disconnected, so that the current provided by the corresponding second current source y2 cannot be injected into the connection node P0, thereby realizing the function of the digital-to-analog converter 20.

[0072] The second current source y2 may include a transistor, and the type of transistor may be a P-type transistor. It should be understood that, to avoid making the accompanying drawings overly complex, Figure 4 The transistor in the second current source y2 is not shown in the diagram.

[0073] 2.3 Digital processing circuit 30.

[0074] For example, during black level correction, the digital processing circuit 30 performs integer bit correction processing and other processing; when black level correction is not performed, the digital processing circuit 30 performs other processing, which may include, but is not limited to, imaging-related arithmetic processing, etc., and can be specifically set according to actual needs, without being specifically limited here. It should be understood that the structure of the digital processing circuit 30 can be any other structure known to those skilled in the art that can achieve its function, without being specifically limited here.

[0075] The working process of the reading circuit is explained below.

[0076] Combination Figure 5a The timing diagram shown uses the reference signal Vref at the connection node P0. The first control signal S11 and the second control signal S12 have the same period, both represented by T0. In any period T0, when the second control signal S12 is on its rising edge and reaches time t1, the second controller 60 controls all the second switches k2 to close, so that each second current source y2 can inject the second current into the connection node P0, thus increasing the voltage at the connection node P0 to V1.

[0077] When the first control signal S11 reaches time t2 at the first falling edge, the second controller 60 controls all the second switches k2 to open in sequence, so the second current injected into the connection node P0 gradually decreases, causing the voltage at the connection node P0 to gradually decrease.

[0078] When the enable signal EN is high, it indicates that a black level correction signal has been received. At this time, it is time t3. On the one hand, the second controller 60 controls all the second switches k2 to close, so that each second current source y2 can inject the second current into the connection node P0. On the other hand, the first controller 50 controls the first switch k1 corresponding to the identifier of the first switch k1 carried in the gear signal Ck to close, so that the corresponding first current source y1 can inject the first current into the connection node P0. The first current and the second current converge at the connection node P0, so the voltage at the connection node P0 is V2 at this time. Since the first current is injected into the connection node P0 at this time, the voltage V2 at the connection node P0 is higher than the voltage V1 at time t1. At time t3, the first control signal S11 is on the rising edge, and the second switches k2 are not all open, that is, only some of the second switches k2 are open, and some of the second switches k2 are closed.

[0079] When the first control signal S11 reaches time t4 at its second falling edge, the second controller 60 controls all the second switches k2 to open sequentially, so the second current injected into the connection node P0 gradually decreases, causing the voltage at the connection node P0 to gradually decrease; when all the second switches k2 are open, time t5 is reached. At time t5, the second controller 60 controls some of the second switches k2 to close, so that some of the second current sources y2 can inject the second current into the connection node P0. At this time, the voltage at the connection node P0 is V0 and remains so until time t6; where time t6 is the end time of the current cycle of the second control signal S12.

[0080] The above process is repeated in the next cycle T0.

[0081] In combination Figure 5b The timing diagram shown is similar to the above-mentioned working process, with the following differences: time t1 is the time when the first control signal S11 is at its first rising edge.

[0082] In this way, decimal correction is achieved on the analog side, which avoids the problem of increased computational load and power consumption caused by performing decimal correction on the digital side. While achieving high-precision decimal correction, the computational load and power consumption of the digital processing circuit 30 are reduced.

[0083] Figure 6 An exemplary schematic diagram of another image sensor provided in an embodiment of this application is shown, with reference to... Figure 6 As shown, the image sensor in this embodiment is the same as that in the previous embodiment. Figure 4The structures of the image sensors described in the article are basically similar, except that the transistors in the first current source y1 and the second current source y2 are both N-type transistors. At this time, the resistor R0 is connected between the signal terminal used to provide the first constant voltage signal VDD and the connection node P0. The first current source y1 is also connected to the ground terminal GND, and the second current source y2 is also connected to the ground terminal GND.

[0084] It should be understood that the image sensor in this embodiment is the same as that in the foregoing embodiments. Figure 4 The structural similarities of the image sensors described herein can be found in the relevant descriptions in the foregoing embodiments, and will not be elaborated upon here.

[0085] This application also provides an image sensor, which is similar to the image sensor in the foregoing embodiments. Figure 3 The structures of the image sensors described in the article are basically similar, with the difference being that the calibration module is implemented using a device with logic processing function, such as, but not limited to, a microprocessor with logic processing function. The device with logic processing function can be a chip or a circuit structure, which can be set according to actual needs, as long as it can output a calibration signal to the connection node under the control of the first controller.

[0086] It should be understood that the image sensor in this embodiment is the same as that in the foregoing embodiments. Figure 3 The structural similarities of the image sensors described herein can be found in the relevant descriptions in the foregoing embodiments, and will not be elaborated upon here.

[0087] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. An image sensor, characterized in that, include: Pixels, comparators, digital-to-analog converters, and digital processing circuitry; The digital-to-analog converter is connected to the first input terminal of the comparator, the pixel is connected to the second input terminal of the comparator, and the output terminal of the comparator is connected to the digital processing circuit. The image sensor further includes a calibration module and a first controller. The calibration module is connected to the first controller and the first input terminal of the comparator, respectively. The first controller is also connected to the digital processing circuit. The first controller is configured to: in response to receiving a black level correction signal output by the digital processing circuit, control the correction module to output a correction signal, and the first signal output by the digital-to-analog converter is combined with the correction signal and output to the first input terminal of the comparator; the correction signal is a fractional multiple of the first signal.

2. The image sensor as described in claim 1, characterized in that, The first controller is specifically configured to: in response to receiving a black level correction signal output by the digital processing circuit, control the correction module to output a correction signal corresponding to the gear position signal according to the gear position signal output by the digital processing circuit.

3. The image sensor as described in claim 1 or 2, characterized in that, The correction module includes multiple correction branches arranged in parallel, and the multiple correction branches are respectively connected to the connection node and the first controller; The first controller is specifically configured to: in response to receiving the black level correction signal, control at least a portion of the correction branches among the plurality of correction branches to inject a first current into the connection node; The connection node is the node formed by connecting the correction module, the digital-to-analog converter, and the first input terminal of the comparator, and the correction signal is determined based on the first current.

4. The image sensor as described in claim 3, characterized in that, The first current injected into the connection node by different correction branches among the plurality of correction branches is different.

5. The image sensor as described in claim 3 or 4, characterized in that, The first current injected into the connection node by each correction branch is (1 / m) of the current value of the first signal. n The multiple, m is greater than 1, and n is a positive integer.

6. The image sensor according to any one of claims 3-5, characterized in that, Each correction branch includes: a first current source and a first switch, wherein the first switch is connected between the first current source and the connection node, and the first switch is also connected to the first controller; The first controller is specifically configured to: in response to receiving the black level correction signal, control at least a portion of the first switch to connect the corresponding first current source and the first input terminal of the comparator.

7. The image sensor according to any one of claims 3-6, characterized in that, The digital-to-analog converter includes: a resistor and multiple current branches arranged in parallel, the multiple current branches being respectively connected to a first end of the resistor and the connection node, the first end of the resistor being also connected to the connection node, and the second end of the resistor being connected to a first voltage terminal; The image sensor further includes a second controller, which is connected to the plurality of current branches and the digital processing circuit respectively. The second controller is used to: in response to receiving the black level correction signal, control the plurality of current branches to inject a second current into the connection node; wherein the first signal is determined based on the second current.

8. The image sensor as claimed in claim 7, characterized in that, The second controller is also configured to control the plurality of current branches according to the first control signal; Specifically, within any period of the first control signal, when the first control signal is at its first rising edge, the multiple current branches are controlled to inject the second current into the connection node; when the first control signal is at its first falling edge and its second falling edge, the multiple current branches are controlled to sequentially stop injecting the second current into the connection node; when all the multiple current branches have stopped injecting the second current, some of the multiple current branches are controlled to inject the second current into the connection node; the time period from the moment the first control signal is at its first falling edge to the moment the black level correction signal is received is the first quantization phase; the time period from the moment the first control signal is at its second falling edge to the moment when all the multiple current branches have stopped injecting the second current is the second quantization phase. The pixel includes an optoelectronic device and a pixel circuit. The pixel circuit is connected to the optoelectronic device and the second input terminal of the comparator, respectively. In the first quantization stage, the optoelectronic device is disconnected from the second input terminal of the comparator under the control of the pixel circuit. In the second quantization stage, the optoelectronic device is connected to the second input terminal of the comparator under the control of the pixel circuit.

9. A method for correcting the decimal places of black level, characterized in that, An image processor is applied to an image sensor, the image sensor comprising: pixels, a comparator, a digital-to-analog converter (DAC), and a digital processing circuit; the DAC is connected to a first input terminal of the comparator, the pixels are connected to a second input terminal of the comparator, and the output terminal of the comparator is connected to the digital processing circuit; the image sensor further comprises a calibration module and a first controller, the calibration module being connected to the first controller and the first input terminal of the comparator respectively, and the first controller being further connected to the digital processing circuit; the method comprises: In response to receiving the black level correction signal output by the digital processing circuit, the correction module is controlled to output a correction signal. The first signal output by the digital-to-analog converter is combined with the correction signal and then output to the first input terminal of the comparator. The correction signal is a fractional multiple of the first signal.

10. An electronic device, characterized in that, include: An image signal processor and an image sensor as described in any one of claims 1-8, wherein the image sensor is connected to the image signal processor; The image sensor is used to: output a digital quantization value of each pixel to the image signal processor; The image signal processor is used to generate an image based on the digital quantization value of each pixel.

Images