Optimization method and device for PCIE bearing AXI write data

Abstract

The invention relates to the technical field of data compression, and provides an optimization method and device for PCIE bearing AXI write data. The method comprises the steps of determining at least one cavity position in to-be-carried data; generating a hole identification bit according to the at least one hole position; generating an original TLP packet according to the to-be-carried data; adding the hole identification bit in the original TLP packet to obtain a target TLP packet; and transmitting the target TLP packet to a target device so as to write the to-be-carried data into the target device, thereby solving the problem of low transmission efficiency caused by splitting into a plurality of TLPs for transmission when holes exist in AXI burst data writing.

Description

Technical Field

[0001] This invention relates to the field of data compression technology, and in particular to an optimization method and apparatus for PCIe carrying AXI write data. Background Technology

[0002] Within a single chip, data transmission is typically handled via bus protocols such as Advanced eXtensible Interface (AXI). However, when data needs to be transferred across chips, the Peripheral Component Interconnect Express (PCIe) standard is an option, especially when data is transferred between a host and a device. In PCIe, the host initiates, controls, and manages the data transfer, typically possessing central processing capabilities and system resource scheduling abilities; for example, the host can be a Central Processing Unit (CPU). The device is the passive responder to the data transfer, relying on instructions provided by the host to execute specific functions; for example, the device can be a Graphics Processing Unit (GPU).

[0003] When transmitting AXI write data via PCIe, a single AXI burst write is typically packaged into a Transaction Layer Packet (TLP) for transmission. A burst write refers to the host sending a group of data to the slave via consecutive addresses. However, if this AXI burst write data is discontinuous, indicating gaps (i.e., invalid data), it needs to be split at the corresponding gaps, thus dividing the AXI burst write data into multiple TLP packets for transmission. This significantly reduces transmission efficiency.

[0004] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an optimization method and apparatus for carrying AXI write data in PCIe. The purpose is to solve the performance loss of hole splitting by adding a hole marker bit to the TLP packet to mark the hole location and add minimal overhead, thereby avoiding splitting into multiple TLP packets for transmission. This solves the problem that when there are holes in AXI burst write data, it must be split into multiple TLP packets for transmission, resulting in low transmission efficiency.

[0006] The present invention adopts the following technical solution: In a first aspect, the present invention provides an optimization method for PCIe carrying AXI write data, comprising: Identify at least one void location in the data to be transferred; A cavity identifier is generated based on the location of at least one cavity; A raw TLP packet is generated based on the data to be transported; the void identifier bit is added to the raw TLP packet to obtain the target TLP packet; The target TLP packet is transmitted to the target device to write the data to be transferred into the target device.

[0007] Furthermore, determining the location of at least one void in the data to be transported includes: Determine the first location of the first invalid data in the data to be transferred; Determine the second location of the remaining invalid data in the data to be transferred.

[0008] Further, generating a cavity identifier bit based on the at least one cavity location includes: The first position is designated as the cavity marker.

[0009] Further, the step of generating an original TLP packet based on the data to be transported, and adding the void identifier bit to the original TLP packet to obtain the target TLP packet includes: Valid or invalid data from the data to be transferred are obtained sequentially; for each valid data, the valid data is determined as the corresponding valid byte; For each invalid data, determine the next invalid data in the data to be transferred; determine the second position of the next invalid data as the position byte corresponding to the invalid data; Construct the original TLP packet based on the valid bytes and the position bytes; The first position is used as the starting byte and added to the available fields of the header of the original TLP packet to obtain the target TLP packet.

[0010] Furthermore, the starting byte is a valid preset value, which indicates that there is no invalid data in the data to be transferred.

[0011] Further, generating a cavity identifier bit based on the at least one cavity location includes: The number of invalid data in the data to be transferred is determined, and the number is identified as a void identifier.

[0012] Further, the step of generating an original TLP packet based on the data to be transported, and adding the void identifier bit to the original TLP packet to obtain the target TLP packet includes: Determine the valid bytes of each valid data in the data to be transferred, so as to construct the original TLP packet based on the data to be transferred; The hole identifier is added to the available field of the header of the original TLP packet to obtain the intermediate TLP packet; Obtain the third location of each invalid data in the data to be transferred; Based on the byte size represented by the hole identifier, all the third positions are stored using the first preset number of bits in the payload of the intermediate TLP packet to obtain the target TLP packet.

[0013] Furthermore, before determining the location of at least one void in the data to be transported, the method further includes: Determine the degree of dispersion of invalid data distribution in the data to be transferred; When the degree of dispersion meets the preset conditions, at least one void location in the data to be transported is determined to generate the target TLP package.

[0014] Secondly, the present invention also provides an optimization device for PCIe carrying AXI write data, comprising: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the processor for performing the PCIe carrying AXI write data optimization method described in the first aspect.

[0015] Thirdly, the present invention also provides a non-volatile computer storage medium storing computer-executable instructions, which are executed by one or more processors to perform the PCIe carrying AXI write data optimization method described in the first aspect.

[0016] Fourthly, a computer program product containing instructions is provided, which, when executed on a computer or processor, causes the computer or processor to perform an optimized method for writing PCIe AXI data as described in the first aspect.

[0017] Fifthly, the present invention also provides an optimization system for PCIe carrying AXI write data, including the PCIe carrying AXI write data optimization device as described in the second aspect, and using the PCIe carrying AXI write data optimization method as described in the first aspect to complete the interaction of the PCIe carrying AXI write data optimization device of the second aspect.

[0018] Unlike existing technologies, the present invention has at least the following beneficial effects: This invention identifies hole locations by adding a hole identifier bit to the TLP packet, enabling discontinuous data to be transported to be transmitted through a single TLP packet without having to split the data into multiple TLP packets based on hole locations. Since the overhead of adding the hole identifier bit is minimal, it can significantly improve the data transmission efficiency for data with many hole locations compared to splitting the data into multiple TLP packets. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0020] Figure 1 This is a schematic diagram illustrating a specific example of a data transfer matrix provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating a specific example of a host's storage space provided in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating a specific example of a GPU storage space provided in an embodiment of the present invention; Figure 4 This is a flowchart illustrating an optimized method for carrying AXI write data via PCIe, provided in an embodiment of the present invention. Figure 5 This is a flowchart illustrating step 10 provided in an embodiment of the present invention; Figure 6 This is a flowchart illustrating step 30 provided in an embodiment of the present invention; Figure 7 This is a schematic diagram illustrating a specific example of a target TLP packet data structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating a specific example of parsing data to be transferred from a target TLP packet, as provided in an embodiment of the present invention. Figure 9 This is a flowchart illustrating another step 30 provided in an embodiment of the present invention; Figure 10 This is a schematic diagram illustrating a specific example of another target TLP packet data structure provided in this embodiment of the invention; Figure 11 This is a schematic diagram of the architecture of an optimized device for carrying AXI write data on PCIE, provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0022] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0023] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0024] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0025] In describing some embodiments, the terms "coupled," "coupled," and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "connected" or "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other, such as "optical coupling," "wireless connection," etc. The embodiments disclosed herein are not necessarily limited to the scope of this invention.

[0026] In the description of this invention, the expression “A and / or B” (where A and B are used to formally represent specific features) will be used. The corresponding expression includes the following three combinations: only A, only B, and a combination of A and B.

[0027] As used in this invention, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from a particular value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0028] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0029] The Write Strobe (wstrob) signal is a write transaction signal in the AXI protocol. It's a signal with the same width as the write data, with each bit corresponding to a byte channel and indicating whether the data in that channel is valid. When a bit in the Write Strobe signal is 1, it indicates that the corresponding byte channel data is valid and needs to be written to the target address; when a bit is 0, it indicates that the corresponding byte channel data is invalid or does not need to be written. For ease of description, invalid or unnecessary data will be referred to as invalid data in the following text.

[0030] Devices using the PCIe protocol exchange TLP packets for data transmission and communication. All data interaction between the host and the device is achieved through TLP packets, which define the rules and formats for data transmission, ensuring that data can be transmitted accurately and efficiently over the PCIe link.

[0031] When transmitting AXI write data via PCIe, a single AXI burst write data is typically packaged into a TLP packet for transmission to reduce the number of transmissions and improve efficiency. During this process, the write enable signal is included in the TLP packet along with the AXI burst write data. The receiving device can use the write enable signal to determine which bytes of data are valid and perform the correct write operation.

[0032] However, if the AXI burst write data is discontinuous (i.e., the write enable signal contains a 0 in the middle), it indicates that there are gaps (i.e., invalid data) in the AXI burst write data. Since PCIe's TLP packets require data to be continuous, it cannot directly process discontinuous data containing gaps. In this case, the burst write data needs to be split into multiple TLP packets at the gaps for transmission. Each split TLP packet contains only continuous valid data and the corresponding write enable signal.

[0033] Splitting an AXI burst write into multiple TLP packets for transmission significantly reduces transmission efficiency. Firstly, each TLP packet needs to contain necessary control information, such as a header and checksum. Splitting the TLP packet increases the overhead of this control information, reducing the amount of valid data transmitted. Secondly, since each TLP packet needs to be transmitted and processed through the PCIe link, the increased number of split TLP packets leads to a corresponding increase in transmission time, thus further increasing transmission latency.

[0034] For example, when the host machine needs the GPU or other coprocessors (i.e., devices) to move matrix data for matrix operations, the matrix data is moved from the host machine's memory to the GPU's memory. For efficient data movement, Direct Memory Access (DMA) is generally used.

[0035] like Figure 1 As shown, the matrix of an AXI burst write data resides in the host's memory. Data already exists in the GPU's memory. The DMA needs to move this AXI burst write data to the GPU's memory, overwriting the matrix within the solid-line box in the original GPU memory data. During the move, the DMA specifies a start address and an end address. Based on these addresses, it determines the specific AXI burst write data to be moved, transferring all of this data to the GPU's memory. An AXI burst write data refers to the multiple data items that need to be continuously transferred in the AXI bus to reduce the overhead of individual transfers.

[0036] However, in the host's storage space, the placement of this AXI burst write data is as follows: Figure 2 As shown, the location where this AXI burst write data needs to be placed in the GPU's storage space is as follows: Figure 3 As shown, the required placement positions are not contiguous. This means that when writing data to the GPU's memory, there are intermediate positions that don't need to be moved, requiring a skip operation. Therefore, during DMA operations... Figure 3 The write enable signal corresponding to the data in the dashed box should be set to 0.

[0037] However, since skipping operations rely on the transmission of the write enable signal, one bit is needed for every 8 bits of data, resulting in a significant bandwidth loss. Furthermore, the PCIe protocol does not support skipping operations for PCIe-based TLP packets, so currently, TLP packets based on PCIe provided by major manufacturers do not support skipping operations.

[0038] Because skipping operations within a TLP packet are not supported, existing technology must resend a new TLP packet whenever a gap (i.e. invalid data) is encountered when handling a discontinuous AXI burst of write data.

[0039] Furthermore, a TLP packet consists of a header and data. The TLP header typically has more than 20 bytes, leaving a limited amount of actual valid data to be carried within it. When the amount of data in an AXI burst write is large, if there are very few gaps, splitting it into multiple TLP packets for transmission has an acceptable impact on the transmission efficiency of that AXI burst write. For example, when an AXI burst write has 256 bytes, if all 256 bytes are consecutive (i.e., all are valid data), only one TLP packet is needed to transport these 256 bytes, requiring only the header of one TLP packet. In this case, the percentage of valid data is approximately 90%, and the ratio of the 20+ bytes required for the header to the total 256 bytes is reasonable. However, if there is one invalid byte in the middle of the 256 bytes, then transporting those 256 bytes requires splitting them into two TLP packets. Each TLP packet's header incurs an additional 20 bytes of overhead, meaning a TLP packet needs to be split every 100 bytes. In this case, splitting into multiple TLP packets for transmission has a significant impact on the transmission efficiency of this AXI burst write data and is very inefficient. Furthermore, if there are four invalid bytes in the middle of the 256 bytes, then a TLP packet needs to be split every 50 bytes, resulting in excessive overhead. In one embodiment, the existing PCIe scheme is used to implement... Figures 1 to 3 When transferring matrix data, it is necessary to split it into 3 TLP packets for transmission.

[0040] In current applications using GPU-accelerated artificial intelligence (AI) computing, invalid bytes frequently appear within a single AXI burst write data. The data to be transported is often fragmented, meaning that valid and invalid data are frequently interleaved. Therefore, in such practical applications, the number of TLP packets required to transport a single AXI burst write data is excessive. Splitting it into multiple TLP packets for transmission has a significant impact on the transmission efficiency of this AXI burst write data, severely affecting transmission efficiency and resulting in poor performance.

[0041] To solve the above problems, such as Figure 4 As shown, this embodiment of the invention provides an optimization method for PCIe carrying AXI write data, including: Step 10: Identify at least one void location in the data to be transferred.

[0042] The data to be transferred refers to a single AXI burst write data that needs to be transferred. A hole location is the position of invalid data within the data to be transferred; the specific representation of the hole location is chosen by those skilled in the art based on the specific application scenario. In one embodiment, the hole location can be represented by the byte number of the invalid data within the data to be transferred.

[0043] First, the host sends a DMA write command and data address through software. Then, the DMA controller generates a write start signal for the memory and starts the generation of TLP packets. During the generation process, instead of dividing and encapsulating the data to be transferred into multiple TLP packets according to existing technology, the operations from step 10 to step 30 below are performed.

[0044] Step 20: Generate a cavity identifier bit based on the at least one cavity location.

[0045] Step 30: Generate an original TLP packet based on the data to be transported; add the void identifier bit to the original TLP packet to obtain the target TLP packet.

[0046] Each TLP contains a target address and control information, etc. The specific method of generating TLP packets based on the data to be transferred shall be determined by those skilled in the art based on the specific use case, and is not limited here.

[0047] This invention avoids splitting TLP packets by adding a hole identifier bit to the TLP packet to identify the hole location in the data to be transferred, thereby increasing the overhead by very little.

[0048] Step 40: Transmit the target TLP packet to the target device to write the data to be transferred into the target device.

[0049] After obtaining the target TLP packet, it is routed to the GPU via the PCIe bus. The GPU receives the target TLP packet and writes it to local memory via the DMA module.

[0050] This invention identifies hole locations by adding a hole identifier bit to the TLP packet, enabling discontinuous data to be transported to be transmitted through a single TLP packet without having to split the data into multiple TLP packets based on hole locations. Since the overhead of adding the hole identifier bit is minimal, it can significantly improve the data transmission efficiency for data with many hole locations compared to splitting the data into multiple TLP packets.

[0051] The following is a further explanation of the optimization method for PCIe carrying AXI write data according to an embodiment of the present invention: Before step 10, the method further includes: determining the degree of dispersion of invalid data distribution in the data to be transferred; when the degree of dispersion meets a preset condition, determining at least one void location in the data to be transferred to generate the target TLP package.

[0052] The preset conditions are determined by those skilled in the art based on the specific application scenario. In one embodiment, the degree of dispersion of invalid data distribution in the data to be transferred can be determined according to the write enable signal of the data to be transferred, and the preset condition can be that the degree of dispersion is greater than a specified value.

[0053] Specifically, since a bit of the write enable signal being 1 indicates valid data in the corresponding byte channel, and a bit being 0 indicates invalid data (i.e., invalid or unnecessary data) in the corresponding byte channel, in the process of generating multiple TLP packets according to existing technology, when invalid data is detected, the next most recent valid data is found, and a new TLP packet is created starting from that valid data. At this time, since the discreteness of invalid data in the data to be transported is low (i.e., the continuity is high), the number of TLP packets that need to be split is not large. Moreover, since there is a lot of continuous invalid data, if the target TLP packet is generated according to the operations of steps 10 to 40, the original TLP packet is generated using the data to be transported and a hole marker is added, which requires the same amount of computing resources as transporting these invalid data. Especially when there is a lot of invalid data, it seriously affects the transmission efficiency.

[0054] In this embodiment of the invention, when the dispersion of invalid data in the data to be transferred is less than or equal to a specified value, instead of generating and transmitting a target TLP packet according to steps 10 to 40, the invention follows existing technology. When encountering a gap in invalid data, it finds the next valid data and creates a new TLP packet, transmitting the data to be transferred by splitting the TLP packet. For cases where the dispersion is greater than the specified value, since existing technology requires splitting too much data into TLP packets, following steps 10 to 40 maximizes the proportion of valid data in the TLP packet, thereby improving transmission efficiency.

[0055] This invention provides two methods for generating target TLP packets. The first method will be described below: In constructing the target TLP package, the first step is to determine the location of the holes, such as... Figure 5 As shown, step 10 includes: Step 101: Determine the first location of the first invalid data in the data to be transferred.

[0056] For example, such as Figure 3 As shown, the first dashed box data C03 is the first invalid data in the data to be transferred. It is located in the fourth byte of the data to be transferred, that is, the first position is the fourth byte.

[0057] Step 102: Determine the second location of the remaining invalid data in the data to be transferred.

[0058] For example, such as Figure 3 As shown, the dashed box data C04, dashed box data C13, dashed box data C14, dashed box data C23, and dashed box data C24 are the remaining invalid data in the data to be transferred. They are located in the fifth, ninth, tenth, fourteenth, and fifteenth bytes of the data to be transferred, respectively. That is, the second positions of these remaining invalid data are the fifth, ninth, tenth, fourteenth, and fifteenth bytes, respectively.

[0059] In one embodiment, step 20 includes: determining the first position as a hole identifier bit. For example, when the first position is the fourth byte, the value of the hole identifier bit is set to 4.

[0060] After obtaining the cavity marker, such as Figure 6 As shown, step 30 includes: Step 301a: Sequentially obtain valid data or invalid data from the data to be transferred; for each piece of valid data, determine the valid data as the corresponding valid byte.

[0061] The valid bytes of the valid data are determined, that is, the valid data is converted into the form required in the TLP packet. After obtaining the valid bytes of each valid data in the data to be transferred, these valid bytes can be used to generate the original TLP packet. The specific method of converting the data into the form required in the TLP packet is selected by those skilled in the art according to the specific use case, and is not limited here.

[0062] When constructing the original TLP packet, for the data to be transferred, valid bytes are determined when valid data is detected, and position bytes are determined when invalid data is detected, thereby generating the original TLP packet.

[0063] For example, for such Figure 3 The data to be transferred shown is as follows: Figure 7 The image shows a specific example of a target TLP packet's data structure; in order to generate such... Figure 7 The target TLP packet shown is first read sequentially as follows: Figure 3 The data to be transferred is shown below. When valid data A00, A01, and A02 are read, valid data A00 is directly converted to valid byte A00, valid data A01 is converted to valid byte A01, and valid data A02 is converted to valid byte A02. Valid bytes A00, A01, and A02 are then arranged sequentially. Next, invalid data C03 and C04 are read. The handling of invalid data will be explained below. Then, valid data A10, A11, and A12 are read. Similarly, valid data A00, A01, and A02 are processed by directly converting valid data A10 to valid byte A10, valid data A11 to valid byte A11, and valid data A12 to valid byte A12. Valid bytes A10, A11, and A12 are then arranged sequentially. This process continues until invalid data C24 is processed.

[0064] Step 302a: For each invalid data, determine the next invalid data in the data to be transferred; determine the second position of the next invalid data as the position byte corresponding to the invalid data.

[0065] In this context, the data in the position byte corresponding to each invalid data indicates the second position of the next invalid data; the position byte corresponding to the last invalid data in the data to be moved points to itself.

[0066] For example, when invalid data C03 is read, since the next invalid data after C03 is invalid data C04, the byte at the position corresponding to invalid data C03 is the position of invalid data C04. For example, when using an index to identify the second position... Figure 3 The position of invalid data C04 is 5; that is, when generating the TLP packet, the next byte after the valid byte A02 is position byte 5. Similarly, since the next invalid data after invalid data C04 is invalid data C13, the next byte after position byte 5 is position byte 9. Then, valid data A10, A11, and A12 are read, and the processing method is not described here. Next, invalid data C13 is read; similarly, after processing invalid data C13, the next byte after the valid byte A12 is position byte 10, and so on.

[0067] Step 303a: Construct the original TLP packet based on the valid bytes and the position bytes.

[0068] Step 304a: Take the first position as the starting byte and add it to the available fields of the header of the original TLP packet to obtain the target TLP packet.

[0069] In one embodiment, the starting byte is a valid preset value, which indicates that there is no invalid data in the data to be transferred. In an optional embodiment, the valid preset value can be 0.

[0070] When generating a TLP packet, in addition to the data to be transferred, a packet header also needs to be added; the packet header often includes a TLP packet prefix. In one embodiment, the available fields in the packet header can be the TLP packet prefix; the TLP packet prefix, which can occupy one byte, is used to indicate the first position, that is, the position of the first invalid data in the data to be transferred; the maximum target TLP packet supported by the one-byte TLP packet prefix is ​​2 kilobits.

[0071] After generating the target TLP packet using the first method, the target TLP packet is transmitted to the target device. Upon receiving the target TLP packet, the target device parses it and writes the data to be transferred into the target device. Specifically, as follows... Figure 8 As shown, the relevant modules will be explained below: The AXI write cache module is used to cache AXI burst write data sent from the AXI bus (i.e., Figure 8 The AXI write parser is used to collect information about AXI burst write data from the AXI bus. The AXI conversion module is used to convert the format of the target TLP packet according to the parsing method corresponding to the target TLP packet generation method in this embodiment of the invention, which will be described below. The PCIe physical layer is used to receive the conversion results in the form of a byte stream from the AXI conversion module. Here, a byte stream is the basic unit for processing binary data, transmitting or manipulating data in a continuous sequence of bytes.

[0072] When the target device completes receiving an AXI burst write data, the AXI write buffer module temporarily stores the AXI burst write data. The AXI write parser obtains the write strobe (wstrob) signal of the AXI burst write data, and then uses all the write strobe signals in the AXI burst write data to determine if there are any gaps and to determine the location of the gaps. Then, it can use the write start signal to inform the AXI conversion module to start format conversion. By analyzing the write strobe signals, it determines the parts of the AXI burst write data that do not need to be written (i.e., gaps). For example, when an AXI burst write data can control 12 addresses, and the user needs to write some data to addresses 0 to 5, not write data to address 6, and write some data to addresses 7 to 10, a gap will appear at address 6.

[0073] The AXI conversion module follows these rules for format conversion: Obtain the first position of the data to be transferred (i.e., the location of the first hole) from the available fields in the header of the target TLP packet; a value of 0 indicates no hole. Read each byte of the payload of the target TLP packet, and determine the position byte in the first position of the data to be transferred as the second position of the next hole in the target TLP packet (i.e., the location of holes in the data to be transferred excluding the first hole), and so on. When the position byte of a hole points to itself, it indicates that it is the last hole in the data to be transferred.

[0074] The following describes another method for generating a target TLP package provided by an embodiment of the present invention: First, a void identifier is set. Step 20 includes: determining the number of invalid data in the data to be transferred, and setting the number as the void identifier. For example, ... Figure 3 As shown, when the number of invalid data is 6, the value of the hole flag is set to 6. When the value of the hole flag is 0, it indicates that there is no invalid data (i.e., no holes) in the data to be transferred.

[0075] After obtaining the cavity marker, such as Figure 9 As shown, step 30 includes: Step 301b: Determine the valid bytes of each valid data in the data to be transferred, so as to construct the original TLP packet based on the data to be transferred.

[0076] The valid data is directly converted into the form required in the TLP packet to obtain at least one valid byte; and according to the existing technology, the necessary structure of the TLP packet, such as the packet header, is added before the at least one valid byte to obtain the original TLP packet.

[0077] For example, for such Figure 3 The data to be transferred shown is as follows: Figure 10 The image shows a specific example of a different target TLP packet data structure; in order to generate such... Figure 10 The target TLP packet shown is read as follows: Figure 3 The data to be transferred shown is converted into corresponding valid bytes A00, A01, A02, A10, A11, A12, A20, A21, and A22 when valid data A00, A01, A02, A10, A11, A12, A20, A21, and A22 are taken out. Valid bytes A00 to A22 are then arranged sequentially to obtain the original TLP packet.

[0078] Step 302b: Add the hole identifier to the available field of the header of the original TLP packet to obtain the intermediate TLP packet.

[0079] In one embodiment, the available fields in the packet header can be a TLP packet prefix; the TLP packet prefix, which can occupy one byte, is used to indicate the number of invalid data in the data to be transferred.

[0080] Step 303b: Obtain the third location of each invalid data in the data to be transferred.

[0081] For example, such as Figure 3 As shown, the invalid data includes: dashed box data C03, dashed box data C04, dashed box data C13, dashed box data C14, dashed box data C23, and dashed box data C24; these are located in the fourth, fifth, ninth, tenth, fourteenth, and fifteenth bytes of the data to be transferred, respectively. That is, the third positions of these remaining invalid data are the fourth, fifth, ninth, tenth, fourteenth, and fifteenth bytes, respectively.

[0082] Step 304b: According to the byte size represented by the hole identifier, store all the third positions using the first preset number of bits in the payload of the intermediate TLP packet to obtain the target TLP packet.

[0083] The preset bit length refers to the byte size represented by the hole identifier bit.

[0084] For example, if the hole flag is set to 6, then the first 6 bits of the payload in the intermediate TLP packet are used to store the third position of all 6 invalid data points, with one invalid data point corresponding to one bit in the payload. Figure 10 As shown, the first 6 bits of the payload of the intermediate TLP packet are used to store the positions of invalid data C03, invalid data C04, invalid data C13, invalid data C14, invalid data C23, and invalid data C24 respectively; for example, when the third position is identified by the subscript number, the first 6 bits of the payload are 4, 5, 9, 10, 14, and 15 respectively.

[0085] The payload of a TLP packet is the data segment that follows the header of the TLP packet. It is used to transmit the actual data content (e.g., data for memory read / write requests, data for configuration space access, etc.) or control instructions.

[0086] After generating the target TLP packet using the second method, the target TLP packet is transmitted to the target device. Upon receiving the target TLP packet, the target device parses it and writes the data to be transferred into the target device. Specifically, as follows... Figure 8 As shown, the workflow of the relevant modules is the same as that of parsing the target TLP package generated by the first method, and will not be repeated here. The difference between the parsing process of the target TLP package generated by the second method and the parsing process of the target TLP package generated by the first method lies in the format conversion rules of the AXI conversion module.

[0087] The AXI conversion module follows these rules for format conversion: Obtain the number of third positions (i.e., the locations of holes) in the data to be transported from the available fields in the header of the target TLP packet; where a value of 0 indicates that there are no holes in the data to be transported. Read each byte in the payload of the target TLP packet, and store the first preset number of bytes in the payload (i.e., the number obtained from the available fields in the header) in the third position to determine the location of each hole in the data to be transported.

[0088] Using the optimized method for PCIE carrying AXI write data of the present invention, the transmission of data to be transferred can be completed with only one TLP packet. Since there is no need to split the TLP packet, the bandwidth loss during the transmission of data to be transferred is greatly reduced.

[0089] like Figure 11 The diagram shown is an architectural schematic of an optimization device for PCIe carrying AXI write data according to an embodiment of the present invention. This optimization device for PCIe carrying AXI write data includes one or more processors 21 and a memory 22. Figure 11 Take a processor 21 as an example.

[0090] Processor 21 and memory 22 can be connected via a bus or other means. Figure 11 Taking the example of a connection between China and Israel via a bus.

[0091] The memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs and non-volatile computer-executable programs, such as the PCIe carrying AXI data writing optimization method in this embodiment. The processor 21 executes the PCIe carrying AXI data writing optimization method by running the non-volatile software program and instructions stored in the memory 22.

[0092] Memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 22 may optionally include memory remotely located relative to processor 21, which can be connected to processor 21 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0093] The program instructions / modules are stored in the memory 22. When executed by one or more processors 21, they perform the optimization method for PCIE carrying AXI data writing in the above embodiments, for example, performing each step of the optimization method for PCIE carrying AXI data writing in the embodiments of the present invention described above.

[0094] This invention also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors, for example... Figure 11 A processor 21 can enable one or more processors to execute the PCIE-carrying AXI data write optimization method in the specific embodiments of the present invention, for example, to execute the various steps of the PCIE-carrying AXI data write optimization method described above in the embodiments of the present invention; it can also implement Figure 11 The various modules and units described above; or the optimization method for PCIE carrying AXI data writing in the specific embodiments of the present invention, for example, executing the various steps of the optimization method for PCIE carrying AXI data writing in the embodiments of the present invention described above; can also achieve Figure 11 The aforementioned modules and units.

[0095] It is worth noting that the information interaction and execution process between the modules and units in the above-mentioned device and system are based on the same concept as the processing method embodiment of the present invention. For details, please refer to the description in the method embodiment of the present invention, and will not be repeated here.

[0096] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An optimization method for PCIe carrying AXI write data, characterized in that, include: Identify at least one void location in the data to be transferred; A cavity identifier is generated based on the location of at least one cavity; Generate the original TLP packet based on the data to be transported; Add the hole identifier bit to the original TLP packet to obtain the target TLP packet; The target TLP packet is transmitted to the target device to write the data to be transferred into the target device.

2. The optimization method for PCIe carrying AXI write data according to claim 1, characterized in that, The method includes: Determine the first location of the first invalid data in the data to be transferred; Determine the second location of the remaining invalid data in the data to be transferred.

3. The optimization method for PCIe carrying AXI write data according to claim 2, characterized in that, The method includes: The first position is designated as the cavity marker.

4. The optimization method for PCIe carrying AXI write data according to claim 3, characterized in that, The method includes: Valid or invalid data from the data to be transferred are obtained sequentially; for each valid data, the valid data is determined as the corresponding valid byte; For each invalid data, determine the next invalid data in the data to be transferred; determine the second position of the next invalid data as the position byte corresponding to the invalid data; Construct the original TLP packet based on the valid bytes and the position bytes; The first position is used as the starting byte and added to the available fields of the header of the original TLP packet to obtain the target TLP packet.

5. The optimization method for PCIe carrying AXI write data according to claim 4, characterized in that, The starting byte is a valid preset value, which indicates that there is no invalid data in the data to be transferred.

6. The optimization method for PCIe carrying AXI write data according to claim 1, characterized in that, The method includes: The number of invalid data in the data to be transferred is determined, and the number is identified as a void identifier.

7. The optimization method for PCIe carrying AXI write data according to claim 6, characterized in that, The method includes: Determine the valid bytes of each valid data in the data to be transferred, so as to construct the original TLP packet based on the data to be transferred; The hole identifier is added to the available field of the header of the original TLP packet to obtain the intermediate TLP packet; Obtain the third location of each invalid data in the data to be transferred; Based on the byte size represented by the hole identifier, all the third positions are stored using the first preset number of bits in the payload of the intermediate TLP packet to obtain the target TLP packet.

8. The optimization method for PCIe carrying AXI write data according to any one of claims 1 to 7, characterized in that, Also includes: Determine the degree of dispersion of invalid data distribution in the data to be transferred; When the degree of dispersion meets the preset conditions, at least one void location in the data to be transported is determined to generate the target TLP package.

9. An optimized device for carrying AXI write data on PCIe, characterized in that, The PCIe carrying AXI write data optimization device includes at least one processor and a memory, which are connected via a data bus. The memory stores instructions that can be executed by the at least one processor. After being executed by the processor, the instructions are used to implement the PCIe carrying AXI write data optimization method according to any one of claims 1 to 8.

10. A non-volatile computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions, which are executed by one or more processors to perform the optimized method for PCIe carrying AXI write data as described in any one of claims 1 to 8.

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