Fast near-field imaging method for quadrilateral MIMO array based on GPU

Abstract

The application relates to the technical field of fast near-field imaging, in particular to a quadrilateral MIMO array fast near-field imaging method based on a GPU, which comprises the following steps: a host end issues control instructions and parameters to a high-speed signal processing board carrying an FPGA, an FPGA drives a frequency synthesizer module to generate a local oscillation signal and distributes the local oscillation signal to a quadrilateral MIMO array; the FPGA controls T / R radio frequency front-end devices, sequentially completes scanning operation of multichannel transmission and reception in a time division multiplexing mode, an ADC samples and converts collected echo signals into digital signals, and then the digital signals are transmitted to a GPU; a parallel imaging architecture is constructed in the GPU, and the whole imaging task is decomposed into several independent sub-imaging tasks; after the current sub-imaging task is completed, the current sub-image is superimposed with the last sub-image, until all the sub-imaging tasks are completed, three-dimensional imaging results of the whole imaging area are obtained, and the three-dimensional imaging results are returned to the host end for display.

Description

Technical Field

[0001] The embodiments of this application relate to the field of fast near-field imaging technology, and in particular to a GPU-based quadrilateral MIMO array fast near-field imaging method. Background Technology

[0002] Millimeter-wave near-field 3D imaging technology, leveraging the excellent penetrating power of millimeter waves through most non-metallic materials and the absence of known health hazards to humans at moderate power levels, has been widely applied in security inspection and other security scenarios. In traditional imaging systems, to simultaneously obtain high-resolution images in both the horizontal and vertical directions, mechanical guides are typically used to drive the radar for two-dimensional scanning to form a large aperture. However, the mechanical movement process is time-consuming, severely limiting overall imaging efficiency. In contrast, electronic scanning systems employing numerous radio frequency channels can significantly improve imaging speed and have gradually become the preferred solution for achieving real-time imaging.

[0003] Quadrilateral MIMO arrays deploy multiple antenna elements at both the transmitter and receiver ends, significantly reducing the number of radio frequency devices while ensuring imaging performance. This makes them a preferred system architecture that balances cost and performance, featuring high spatial resolution, high azimuth resolution, and strong penetration. They are widely used in near-field imaging, non-destructive testing, and security inspection imaging. Quadrilateral array MIMOs also possess excellent directivity and spatial filtering characteristics, enabling flexible three-dimensional beamforming.

[0004] However, in actual large-scale array systems (such as quadrilateral MIMO arrays), due to the large number of transceiver units, if a serial computing architecture is still used, the system hardware cost will increase dramatically, and the computational complexity of the imaging algorithm will also increase, making it difficult to meet the requirements of real-time processing.

[0005] To achieve real-time imaging in radar systems, a parallel computing architecture needs to be designed at the radar signal processing end. Traditional radar signal processing systems mostly rely on embedded platforms such as FPGAs or DSPs for parallel computation acceleration, but these systems suffer from complex architectures, poor maintainability, and long development cycles. In recent years, the rapid development of GPUs has provided a new solution to this problem. GPUs have evolved from initial graphics rendering processors into highly parallel processing platforms with general-purpose computing capabilities. GPUs based on general-purpose development frameworks such as CUDA (Compute Unified Device Architecture) offer advantages such as low development costs and strong parallel computing capabilities, effectively overcoming the limitations of traditional embedded systems and providing a new technical approach for imaging computation.

[0006] However, there are no mature GPU-based near-field imaging solutions on the market yet, and how to fully leverage the massive parallel computing potential of GPUs remains a gap in fast near-field imaging. Summary of the Invention

[0007] To address the aforementioned technical issues, embodiments of this application propose a GPU-based quadrilateral MIMO array fast near-field imaging method. This method aims to build an imaging system based on MIMO arrays, FPGAs, and GPUs, fully leveraging the massive parallel computing potential of GPUs and significantly improving overall imaging efficiency.

[0008] To achieve the above objectives, embodiments of this application propose a GPU-based fast near-field imaging method for quadrilateral MIMO arrays. The method includes: sending control commands and parameters from the host to a high-speed signal processing board equipped with an FPGA; the FPGA, acting as the main control unit of the imaging system, drives a frequency synthesizer module to generate a local oscillator signal and distributes it to the transmitting and receiving units of the quadrilateral MIMO array; the FPGA controls the T / R RF front-end devices to sequentially complete multi-channel transmission and reception scanning operations in a time-division multiplexing mode, transmitting the acquired echo signals to the GPU in real time; constructing a parallel imaging architecture in the GPU based on the SAR-FFT algorithm, decomposing the overall imaging task into several independent sub-imaging tasks according to slices and transmission channels; each sub-imaging task includes four main CUDA parallel computing kernel functions; after the current sub-imaging task is completed, the current sub-image is superimposed with the previous sub-image until all sub-imaging tasks are completed, obtaining the three-dimensional imaging result of the entire imaging area, and transmitting the three-dimensional imaging result of the entire imaging area back to the host for display.

[0009] To achieve the above objectives, embodiments of this application also propose an electronic device, including a processor and a memory, wherein the memory stores instructions executable by the processor, and the processor is configured to execute the instructions such that the electronic device can implement a GPU-based quadrilateral MIMO array fast near-field imaging method as described above.

[0010] To achieve the above objectives, embodiments of this application also propose a computer-readable storage medium storing a computer program that, when executed by a processor, enables a GPU-based quadrilateral MIMO array fast near-field imaging method as described above.

[0011] Optionally, the quadrilateral MIMO array consists of six quadrilateral MIMO subarrays, all of the same size, cascaded at fixed intervals to form an overall imaging system. Each quadrilateral MIMO subarray has 64 receiving units on each of its left and right sides and 64 transmitting units on each of its top and bottom sides. After the parameters are configured, the host computer sends a synchronization signal to each quadrilateral MIMO subarray to synchronize the entire antenna array. After each quadrilateral MIMO subarray is reset, it feeds back its ready status to the timing control board.

[0012] Optionally, the acquired echo signal is represented as The bottom right corner mark and These represent the indices for all transmitting and receiving units, respectively. The wavenumber is indicated. Compared to a full array configuration, the receiving structure of a quadrilateral MIMO array is considered as a sparse sampling of a full array. Since sparse sampling reduces data bandwidth, the FPGA uses a 10 Gigabit Ethernet interface to upload the digital signal obtained from the echo signal to the GPU.

[0013] Optionally, in the SAR-FFT algorithm, the echo signal is first divided into several subsets according to the transmission channel, the first subset being... The subset of echo signals corresponding to each transmitting unit is represented as follows: ; For sparse array configurations, zero-padding is required at non-sampling locations to generate imaging data in full-array reception form, facilitating subsequent rapid imaging and reconstruction. The zero-padding process for the data corresponding to each transmitting unit is expressed by the formula: ; in, Indicates along , A function that performs zero-padding on the signal at non-sampling locations in a given dimension. Indicates the first The zero-padded subset of the echo signal corresponding to each transmitting unit is imaging data in the same form as the data received by the full array. The GPU-based SAR-FFT algorithm employs a slice imaging strategy, assuming the target image is... The reconstruction process of the GPU-based SAR-FFT algorithm is then represented as follows: ; ; ; in, Indicates proceeding along Fourier transform of the plane Indicates proceeding along Inverse Fourier Transform in Plane Indicates proceeding along The Fourier transform of the free-space impulse response in a plane is used for backpropagation phase compensation. Indicates the first Spatial phase compensation factor corresponding to each transmitting unit.

[0014] Optionally, based on the imaging process of the SAR-FFT algorithm, the overall imaging task is decomposed into several independent sub-imaging tasks according to slices and transmission channels, assuming the number of slices is... The number of launch channels is In each sub-imaging task, four main CUDA parallel computing kernel functions are designed: a data zero-padding kernel, an inverse propagation compensation kernel, and two wavenumber direction accumulation kernels. The Fourier transform operation is completed by the efficient FFT computing library provided by CUDA. The computational scale of each sub-imaging task is determined by the dimensions in the horizontal, vertical, and wavenumber directions, denoted as follows: , and All kernel functions are executed on the same CUDA stream, denoted as stream0, and are sequentially scheduled and called by the host. Because the imaging area in human imaging applications is large, the input data scale of each computing core is also relatively large. Therefore, five global memory blocks are allocated on the GPU for caching intermediate results and data interaction, namely GlobalMemory 1, Global Memory 2, Global Memory 3, Global Memory 4 and Global Memory 5. Global Memory 1 is used to store the complete echo data, with a size of [size missing]. ; Global Memory 2 is used to store backpropagation compensation data in the frequency domain, with a size of [size missing]. ; Global Memory 3 and Global Memory 4 are used to store intermediate results during multi-core processing, and both are [size missing]. ; Global Memory 5 is used to store the final imaging results of all slices, with a size of [size missing]. .

[0015] Optionally, the distance is The first slice The calculation process for each sub-image is expressed by the formula: ; in, Indicates distance as The first slice Sub-images.

[0016] Optionally, the implementations of the four main CUDA parallel computing kernels defined in the GPU include: In a single core, the parallel execution structure of the GPU consists of two levels: Block and Thread. Each Block contains several Threads, and the upper limit of the number is determined by the hardware resource constraints of the GPU. In order to achieve efficient parallelization of the SAR-FFT algorithm, the spatial dimension of imaging computation is mapped to the parallel structure of the GPU's hardware resources. During the data padding process, a zero is first allocated on the GPU. The three-dimensional all-zero memory block sets GlobalMemory 2 to zero and fills the corresponding positions with valid echo data in parallel. The data zero-filling process is achieved through the collaborative mapping between Block and Thread. In the remaining processing cores, The computational task of dimension is mapped to the Thread hierarchy, meaning each Thread is responsible for one dimension. The calculation of the direction sampling points will Dimensions and The dimensional computation tasks are mapped to the Block x level and the Block y level, respectively.

[0017] Optionally, after the current sub-imaging task is completed, the current sub-image is... Overlay the image with the previous sub-image already stored in Global Memory 5, and write the result back to Global Memory 5; by slicing the image. and transmitter dimension The overlay operation is repeated cyclically to obtain the three-dimensional imaging result of the entire imaging area.

[0018] This application proposes a GPU-based fast near-field imaging method using a quadrilateral MIMO array. The imaging system is built upon a quadrilateral MIMO array, FPGA, and GPU. The user first sends control commands and parameters to a high-speed signal processing board equipped with an FPGA via the host computer. The FPGA, as the system's main control unit, drives the frequency synthesizer module to generate a local oscillator signal and distributes it to the transmitting and receiving units of the quadrilateral MIMO array. Subsequently, the FPGA controls the T / R RF front-end devices to sequentially complete multi-channel transmission and reception scanning operations in a time-division multiplexing mode. When electromagnetic waves irradiate the target, scattered echoes are generated. The receiving array works synchronously, using an analog-to-digital converter to sample the received signals at high speed and convert them into digital signals. Then, the FPGA transmits a large amount of digitized scattered signals to the computing platform in real time. The parallel computing model allows for flexible programming of parallel strategies to fully utilize the GPU's computing potential, significantly improving overall imaging efficiency. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies of this application will be briefly introduced below. Obviously, the following drawings are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The drawings described herein are only used to explain this application and are not intended to limit this application.

[0020] Figure 1 This is a flowchart of a GPU-based quadrilateral MIMO array fast near-field imaging method provided in one embodiment of this application; Figure 2 This is a schematic diagram of the imaging system provided in one embodiment of this application; Figure 3 This is a schematic diagram of a single subarray antenna arrangement provided in one embodiment of this application; Figure 4 This is a schematic diagram of a six-subarray cascaded imaging system provided in one embodiment of this application; Figure 5 This is a schematic diagram of a parallel imaging computing architecture provided in one embodiment of this application; Figure 6 This is a schematic diagram of a parallel data zero-padding process provided in one embodiment of this application; Figure 7 This is a schematic diagram of the backpropagation compensation parallel operation process provided in one embodiment of this application; Figure 8 This is a comparison chart of the time consumption of serial and parallel operations provided in one embodiment of this application; Figure 9This is a security screening image of a person carrying dangerous goods provided in one embodiment of this application; Figure 10 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. Those skilled in the art will understand that many technical details have been presented in the embodiments of this application to facilitate better understanding. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this application. The following embodiments can be combined with and referenced by each other without contradiction.

[0022] One embodiment of this application proposes a GPU-based quadrilateral MIMO array fast near-field imaging method. The implementation details of the GPU-based quadrilateral MIMO array fast near-field imaging method proposed in this embodiment are described below. The following implementation details are provided for ease of understanding and are not necessary for implementing this solution.

[0023] The specific process of the GPU-based quadrilateral MIMO array fast near-field imaging method proposed in this embodiment can be described as follows: Figure 1 As shown, this method is based on... Figure 2 The imaging system shown is implemented, specifically consisting of an FPGA, a host computer (CPU), a GPU, a frequency synthesizer, and a radio frequency front-end (quadrilateral MIMO array). The method specifically includes: Step 11: The host sends control commands and parameters to the high-speed signal processing board equipped with FPGA. The FPGA, as the main control unit of the imaging system, drives the frequency synthesizer module to generate local oscillator signals and distributes them to the transmitting and receiving units of the quadrilateral MIMO array.

[0024] In the specific implementation, before imaging, control commands and parameters are first sent from the host (CPU) to the high-speed signal processing board equipped with FPGA. The FPGA, as the main control unit of the imaging system, drives the frequency synthesizer module to generate local oscillator signals and distributes them to the transmitting and receiving units of the quadrilateral MIMO array (RF front end).

[0025] In one example, the quadrilateral MIMO array consists of six identical quadrilateral MIMO subarrays, which are cascaded at fixed intervals to form the overall imaging system (i.e., the quadrilateral MIMO array). Each quadrilateral MIMO subarray has 64 receiving units on each of its left and right sides and 64 transmitting units on each of its top and bottom sides.

[0026] The specific structure of the quadrilateral MIMO singleton array can be described as follows: Figure 3 As shown, the specific structure of a quadrilateral MIMO array composed of six quadrilateral MIMO subarrays can be described as follows: Figure 4 As shown. Boundary length and spacing of the quadrilateral MIMO subarray. All values ​​are set to 0.1701m, and the size of the quadrilateral MIMO array, which consists of six quadrilateral MIMO subarrays, is set to 0.8505m × 0.5103m.

[0027] After the host computer completes the parameter configuration, it sends a synchronization signal to each quadrilateral MIMO subarray to achieve synchronization of the entire antenna array. After resetting, each quadrilateral MIMO subarray reports its ready status to the timing control board. The relevant parameter settings for the MIMO millimeter-wave radar configuration are shown in Table 1.

[0028] Table 1: MIMO Millimeter-Wave Radar Configuration Parameter Settings

[0029] Step 12: The FPGA controls the T / R RF front-end device to complete the scanning operation of multi-channel transmission and reception in time-division multiplexing mode, and transmits the collected echo signal to the GPU in real time.

[0030] In the specific implementation, after the control commands and parameters are issued and configured, the FPGA can control the T / R RF front-end device to complete the scanning operation of multi-channel transmission and reception in a time-division multiplexing mode. The collected echo signals are sampled and converted by the ADC and then transmitted to the GPU in real time.

[0031] In one example, due to the use of time-division multiplexing RF scanning mode and time-slicing, the acquired echo signal can be represented as follows: The bottom right corner mark and These represent the indices for all transmitting and receiving units, respectively. This represents the wavenumber. Compared to a full array configuration, the receiver structure of a quadrilateral MIMO array can be viewed as a sparse sampling of a full array, i.e. and They represent respectively to and The Secondary sampling, due to the reduced data bandwidth of sparse sampling, allows the FPGA to use a 10 Gigabit Ethernet interface to upload the digital signal obtained from the echo signal to the GPU.

[0032] Step 13: Construct a parallel imaging architecture in the GPU based on the SAR-FFT algorithm. Decompose the overall imaging task into several independent sub-imaging tasks according to slices and transmission channels. Each sub-imaging task has four main CUDA parallel computing kernel functions.

[0033] In practical implementation, GPUs possess large-scale parallel computing resources, making them particularly suitable for real-time imaging algorithms with strong parallel characteristics. Furthermore, the CUDA parallel computing model allows for flexible setting of parallel strategies in a programmatic manner to fully leverage the computing potential of GPUs. Considering that the SAR-FFT algorithm has significant advantages in both computational efficiency and imaging quality, this embodiment constructs a parallel imaging architecture based on the SAR-FFT algorithm in the GPU. The overall imaging task is decomposed according to slices and transmission channels, forming several independent sub-imaging tasks. Each sub-imaging task is designed with four main CUDA parallel computing kernel functions.

[0034] In the SAR-FFT algorithm, the echo signal is first divided into several subsets according to the transmission channel, the... The subset of echo signals corresponding to each transmitting unit is represented as follows: For this type of sparse array configuration, non-sampling locations need to be pre-padded with zeros to form imaging data in full-array reception form, which facilitates subsequent rapid imaging and reconstruction.

[0035] No. The zero-padding process for the data corresponding to each transmitting unit is expressed by the formula: ; in, Indicates along , A function that performs zero-padding on the signal at non-sampling locations in a given dimension. Indicates the first The zero-padded subset of the echo signal corresponding to each transmitting unit is imaging data in the same form as the data received by the full array.

[0036] The GPU-based SAR-FFT algorithm employs a slice imaging strategy, assuming the target image is... The reconstruction process of the GPU-based SAR-FFT algorithm is then represented as follows: ; ; ; in, Indicates proceeding along Fourier transform of the plane Indicates proceeding along Inverse Fourier Transform in Plane Indicates proceeding along The Fourier transform of the free-space impulse response in a plane is used for backpropagation phase compensation. Indicates the first Spatial phase compensation factor corresponding to each transmitting unit.

[0037] To fully leverage the parallel computing potential of GPUs, based on the SAR-FFT algorithm's imaging workflow, the overall imaging task is decomposed into several independent sub-imaging tasks according to slices and transmission channels. Let the number of slices be... The number of launch channels is In each sub-imaging task, four main CUDA parallel computing kernel functions are designed: a data zero-padding kernel, an inverse propagation compensation kernel, and two wavenumber direction accumulation kernels. The Fourier transform operation is performed by the efficient FFT computing library (CUFFT) provided by CUDA.

[0038] The computational scale of each sub-imaging task is determined by the dimensions in the horizontal, vertical, and wavenumber directions, denoted as follows: , and All kernel functions execute on the same CUDA stream, denoted as stream0, and are sequentially scheduled and called by the host. The parallel imaging computation architecture can be as follows: Figure 5 As shown.

[0039] Because the imaging area in human imaging applications is large, the input data scale of each computing core is also relatively large. Therefore, five global memory blocks are allocated on the GPU for caching intermediate results and data interaction, namely GlobalMemory 1 to Global Memory 5.

[0040] Global Memory 1 is used to store the complete echo data, with a size of [size missing]. .

[0041] Global Memory 2 is used to store backpropagation compensation data in the frequency domain, with a size of [size missing]. .

[0042] Global Memory 3 and Global Memory 4 are used to store intermediate results during multi-core processing, and both are [size missing]. .

[0043] Global Memory 5 is used to store the final imaging results of all slices, with a size of [size missing]. .

[0044] Distance is The first slice The calculation process for each sub-image is expressed by the formula: ; in, Indicates distance as The first slice Sub-images.

[0045] The implementations of the four main CUDA parallel computing kernels defined in the GPU are as follows.

[0046] Within a single kernel, the parallel execution structure of a GPU consists of two levels: Blocks and Threads. Each Block contains several Threads, the upper limit of which is determined by the GPU's hardware resource constraints. To achieve efficient parallelization of the SAR-FFT algorithm, the spatial dimension of imaging computation is mapped to the parallel structure of the GPU's hardware resources.

[0047] During the data padding process, a zero is first allocated on the GPU. A three-dimensional all-zero memory block is used. GlobalMemory 2 is set to zero, and valid echo data is filled into the corresponding positions in parallel. The zero-padding process is achieved through the collaborative mapping between Block and Thread, as follows: Figure 6 As shown.

[0048] In the remaining processing cores, The computational task of dimension is mapped to the Thread hierarchy, meaning each Thread is responsible for one dimension. The calculation of the direction sampling points will Dimensions and The dimensional computation tasks are mapped to Block x and Block y levels, respectively. For a clearer understanding of this mapping structure, please refer to [reference needed]. Figure 7 , Figure 7 The parallel computation process of 2DFFT and backpropagation compensation is demonstrated.

[0049] Step 14: After the current sub-imaging task is completed, the current sub-image is superimposed with the previous sub-image until all sub-imaging tasks are completed, so as to obtain the three-dimensional imaging result of the entire imaging area, and the three-dimensional imaging result of the entire imaging area is sent back to the host for display.

[0050] In the specific implementation, after the current sub-imaging task is completed, the current sub-image can be superimposed with the previous sub-image until all sub-imaging tasks are completed, so as to obtain the three-dimensional imaging result of the entire imaging area, and then the three-dimensional imaging result of the entire imaging area is sent back to the host for display.

[0051] In one example, after the current sub-imaging task is completed, the current sub-image is... Overlay the image with the previous sub-image already stored in Global Memory 5, and write the result back to Global Memory 5, by slicing the image. and transmitter dimension The overlay operation is performed iteratively to obtain the three-dimensional imaging result of the entire imaging area. This mapping strategy fully leverages the multi-dimensional parallel computing capabilities of the GPU, achieving efficient acceleration of the SAR-FFT algorithm and effectively improving the real-time performance of the entire imaging system.

[0052] This embodiment proposes a GPU-based fast near-field imaging method using a quadrilateral MIMO array. The imaging system is built using a quadrilateral MIMO array, FPGA, and GPU. The user first sends control commands and parameters to a high-speed signal processing board equipped with an FPGA via the host computer. The FPGA, as the system's main control unit, drives the frequency synthesizer module to generate a local oscillator signal and distributes it to the transmitting and receiving units of the quadrilateral MIMO array. Subsequently, the FPGA controls the T / R RF front-end devices to sequentially complete multi-channel transmission and reception scanning operations in a time-division multiplexing mode. When electromagnetic waves irradiate the target, scattered echoes are generated. The receiving array works synchronously, using an analog-to-digital converter to sample the received signals at high speed and convert them into digital signals. Then, the FPGA transmits a large amount of digitized scattered signals to the computing platform in real time. The parallel computing model allows for flexible programming of parallel strategies to fully utilize the GPU's computing potential, significantly improving overall imaging efficiency.

[0053] The steps described above are merely for clarity in describing the technical solution. In actual implementation, they can be combined into one step, or certain steps can be broken down into multiple steps, as long as they involve the same logical relationship, they are all within the scope of protection of this application. Any insignificant modifications or designs added to the algorithm or process, as long as they do not change the core of the algorithm or process, are also within the scope of protection of this application.

[0054] In one embodiment, to verify the effectiveness of the GPU-based quadrilateral MIMO array fast near-field imaging method proposed in this application, we conducted simulation verification.

[0055] In the actual system, the size of the imaging region is set according to the target size. The number of ADC sampling points is set to 200. To accelerate imaging, the signal along the sampling point dimension is filtered and decimated to 50 points. To evaluate the performance of the proposed parallel strategy, a serial imaging operation was designed on the Matlab platform. The computation time of the two calculation methods under different imaging regions is as follows: Figure 8 As shown in the figure. The results show that, compared with serial computation, the parallel strategy proposed in this application achieves a speedup of approximately two orders of magnitude.

[0056] To verify the performance of the parallel strategy and imaging system proposed in this application in a real-world scenario, we conducted an experiment on a person carrying dangerous items using a real imaging system. In the experiment, the person stood 0.8m directly in front of the imaging system. Based on typical human body dimensions, the imaging area was set to 256×384, with 5 slices and a slice spacing of 0.01m. The person being tested was carrying a knife on their back. The imaging results are as follows: Figure 9 As shown, the outline of dangerous goods can be clearly identified, which verifies the effectiveness and feasibility of the parallel strategy proposed in this application in real security inspection scenarios.

[0057] Another embodiment of this application provides an electronic device, such as Figure 10 As shown, it includes a processor 21 and a memory 22. The memory 22 stores instructions that the processor 21 can execute. When the processor 21 is configured to execute the instructions, the electronic device can realize a GPU-based quadrilateral MIMO array fast near-field imaging method as described in the above method embodiment.

[0058] The memory and processor are connected via a bus, which includes any number of interconnecting buses and bridges, connecting various circuits of one or more processors and the memory. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.

[0059] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0060] Another embodiment of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, enables a GPU-based quadrilateral MIMO array fast near-field imaging method as described in the above method embodiments.

[0061] That is, those skilled in the art will understand that all or part of the steps in the above method embodiments can be implemented by a program instructing related hardware. The program is stored in a storage medium and includes several instructions to cause a device (such as a microcontroller, chip, etc.) or processor to execute all or part of the steps of the method described in the method embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

[0062] It will be understood by those skilled in the art that the above embodiments are specific implementations of this application, and various changes in form and detail can be made in practical applications without departing from the spirit and scope of this application. For those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A fast near-field imaging method based on a GPU-based quadrilateral MIMO array, characterized in that, The method includes: The host sends control commands and parameters to the high-speed signal processing board equipped with FPGA. The FPGA, as the main control unit of the imaging system, drives the frequency synthesizer module to generate local oscillator signals and distributes them to the transmitting and receiving units of the quadrilateral MIMO array. The FPGA controls the T / R RF front-end device, and in time-division multiplexing mode, it sequentially completes the scanning operation of multi-channel transmission and reception, and transmits the collected echo signal to the GPU in real time. A parallel imaging architecture based on the SAR-FFT algorithm is constructed in the GPU. The overall imaging task is decomposed into several independent sub-imaging tasks according to slices and transmission channels. Each sub-imaging task is designed with four main CUDA parallel computing kernel functions. After the current sub-imaging task is completed, the current sub-image is superimposed with the previous sub-image until all sub-imaging tasks are completed, thus obtaining the three-dimensional imaging result of the entire imaging area. The three-dimensional imaging result of the entire imaging area is then sent back to the host for display.

2. The fast near-field imaging method based on a GPU quadrilateral MIMO array according to claim 1, characterized in that, The quadrilateral MIMO array consists of six quadrilateral MIMO subarrays, all of which are the same size and are cascaded at fixed intervals to form an overall imaging system. Each quadrilateral MIMO subarray has 64 receiving units on the left and right sides of its boundary and 64 transmitting units on the top and bottom sides. After the parameters are configured, the host will send a synchronization signal to each quadrilateral MIMO subarray to achieve synchronization of the entire antenna array. After the quadrilateral MIMO subarray is reset, it will report the ready status to the timing control board.

3. The fast near-field imaging method based on a GPU quadrilateral MIMO array according to claim 1, characterized in that, The acquired echo signal is represented as The bottom right corner mark and These represent the indices for all transmitting and receiving units, respectively. Indicates wave number; Compared to a full array configuration, the receiving structure of a quad MIMO array is considered a sparse sampling of the full array. Since sparse sampling reduces data bandwidth, the FPGA uses a 10 Gigabit Ethernet interface to upload the digital signal obtained from the echo signal to the GPU.

4. The fast near-field imaging method based on a GPU quadrilateral MIMO array according to claim 3, characterized in that, In the SAR-FFT algorithm, the echo signal is first divided into several subsets according to the transmission channel, the... The subset of echo signals corresponding to each transmitting unit is represented as follows: ; For sparse array configurations, zero-padding is required at non-sampling locations to generate imaging data in full-array reception form, facilitating subsequent rapid imaging and reconstruction. The zero-padding process for the data corresponding to each transmitting unit is expressed by the formula: ； in, Indicates along , A function that performs zero-padding on the signal at non-sampling locations in a given dimension. Indicates the first The zero-padded subset of the echo signal corresponding to each transmitting unit is imaging data in the same form as the data received by the full array. The GPU-based SAR-FFT algorithm employs a slice imaging strategy, assuming the target image is... The reconstruction process of the GPU-based SAR-FFT algorithm is then represented as follows: ； ； ； in, Indicates proceeding along Fourier transform of the plane Indicates proceeding along Inverse Fourier Transform in Plane Indicates proceeding along The Fourier transform of the free-space impulse response in a plane is used for backpropagation phase compensation. Indicates the first Spatial phase compensation factor corresponding to each transmitting unit.

5. The fast near-field imaging method based on a GPU quadrilateral MIMO array according to claim 4, characterized in that, Based on the imaging process of the SAR-FFT algorithm, the overall imaging task is decomposed into several independent sub-imaging tasks according to slices and transmission channels. Let the number of slices be... The number of launch channels is In each sub-imaging task, four main CUDA parallel computing kernel functions are designed: a data zero-padding kernel, an inverse propagation compensation kernel, and two wavenumber direction accumulation kernels. The Fourier transform operation is completed by the efficient FFT computing library provided by CUDA. The computational scale of each sub-imaging task is determined by the dimensions in the horizontal, vertical, and wavenumber directions, denoted as follows: , and All kernel functions are executed on the same CUDA stream, denoted as stream0, and are sequentially scheduled and called by the host. Because the imaging area in human imaging applications is large, the input data scale of each computing core is also relatively large. Therefore, five global memory blocks are allocated on the GPU for caching intermediate results and data interaction, namely Global Memory 1, Global Memory 2, Global Memory 3, Global Memory 4 and Global Memory 5. Global Memory 1 is used to store the complete echo data, with a size of [size missing]. ; Global Memory 2 is used to store backpropagation compensation data in the frequency domain, with a size of [size missing]. ; Global Memory 3 and Global Memory 4 are used to store intermediate results during multi-core processing, and both are [size missing]. ; Global Memory 5 is used to store the final imaging results of all slices, with a size of [size missing]. .

6. The fast near-field imaging method based on a GPU quadrilateral MIMO array according to claim 5, characterized in that, Distance is The first slice The calculation process for each sub-image is expressed by the formula: ； in, Indicates distance as The first slice Sub-images.

7. A fast near-field imaging method based on a GPU quadrilateral MIMO array according to claim 6, characterized in that, The implementations of the four main CUDA parallel computing kernels defined in the GPU include: In a single core, the parallel execution structure of the GPU consists of two levels: Block and Thread. Each Block contains several Threads, and the upper limit of the number is determined by the hardware resource constraints of the GPU. In order to achieve efficient parallelization of the SAR-FFT algorithm, the spatial dimension of imaging computation is mapped to the parallel structure of the GPU's hardware resources. During the data padding process, a zero is first allocated on the GPU. The three-dimensional all-zero memory block sets Global Memory 2 to zero and fills the corresponding positions with valid echo data in parallel. The data zero-filling process is achieved through the collaborative mapping between Block and Thread. In the remaining processing cores, The computational task of dimension is mapped to the Thread hierarchy, meaning each Thread is responsible for one dimension. The calculation of the direction sampling points will Dimensions and The dimensional computation tasks are mapped to the Block x level and the Block y level, respectively.

8. A fast near-field imaging method based on a GPU quadrilateral MIMO array according to claim 6, characterized in that, After the current sub-imaging task is completed, the current sub-image will be... Overlay the image with the previous sub-image already stored in Global Memory 5, and write the result back to Global Memory 5; By slice dimension and transmitter dimension The overlay operation is repeated cyclically to obtain the three-dimensional imaging result of the entire imaging area.

9. An electronic device, characterized in that, include: A processor and a memory, wherein the memory stores instructions executable by the processor, and the processor is configured to, when executing the instructions, enable the electronic device to implement a GPU-based quadrilateral MIMO array fast near-field imaging method as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it can implement a GPU-based quadrilateral MIMO array fast near-field imaging method as described in any one of claims 1 to 8.

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