Display substrate and display device

Abstract

The display substrate and the display device are provided. The display substrate comprises a substrate and a plurality of sub-pixels arranged on one side of the substrate. The sub-pixel comprises a pixel driving circuit, and the pixel driving circuit comprises a plurality of transistors. The transistor comprises an active layer and at least one gate electrode. In the same transistor, the at least one gate electrode at least partially overlaps with the active layer, and the at least one gate electrode comprises at least one of a top gate and a bottom gate. The bottom gate is located on the side of the active layer close to the substrate, and the top gate is located on the side of the active layer away from the substrate. In the same pixel driving circuit, the plurality of transistors comprise at least one first type transistor and at least one second type transistor. The first type transistor comprises at least one of a top gate and a bottom gate, and the second type transistor comprises a top gate and a bottom gate. The technical scheme provided by the display substrate and the display device can reduce the difficulty of narrowing the frame of the display substrate.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Currently, display substrates face the technical challenge of narrowing bezels. Summary of the Invention

[0004] The problem to be solved by the embodiments of this disclosure is to provide a display substrate and a display device to solve the technical problem of the difficulty in narrowing the bezel of existing display substrates.

[0005] To address the aforementioned technical problems, in a first aspect, embodiments of this disclosure provide a display substrate, comprising: a substrate and a plurality of sub-pixels disposed on one side of the substrate, at least one sub-pixel including a pixel driving circuit, the at least one pixel driving circuit including a plurality of transistors, the transistors including an active layer and at least one gate; in the same transistor, the at least one gate at least partially overlaps with the active layer, the at least one gate including at least one of a top gate and a bottom gate; in a direction perpendicular to the plane of the substrate, the bottom gate is located on the side of the active layer closer to the substrate, and the top gate is located on the side of the active layer away from the substrate;

[0006] In the same pixel driving circuit, the plurality of transistors include at least one first type transistor and at least one second type transistor, wherein the first type transistor includes at least one of a top gate and a bottom gate, and the second type transistor includes a top gate and a bottom gate.

[0007] In an exemplary embodiment, the plurality of transistors includes a third transistor as a driving transistor, a fifth transistor as a light-emitting control transistor, and a sixth transistor as a light-emitting control transistor, wherein the first terminal of the third transistor is connected to the second terminal of the fifth transistor, and the second terminal of the third transistor is connected to the first terminal of the sixth transistor; the second type of transistor includes the third transistor.

[0008] In an exemplary embodiment, the plurality of transistors further includes a first transistor as a reset transistor, a second transistor as a reset transistor, and a fourth transistor as a data write transistor, wherein one or more of the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are first type transistors;

[0009] The second terminals of the first transistor and the fourth transistor are connected to the control terminal of the third transistor, and the second terminal of the second transistor is connected to the second terminal of the sixth transistor.

[0010] In an exemplary embodiment, the display substrate further includes a first reset control line, a second reset control line, and a scan signal line. The control electrode of the first transistor is connected to the first reset control line, the control electrode of the second transistor is connected to the second reset control line, and the control electrode of the fourth transistor is connected to the scan signal line.

[0011] In an exemplary embodiment, the display substrate further includes a plurality of gate control signal lines, the plurality of gate control signal lines including a first light emission control line and a second light emission control line, the first type of transistor including at least one of the fifth transistor and the sixth transistor, the first light emission control line being connected to the control electrode of the fifth transistor, and the second light emission control line being connected to the control electrode of the sixth transistor.

[0012] In an exemplary embodiment, the pixel driving circuit further includes at least one capacitor, the capacitor including a first plate and a second plate;

[0013] In a direction perpendicular to the plane of the substrate, the display substrate includes: an active layer of a first type of transistor located on one side of the substrate, a top gate of a first type of transistor located on the side of the active layer of the first type of transistor away from the substrate, a bottom gate of a second type of transistor located on the side of the top gate of the first type of transistor away from the substrate, an active layer of a second type of transistor located on the side of the bottom gate of the second type of transistor away from the substrate, a top gate of a second type of transistor located on the side of the active layer of the second type of transistor away from the substrate, and a first electrode and a second electrode of a plurality of transistors located on the side of the top gate of the second type of transistor away from the substrate;

[0014] The first plate of the capacitor is disposed on the same layer as the top gate of the first type of transistor, and the second plate of the capacitor is disposed on the same layer as the bottom gate of the second type of transistor.

[0015] In an exemplary embodiment, the at least one capacitor includes a first capacitor and a second capacitor, and the second type of transistor further includes a first transistor as a reset transistor, a second transistor as a reset transistor, and a fourth transistor as a data write transistor; the second terminal of the first transistor is connected to the first plate of the first capacitor, the second terminal of the second transistor is connected to the second terminal of the sixth transistor, the second terminal of the fourth transistor is connected to the first plate of the first capacitor and the top gate of the third transistor, the second terminal of the third transistor and the first terminal of the sixth transistor are connected to the second plate of the first capacitor and the second plate of the second capacitor, and the first terminal of the fifth transistor is connected to the first plate of the second capacitor;

[0016] In the same sub-pixel, the orthogonal projection of the second capacitor onto the substrate at least partially overlaps with the orthogonal projection of the third transistor onto the substrate. In a second direction, the first transistor and the fourth transistor are located on opposite sides of the third transistor, the fifth transistor is located on the side of the fourth transistor away from the third transistor, the sixth transistor is located on the side of the first transistor away from the third transistor, and the second transistor is located on the side of the sixth transistor away from the third transistor. At least a portion of the structure of the first capacitor is located between the third transistor and the sixth transistor. In a first direction, at least a portion of the structure of the first capacitor, the first transistor, and the fourth transistor are located on the same side of the second transistor, the third transistor, the fifth transistor, and the sixth transistor. In a plane parallel to the substrate, the first direction intersects the second direction.

[0017] In an exemplary embodiment, the display substrate further includes a first reset control line, a second reset control line, and a scan signal line; the first reset control line, the second reset control line, and the scan signal line are disposed on the same layer as the first and second electrodes of the plurality of transistors;

[0018] The first reset control line is connected to the top and bottom gates of the first transistor, the second reset control line is connected to the top and bottom gates of the second transistor, and the scan signal line is connected to the top and bottom gates of the fourth transistor; in the same sub-pixel, in the second direction, the first reset control line is located between the third transistor and the sixth transistor, the second reset control line is located on the side of the sixth transistor away from the third transistor, and the scan signal line is located between the third transistor and the fifth transistor.

[0019] In an exemplary embodiment, the display substrate further includes a first light-emitting control line and a second light-emitting control line, the first type of transistor includes the fifth transistor, and the second type of transistor further includes the sixth transistor; the region where the first light-emitting control line overlaps with the active layer of the fifth transistor serves as the top gate of the fifth transistor, and the region where the second light-emitting control line overlaps with the active layer of the sixth transistor serves as the top gate of the sixth transistor.

[0020] The first light-emitting control line is disposed on the same layer as the top gate of the first type of transistor, and the second light-emitting control line is disposed on the same layer as the top gate of the second type of transistor; in the same sub-pixel, in the second direction, the first light-emitting control line and the fifth transistor are located on the same side of the third transistor, and the second light-emitting control line and the sixth transistor are located on the same side of the third transistor.

[0021] In an exemplary embodiment, the display substrate further includes a first shielding line, which is disposed on the same layer as the bottom gate of the second type of transistor, and the orthographic projection of the first shielding line on the substrate at least partially overlaps with the orthographic projection of the second light-emitting control line on the substrate.

[0022] The area where the first shielding line overlaps with the active layer of the sixth transistor serves as the bottom gate of the sixth transistor.

[0023] In an exemplary embodiment, the substrate includes a display area and a border area surrounding the display area. The plurality of sub-pixels are located in the display area. The border area located on at least one side of the display area is provided with a plurality of gate driving circuit groups. The plurality of gate driving circuits in the same gate driving circuit group are cascaded. The plurality of gate driving circuit groups include a first light-emitting gate driving circuit group and a second light-emitting gate driving circuit group.

[0024] The plurality of sub-pixels form multiple rows. In at least one first light-emitting gate driving circuit in the first light-emitting gate driving circuit group, the same first light-emitting gate driving circuit is configured to be connected to the control electrode of the fifth transistor in at least two rows of sub-pixels. In at least one second light-emitting gate driving circuit in the second light-emitting gate driving circuit group, the same second light-emitting gate driving circuit is configured to be connected to the control electrode of the sixth transistor in at least two rows of sub-pixels.

[0025] In an exemplary embodiment, the nth-level first light-emitting gate driving circuit is configured to be connected to the control electrode of the fifth transistor in the (2n-1)th and (2n-1)th row sub-pixels; the nth-level second light-emitting gate driving circuit is configured to be connected to the control electrode of the sixth transistor in the (2n-1)th and (2n-1)th row sub-pixels; where n is a positive integer greater than or equal to 1.

[0026] In a second aspect, the present disclosure also provides a display substrate, which may include: a display area and a border area surrounding the display area, the display area having a plurality of sub-pixels, at least one sub-pixel including a pixel driving circuit, at least one pixel driving circuit including a plurality of transistors, and a border area located on at least one side of the display area having a plurality of gate driving circuit groups, the plurality of gate driving circuits in the same gate driving circuit group being cascaded.

[0027] In at least one of the plurality of gate driving circuit groups, the same gate driving circuit group is configured to be electrically connected to at least two transistors in the same pixel driving circuit.

[0028] In an exemplary embodiment, the plurality of transistors includes a third transistor as a driving transistor, a first transistor as a reset transistor, a second transistor as a reset transistor, and a sixth transistor as a light-emitting control transistor; the second terminal of the first transistor is connected to the control terminal of the third transistor, the second terminal of the second transistor is connected to the second terminal of the sixth transistor, and the first terminal of the sixth transistor is connected to the second terminal of the third transistor.

[0029] The control electrode of the first transistor and the control electrode of the second transistor are configured to be electrically connected to the same gate drive circuit group.

[0030] In an exemplary embodiment, the plurality of gate driving circuit groups includes a second light-emitting gate driving circuit group, which is configured to be electrically connected to the control electrode of the first transistor, the control electrode of the second transistor, and the control electrode of the sixth transistor.

[0031] In an exemplary embodiment, the plurality of sub-pixels form multiple rows. In the second light-emitting gate driving circuit group, the nth level second light-emitting gate driving circuit is connected to the control electrode of a plurality of first transistors in at least one row of sub-pixels, the (n+x)th level second light-emitting gate driving circuit is connected to the control electrode of a plurality of second transistors in the at least one row of sub-pixels, and the (n+y)th level second light-emitting gate driving circuit is connected to the control electrode of a plurality of sixth transistors in the at least one row of sub-pixels; wherein, n, x, and y are positive integers greater than or equal to 1, and y is greater than or equal to x.

[0032] In an exemplary embodiment, the sixth transistor is a first type of transistor, and the first transistor, the second transistor, and the third transistor are second type of transistors; or, the first transistor and the second transistor are first type of transistors, and the third transistor and the sixth transistor are second type of transistors.

[0033] In an exemplary embodiment, in the (2n-1)th row of sub-pixels and the 2nth row of sub-pixels, the control electrodes of a plurality of first transistors are configured to be connected to the nth level second light-emitting gate driving circuit, the control electrodes of a plurality of second transistors are configured to be connected to the (n+x)th level second gate driving circuit, and the control electrodes of a plurality of sixth transistors are configured to be connected to the (n+y)th level second light-emitting gate driving circuit.

[0034] In an exemplary embodiment, the plurality of gate drive circuit groups include a first reset gate drive circuit group;

[0035] The first reset gate drive circuit group is configured to be electrically connected to the control electrode of the first transistor and the control electrode of the second transistor.

[0036] In an exemplary embodiment, the plurality of sub-pixels form multiple rows. In the first reset gate driving circuit group, the nth level first reset gate driving circuit is connected to the control electrode of a plurality of first transistors in at least one row of sub-pixels, and the n+bth level first reset gate driving circuit is connected to the control electrode of a plurality of second transistors in the at least one row of sub-pixels; wherein, n and b are positive integers greater than or equal to 1.

[0037] In an exemplary embodiment, in the 2nth row of sub-pixels, the control electrodes of a plurality of first transistors are configured to be connected to the 2nth level first reset gate drive circuit, and the control electrodes of a plurality of second transistors are configured to be connected to the 2n+b level first reset gate drive circuit.

[0038] In an exemplary embodiment, the plurality of gate driving circuit groups include a first light-emitting gate driving circuit group, and the plurality of transistors further include a fifth transistor as a light-emitting control transistor, wherein the second terminal of the fifth transistor is connected to the first terminal of the third transistor;

[0039] The first light-emitting gate driving circuit group is configured to be electrically connected to the control electrode of the fifth transistor and the control electrode of the sixth transistor.

[0040] In an exemplary embodiment, the plurality of sub-pixels form multiple rows. In the first light-emitting gate driving circuit group, the nth level first light-emitting gate driving circuit is connected to the control electrode of a plurality of fifth transistors in at least one row of sub-pixels, and the (n+a)th level first light-emitting gate driving circuit is connected to the control electrode of a plurality of sixth transistors in the at least one row of sub-pixels; wherein, n and a are positive integers greater than or equal to 1.

[0041] In an exemplary embodiment, in the (2n-1)th row of sub-pixels and the 2nth row of sub-pixels, the control electrodes of a plurality of fifth transistors are configured to be connected to the nth-level first light-emitting gate driving circuit, and the control electrodes of a plurality of sixth transistors are configured to be connected to the (n+a)th-level first light-emitting gate driving circuit.

[0042] In an exemplary embodiment, the plurality of sub-pixels form multiple rows, and in at least one of the plurality of gate driving circuit groups, the same gate driving circuit is configured to be electrically connected to at least two rows of sub-pixels.

[0043] In an exemplary embodiment, the border region includes a third border region and a fourth border region. In a first direction, the third border region and the fourth border region are located on both sides of the display region. The plurality of gate driving circuit groups are located in the third border region and the fourth border region. The main body portions of the third border region and the fourth border region extend along a second direction. On a plane parallel to the display substrate, the first direction intersects with the second direction.

[0044] In the frame region located on the same side of the display area in the first direction, multiple gate driving circuits are arranged along the extension direction of the frame region in the same gate driving circuit group.

[0045] Thirdly, this disclosure also provides a display device including the display substrate described in any of the above embodiments.

[0046] The display substrate and display device provided in the embodiments of this disclosure include a display substrate in which multiple transistors in the same pixel driving circuit include at least one first type transistor and at least one second type transistor. The first type transistor includes at least one of a top gate and a bottom gate, and the second type transistor includes a top gate and a bottom gate. By setting at least one transistor in the pixel driving circuit as a first type transistor, the bezel size of the display substrate can be reduced and the difficulty of narrowing the bezel can be reduced.

[0047] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0048] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0049] Figure 1 This is a schematic diagram of the structure of a display device;

[0050] Figure 2a This is a schematic diagram of the structure of a display substrate;

[0051] Figure 2b The diagram shown is a schematic diagram of the structure of a display substrate;

[0052] Figure 2cThe diagram shown is an enlarged view of the first border area.

[0053] Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0054] Figure 4a This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0055] Figure 4b This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0056] Figure 4c This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0057] Figure 4d This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0058] Figure 4e This is a timing diagram of a pixel driving circuit.

[0059] Figure 4f This is a schematic diagram of the structure of a display substrate;

[0060] Figure 5a The diagram shown is a structural schematic of a display substrate provided in an embodiment of this disclosure;

[0061] Figure 5b The diagram shown is a schematic diagram of the structure of a display substrate;

[0062] Figure 5c The diagram shown is a schematic diagram of a display substrate structure provided in an exemplary embodiment of this disclosure;

[0063] Figure 5d The diagram shown is a schematic representation of the structure of a display substrate provided in an exemplary embodiment of this disclosure.

[0064] Figure 5e The diagram shown is a schematic representation of the structure of a display substrate provided in an exemplary embodiment of this disclosure.

[0065] Figure 5f The diagram shown is a schematic representation of the structure of a display substrate provided in an exemplary embodiment of this disclosure.

[0066] Figure 5g The diagram shown is a schematic representation of the structure of a display substrate provided in an exemplary embodiment of this disclosure.

[0067] Figure 6a The diagram shown is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0068] Figure 6bThe diagram shown is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0069] Figure 6c The diagram shown is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0070] Figure 6d The diagram shown is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0071] Figure 6e The diagram shown is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0072] Figure 6f The diagram shown is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0073] Figure 6g The diagram shown is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0074] Figure 6h The diagram shown is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0075] Figure 6i The diagram shown is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0076] Figure 6j The diagram shown is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0077] Figure 6k The diagram shown is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0078] Figure 7a The diagram shown is a timing diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0079] Figure 7b The diagram shown is a timing diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0080] Figure 7c The diagram shown is a timing diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0081] Figure 7d The diagram shown is a timing diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0082] Figure 7eThe diagram shown is a timing diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0083] Figure 7f The diagram shown is a timing diagram of a pixel driving circuit provided in an exemplary embodiment of this disclosure.

[0084] Figure 8 The diagram shown is a schematic diagram of a display substrate after a first semiconductor layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0085] Figure 9a The diagram shown is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0086] Figure 9b The diagram shown is a schematic diagram of the first conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0087] Figure 10a The diagram shown is a schematic diagram of a display substrate after the second conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0088] Figure 10b The diagram shown is a schematic diagram of the second conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0089] Figure 11a The diagram shown is a schematic diagram of a display substrate after a second semiconductor layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0090] Figure 11b The diagram shown is a schematic diagram of the second semiconductor layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0091] Figure 12a The diagram shown is a schematic diagram of a display substrate after the formation of the third conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0092] Figure 12b The diagram shown is a schematic diagram of the third conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0093] Figure 13 The diagram shown is a schematic diagram of a display substrate after the fifth insulating layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0094] Figure 14a The diagram shown is a schematic diagram of a display substrate after the fourth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0095] Figure 14b The diagram shown is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0096] Figure 15 The diagram shown is a schematic diagram of the formation of a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0097] Figure 16a The diagram shown is a schematic diagram of a display substrate after the fifth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0098] Figure 16b The diagram shown is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0099] Figure 17 The diagram shown is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0100] Figure 18a The diagram shown is a schematic diagram of a display substrate after the second conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0101] Figure 18b The diagram shown is a schematic diagram of the second conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0102] Figure 19a The diagram shown is a schematic diagram of a display substrate after a second semiconductor layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0103] Figure 19b The diagram shown is a schematic diagram of the second semiconductor layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0104] Figure 20a The diagram shown is a schematic diagram of a display substrate after the formation of the third conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0105] Figure 20b The diagram shown is a schematic diagram of the third conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0106] Figure 21 The diagram shown is a schematic diagram of a display substrate after the fifth insulating layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0107] Figure 22a The diagram shown is a schematic diagram of a display substrate after the fourth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0108] Figure 22b The diagram shown is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0109] Figure 23The diagram shown is a schematic diagram of the formation of a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0110] Figure 24a The diagram shown is a schematic diagram of a display substrate after the fifth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0111] Figure 24b The diagram shown is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0112] Figure 25 The diagram shown is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0113] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0114] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted according to actual conditions. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0115] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0116] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0117] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0118] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0119] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged. In embodiments of this disclosure, the gate electrode can be referred to as the control electrode.

[0120] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0121] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0122] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0123] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0124] In the embodiments of this disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0125] Figure 1The diagram shows a schematic of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is connected to multiple data signal lines (D1 to Dn), the scan signal driving circuit is connected to multiple scan signal lines (G1 to Gm), and the light emission signal driving circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines (which may be referred to as data lines). In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driving circuit to the data signal driving circuit, clock signals, scan start signals, etc. of specifications suitable for the scan signal driving circuit to the scan signal driving circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driving circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driving circuit can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driving circuit can sequentially provide scan signals with conduction level pulses to scan signal lines G1 to Gm. For example, a scan signal driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A light-emitting signal driving circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, a light-emitting signal driving circuit can sequentially provide transmit signals with cutoff level pulses to light-emitting signal lines E1 to Eo. For example, a light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0126] Figure 2aThis is a schematic diagram of a planar structure of a display substrate. Figure 2a As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0127] In an exemplary embodiment, a pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0128] Figure 2b The diagram shown is a structural schematic of a display panel. Figure 2b As shown, the display panel may include a display area AA and a border area BB surrounding the display area AA. In some examples, the border area BB may include: a first border area (bottom border) B1 and a second border area (top border) B2 arranged opposite each other in the second direction Y, and a third border area (left border) B3 and a fourth border area (right border) B4 arranged opposite each other in the first direction X. The first border area B1 is connected to the third border area B3 and the fourth border area B4, and the second border area B2 is connected to the third border area B3 and the fourth border area B4. In some examples, the display area AA may include a first edge (bottom edge) and a second edge (top edge) arranged opposite each other in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) arranged opposite each other in the first direction X. The display area AA may include a plurality of regularly arranged sub-pixels Pxij. The sub-pixels may include pixel driving circuits and light-emitting devices. The first border area B1 may include a bonding circuit that connects signal lines to an external driving device. The third border area B3 and the fourth border area B4 may include gate driving circuits and a second power supply line VSS that transmits voltage signals to the plurality of sub-pixels.

[0129] Figure 2c The diagram shows a planar structural schematic of the first bezel region B1. In a plane parallel to the display substrate, the first bezel region B1 may include a first fan-out area 11, a bending area 12, a second fan-out area 13, and a bonding area 14 arranged sequentially along a direction away from the display area AA. The bonding area 14 may include a driver chip area 141, a third fan-out area 142, and a bonding electrode area 143 arranged sequentially along a direction away from the bending area 12 from the second fan-out area 13. The first fan-out area 11 may include a data fan-out line, a first power line, and a second power line VSS. The data fan-out line is located in the middle of the first fan-out area 11 and includes multiple data connection lines configured to connect to the data signal lines (Data Line) of the display area AA in a fan-out routing manner. The first power line is configured to connect to the high-voltage power line (VDD) of the display area AA. The second power line is a low-voltage power line (VSS) located in the third bezel region B3 and the fourth bezel region B4. The bending area 12 may include a composite insulating layer with grooves, configured to bend the bonding area 14 to the back of the display area AA. The second fan-out area 13 includes multiple data connection lines led out in a fan-out routing manner. The driver chip area 141 may house an integrated circuit (IC) 20, configured to connect to the multiple data connection lines. The bonding electrode area 143 includes multiple bonding pads, configured to bond to the flexible printed circuit (FPC) 30. In an exemplary embodiment, the integrated circuit (IC) 20 may be bonded to the driver chip area 141, and the flexible printed circuit (FPC) 30 may be bonded to the bonding electrode area 142. In an exemplary embodiment, the integrated circuit 20 (which may be referred to as a data driving circuit or driving circuit) may generate driving signals required to drive sub-pixels and may provide the driving signals to the sub-pixel Pxij located in the display area AA. For example, the driving signal may be a data signal controlling the brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode area 143 may be provided with a pad including a plurality of pins, and the flexible circuit board 30 may be bonded to the pad.

[0130] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels in an OLED display substrate. Figure 3As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0131] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 for each sub-pixel may include multiple transistors and storage capacitors constituting the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, an organic light-emitting layer 302, and a cathode 303. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 emits light of a corresponding color under the driving force of the anode 301 and the cathode 303. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first and third encapsulation layers 401 and 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first and third encapsulation layers 401 and 403, ensuring that external moisture cannot enter the light-emitting structure layer 103.

[0132] In an exemplary embodiment, the organic light-emitting layer 302 may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0133] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, 8T1C, or 7T2C structure. Figures 4a to 4d The diagram shows equivalent circuit diagrams for several types of pixel driving circuits. For example... Figures 4a to 4d As shown, the pixel driving circuit may include six transistors (first transistor T1 to sixth transistor T6) and two capacitors C (first capacitor C1 and second capacitor C2). The pixel driving circuit can be connected to ten signal lines (data signal line D, scan signal line Gate, first reset control line Reset1, second reset control line Reset2, first light emission control line EM1, second light emission control line EM2, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD and second power supply line VSS). The following is in conjunction with... Figures 4a to 4d The pixel driving circuit is described below:

[0134] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the control electrode of the third transistor T3, the second electrode of the fourth transistor T4, the first terminal of the first capacitor C1, and the second electrode of the first transistor T1. The second node N2 is connected to the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5. The third node N3 is connected to the second terminal of the first capacitor C1, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The fourth node N4 is connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the anode of the light-emitting device EL.

[0135] In an exemplary embodiment, the first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal of the first capacitor C1 is connected to the third node N3; the first terminal of the second capacitor C2 is connected to the third node N3, and the second terminal of the second capacitor C2 can be connected to a DC signal line, for example, as shown below. Figure 4a As shown, the second terminal of the second capacitor C2 can be connected to the first power supply line VDD, or as... Figure 4b As shown, the second terminal of the second capacitor C2 can be connected to the first initial signal line Vinit1, or as... Figure 4c As shown, the second terminal of the second capacitor C2 can be connected to the second initial signal line Vinit2, or as... Figure 4d As shown, the second terminal of the second capacitor C2 can be connected to the second power supply line VSS. Figures 4a to 4dIn the pixel driving circuit shown, the second terminal of the second capacitor C2 is connected to a DC signal line (for example, to one of the first power line VDD, the second power line VSS, the first initial signal line Vinit1, and the second initial signal line Vinit2), which helps to save space on the display substrate.

[0136] The control electrode of the first transistor T1 is connected to the first reset control line Reset1, the first terminal of the first transistor T1 is connected to the first initial signal line Vinit1, and the second terminal of the first transistor is connected to the first node N1. When a conduction-level reset signal is applied to the first reset control line Reset1, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the charge on the control electrode of the third transistor T3.

[0137] The control electrode of the second transistor T2 is connected to the second reset control line Reset2, the first electrode of the second transistor T2 is connected to the second initial signal line Vinit2, and the second electrode of the second transistor T2 is connected to the first electrode of the light-emitting device (also the fourth node N4). When a conduction-level reset signal is applied to the second reset control line Reset2, the second transistor T2 transmits an initialization voltage to the first electrode of the light-emitting device EL, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device EL.

[0138] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.

[0139] The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor. When a conduction-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0140] The control electrode of the fifth transistor T5 is connected to the first light-emitting control line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the second light-emitting control line M2E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device (also the fourth node N4). The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors (or light-emitting control transistors). When a conduction-level light-emitting signal is applied to the first light-emitting control line EM1 and the second light-emitting control line EM2, the fifth transistor T5 and the sixth transistor T6 conduct, forming a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device to emit light.

[0141] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, where the signal on the second power line VSS is a low-level signal, and the signal on the first power line VDD is a continuously high-level signal. In this exemplary embodiment, the first transistor T1 to the sixth transistor T6 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the sixth transistor T6 may include both P-type and N-type transistors.

[0142] In an exemplary embodiment, the first transistor T1 to the sixth transistor T6 can be a low-temperature polycrystalline silicon thin-film transistor (LTPS), or an oxide thin-film transistor (N-type transistor), or a combination of both. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing complexity of the display panel, and improves product yield. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current, low-frequency driving capability, and low power consumption. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0143] In an exemplary embodiment, the light-emitting device EL can be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0144] In an exemplary embodiment Figure 4a The operating timing of the pixel driving circuit shown can be as follows: Figure 4e As shown, in an exemplary embodiment, with Figure 4a The operation of a pixel driving circuit is illustrated using the example of six N-type transistors in the pixel driving circuit (high-level signal for on, low-level signal for off). Figure 4e As shown, the operation of the pixel driving circuit can include:

[0145] Phase 1, P11, can be called the reset phase. The second reset control line, Reset2, is a high-level signal, while the scan signal line, Gate, and the first light-emitting control line, EM1, are low-level signals. Because Reset2 is high, the second transistor T2 is turned on. The signal from the second initial signal line, Vinit2, is provided to the fourth node, N4, via the second transistor T2, clearing the charge from N4. The potential of N4 is the voltage of the second initial signal, VINIT2. Because the scan signal line, Gate1, and the first light-emitting control line, EM1, are low, the fourth transistor, T4, and the sixth transistor, T6, are turned off. The OLED does not emit light during this phase. Phase 1, P11, can be divided into three sub-phases based on the signal changes of the first reset control line, Reset1, and the second light-emitting control line, EM2 (sub-phase 1, P01, sub-phase 2, and sub-phase 3).

[0146] The first sub-stage P01 can be called the first reset sub-stage. The first reset control line Reset1 is a low-level signal, and the second light-emitting control line EM2 is a high-level signal. Since the second light-emitting control line EM2 is a high-level signal, the sixth transistor T6 is turned on. The signal of the fourth node N4 is written to the third node N3 through the sixth transistor T6. The potential of the third node N3 is the voltage VINIT2 of the second initial signal. The potential of the third node N3 is coupled to the first node N1, and the signal of the first node N1 changes from high level to low level. The third transistor T3 is turned off. Since the first reset control line Reset1 is a low-level signal, the first transistor T1 is turned off.

[0147] The second sub-stage P02 can be called the second reset sub-stage. The first reset control line Reset1 and the second light emission control line EM2 are high-level signals. Since the first reset control line Reset1 is high-level, the first transistor T1 is turned on, and the signal of the first initial signal line Vinit1 is provided to the first node N1 to initialize the first capacitor C1 and the control electrode of the third transistor T3, clearing the charge of the first node N1. The potential of the first node N1 is the voltage VINIT1 of the first initial signal, and the third transistor T3 is turned on. Since the second light emission control line EM2 is high-level, the sixth transistor T6 is turned on, and the signal of the fourth node N4 is continuously written to the third node N3 through the sixth transistor T6. The potential of the third node N3 is the voltage VINIT2 of the second initial signal.

[0148] The third sub-stage P03 can be called the third reset sub-stage. The first reset control line Reset1 is a high-level signal, and the second light-emitting control line EM2 is a low-level signal. Since the first reset control line Reset1 is a high-level signal, the first transistor T1 is continuously turned on, and the signal of the first initial signal line Vinit1 is continuously provided to the first node N1 to initialize the first capacitor C1 and the control electrode of the third transistor T3, clearing the charge of the first node N1. The potential of the first node N1 is the voltage of the first initial signal VINIT1, and the third transistor T3 is turned on. Since the second light-emitting control line EM2 is a low-level signal, the sixth transistor T6 is turned off, and the signals of the third node N3 and the fourth node N4 remain unchanged.

[0149] The second stage, P12, can be called the threshold compensation stage. The scanning signal line Gate and the second light emission control line EM2 are low-level signals, while the first reset control line Reset1, the second reset control line Reset2, and the first light emission control line EM1 are high-level signals. Since the first reset control line Reset1, the second reset control line Reset2, and the first light emission control line EM1 are high-level signals, the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on. Because the first transistor T1 is turned on, the signal of the first initial signal line Vinit1 is provided to the first node N1 to initialize the first capacitor C1 and the control electrode of the third transistor T3. The potential of the first node N1 is the voltage VINIT1 of the first initial signal, and the third transistor T3 is turned on. Because the second transistor T2 is turned on, the signal of the second initial signal line Vinit2 is used to initialize the fourth node N4, and the potential of the fourth node N4 is VINIT2. Because the fifth transistor T5 is turned on, the voltage of the first power line VDD is written to the third node N3 through the fifth transistor T5, the second node N2, and the third transistor T3 until the voltage of the third node N3 satisfies VINIT2-Vth, where Vth is the threshold voltage of the third transistor T3. The potential of the second node N2 is the voltage of the first power line VDD. Since the scan signal line Gate and the second light emission control line EM2 are low-level signals, the fourth transistor T4 and the sixth transistor T6 are disconnected, and the potential of the fourth node N4 maintains the voltage VINIT2 of the second initial signal.

[0150] The third stage, P13, can be called the data writing stage. The first reset control line Reset1, the first light emission control line EM1, and the second light emission control line EM2 are low-level signals, while the scan signal line Gate and the second reset control line Reset2 are high-level signals. Since the first reset control line Reset1, the first light emission control line EM1, and the second light emission control line EM2 are low-level signals, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are disconnected, and the fourth node N4 maintains the voltage VINIT2 of the second initial signal. Since the scan signal line Gate and the second reset control line Reset2 are high-level signals, the second transistor T2 and the fourth transistor T4 are turned on. Since the second transistor T2 is turned on, the second initial signal line Vinit2 is written to the fourth node N4 via the second transistor T2, and the potential of the fourth node N4 is the voltage VINIT2 of the second initial signal. Since the fourth transistor T4 is turned on, the data voltage output by the data signal line D is written to the first node N1 via the fourth transistor T4, and the potential of the first node N1 becomes VData, which is the data voltage output by the data signal line D. The third transistor T3 is turned on. Since the sixth transistor T6 is turned off, the potential of the fourth node N4 cannot be written to the third node N3, and the voltage of the first node N1 is coupled to the third node N3, causing the third node N3 to rise.

[0151] The fourth stage, P14, can be called the light-emitting stage. The first light-emitting control line EM1 and the second light-emitting control line EM2 are high-level signals, while the first reset control line Reset1, the scan signal line Gate, and the second reset control line Reset2 are low-level signals. Because the first reset control line Reset1, the scan signal line Gate, and the second reset control line Reset2 are low-level signals, the first transistor T1, the second transistor T2, and the fourth transistor T4 are disconnected. The voltage across the first capacitor C1 will not change abruptly, and the first node N1 basically maintains the potential of the previous stage. The third transistor T3 is turned on. Because the first light-emitting control line EM1 and the second light-emitting control line EM2 are high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting device EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0152] exist Figure 4e shown Figure 4a In the timing diagram of the pixel driving circuit, threshold compensation is performed in the second stage P12 to the third stage P13. The threshold compensation time is relatively long, which can reduce the technical problem of insufficient threshold voltage compensation to a certain extent.

[0153] Figures 4a to 4d The pixel driving circuit shown is an all-oxide pixel driving circuit, meaning all transistors in the pixel driving circuit are NMOS. The active layer of NMOS is basically oxide such as IGZO or IGO, and it is mostly a top-bottom dual-gate design. This increases the capacitance between the gate and the source and drain, resulting in a large load (e.g., resistance or capacitance) on the gate driving signal line (which can be called the GOA driving signal line or gate control signal line). This causes technical problems such as poor crosstalk and high power consumption. In addition, due to the low mobility of oxide materials, the transistors need to be wider to ensure charging or high brightness. Under the same conditions, oxide transistors (NMOS transistors) require more space than PMOS transistors. At the same time, due to the oxide dual-gate design, the layout space requirement is further increased, making it difficult to improve pixel density (Pixels Per Inch, abbreviated as PPI). The corresponding gate driving circuit (GOA circuit) of oxide pixel circuit is also mostly oxide, so it also requires a larger bezel size. It can be seen that all-oxide pixel driving circuits have technical problems such as difficulty in improving PPI and narrowing bezels, high power consumption, and crosstalk.

[0154] A display substrate typically includes a display area and a bezel area surrounding the display area. Gate drive circuits are usually located on the left and right bezels of the display area. Figures 4a to 4d The all-oxide pixel driving circuit shown typically requires five sets of gate driving circuits (i.e., GOA circuits), meaning that five sets of GOA circuits need to be set on each of the left and right edges of the display substrate. Figures 4a to 4d The gate driving circuit corresponding to the pixel driving circuit shown can be as follows: Figure 4f As shown, Figure 4fThe diagram shows the connection relationship between the gate driving circuit located on the left frame and the sub-pixels located in the display area. Five groups of gate driving circuits are set in the left frame area, including a scanning gate driving circuit group (Gate GOA), a first reset gate driving circuit group (Reset1 GOA), a second reset gate driving circuit group (Reset2 GOA), a first light-emitting gate driving circuit group (EM1 GOA), and a second light-emitting gate driving circuit group (EM2 GOA). Multiple gate driving circuits in the same group can be arranged sequentially along the extension direction of the frame, and multiple gate driving circuits in the same group can be cascaded. For example, the input terminal of the first-stage scanning gate driving circuit (Gate GOA(1)) is connected to the scanning initial signal line (GSTV), and the output terminal of the first-stage scanning gate driving circuit (Gate GOA(1)) is connected to the input terminal of the second-stage scanning gate driving circuit (Gate GOA(2)). The output terminal of GOA(2) is connected to the input terminal of the third-stage scanning gate drive circuit GateGOA(3), and so on; the input terminal of the first-stage first reset gate drive circuit Reset1GOA(1) can be connected to the first reset initial signal line RSTV1, the input terminal of the first-stage second reset gate drive circuit Reset2 GOA(1) can be connected to the second reset initial signal line RSTV2, the input terminal of the first-stage first light-emitting gate drive circuit EM1 GOA(1) can be connected to the first light-emitting initial signal line ESTV1, and the input terminal of the first-stage second light-emitting gate drive circuit EM2 GOA(1) can be connected to the second light-emitting initial signal line ESTV2.In this circuit, the nth-level scanning gate drive circuit Gate GOA(n) is connected to the control electrode of the fourth transistor T4 in the nth row sub-image P(n); the nth-level first reset gate drive circuit Reset1 GOA(n) is connected to the control electrode of the first transistor T1 in the nth row sub-image P(n); the nth-level second reset gate drive circuit Reset2 GOA(n) is connected to the control electrode of the second transistor T2 in the nth row sub-image P(n); the nth-level first light-emitting gate drive circuit EM1 GOA(n) is connected to the control electrode of the fifth transistor T5 in the nth row sub-image P(2n) and the (2n-1)th row sub-image P(2n-1); and the nth-level second light-emitting gate drive circuit EM2 GOA(n) is connected to the control electrode of the sixth transistor T6 in the nth row sub-image P(2n) and the (2n-1)th row sub-image P(2n-1). For example, the first-level scanning gate drive circuit Gate... The output terminal of GOA(1) is connected to the control terminal of the fourth transistor T4 in the first row sub-pixel P(1). The output terminal of the first-stage first reset gate drive circuit Reset1 GOA(1) is connected to the control terminal of the first transistor T1 in the first row sub-pixel P(1). The output terminal of the first-stage second reset gate drive circuit Reset2 GOA(1) is connected to the second terminal of the second transistor T2 in the first row sub-pixel P(1). The output terminal of the first-stage first light-emitting gate drive circuit EM1 GOA(1) is connected to the control terminal of the fifth transistor T5 in the first row sub-pixel P(1) and the second row sub-pixel P(2). The output terminal of the first-stage second light-emitting gate drive circuit EM2 GOA(1) is connected to the control terminal of the sixth transistor T6 in the first row sub-pixel P(1) and the second row sub-pixel P(2). And so on. The output terminal of the second-stage scan gate drive circuit Gate GOA(2) is connected to the control terminal of the fourth transistor T4 in the second row sub-pixel P(2). The second-stage first reset gate drive circuit Reset1 The output terminal of GOA(2) is connected to the control electrode of the first transistor T1 in the second row sub-pixel P(2). The output terminal of the second-stage second reset gate drive circuit Reset2 GOA(2) is connected to the second electrode of the second transistor T2 in the second row sub-pixel P(2). The output terminal of the second-stage first light-emitting gate drive circuit EM1 GOA(2) is connected to the control electrode of the fifth transistor T5 in the third row sub-pixel P(3) and the fourth row sub-pixel P(4). The output terminal of the second-stage second light-emitting gate drive circuit EM2 GOA(2) is connected to the control electrode of the sixth transistor T6 in the third row sub-pixel P(3) and the fourth row sub-pixel P(4).

[0155] exist Figure 4fIn the structure shown, the first light-emitting gate driving circuit EM1 GOA and the second light-emitting gate driving circuit EM2 GOA are a one-to-two architecture, that is, one level of gate driving circuit can drive two rows of sub-pixels, which can reduce the number of gate driving circuits and is beneficial to narrowing the bezel; the scanning gate driving circuit group Gate GOA, the first reset gate driving circuit group Reset1 GOA, and the second reset gate driving circuit group Reset2 GOA are a one-to-one architecture, that is, one level of gate driving circuit can drive one row of sub-pixels.

[0156] In such Figures 4a to 4d In the all-oxide pixel driving circuit shown, it is usually necessary to set such a pixel in the border area. Figure 4f The five gate drive circuits shown (i.e. GOA circuits) result in a large bezel size and make it difficult to narrow the bezel.

[0157] An exemplary embodiment of this disclosure provides a display substrate, which may include: a substrate and a plurality of sub-pixels disposed on one side of the substrate, at least one sub-pixel including a pixel driving circuit, at least one pixel driving circuit including a plurality of transistors, the transistors including an active layer and at least one gate; in the same transistor, the at least one gate at least partially overlaps with the active layer, the at least one gate including at least one of a top gate and a bottom gate; in a direction perpendicular to the plane of the substrate, the bottom gate is located on the side of the active layer closer to the substrate, and the top gate is located on the side of the active layer away from the substrate;

[0158] In the same pixel driving circuit, the plurality of transistors include at least one first type transistor and at least one second type transistor, wherein the first type transistor includes at least one of a top gate and a bottom gate, and the second type transistor includes a top gate and a bottom gate.

[0159] The display substrate provided in this embodiment includes at least one first-type transistor and at least one second-type transistor in the same pixel driving circuit. The first-type transistor includes at least one of a top gate and a bottom gate, and the second-type transistor includes both a top gate and a bottom gate. By setting at least one transistor in the pixel driving circuit as a first-type transistor, on the one hand, the first-type transistor can be configured as a single-gate structure, which can reduce the space occupied by the pixel driving circuit and reduce the coupling capacitance generated by the dual-gate junction, thereby improving the PPI of the display substrate and reducing power consumption and load. On the other hand, the gate driving circuit corresponding to the first-type transistor in the pixel driving circuit usually adopts the first-type transistor. The space occupied by the first-type transistor in the bezel area is smaller than that occupied by the second-type transistor, which can reduce the bezel size of the display substrate and reduce the difficulty of narrowing the bezel.

[0160] like Figure 5a , Figures 6a to 6hThe diagram shown is a schematic diagram of a planar structure of a display substrate provided in an embodiment of this disclosure. The display substrate provided in this embodiment may include: a substrate and a plurality of sub-pixels Pxij disposed on one side of the substrate. At least one sub-pixel Pxij may include a pixel driving circuit pdc. At least one pixel driving circuit pdc may include a plurality of transistors. The transistors may include an active layer and at least one gate. In the same transistor, at least one gate at least partially overlaps with the active layer. At least one gate includes at least one of a top gate and a bottom gate. In a direction perpendicular to the plane of the substrate, the bottom gate may be located on the side of the active layer closer to the substrate, and the top gate may be located on the side of the active layer away from the substrate.

[0161] In the same pixel driving circuit (PDC), multiple transistors may include at least one first-type transistor and at least one second-type transistor. The first-type transistor may include at least one of a top gate and a bottom gate, and the second-type transistor may include a top gate and a bottom gate.

[0162] In an exemplary embodiment, the full English name of the pixel driving circuit is pixel driving circuit (abbreviated as pdc).

[0163] In an exemplary implementation, such as Figure 5a , Figures 6a to 6h As shown, the multiple transistors may include a third transistor T3 as a driving transistor, a fifth transistor T5 as a light-emitting control transistor, and a sixth transistor T6 as a light-emitting control transistor. The first terminal of the third transistor T3 is connected to the second terminal of the fifth transistor T5, and the second terminal of the third transistor T3 is connected to the first terminal of the sixth transistor T6. The second type of transistor may include the third transistor T3.

[0164] In an exemplary implementation, such as Figure 5a , Figures 6a to 6h As shown, the plurality of transistors may further include a first transistor T1 as a reset transistor, a second transistor T2 as a reset transistor, and a fourth transistor T4 as a data write transistor. One or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are first type transistors.

[0165] The second terminals of the first transistor T1 and the fourth transistor T4 are connected to the control terminal of the third transistor T3, and the second terminal of the second transistor T2 is connected to the second terminal of the sixth transistor T6.

[0166] In an exemplary implementation, such as Figures 6a to 6fAs shown, the display substrate may also include multiple gate control signal lines. These multiple gate control signal lines may include a first reset control line Reset1, a second reset control line Reset2, a scan signal line Gate, a first light emission control line EM1, and a second light emission control line EM2. The control electrode of the first transistor T1 may be connected to the first reset control line Reset1, the control electrode of the second transistor T2 may be connected to the second reset control line Reset2, the control electrode of the fourth transistor T4 may be connected to the scan signal line Gate, the first light emission control line EM1 may be connected to the control electrode of the fifth transistor T5, and the second light emission control line EM2 may be connected to the control electrode of the sixth transistor T6.

[0167] In an exemplary implementation, such as Figures 6a to 6c , Figure 6g As shown, the first type of transistor may include at least one of the fifth transistor T5 and the sixth transistor T6, that is, at least one transistor (i.e., the light-emitting control transistor) on the light-emitting path is set as the first type of transistor.

[0168] In an exemplary embodiment, the first type of transistor can be a P-type transistor (PMOS), and the second type of transistor can be an N-type transistor (NMOS).

[0169] In an exemplary implementation, such as Figure 5a and Figure 6a As shown, the first type of transistor may include the fifth transistor T5, and the second type of transistor may include the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6; Figure 5a and Figure 6a and Figure 4a The difference lies in the fact that the fifth transistor T5 is set as a first-class transistor. The fifth transistor T5 can be set as a single-gate structure. On the one hand, it can reduce the parasitic capacitance of the fifth transistor T5 and reduce the load of the first light-emitting control line EM1, thereby improving the brightness uniformity. On the other hand, it can reduce the space occupied by the fifth transistor T5 and increase the PPI of the display substrate.

[0170] like Figure 6b and Figure 6g As shown, the first type of transistor may include the sixth transistor T6, and the second type of transistor may include the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5; Figure 6b and Figure 4aThe difference lies in the fact that the sixth transistor T6 is set as a first-class transistor. The sixth transistor T6 can be set as a single-gate structure. On the one hand, it can reduce the parasitic capacitance of the sixth transistor T6 and reduce the load of the second light-emitting control line EM2, thereby improving the brightness uniformity. On the other hand, it can reduce the space occupied by the sixth transistor T6 and increase the PPI of the display substrate.

[0171] like Figure 6c As shown, the first type of transistor may include the sixth transistor T6 and the fifth transistor T5, and the second type of transistor may include the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4; Figure 6c and Figure 4a The difference lies in the fact that the fifth transistor T5 and the sixth transistor T6 are set as first-class transistors. The fifth transistor T5 and the sixth transistor T6 can be set as a single-gate structure. On the one hand, this can reduce the parasitic capacitance of the fifth transistor T5 and the sixth transistor T6 and reduce the load of the first light-emitting control line EM1 and the second light-emitting control line EM2, thereby improving the brightness uniformity. On the other hand, it can reduce the space occupied by the fifth transistor T5 and the sixth transistor T6 and increase the PPI of the display substrate.

[0172] like Figure 6d As shown, the first type of transistor may include the second transistor T2, and the second type of transistor may include the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6; Figure 6d and Figure 4a The difference is that the second transistor T2 is set as a first type of transistor. The second transistor T2 can be set as a single gate structure. Firstly, it can reduce the parasitic capacitance of the second transistor T2 and reduce the load of the second reset control line Reset2, thereby improving the brightness uniformity. Secondly, it can reduce the space occupied by the second transistor T2 and increase the PPI of the display substrate. Thirdly, it can increase the charging rate of the fourth node N4.

[0173] like Figure 6e As shown, the first type of transistor may include the fourth transistor T4, and the second type of transistor may include the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6; Figure 6e and Figure 4a The difference lies in the fact that the fourth transistor T4 is set as a first-class transistor. The fourth transistor T4 can be set as a single-gate structure. Firstly, it can reduce the parasitic capacitance of the fourth transistor T4 and reduce the load on the scan signal line Gate, thereby improving the brightness uniformity. Secondly, it can reduce the space occupied by the fourth transistor T4 and increase the PPI of the display substrate. Thirdly, it can improve the writing efficiency of the data signal.

[0174] like Figure 6f As shown, the first type of transistor may include a first transistor T1, and the second type of transistor may include a second transistor T2, a third transistor T3, a fourth transistor T5, a fifth transistor T5, and a sixth transistor T6; Figure 6f and Figure 4a The difference is that the first transistor T1 is set as a first type of transistor. The first transistor T1 can be set as a single gate structure. Firstly, it can reduce the parasitic capacitance of the first transistor T1 and reduce the load of the first reset control line Reset1, thereby improving the brightness uniformity. Secondly, it can reduce the space occupied by the first transistor T1 and increase the PPI of the display substrate. Thirdly, it can increase the charging rate of the first node N1.

[0175] like Figure 6h As shown, the first type of transistor may include a first transistor T1 and a second transistor T2, and the second type of transistor may include a third transistor T3, a fourth transistor T5, a fifth transistor T5 and a sixth transistor T6; Figure 6e and Figure 4a The difference lies in the following: the first transistor T1 and the second transistor T2 are set as first-type transistors, and the first transistor T1 and the second transistor T2 can be set as single-gate structures. Firstly, the parasitic capacitance of the first transistor T1 and the second transistor T2 can be reduced, and the load of the first reset control line Reset1 and the second reset control line Reset2 can be reduced, thereby improving brightness uniformity. Secondly, the space occupied by the first transistor T1 and the second transistor T2 can be reduced, thereby increasing the PPI of the display substrate. Thirdly, the charging rate of the first node N1 and the fourth node N4 can be increased.

[0176] In an exemplary implementation, such as Figure 5a and Figure 6a As shown, Figure 5a As shown Figure 6a The schematic diagram of the planar structure of the pixel driving circuit shown is shown. The pixel driving circuit PDC may also include at least one capacitor, which may include a first plate and a second plate.

[0177] In a direction perpendicular to the plane of the substrate, the display substrate may include: an active layer of a first type of transistor located on one side of the substrate, a top gate of a first type of transistor located on the side of the active layer of the first type of transistor away from the substrate, a bottom gate of a second type of transistor located on the side of the top gate of the first type of transistor away from the substrate, an active layer of a second type of transistor located on the side of the bottom gate of the second type of transistor away from the substrate, a top gate of a second type of transistor located on the side of the active layer of the second type of transistor away from the substrate, and a first electrode and a second electrode of a plurality of transistors located on the side of the top gate of the second type of transistor away from the substrate.

[0178] The first plate of the capacitor is disposed on the same layer as the top gate of the first type of transistor, and the second plate of the capacitor is disposed on the same layer as the bottom gate of the second type of transistor.

[0179] In an exemplary implementation, such as Figure 5a and Figure 6a As shown, at least one capacitor may include a first capacitor C1 and a second capacitor C2. The second type of transistor may include a first transistor T1 as a reset transistor, a second transistor T2 as a reset transistor, and a fourth transistor T4 as a data write transistor. The second terminal of the first transistor T1 (the first connecting electrode L1 can be used as the second terminal of the first transistor T1) is connected to the first plate C11 of the first capacitor C1. The second terminal of the second transistor T2 is connected to the second terminal of the sixth transistor T6 (the second connecting electrode L2 can be used as the second terminal of both the second transistor T2 and the sixth transistor T6). The fourth transistor T4... The second electrode (the fifth connecting electrode L5 can be used as the second electrode of the fourth transistor T4) is connected to the first plate C11 of the first capacitor C1 and the top gate T3gt of the third transistor T3. The second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 (the third connecting electrode L3 can be used as the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6) are connected to the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2. The first electrode of the fifth transistor T5 (the sixth connecting electrode L6 can be used as the first electrode of the fifth transistor T5) can be connected to the first plate C21 of the second capacitor C2.

[0180] In the same sub-pixel Pxij, the orthographic projection of the second capacitor C2 on the substrate at least partially overlaps with the orthographic projection of the third transistor T3 on the substrate. In the second direction Y, the first transistor T1 and the fourth transistor T4 can be located on opposite sides of the third transistor T3, the fifth transistor T5 can be located on the side of the fourth transistor T4 away from the third transistor T3, the sixth transistor T6 can be located on the side of the first transistor T1 away from the third transistor T3, the second transistor T2 can be located on the side of the sixth transistor T6 away from the third transistor T3, and at least a portion of the structure of the first capacitor C1 can be located between the third transistor T3 and the sixth transistor T6. In the first direction X, at least a portion of the structure of the first capacitor C1, the first transistor T1, and the fourth transistor T4 can be located on the same side of the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6. In a plane parallel to the substrate, the first direction X intersects the second direction Y.

[0181] In an exemplary implementation, such as Figure 5aAs shown, the display substrate may further include a first reset control line Reset1, a second reset control line Reset2, and a scan signal line Gate; the first reset control line Reset1, the second reset control line Reset2, and the scan signal line Gate may be disposed on the same layer as the first and second electrodes of multiple transistors;

[0182] The first reset control line Reset1 can be connected to the top gate T1gt and bottom gate T1gb of the first transistor T1, the second reset control line Reset2 can be connected to the top gate T2gt and bottom gate T2gb of the second transistor T2, and the scan signal line Gate can be connected to the top gate T4gt and bottom gate T4gb of the fourth transistor T4. In the same sub-pixel Pxij, in the second direction Y, the first reset control line Reset1 can be located between the third transistor T3 and the sixth transistor T6, the second reset control line Reset2 can be located on the side of the sixth transistor T6 away from the third transistor T3, and the scan signal line Gate can be located between the third transistor T3 and the fifth transistor T5.

[0183] In an exemplary implementation, such as Figure 5a As shown, the display substrate may further include a first light-emitting control line EM1 and a second light-emitting control line EM2. The first type of transistor may include a fifth transistor T5, and the second type of transistor may further include a sixth transistor T6. The area where the active layer of the first light-emitting control line EM1 overlaps with that of the fifth transistor T5 may serve as the top gate of the fifth transistor T5, and the area where the active layer of the second light-emitting control line EM2 overlaps with that of the sixth transistor T6 may serve as the top gate of the sixth transistor T6.

[0184] The first light-emitting control line EM1 can be set on the same layer as the top gate of the first type of transistor, and the second light-emitting control line EM2 can be set on the same layer as the top gate of the second type of transistor. In the same sub-pixel Pxij, in the second direction Y, the first light-emitting control line EM1 and the fifth transistor T5 can be located on the same side of the third transistor T3, and the second light-emitting control line EM2 and the sixth transistor T6 can be located on the same side of the third transistor T3.

[0185] In an exemplary implementation, such as Figure 5a As shown, the display substrate also includes a first shielding line BL1, which is disposed on the same layer as the bottom gate of the second type of transistor. The orthographic projection of the first shielding line BL1 on the substrate and the orthographic projection of the second light-emitting control line EM2 on the substrate at least partially overlap.

[0186] The area where the first blocking line BL1 overlaps with the active layer of the sixth transistor T6 serves as the bottom gate of the sixth transistor T6.

[0187] In an exemplary embodiment, the first is as follows Figure 5aAs shown, the orthographic projection of the second light-emitting control line EM2 on the substrate can be located within the range of the orthographic projection of the first occlusion line BL1 on the substrate.

[0188] In an exemplary embodiment, Figure 5a In the structure shown, the first light-emitting control line EM1 serves as the control electrode of the fifth transistor T5. The top and bottom gates of the first transistor T1, the second transistor T2, and the sixth transistor T6 in the second type of transistor can serve as the control electrodes of the corresponding second type of transistor. The top gate T3gt of the third transistor T3 in the second type of transistor can serve as the control electrode of the third transistor T3.

[0189] In an exemplary implementation, such as Figure 2b and Figure 4f As shown, the substrate may include a display area AA and a border area BB surrounding the display area AA. Multiple sub-pixels Pxij may be located within the display area AA. The border area BB, located on at least one side of the display area AA, may have multiple gate driving circuit groups. Multiple gate driving circuits within the same gate driving circuit group may be cascaded. Figure 4f As shown, the multiple gate driving circuit groups may include a first light-emitting gate driving circuit group EM1 GOA and a second light-emitting gate driving circuit group EM2 GOA.

[0190] Multiple sub-pixels Pxij can form multiple rows. In at least one first light-emitting gate driving circuit in the first light-emitting gate driving circuit group EM1 GOA, the same first light-emitting gate driving circuit is configured to be connected to the control electrode of the fifth transistor T5 in at least two rows of sub-pixels Pxij. In at least one second light-emitting gate driving circuit in the second light-emitting gate driving circuit group EM2 GOA, the same second light-emitting gate driving circuit is configured to be connected to the control electrode of the sixth transistor T6 in at least two rows of sub-pixels Pxij.

[0191] In an exemplary implementation, such as Figure 4f As shown, the first light-emitting gate driving circuit EM1 GOA(n) of the nth stage is configured to be connected to the control electrode of the fifth transistor T5 in the (2n-1)th row and the 2nth row sub-pixel Pxij; the second light-emitting gate driving circuit EM2 GOA(n) of the nth stage is configured to be connected to the control electrode of the sixth transistor T6 in the (2n-1)th row sub-pixel P(2n) and the 2nth row sub-pixel P(2n); where n is a positive integer greater than or equal to 1.

[0192] In an exemplary embodiment, multiple gate drive circuit groups can be configured in Figure 2bThe third border region B3 and the fourth border region B4 are defined in the image. The same first light-emitting gate driving circuit is configured to be connected to the control electrode of the fifth transistor T5 in at least two rows of sub-pixels Pxij; in at least one second light-emitting gate driving circuit in the second light-emitting gate driving circuit group EM2 GOA, the same second light-emitting gate driving circuit is configured to be connected to the control electrode of the sixth transistor T6 in at least two rows of sub-pixels Pxij. This reduces the number of gate driving circuits, decreases the size of the third border region B3 and the fourth border region B4, and facilitates border narrowing.

[0193] In an exemplary embodiment, the first light-emitting gate driving circuit EM1 GOA can be connected to the control electrode of the corresponding fifth transistor T5 through the first light-emitting control line, and the second light-emitting gate driving circuit EM2 GOA can be connected to the control electrode of the sixth transistor T6 through the second light-emitting control line EM2. The gate driving circuit can include multiple transistors. The multiple transistors in the first light-emitting gate driving circuit EM1 GOA and the second light-emitting gate driving circuit EM2 GOA can be first-type transistors. The first-type transistors can be configured as a single-gate structure, which can reduce the parasitic capacitance between the first power line VDD and the first light-emitting control line EM1 and the second light-emitting control line EM2, thereby improving display uniformity and reducing horizontal lines caused by signal crosstalk.

[0194] In an exemplary embodiment Figures 6a to 6f The connection relationship between the gate driving circuit corresponding to the pixel driving circuit and the sub-pixel can be shown in 4f.

[0195] In an exemplary embodiment Figure 4a The planar structure of the pixel driving circuit shown can be as follows: Figure 5b As shown, Figure 5b and Figure 5a The main difference between the structures shown is: Figure 5b The fifth transistor T5 is an N-type transistor, and a second blocking line BL2 needs to be set as the bottom gate of the fifth transistor T5; Figure 5a The fifth transistor T5 is a P-type transistor, so there is no need to set a second blocking line BL2 as the bottom gate of the fifth transistor T5.

[0196] This disclosure also provides a display substrate, such as... Figure 2b and Figure 5c , Figure 5d , Figures 6g to 6kAs shown, the display substrate may include: a display area AA and a border area BB located around the display area AA. The display area AA is provided with a plurality of sub-pixels Pxij. At least one sub-pixel Pxij includes a pixel driving circuit. At least one pixel driving circuit includes a plurality of transistors. The border area BB located on at least one side of the display area AA is provided with a plurality of gate driving circuit groups. The plurality of gate driving circuits in the same gate driving circuit group are cascaded.

[0197] In at least one of the multiple gate drive circuit groups, the same gate drive circuit group is configured to be electrically connected to at least two transistors in the same pixel drive circuit.

[0198] The display substrate provided in this embodiment of the present disclosure is configured such that the same gate driving circuit group is electrically connected to at least two transistors in the same pixel driving circuit, which can reduce the number of gate driving circuit groups, reduce the bezel size of the gate driving circuit group to a certain extent, and reduce the difficulty of narrowing the bezel.

[0199] In an exemplary implementation, such as Figures 6g to 6k As shown, the multiple transistors may include a third transistor T3 as a driving transistor, a first transistor T1 as a reset transistor, a second transistor T2 as a reset transistor, and a sixth transistor T6 as a light-emitting control transistor; the second terminal of the first transistor T1 is connected to the control terminal of the third transistor T3, the second terminal of the second transistor T2 is connected to the second terminal of the sixth transistor T6, and the first terminal of the sixth transistor T6 is connected to the second terminal of the third transistor T3.

[0200] like Figures 6g to 6i , Figure 6k As shown, the control electrode of the first transistor T1 and the control electrode of the second transistor T2 can be electrically connected to the same gate drive circuit group.

[0201] In an exemplary implementation, such as Figure 5c , Figure 6g and Figure 6h As shown, the multiple gate driving circuit groups may include a second light-emitting gate driving circuit group EM2 GOA, which is configured to be electrically connected to the control electrode of the first transistor T1, the control electrode of the second transistor T2, and the control electrode of the sixth transistor T6.

[0202] In an exemplary implementation, such as Figure 5c Figure 5d , Figure 6g and Figure 6hAs shown, multiple sub-pixels Pxij can form multiple rows. In the second light-emitting gate driving circuit group EM2 GOA, the nth level second light-emitting gate driving circuit EM2 GOA(n) can be connected to the control electrode of multiple first transistors T1 in at least one row of sub-pixels Pxij, the (n+x)th level second light-emitting gate driving circuit EM2 GOA(n+x) can be connected to the control electrode of multiple second transistors T2 in the at least one row of sub-pixels Pxij, and the (n+y)th level second light-emitting gate driving circuit EM2 GOA(n+y) can be connected to the control electrode of multiple sixth transistors T6 in the at least one row of sub-pixels Pxij; where n, x, and y are positive integers greater than or equal to 1, and y is greater than or equal to x.

[0203] In an exemplary implementation, such as Figure 6g As shown, the sixth transistor T6 is a first-class transistor, and the first transistor T1, the second transistor T2, and the third transistor T3 are second-class transistors; or, as... Figure 6h As shown, the first transistor T1 and the second transistor T2 are first-type transistors, and the third transistor T3 and the sixth transistor T6 are second-type transistors.

[0204] In an exemplary implementation, such as Figure 5c , Figure 6g and Figure 6h As shown, in the (2n-1)th row sub-pixel P(2n) and the 2nth row sub-pixel P(2n), the control electrodes of multiple first transistors T1 are configured to be connected to the nth level second light-emitting gate driving circuit EM2 GOA(n), the control electrodes of multiple second transistors T2 are configured to be connected to the (n+x)th level second light-emitting gate driving circuit EM2GOA(n+x), and the control electrodes of multiple sixth transistors T6 are configured to be connected to the (n+y)th level second light-emitting gate driving circuit EM2GOA(n+y).

[0205] In an exemplary embodiment Figure 5c , Figure 5d As shown Figure 6g and Figure 6h The structure diagram is shown with x = 2 and y = 3 as an example. Figure 5c In the structure shown, the first-level second light-emitting gate driving circuit can be connected to the eight rows of sub-pixels, which can make full use of the second light-emitting gate driving circuit, reduce the number of second light-emitting gate driving circuits, and minimize the size of the bezel.

[0206] In an exemplary embodiment, Figure 5dIn the structure shown, in the nth row sub-pixel P(n), the control electrodes of multiple first transistors T1 are connected to the nth-level second light-emitting gate driving circuit EM2 GOA(n), the control electrodes of multiple second transistors T2 are connected to the (n+x)th-level second light-emitting gate driving circuit EM2 GOA(n+x), and the control electrodes of multiple sixth transistors T6 are connected to the (n+y)th-level second light-emitting gate driving circuit EM2 GOA(n+y). The first-level second light-emitting gate driving circuit can be connected to three rows of sub-pixels, which can fully utilize the second light-emitting gate driving circuit, reduce the number of second light-emitting gate driving circuits, and minimize the border size.

[0207] In an exemplary embodiment Figure 5c and Figure 5d The difference is that, Figure 5c The second light-emitting gate driving circuit EM2 GOA(n) of the nth stage can be connected to the control electrode of the first transistor T1 in the sub-pixel P(2n-1) of the 2n-1th row and the sub-pixel P(2n) of the 2nth row; Figure 5d The second light-emitting gate driving circuit EM2 GOA(n) of the nth level can be connected to the control electrode of the first transistor T1 in the nth row sub-pixel P(n).

[0208] In an exemplary implementation, such as Figure 6i and Figure 5e As shown, the multiple gate drive circuit groups may include a first reset gate drive circuit group Reset1 GOA;

[0209] The first reset gate drive circuit group Reset1 GOA is configured to be electrically connected to the control electrode of the first transistor T1 and the control electrode of the second transistor T2.

[0210] In an exemplary implementation, such as Figure 6i and Figure 5e As shown, multiple sub-pixels Pxij form multiple rows. In the first reset gate drive circuit group Reset1 GOA, the 2n-th stage first reset gate drive circuit Reset1 GOA(n) is connected to the control electrode of multiple first transistors T1 in at least one row of sub-pixels Pxij, and the 2n+b-th stage first reset gate drive circuit Reset1GOA(2n+b) is connected to the control electrode of multiple second transistors T2 in the at least one row of sub-pixels Pxij; where n and b are positive integers greater than or equal to 1.

[0211] In an exemplary implementation, such as Figure 6i and Figure 5eAs shown, in the 2nth row sub-pixel P(2n), the control electrodes of multiple first transistors T1 are configured to be connected to the nth stage first reset gate drive circuit Reset1 GOA(n), and the control electrodes of multiple second transistors T2 are configured to be connected to the (n+b)th stage first reset gate drive circuit Reset1 GOA(n+b). Figure 5e The diagram shows a structure where b takes the value 1, but the value of b is not limited to 1.

[0212] In an exemplary implementation, such as Figure 6j and Figure 5f As shown, the multiple gate driving circuit groups may include a first light-emitting gate driving circuit group EM1 GOA, and the multiple transistors may also include a fifth transistor T5 as a light-emitting control transistor, with the second terminal of the fifth transistor T5 connected to the first terminal of the third transistor T3.

[0213] The first light-emitting gate driving circuit group EM1 GOA can be configured to be electrically connected to the control electrode of the fifth transistor T5 and the control electrode of the sixth transistor T6.

[0214] In an exemplary implementation, such as Figure 6j and Figure 5f As shown, multiple sub-pixels Pxij can form multiple rows. In the first light-emitting gate driving circuit group EM1 GOA, the nth-level first light-emitting gate driving circuit EM1 GOA(n) is connected to the control electrode of multiple fifth transistors T5 in at least one row of sub-pixels Pxij, and the (n+a)th-level first light-emitting gate driving circuit is connected to the control electrode of multiple sixth transistors T6 in the at least one row of sub-pixels Pxij; where n and a are positive integers greater than or equal to 1. Figure 5f The diagram shows a structure where 'a' has a value of 1, but the value of 'a' is not limited to 1.

[0215] In an exemplary implementation, such as Figure 6j and Figure 5f As shown, in the sub-pixels P(2n-1) and P(2n) in the 2n-1th row, the control electrodes of multiple fifth transistors T5 are configured to be connected to the first light-emitting gate driving circuit EM1 GOA(n) of the nth level, and the control electrodes of multiple sixth transistors T6 are configured to be connected to the first light-emitting gate driving circuit EM1 GOA(n+a) of the n+a level.

[0216] In an exemplary implementation, such as Figure 6k and Figure 5gAs shown, in the first light-emitting gate driving circuit group EM1 GOA, the nth-level first light-emitting gate driving circuit EM1 GOA(n) is connected to the control electrode of multiple fifth transistors T5 in at least one row of sub-pixels Pxij, and the (n+a)th-level first light-emitting gate driving circuit is connected to the control electrode of multiple sixth transistors T6 in the at least one row of sub-pixels Pxij; where n and a are positive integers greater than or equal to 1; in the first reset gate driving circuit group Reset1 GOA, the 2nth-level first reset gate driving circuit Reset1 GOA(n) is connected to the control electrode of multiple first transistors T1 in at least one row of sub-pixels Pxij, and the (2n+b)th-level first reset gate driving circuit Reset1GOA(2n+b) is connected to the control electrode of multiple second transistors T2 in the at least one row of sub-pixels Pxij; where n and b are positive integers greater than or equal to 1. Figure 5g The diagram shows a structure where a and b are both 1, but the values ​​of a and b are not limited to 1.

[0217] In an exemplary implementation, such as Figure 6k and Figure 5g As shown, in sub-pixels P(2n-1) and P(2n) in row 2n-1, the control electrodes of multiple fifth transistors T5 are connected to the first light-emitting gate driving circuit EM1 GOA(n) of the nth level, and the control electrodes of multiple sixth transistors T6 are connected to the first light-emitting gate driving circuit EM1 GOA(n+a) of the n+a level; in sub-pixels P(2n) in row 2n, the control electrodes of multiple first transistors T1 are connected to the first reset gate driving circuit Reset1 GOA(n) of the nth level, and the control electrodes of multiple second transistors T2 are connected to the first reset gate driving circuit Reset1 GOA(n+b) of the n+b level.

[0218] exist Figures 5c to 5g In this circuit, R1 can be the first reset control line Reset1 connected to the control electrode of the first transistor, R2 can be the second reset control line Reset2 connected to the control electrode of the second transistor, EM1 can be the first light emission control line EM1 connected to the control electrode of the fifth transistor T5, and EM2 can be the second light emission control line EM2 connected to the control electrode of the sixth transistor T6.

[0219] In an exemplary implementation, multiple sub-pixels Pxij form multiple rows, such as Figures 5c to 5g As shown, in at least one of the multiple gate drive circuit groups, the same gate drive circuit is configured to be electrically connected to at least two rows of sub-pixels Pxij, which can reduce the number of gate drive circuits and reduce the border size to a great extent.

[0220] In an exemplary implementation, such as Figure 6g , Figure 6h , Figure 5c As shown, the first transistor T1, the second transistor T2, and the sixth transistor T6 share a second light-emitting gate driving circuit group EM2 GOA. The fifth transistor T5 receives the light-emitting control signal through a first light-emitting gate driving circuit group EM1 GOA, and the fourth transistor T4 receives the scanning signal through a scanning gate driving circuit group Gate GOA. This means that only three gate driving circuits are needed in the border area BB. Figure 4a and Figure 4f Compared to the previous method which required five sets of gate drive circuits, this method reduces the number of gate drive circuits and can significantly reduce the bezel size.

[0221] In an exemplary implementation, such as Figure 6i and Figure 5e As shown, the first transistor T1 and the second transistor T2 share a first reset gate drive circuit group Reset1 GOA. The fifth transistor T5 receives the light emission control signal through a first light-emitting gate drive circuit group EM1 GOA. The sixth transistor T6 receives the light emission control signal through a second light-emitting gate drive circuit group EM2 GOA. The fourth transistor T4 receives the scan signal through a scan gate drive circuit group Gate GOA. Therefore, only four gate drive circuits are needed in the border area BB. Figure 4a and Figure 4f Compared to the previous method which required five sets of gate drive circuits, this method reduces the number of gate drive circuits and can reduce the bezel size.

[0222] In an exemplary implementation, such as Figure 6j and Figure 5f As shown, the fifth transistor T5 and the sixth transistor share a first light-emitting gate driving circuit group EM1 GOA. The first transistor T1 receives a reset signal through a first reset gate driving circuit group Reset1 GOA, the second transistor T2 receives a reset signal through a second reset gate driving circuit group Reset2 GOA, and the fourth transistor T4 receives a scan signal through a scan gate driving circuit group Gate GOA. This means that only four gate driving circuits are needed in the border area BB. Figure 4a and Figure 4f Compared to the previous method which required five sets of gate drive circuits, this method reduces the number of gate drive circuits and can reduce the bezel size.

[0223] In an exemplary implementation, such as Figure 6k and Figure 5gAs shown, the first transistor T1 and the second transistor T2 share a first reset gate drive circuit group Reset1 GOA, the fifth transistor T5 and the sixth transistor T6 share a first light-emitting gate drive circuit group EM1 GOA, and the fourth transistor T4 provides the scan signal through a scan gate drive circuit group Gate GOA. In other words, only three gate drive circuits are needed in the border area BB. Figure 4a and Figure 4f Compared to the previous method which required five sets of gate drive circuits, this method reduces the number of gate drive circuits and can significantly reduce the bezel size.

[0224] In an exemplary embodiment Figure 6g The operating timing of the pixel driving circuit shown can be as follows: Figure 7a As shown, Figure 6h The operating timing of the pixel driving circuit shown can be as follows: Figure 7b As shown, Figure 6k The operating timing of the pixel driving circuit shown can be as follows: Figure 7c The illustrated work sequence may include stage 1 (P11), stage 2 (P12), stage 3 (P13), and stage 4 (P14), and... Figure 4e The first stage P11, the second stage P12, the third stage P13 and the fourth stage P14 shown are basically the same. The main difference is that the conduction signal of the first type of transistor is the opposite of the conduction signal of the second type of transistor.

[0225] In an exemplary embodiment Figure 6d In the pixel driving circuit shown, the PWM dimming timing can be as follows: Figure 7d As shown, the low-frequency timing of split-screen can be as follows: Figure 7e As shown, the high-frequency timing of split-screen can be as follows: Figure 7f As shown. Figures 7d to 7e The refresh frame in the middle can be compared with Figure 4e The first stage (P11), the second stage (P12), the third stage (P13), and the fourth stage (P14) are basically the same, the difference being... Figures 7d to 7e The signal of the second reset control line Reset2 and Figure 4e The signal for Reset2 is reversed. In an exemplary embodiment, PWM dimming refers to Pulse Width Modulation (PWM) dimming, which means adjusting the pulse width of the gate drive signal through a control circuit with PWM function. Figure 7e and Figure 7fIn this approach, a split-screen timing scheme using high and low frequencies is employed. For the same scene, one part can use a low-frequency refresh rate, while another part can use a high-frequency refresh rate. For example, in a game scene, static areas can use a low-frequency refresh rate, while dynamic areas can use a high-frequency refresh rate. This satisfies the high image quality requirements of high-definition areas while appropriately reducing power consumption. In this exemplary implementation... Figures 7d to 7f The timing of the M1 stage can be the timing of one or more subsequent hold frames, for example... Figure 7d The timing sequence of the M1 stage can be one or more Figure 7d Maintain the timing of frames. Figure 7e The timing sequence of the M1 stage can be one or more Figure 7e Maintain the timing of frames. Figure 7f The timing sequence of the M1 stage can be one or more Figure 7f Maintain the timing of frames.

[0226] exist Figure 7d In the PWM timing shown, during the hold frame phase, the signals of the first light-emitting control line EM1, the second light-emitting control line EM2, and the second reset control line Reset2 are basically consistent with the refresh frame signal. The signals of the scan signal line Gate and the first reset control line Reset1 remain at a low level, meaning that the first transistor T1 and the fourth transistor T4 are always in the off state during the hold frame.

[0227] exist Figure 7e In the low-frequency timing diagram shown, during the hold frame phase, the first light emission control line EM1 and the second light emission control line EM2 are high-level signals, while the second reset control line Reset2, the scan signal line Gate, and the first reset control line Reset1 are low-level signals. That is, during the hold frame, the fifth transistor T5 and the sixth transistor T6 are always in the on state, while the first transistor T1, the second transistor T2, and the fourth transistor T4 are always in the off state.

[0228] exist Figure 7f In the high-frequency timing diagram shown, during the hold frame stage, the first light emission control line EM1 and the second light emission control line EM2 are high-level signals. That is, during the hold frame, the fifth transistor T5 and the sixth transistor T6 are always in the on state. The signals of the second reset control line Reset2, the scan signal line Gate, and the first reset control line Reset1 are basically the same as those of the refresh frame.

[0229] In an exemplary implementation, such as Figure 2bAs shown, the border area BB may include a third border area B3 and a fourth border area B4. In the first direction X, the third border area B3 and the fourth border area B4 may be located on both sides of the display area AA. Multiple gate drive circuit groups may be located in the third border area B3 and the fourth border area B4. The main body of the third border area B3 and the fourth border area B4 extends along the second direction Y. In a plane parallel to the display substrate, the first direction X intersects with the second direction Y.

[0230] In the bezel area on the same side of the display area AA in the first direction X, multiple gate drive circuits can be arranged along the extension direction of the bezel area BB in the same gate drive circuit group.

[0231] In an exemplary embodiment Figures 6g to 6k In the circuit, the first light-emitting gate driving circuit EM1 GOA can be connected to the control electrode of the corresponding fifth transistor T5 through the first light-emitting control line EM1. Figures 6g to 6i The second light-emitting gate driving circuit is configured such that EM2 GOA can be connected to the control electrode of the sixth transistor T6 via the second light-emitting control line EM2. The gate driving circuit may include multiple transistors. The multiple transistors in the first light-emitting gate driving circuit EM1 GOA and the second light-emitting gate driving circuit EM2 GOA may be first-type transistors. The first-type transistors may be configured as a single-gate structure, which can reduce the parasitic capacitance between the first power line VDD and the first light-emitting control line EM1 and the second light-emitting control line EM2, thereby improving display uniformity and reducing horizontal lines caused by signal crosstalk.

[0232] In an exemplary embodiment, the gate drive circuit group can employ single-sided driving, for example, different gate drive circuit groups can be set in the third frame region B3 and the fourth frame region B4 to reduce the number of gate drive circuit groups. Alternatively, the gate drive circuit group can employ double-sided driving, for example, the same gate drive circuit group can be set in the third frame region B3 and the fourth frame region B4; for example, in... Figure 6k and Figure 5g In the structure shown, a first light-emitting gate driving circuit group EM1 GOA and a scanning gate driving circuit group Gate GOA can be set in the third border region B3, and a second light-emitting gate driving circuit group EM2 GOA and a scanning gate driving circuit group Gate GOA can be set in the fourth border region. This way, both the third border region B3 and the fourth border region B4 have two gate driving circuit groups, which can make the border size smaller; or, as... Figure 6k and Figure 5gIn the structure shown, a first light-emitting gate driving circuit group EM1 GOA, a second light-emitting gate driving circuit group EM2 GOA, and a scanning gate driving circuit group Gate GOA can be set in the third frame region B3, and a first light-emitting gate driving circuit group EM1 GOA, a second light-emitting gate driving circuit group EM2 GOA, and a scanning gate driving circuit group Gate GOA can be set in the fourth frame region. Thus, both the third frame region B3 and the fourth frame region B4 can each have three gate driving circuit groups. Figure 4a Compared to the structure shown, this reduces the number of gate drive circuit groups by two, making it easier to narrow the bezel.

[0233] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate (or substrate plate) using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0234] In an exemplary embodiment, a sub-pixel (1 sub-pixel row, 1 sub-pixel column) in the display area (AA) is used, and the pixel driving circuit employs... Figure 5a Taking the 6T2C structure shown as an example, the fabrication process of one type of display substrate may include the following operations:

[0235] (101) A substrate is prepared on a glass substrate. In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, an adhesive layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers, and the material of the adhesive layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible material (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible material (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0236] (102) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: depositing a first semiconductor thin film on a substrate, and patterning the semiconductor thin film using a patterning process to form the first semiconductor layer pattern, such as... Figure 8 As shown, Figure 8 The diagram shown is a planar schematic of a sub-pixel after the first semiconductor layer has been formed.

[0237] In an exemplary embodiment, the first semiconductor layer pattern in at least a portion of the sub-pixels includes at least: the active layer AT5 of the fifth transistor T5.

[0238] In an exemplary embodiment, the active layer AT5 of the fifth transistor T5 may be in the shape of an "I" or a strip extending along the second direction Y.

[0239] In an exemplary embodiment, the active layer of at least some transistors may include a first region, a second region, and a channel region located between the first region and the second region, and the first region AT51 and the second region AT52 of the active layer AT5 of the fifth transistor T5 may be set separately.

[0240] In an exemplary embodiment, the first semiconductor layer may be polycrystalline silicon (p-Si), meaning the fifth transistor T5 may be an LTPS thin-film transistor. In another exemplary embodiment, patterning the first semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; then performing a hydrogen removal treatment on the amorphous silicon thin film; and finally performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the pattern of the first semiconductor layer.

[0241] (103) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed, and patterning the first conductive film using a patterning process to form a first conductive layer pattern covering the first semiconductor layer pattern, such as... Figure 9a and Figure 9b As shown, Figure 9a This is a schematic diagram of the planar structure of a sub-pixel after the formation of the first conductive layer. Figure 19b for Figure 19a A schematic diagram of the first conductive layer. The first conductive layer can be called the first gate metal (GATE1) layer.

[0242] In an exemplary embodiment, the first conductive layer pattern may include at least: the first electrode C11 of the first capacitor C1, the first electrode C21 of the second capacitor C2, and the first light-emitting control line EM1.

[0243] In an exemplary embodiment, the first light-emitting control line EM1 can be a zigzag structure or a strip structure extending along the first direction X; in the same sub-pixel, the first light-emitting control line EM1 and the active layer AT5 of the fifth transistor T5 can be located on the side of the first plate C21 of the second capacitor C2 away from the first plate C11 of the first capacitor C1.

[0244] In an exemplary embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be block structures, and the shape of the block structure can be polygonal. In an exemplary embodiment, at least one edge of the polygonal block structure is a broken line. For example, the polygonal block structure can be rectangular, and at least one edge of the rectangle is a broken line. In an exemplary embodiment, in the second direction Y, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be arranged sequentially.

[0245] In an exemplary embodiment, the first plate C11 of the first capacitor C1 may be provided with a first connection portion CL1. The first connection portion CL1 is configured to accommodate a subsequently formed fifteenth via. The orthographic projection of the fifteenth via on the substrate is within the range of the orthographic projection of the first connection portion CL1 on the substrate, and exposes the surface of the first connection portion CL1, so that the second electrode of the subsequently formed first transistor T1 and the second electrode of the fourth transistor T4 are connected to the first plate C11 of the first capacitor C1 through the fifteenth via and the first connection portion CL1.

[0246] In an exemplary embodiment, the first electrode plate C21 of the second capacitor C2 may be provided with a second connection portion CL2. The second connection portion CL2 is configured to accommodate a subsequently formed thirteenth via. The orthographic projection of the thirteenth via on the substrate is within the range of the orthographic projection of the second connection portion CL2 on the substrate, and exposes the surface of the second connection portion CL2, so that the first electrode of the subsequently formed fifth transistor T5 is connected to the first electrode plate C21 of the second capacitor C2 through the thirteenth via and the second connection portion CL2.

[0247] Taking the Mth row and Nth column sub-pixel as an example: In the second direction Y, the main body of the first plate C11 of the first capacitor C1 in the Mth row can be located on the side of the first plate C21 of the second capacitor C2 of the same sub-pixel near the M+1th row sub-pixel, and the first light-emitting control line EM1 can be located on the side of the first plate C21 of the second capacitor C2 of the same sub-pixel near the M-1th row sub-pixel; In the first direction X, at least a part of the structure of the first plate C11 of the first capacitor C1 is located on the side of the first plate C21 of the second capacitor C2 of the same sub-pixel near the N-1th column sub-pixel.

[0248] In an exemplary embodiment, the region where the first light-emitting control line EM1 overlaps with the active layer AT5 of the fifth transistor T5 can serve as the control electrode of the fifth transistor T5.

[0249] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the fifth transistor T5, and the first semiconductor layer in the area not shielded by the first conductive layer is conducted. That is, the first region and the second region of the active layer AT5 of the fifth transistor T5 are both conducted.

[0250] (104) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a first insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the first insulating layer, such as... Figures 10a to 10b As shown, Figure 10a This is a planar structure diagram of a sub-pixel after the second conductive layer has been formed. Figure 10b for Figure 10a A schematic planar view of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0251] In an exemplary embodiment, the second conductive layer pattern may include at least: the second electrode C12 of the first capacitor C1, the second electrode C22 of the second capacitor C2, the first shielding line BL1, the bottom gate T1gb of the first transistor T1, the bottom gate T2gb of the second transistor T2, and the bottom gate T4gb of the fourth transistor T4.

[0252] In an exemplary embodiment, in the second direction Y, within the same sub-pixel, the bottom gate T1gb of the first transistor T1 and the bottom gate T2gb of the second transistor T2 can be located on opposite sides of the first blocking line BL1. The bottom gate T1gb of the first transistor T1 can be located between the first blocking line BL1 and the second plate C12 of the first capacitor C1. The second plate C22 of the second capacitor C2 and the bottom gate T4gb of the fourth transistor T4 can be located on the side of the second plate C12 of the first capacitor C1 away from the first blocking line BL1. For example, in the same sub-pixel, the bottom gate T2gb of the second transistor T2, the first blocking line BL1, the bottom gate T1gb of the first transistor T1, the second plate C12 of the first capacitor C1, and the second plate C22 of the second capacitor C2 can be arranged sequentially along the second direction Y.

[0253] In an exemplary embodiment, the first shielding line BL1 can be strip-shaped or zigzag-shaped, and its main body can extend along the first direction X. The first shielding line BL1 is configured as a shielding layer for the sixth transistor T6, shielding the channel of the sixth transistor T6 and ensuring the electrical performance of the oxide sixth transistor T6. In an exemplary embodiment, the signal of the first shielding line BL1 and the subsequently formed second light-emitting control line EM2 can be the same, that is, the first shielding line BL1 and the subsequently formed second light-emitting control line EM2 are connected in parallel and connected to the same signal source, so that the first shielding line BL1 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the sixth transistor T6, forming a double-gate structure sixth transistor T6.

[0254] In an exemplary embodiment, the bottom gate T1gb of the first transistor T1 can be strip-shaped or zigzag-shaped, and its main body can extend along the first direction X. The bottom gate T1gb of the first transistor T1 is configured as a shielding layer of the first transistor T1, shielding the channel of the first transistor T1 and ensuring the electrical performance of the oxide first transistor T1. In an exemplary embodiment, the signal of the bottom gate T1gb of the first transistor T1 and the subsequently formed first reset control line Reset1 can be the same, that is, the first shielding structure BSM1 is connected to the subsequently formed first reset control line Reset1 and is connected in parallel with the top gate T1gt of the subsequently formed first transistor T1. Both are connected to the same signal source, so that the bottom gate T1gb of the first transistor T1 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the first transistor T1, forming a dual-gate structure first transistor T1.

[0255] In an exemplary embodiment, the bottom gate T2gb of the second transistor T2 can be a strip structure or a zigzag structure extending along the first direction X, configured as a shielding layer for the second transistor T2, shielding the channel of the second transistor T2 and ensuring the electrical performance of the oxide second transistor T2. In an exemplary embodiment, the signal of the bottom gate T2gb of the second transistor T2 and the subsequently formed second reset control line Reset2 can be the same, that is, the bottom gate T2gb of the second transistor T2 is connected to the subsequently formed second reset control line Reset2 and is connected in parallel with the top gate T2gt of the subsequently formed second transistor T2, and both are connected to the same signal source, so that the bottom gate T2gb of the second transistor T2 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming a dual-gate structure second transistor T2.

[0256] In an exemplary embodiment, the bottom gate T4gb of the fourth transistor T4 can be a strip structure or a zigzag structure extending along the first direction X, configured as a shielding layer for the fourth transistor T4, shielding the channel of the fourth transistor T4 and ensuring the electrical performance of the oxide fourth transistor T4. In an exemplary embodiment, the signal of the bottom gate T4gb of the fourth transistor T4 can be the same as that of the subsequently formed scan signal line Gate, that is, the bottom gate T4gb of the fourth transistor T4 is connected to the subsequently formed scan signal line Gate and is connected in parallel with the subsequently formed top gate T4gt of the fourth transistor T4, both connected to the same signal source, so that the bottom gate T4gb of the fourth transistor T4 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the fourth transistor T4, forming a dual-gate structure fourth transistor T4.

[0257] In an exemplary embodiment, the outline of the second plate C12 of the first capacitor C1 may coincide with the outline of the first plate C11 of the first capacitor C1, and the outline of the second plate C22 of the second capacitor C2 may coincide with the outline of the first plate C21 of the second capacitor C2. For example, the outlines of the second plates C12 of the first capacitor C1 and C22 of the second capacitor C2 may be polygonal (e.g., rectangular, and at least one edge of the rectangle is a polygonal line). In an exemplary embodiment, the orthographic projection of the second plate C12 of the first capacitor C1 onto the substrate overlaps with the orthographic projection of the first plate C11 of the first capacitor C1 onto the substrate, and the orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate overlaps with the orthographic projection of the first plate C21 of the second capacitor C2 onto the substrate. For example, the orthographic projection of the second plate C12 of the first capacitor C1 onto the substrate may be within the range of the orthographic projection of the first plate C11 of the first capacitor C1 onto the substrate, and the orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate may be within the range of the orthographic projection of the first plate C21 of the second capacitor C2 onto the substrate. In an exemplary embodiment, the first plate C11 and the second plate C12 of the first capacitor C1 constitute the first capacitor C1, and the first plate C21 and the second plate C22 of the second capacitor C2 constitute the second capacitor C2.

[0258] In an exemplary embodiment, the second plate C22 of the second capacitor C2 can block the channel of the third body tube T3, thereby ensuring the electrical performance of the oxide third body tube T3.

[0259] (105) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a third insulating film and a semiconductor film on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film using a patterning process to form a second insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the second insulating layer, such as... Figures 11a to 11b As shown, Figure 11a This is a planar structure diagram of a sub-pixel after the formation of the first semiconductor layer. Figure 11b for Figure 11a A planar schematic diagram of the semiconductor layer.

[0260] In an exemplary embodiment, the semiconductor layer pattern in at least some of the sub-pixels includes at least: the active layer AT1 of the first transistor T1 to the active layer AT4 of the fourth transistor T4 and the active layer AT6 of the sixth transistor T6.

[0261] In an exemplary embodiment, within the same sub-pixel, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, and the active layer AT6 of the sixth transistor T6 can be interconnected. For example, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, and the active layer AT6 of the sixth transistor T6 can be an interconnected integral structure.

[0262] In an exemplary embodiment, within the same sub-pixel, in the first direction X, the active layer AT1 of the first transistor T1 and the active layer AT4 of the fourth transistor T4 may be located on the same side of the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, and the active layer AT6 of the sixth transistor T6; in the second direction Y, the active layer AT2 of the second transistor T2 and the active layer AT3 of the third transistor T3 are located on opposite sides of the active layer AT6 of the sixth transistor T6, the active layer AT4 of the fourth transistor T4 and the active layer AT5 of the fifth transistor T5 are located on the same side of the active layer AT6 of the sixth transistor T6, and the active layer AT1 of the first transistor T1 and the active layer AT2 of the second transistor T2 are located on the same side of the active layer AT3 of the third transistor T3.

[0263] In an exemplary embodiment, taking the sub-pixel in the Mth row and Nth column as an example: In the first direction X, the active layer of the first transistor T1 and the active layer AT4 of the fourth transistor T4 can be located on the side away from the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, and the active layer AT6 of the sixth transistor T6, respectively. The active layer AT5 of the fifth transistor T5 can be located close to the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, and the active layer AT6 of the sixth transistor T6, respectively. On one side of the pixel; in the second direction Y, the active layer AT4 of the fourth transistor T4 can be located on the side of the active layer AT1 of the first transistor T1 away from the (M+1)th row of sub-pixels, the active layer AT6 of the sixth transistor T6 can be located on the side of the active layer AT3 of the third transistor T3 away from the (M-1)th row of sub-pixels, the active layer AT2 of the second transistor T2 can be located on the side of the active layer AT6 of the sixth transistor T6 close to the (M+1)th row of sub-pixels, and the active layer AT5 of the fifth transistor T5 can be located on the side of the active layer AT6 of the sixth transistor T6 away from the (M+1)th row of sub-pixels.

[0264] In an exemplary embodiment, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, and the active layer AT6 of the sixth transistor T6 can be in the shape of an "I" or a strip.

[0265] In an exemplary embodiment, the active layer of at least some transistors may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region AT32 of the active layer AT3 of the third transistor T3 may serve as the first region AT61 of the active layer AT6 of the sixth transistor T6, and the second region AT62 of the active layer AT6 of the sixth transistor T6 may serve as the second region AT22 of the active layer AT2 of the second transistor T2. The first region AT11 and the second region AT12 of the active layer AT1 of the first transistor T1, the first region AT21 of the active layer AT2 of the second transistor T2, the first region AT31 of the active layer AT3 of the third transistor T3, and the first region AT41 and the second region AT42 of the active layer AT4 of the fourth transistor T4 may be individually configured.

[0266] In an exemplary embodiment, the conductor layer may be an oxide, i.e., the first transistor T1 to the fourth transistor T4 and the sixth transistor T6 are oxide thin-film transistors. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfide oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film may be indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon.

[0267] (106) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fourth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a fourth insulating layer covering the second semiconductor layer; and a third conductive layer pattern disposed on the third insulating layer, such as... Figures 12a to 12b As shown, Figure 12a This is a planar structure diagram of a sub-pixel after the formation of the third conductive layer. Figure 12b for Figure 12a A schematic planar view of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the third gate metal (GATE3) layer.

[0268] In an exemplary embodiment, the third conductive layer pattern includes at least: a second light-emitting control line EM2, a top gate T1gt of a first transistor T1, a top gate T2gt of a second transistor T2, a top gate T3gt of a third transistor T3, and a top gate T4gt of a fourth transistor T4.

[0269] In an exemplary embodiment, the second light-emitting control line EM2 can be a zigzag or strip shape extending along the first direction X of the main body. In the same sub-pixel row, in the second direction Y, the top gate T1gt of the first transistor T1 and the top gate T2gt of the second transistor T2 can be located on opposite sides of the second light-emitting control line EM2, the top gate T3gt of the third transistor T3 can be located on the side of the top gate T1gt of the first transistor T1 away from the second light-emitting control line EM2, and the top gate T4gt of the fourth transistor T4 can be located on the side of the top gate T3gt of the third transistor T3 away from the second light-emitting control line EM2; in the first direction X, the top gate T4gt of the fourth transistor T4 and the top gate T1gt of the first transistor T1 can be located on the same side of the top gate T3gt of the third transistor T3 and the top gate T2gt of the second transistor T2; Taking the Mth row and Nth column sub-pixel as an example: In the second direction Y, the top gate T1gt of the first transistor T1 can be located on the side of the second light-emitting control line EM2 away from the M+1th row sub-pixel, the top gate T2gt of the second transistor T2 can be located on the side of the second light-emitting control line EM2 close to the M+1th row sub-pixel, the top gate T3gt of the third transistor T3 can be located on the side of the first transistor T1's top gate T1gt away from the M+1th row sub-pixel, and the top gate T4gt of the fourth transistor T4 can be located on the side of the third transistor T3's top gate T3gt away from the M+1th row sub-pixel; In the first direction X, the top gate T4gt of the fourth transistor T4 and the top gate T1gt of the first transistor T1 can be located on the side of the third transistor T3's top gate T3gt and the second transistor T2's top gate T2gt close to the N-1th column sub-pixel.

[0270] In an exemplary embodiment, the region where the second light-emitting control line EM2 overlaps with the active layer AT6 of the sixth transistor T6 can serve as the top gate T6gt of the sixth transistor T6. In another exemplary embodiment, the orthographic projection of the second light-emitting control line EM2 onto the substrate at least partially overlaps with the orthographic projection of the first blocking line BL1 onto the substrate. For example, the orthographic projection of the second light-emitting control line EM2 onto the substrate can be located within the range of the orthographic projection of the first blocking line BL1 onto the substrate, which can save space on the display substrate and improve the utilization rate of the display substrate space.

[0271] In an exemplary embodiment, the orthographic projection of the top gate T1gt of the first transistor T1 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate; the orthographic projection of the top gate T2gt of the second transistor T2 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate; the orthographic projection of the top gate T3gt of the third transistor T3 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT3 of the third transistor T3 onto the substrate; and the orthographic projection of the top gate T4gt of the fourth transistor T4 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT4 of the fourth transistor T4 onto the substrate.

[0272] In an exemplary embodiment, after the third conductive layer pattern is formed, the third conductive layer can be used as a shield to conduct the second semiconductor layer. The semiconductor layer in the region shielded by the third conductive layer forms the channel regions of the first transistor T1 to the fourth transistor T4 and the sixth transistor T6. The semiconductor layer in the region not shielded by the third conductive layer is conducted, that is, the first region and the second region of the active layer AT1 of the first transistor T1 to the active layer AT4 of the fourth transistor T4 and the active layer AT6 of the sixth transistor T6 are all conducted.

[0273] (107) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering a third conductive layer, wherein a plurality of vias are provided on the fifth insulating layer, such as... Figure 13 As shown, Figure 13 This is a planar structure diagram of a sub-pixel after the formation of the fifth insulating layer.

[0274] In an exemplary embodiment, at least some of the vias in the sub-pixels include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, and a twenty-second via V22.

[0275] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The fifth and fourth insulating layers within the first via V1 are etched away, exposing the surface of the first region AT11 of the active layer AT1 of the first transistor T1. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the active layer AT1 of the first transistor T1 through the via.

[0276] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The fifth and fourth insulating layers within the second via V2 are etched away, exposing the surface of the second region AT12 of the active layer AT1 of the first transistor T1. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the active layer AT1 of the first transistor T1 through the via.

[0277] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate. The fifth and fourth insulating layers within the third via V3 are etched away, exposing the surface of the first region AT21 of the active layer AT2 of the second transistor T2. The third via V3 is configured to allow the first electrode of the subsequently formed second transistor T2 to be connected to the active layer AT2 of the second transistor T2 through the via.

[0278] In an exemplary embodiment, the orthogonal projection of the fourth via V4 onto the substrate lies within the orthogonal projection of the second region AT22 of the active layer AT2 of the second transistor T2 (which is also the second region AT62 of the active layer AT6 of the sixth transistor T6) onto the substrate. The fifth and fourth insulating layers within the fourth via V4 are etched away, exposing the surface of the second region AT22 of the active layer AT2 of the second transistor T2 (which is also the second region AT62 of the active layer AT6 of the sixth transistor T6). The fourth via V4 is configured to connect the second electrode of the subsequently formed second transistor T2 to the active layer AT2 of the second transistor T2 through the via, and to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer AT6 of the sixth transistor T6 through the via.

[0279] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the orthographic projection of the active layer AT3 of the third transistor T3 onto the substrate. The fifth and fourth insulating layers within the fifth via V5 are etched away, exposing the surface of the second region AT32 of the active layer AT3 of the third transistor T3 (which is also the first region AT61 of the active layer AT6 of the sixth transistor T6). The fifth via V5 is configured to connect the second electrode of the subsequently formed third transistor T3 to the active layer AT3 of the third transistor T3 through the via, and to connect the first electrode of the subsequently formed sixth transistor T6 to the active layer AT6 of the sixth transistor T6 through the via.

[0280] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate lies within the orthographic projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The fifth and fourth insulating layers within the sixth via V6 are etched away, exposing the first region AT41 of the active layer AT4 of the fourth transistor T4. The sixth via V6 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the active layer AT4 of the fourth transistor T4 through this via.

[0281] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the substrate lies within the orthogonal projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The fifth and fourth insulating layers within the seventh via V7 are etched away, exposing the second region AT42 of the active layer AT4 of the fourth transistor T4. The seventh via V7 is configured to allow the second electrode of the subsequently formed fourth transistor T4 to be connected to the active layer AT4 of the fourth transistor T4 through this via.

[0282] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the active layer AT5 of the fifth transistor T5 onto the substrate. The fifth, fourth, third, second, and first insulating layers within the eighth via V8 are etched away, exposing the surface of the first region AT51 of the active layer AT5 of the fifth transistor T5. The eighth via V8 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the active layer AT5 of the fifth transistor T5 through this via.

[0283] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the substrate lies within the orthogonal projection of the active layer AT5 of the fifth transistor T5 onto the substrate. The fifth, fourth, third, second, and first insulating layers within the ninth via V9 are etched away, exposing the surface of the active layer AT5 of the fifth transistor T5. The ninth via V9 is configured to allow the second electrode of the subsequently formed fifth transistor T5 to be connected to the active layer AT5 of the fifth transistor T5 through this via.

[0284] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate lies within the range of the orthographic projection of the bottom gate T1gb of the first transistor T1 onto the substrate. The fifth, fourth, and third insulating layers within the tenth via V10 are etched away, exposing the surface of the bottom gate T1gb of the first transistor T1. The tenth via V10 is configured to allow the subsequently formed first reset control line Reset1 to connect to the bottom gate T1gb of the first transistor T1 through this via.

[0285] In an exemplary embodiment, the orthogonal projection of the eleventh via V11 onto the substrate lies within the orthogonal projection of the bottom gate T2gb of the second transistor T2 onto the substrate. The fifth, fourth, and third insulating layers within the eleventh via V11 are etched away, exposing the surface of the bottom gate T2gb of the second transistor T2. The eleventh via V11 is configured to allow the subsequently formed second reset control line Reset2 to connect to the bottom gate T2gb of the second transistor T2 through this via.

[0286] In an exemplary embodiment, the orthogonal projection of the twelfth via V12 onto the substrate lies within the orthogonal projection of the bottom gate T4gb of the fourth transistor T4 onto the substrate. The fifth, fourth, and third insulating layers within the twelfth via V12 are etched away, exposing the surface of the bottom gate T4gb of the fourth transistor T4. The twelfth via V12 is configured to allow the subsequently formed scan signal line Gate to connect to the bottom gate T4gb of the fourth transistor T4 through this via.

[0287] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate lies within the range of the orthographic projection of the first electrode C21 of the second capacitor C2 onto the substrate (the orthographic projection of the thirteenth via V13 may lie within the range of the orthographic projection of the second connection portion CL2 onto the substrate). The fifth, fourth, third, and second insulating layers within the thirteenth via V13 are etched away, exposing the surface of the first electrode C21 of the second capacitor C2. The thirteenth via V13 is configured to allow the subsequently formed sixth connection electrode to be connected to the first electrode C21 of the second capacitor C2 through this via.

[0288] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate is within the range of the orthographic projection of the first electrode C11 of the first capacitor C1 onto the substrate (the orthographic projection of the fourteenth via V14 onto the substrate may be within the range of the orthographic projection of the first connecting portion CL1 onto the substrate). The fifth, fourth, third, and second insulating layers within the fourteenth via V14 are etched away, exposing the surface of the first electrode C11 of the first capacitor C1. The fourteenth via V14 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the first electrode C11 of the first capacitor C1 through this via.

[0289] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the orthographic projection of the first electrode C11 of the first capacitor C1 onto the substrate. The fifth, fourth, third, and second insulating layers within the fifteenth via V15 are etched away, exposing the surface of the first electrode C11 of the first capacitor C1. The fifteenth via V15 is configured to allow the second electrode of the subsequently formed fourth transistor T4 to be connected to the first electrode C11 of the first capacitor C1 through this via.

[0290] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate lies within the orthographic projection of the second electrode C12 of the first capacitor C1 onto the substrate. The fifth, fourth, and third insulating layers within the sixteenth via V16 are etched away, exposing the surface of the second electrode C12 of the first capacitor C1. The sixteenth via V16 is configured to allow the second electrode of the subsequently formed third transistor T3 (which is also the first electrode of the sixth transistor T6) to be connected to the second electrode C12 of the first capacitor C1 through this via.

[0291] In an exemplary embodiment, the orthogonal projection of the seventeenth via V17 onto the substrate lies within the orthogonal projection of the second electrode C22 of the second capacitor C2 onto the substrate. The fourth, third, and second insulating layers within the seventeenth via V17 are etched away, exposing the surface of the second electrode C22 of the second capacitor C2. The seventeenth via V17 is configured to allow the second electrode of the subsequently formed third transistor T3 (which is also the first electrode of the sixth transistor T6) to be connected to the second electrode C22 of the second capacitor C2 through this via.

[0292] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 onto the substrate lies within the orthographic projection of the top gate T1gt of the first transistor T1 onto the substrate. The fifth insulating layer within the eighteenth via V18 is etched away, exposing the surface of the top gate T1gt of the first transistor T1. The eighteenth via V18 is configured to allow the subsequently formed first reset control line Reset1 to be connected to the top gate T1gt of the first transistor T1 through this via.

[0293] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 onto the substrate lies within the orthographic projection of the top gate T2gt of the second transistor T2 onto the substrate. The fifth insulating layer within the nineteenth via V19 is etched away, exposing the surface of the top gate T2g of the second transistor T2. The nineteenth via V19 is configured to allow the subsequently formed second reset control line Reset2 to connect to the top gate T2gt of the second transistor T2 through this via.

[0294] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate lies within the orthographic projection of the top gate T3gt of the third transistor T3 onto the substrate. The fifth insulating layer within the twentieth via V20 is etched away, exposing the surface of the top gate T3gt of the third transistor T3. The twentieth via V20 is configured to allow the second terminal of the subsequently formed fourth transistor T4 to be connected to the top gate T3gt of the third transistor T3 through the via.

[0295] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 onto the substrate lies within the orthographic projection of the top gate T4gt of the fourth transistor T4 onto the substrate. The fifth insulating layer within the twenty-first via V21 is etched away, exposing the surface of the top gate T4gt of the fourth transistor T4. The twenty-first via V21 is configured to allow the subsequently formed scan signal line Gate to be connected to the top gate T4gt of the fourth transistor T4 through this via.

[0296] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate lies within the orthographic projection of the active layer AT3 of the third transistor T3 onto the substrate. The fifth and fourth insulating layers within the 22nd via V22 are etched away, exposing the surface of the first region AT31 of the active layer AT3 of the third transistor T3. The 22nd via V22 is configured to connect the second electrode of the subsequently formed third transistor T3 to the active layer AT3 of the third transistor T3 through the via, and to connect the first electrode of the subsequently formed third transistor T3 to the active layer AT3 of the third transistor T3 through the via.

[0297] (108) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive thin film using a patterning process, and forming a fourth conductive layer disposed on a fifth insulating layer, such as... Figures 14a to 14b As shown, Figure 14a This is a planar structure diagram of a sub-pixel after the fourth conductive layer has been formed. Figure 14b for Figure 14a A schematic planar view of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0298] In an exemplary embodiment, the fourth conductive layer includes at least: a scan signal line Gate, a first reset control line Reset1, a first initial signal line Vinit1, a second reset control line Reset2, a second initial signal line Vinit2, a first connecting electrode L1, a second connecting electrode L2, a third connecting electrode L3, a fourth connecting electrode L4, a fifth connecting electrode L5, a sixth connecting electrode L6, and a seventh connecting electrode L7.

[0299] In an exemplary embodiment, the main body of the scan signal line Gate, the first reset control line Reset1, the first initial signal line Vinit1, the second reset control line Reset2, and the second initial signal line Vinit2 can be a strip-shaped structure or a broken line structure extending along the first direction X. In the same row of sub-pixels, the scan signal line Gate, the first reset control line Reset1, the first initial signal line Vinit1, the second reset control line Reset2, and the second initial signal line Vinit2 can be arranged sequentially at intervals along the opposite direction of the second direction Y.

[0300] In an exemplary embodiment, within the same sub-pixel, in the second direction Y, the first connecting electrode L1, the third connecting electrode L3, and the fifth connecting electrode L5 may be located between the first reset control line Reset1 and the scan signal line Gate; the second connecting electrode L2 may be located between the first initial signal line Vinit1 and the second reset control line Reset2; and the fourth connecting electrode L4, the sixth connecting electrode L6, and the seventh connecting electrode L7 may be located on the side of the scan signal line Gate away from the first reset control line Reset1. In the first direction X, the first connecting electrode L1 and the fourth connecting electrode L4 may be located on the same side of the third connecting electrode L3, the sixth connecting electrode L6, and the seventh connecting electrode L7. Taking the Mth row and Nth column sub-pixel as an example: In the second direction Y, the scan signal line Gate can be located on the side of the first reset control line Reset1 away from the M+1th row sub-pixel, the first initial signal line Vinit1 can be located on the side of the first reset control line Reset1 close to the M+1th row sub-pixel, the second reset control line Reset2 can be located on the side of the first initial signal line Vinit1 close to the M+1th row sub-pixel, and the second initial signal line Vinit2 can be located on the side of the second reset control line Reset2 close to the M+1th row sub-pixel. The first connecting electrode L1 and the third connecting electrode L2... Electrode L3 and fifth connecting electrode L5 can be located on the side of the first reset control line Reset1 away from the sub-pixel of row M+1. Second connecting electrode L2 can be located on the side of the first initial signal line Vinit1 close to the sub-pixel of row M+1. Fourth connecting electrode L4, sixth connecting electrode L6, and seventh connecting electrode L7 can be located on the side of the scan signal line Gate away from the sub-pixel of row M+1. In the first direction X, first connecting electrode L1 and fourth connecting electrode L4 can be located on the side of third connecting electrode L3, sixth connecting electrode L6, and seventh connecting electrode L7 away from the sub-pixel of column N+1.

[0301] In an exemplary embodiment, the scan signal line Gate can be connected to the top gate T4gt of the fourth transistor T4 in a row of sub-pixels via the twenty-first via V21 in that row, and to the bottom gate T4gb of the fourth transistor T4 in that row via the twelfth via V12 in that row, thus providing scan signals to the bottom gate T4gb and top gate T4gt of multiple fourth transistors T4 in that row of sub-pixels. Within the same sub-pixel, the bottom gate T4gb and top gate T4gt of the fourth transistor T4 can be electrically connected via the scan signal line Gate, so that the bottom gate T4gb and top gate T4gt of the fourth transistor T4 in the same sub-pixel have the same potential.

[0302] In an exemplary embodiment, the first reset control line Reset1 can be connected to the top gate T1gt of the first transistor T1 in a row of sub-pixels via the eighteenth via V18 in that row of sub-pixels, and to the bottom gate T1gb of the first transistor T1 in that row of sub-pixels via the tenth via V10 in that row of sub-pixels, configured to provide a first reset control signal to the bottom gate T1gb and top gate T1gt of multiple first transistors T1 in that row of sub-pixels. Within the same sub-pixel, the bottom gate T1gb and top gate T1gt of the first transistor T1 can be electrically connected via the first reset control line Reset1, so that the bottom gate T1gb and top gate T1gt of the first transistor T1 in the same sub-pixel have the same potential.

[0303] In an exemplary embodiment, the first initial signal line Vinit1 can be connected to the first region AT11 of the active layer AT1 of the first transistor T1 in the row of sub-pixels via a first via V1 in the row of sub-pixels, thereby providing a first initial signal to the first transistor T1 in the row of sub-pixels. In an exemplary embodiment, the first initial signal line Vinit1 can serve as the first electrode of the first transistor T1.

[0304] In an exemplary embodiment, the second reset control line Reset2 can be connected to the top gate T2gt of the second transistor T2 in a row of sub-pixels via the nineteenth via V17, and to the bottom gate T2gb of the second transistor T2 in the same row of sub-pixels via the eleventh via V11. This is configured to provide a second reset control signal to the bottom gate T2gb and top gate T2gt of multiple second transistors T2 in that row of sub-pixels. Within the same sub-pixel, the bottom gate T2gb and top gate T2gt of the second transistor T2 can be electrically connected via the second reset control line Reset2, ensuring that the bottom gate T2gb and top gate T2gt of the second transistor T2 in the same sub-pixel have the same potential.

[0305] In an exemplary embodiment, the second initial signal line Vinit2 can be connected to the first region AT21 of the active layer AT2 of the second transistor T2 located in that row of sub-pixels via a third via V3 in that row of sub-pixels, thereby providing a second initial signal to the second transistor T2 in that row of sub-pixels. In an exemplary embodiment, the second initial signal line Vinit2 can serve as the first electrode of the second transistor T2.

[0306] In an exemplary embodiment, the first connecting electrode L1 is generally strip-shaped or zigzag-shaped extending along the first direction X. The first connecting electrode L1 can be connected to the second region AT12 of the active layer AT1 of the first transistor T1 via the second via V2, and to the first electrode C11 of the first capacitor C1 via the fourteenth via V14. The second region AT12 of the active layer AT1 of the first transistor T1 and the first electrode C11 of the first capacitor C1 are electrically connected via the first connecting electrode L1, so that the second electrode of the first transistor T1 and the first electrode C11 of the first capacitor C1 in the same sub-pixel have the same potential. In an exemplary embodiment, the first connecting electrode L1 can serve as the second electrode of the first transistor T1.

[0307] In an exemplary embodiment, the second connection electrode L4 is generally strip-shaped, extending along the first direction X. The second connection electrode L4 can be connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT22 of the active layer AT2 of the second transistor T2) via the fourth via V4. In an exemplary embodiment, the fourth connection electrode L4 can serve as the second electrode of the sixth transistor T6 and the second electrode of the second transistor T2. The fourth connection electrode L4 is configured to be connected to the anode connection electrode of a subsequently formed light-emitting element.

[0308] In an exemplary embodiment, the third connection electrode L3 is approximately shaped like a "7". The third connection electrode L3 can be connected via the fifth via V5, the second region AT32 of the active layer AT3 of the third transistor T3 (which is also the first region AT61 of the active layer AT6 of the sixth transistor T6), the sixteenth via V16 to the second plate C12 of the first capacitor C1, and the seventeenth via V17 to the second plate C22 of the second capacitor C2. This ensures that the second region AT32 of the active layer AT3 of the third transistor T3 (which is also the first region AT61 of the active layer AT6 of the sixth transistor T6), the second plate C12 of the first capacitor C1, and the second plate C22 of the second capacitor C2 in the same sub-pixel have the same potential. In an exemplary embodiment, the third connection electrode L3 can serve as the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.

[0309] In an exemplary embodiment, the fourth connection electrode L4 is generally a block structure or a rectangular structure extending along the first direction X. The fourth connection electrode L4 can be connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the sixth via V6. In an exemplary embodiment, the first connection electrode L1 can serve as the first electrode of the fourth transistor T4 and is configured to be connected to the subsequently formed data signal line.

[0310] In an exemplary embodiment, the fifth connecting electrode L5 is generally a strip structure or a broken line structure extending along the first direction X. The fifth connecting electrode L5 can be connected to the second region AT42 of the active layer AT4 of the fourth transistor T4 through the seventh via V7, to the first plate C11 of the first capacitor C1 through the fifteenth via V15, and to the top gate T3gt of the third transistor T3 through the twentieth via V20, so that the top gate of the third transistor T3, the first plate C11 of the first capacitor C1, and the second region AT42 of the active layer AT4 of the fourth transistor T4 in the same sub-pixel have the same potential. Since the first plate C11 of the first capacitor C1 is connected to the second region AT12 of the active layer AT1 of the first transistor T1 through the first connecting electrode L1, the second region AT12 of the active layer AT1 of the first transistor T1 can have the same potential as the top gate of the third transistor T3, the first plate C11 of the first capacitor C1, and the second region AT42 of the active layer AT4 of the fourth transistor T4. In an exemplary embodiment, the first connection electrode L1 can serve as the second electrode of the fourth transistor T4.

[0311] In an exemplary embodiment, the sixth connecting electrode L6 is generally strip-shaped or zigzag-shaped extending along the first direction X. The sixth connecting electrode L6 can be connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 in the same sub-pixel through an eighth via V8, and to the first electrode C21 of the second capacitor C2 through a thirteenth via V13. In an exemplary embodiment, the sixth connecting electrode L6 can serve as the first electrode of the fifth transistor T5. In the same sub-pixel, the first region AT51 of the active layer AT5 of the fifth transistor T5 and the first electrode C21 of the second capacitor C2 can be electrically connected through the sixth connecting electrode L6, so that the first region AT51 of the active layer AT5 of the fifth transistor T5 and the first electrode C21 of the second capacitor C2 in the same sub-pixel have the same potential.

[0312] In an exemplary embodiment, the seventh connecting electrode L7 can be a strip structure or a zigzag structure extending along the first direction X. The seventh connecting electrode L7 can be connected to the second region AT52 of the active layer AT5 of the fifth transistor T5 through the ninth via V9, and to the first region AT31 of the active layer AT3 of the third transistor T3 through the twenty-second via V22. In an exemplary embodiment, the seventh connecting electrode L7 can serve as the second electrode of the fifth transistor T5 and the first electrode of the third transistor T3. In the same sub-pixel, the second region AT52 of the active layer AT5 of the fifth transistor T5 and the first region AT31 of the active layer AT3 of the third transistor T3 can be electrically connected through the seventh connecting electrode L7, so that the first region AT51 of the active layer AT5 of the fifth transistor T5 and the first region AT31 of the active layer AT3 of the third transistor T3 in the same sub-pixel have the same potential.

[0313] (109) Forming a pattern for the sixth insulating layer and the first planarization layer. In an exemplary embodiment, forming the pattern for the sixth insulating layer and the first planarization layer may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and patterning the first planarization film and the sixth insulating film using a patterning process to form a sixth insulating layer covering the pattern of the fourth conductive layer and a first planarization layer disposed on the sixth insulating layer. Multiple vias are provided on the sixth insulating layer and the first planarization layer, such as... Figure 15 As shown, Figure 15 This is a planar structure diagram of a sub-pixel after the first flattening layer is formed.

[0314] In an exemplary embodiment, the plurality of vias on the sixth insulating layer and the first planarization layer may include at least: a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, and a twenty-sixth via V26.

[0315] In an exemplary embodiment, the orthographic projection of the 23rd via V23 onto the substrate lies within the orthographic projection of the fourth connection electrode L4 onto the substrate. The first planarization layer and the sixth insulating layer within the 23rd via V23 are etched away, exposing the surface of the fourth connection electrode L4. The 23rd via V23 is configured to allow subsequently formed data signal lines to be electrically connected to the fourth connection electrode L4 through this via.

[0316] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate lies within the range of the orthographic projection of the sixth connecting electrode L6 onto the substrate. The first planarization layer and the sixth insulating layer within the 24th via V24 are etched away, exposing the surface of the sixth connecting electrode L6. The 24th via V24 is configured to allow a subsequently formed first power line to be connected to the sixth connecting electrode L6 through this via.

[0317] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate lies within the range of the orthographic projection of the second connecting electrode L2 onto the substrate. The first planarization layer and the sixth insulating layer within the 25th via V25 are etched away, exposing the surface of the second connecting electrode L2. The 25th via V25 is configured to allow the anode connecting electrode of a subsequently formed light-emitting element to be electrically connected to the second connecting electrode L2 through this via.

[0318] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate is within the range of the orthographic projection of the second initial signal line Vinit2 onto the substrate. The first planarization layer and the sixth insulating layer within the 26th via V26 are etched away, exposing the surface of the second initial signal line Vinit2. The 26th via V26 is configured to allow a subsequently formed second initial signal connection line to be electrically connected to the second initial signal line Vinit2 through this via.

[0319] (110) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on the first planarization layer, such as... Figures 16a to 16b As shown, Figure 16a This is a planar structure diagram of a sub-pixel after the formation of the fifth conductive layer. Figure 16b for Figure 16a A planar schematic diagram of the fifth conductive layer. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0320] In an exemplary embodiment, the fifth conductive layer includes at least: a data signal line D, a first power supply line VDD, an anode connection electrode ZL, and a second initial signal connection line Vinit2L.

[0321] In an exemplary embodiment, the data signal line D is a zigzag or strip shape whose main body extends along the second direction Y. The data signal line D is connected to the fourth connection electrode L4 through the twenty-third via V23. Since the fourth connection electrode L4 is connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the via, the connection between the data signal line D and the first electrode of the fourth transistor T4 is realized, and the data signal is written to the fourth transistor T4.

[0322] In an exemplary embodiment, the first power line VDD is a zigzag or strip-shaped portion extending along the second direction Y. The first power line VDD is connected to the sixth connection electrode L6 through the twenty-fourth via V24. Since the sixth connection electrode L6 is connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 and the first plate C21 of the second capacitor C2 through the via, the connection between the first power line VDD and the first plate C21 of the fifth transistor T5 and the second capacitor C2 is realized, and the power signal is written into the first electrode of the fifth transistor T5 and the first plate C21 of the second capacitor C2.

[0323] In an exemplary embodiment, the anode connection electrode ZL can be in the shape of an "I" or a strip structure extending along the second direction Y. The anode connection electrode ZL can be connected to the second connection electrode L2 through the twenty-fifth via V25. Since the second connection electrode L2 is connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT22 of the active layer AT2 of the second transistor T2) through the via, the connection between the anode connection electrode ZL and the second electrode of the sixth transistor T6 and the second electrode of the second transistor T2 is realized.

[0324] In an exemplary embodiment, the second initial signal connection line Vinit2L can be a zigzag or strip shape extending along the second direction Y of the main body. The second initial signal connection line Vinit2L can be connected to the second initial signal line Vinit2 through the twenty-fifth via V25. Multiple second initial signal connection lines Vinit2L and multiple second initial signal lines Vinit2 are interconnected to form a grid structure, so that the second initial signals received by adjacent second transistors T2 are basically consistent, which is beneficial to improve the uniformity of panel display, avoid display defects of display substrate, and ensure the display effect of display substrate.

[0325] In an exemplary embodiment, within the same sub-pixel, the data signal line D, the second initial signal connection line Vinit2L, and the first power line VDD can be arranged sequentially along a first direction X. In the first direction X, the data signal line D and the first power line VDD can be located on opposite sides of the second initial signal connection line Vinit2L, and the anode connection electrode ZL can be located between the first power line VDD and the second initial signal connection line Vinit2L.

[0326] At this point, the driving circuit layer has been fabricated on the substrate. The driving circuit layer contains pixel driving circuits for multiple sub-pixels. Figures 8 to 16bThe diagram shows a planar structure of the pixel driving circuit for a sub-pixel in a display substrate. In an exemplary embodiment, the driving circuit layer may include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate in a direction perpendicular to the plane of the display substrate.

[0327] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, and a first planarization layer. The first insulating layer is disposed between the first semiconductor layer and the first conductive layer, the second insulating layer is disposed between the first conductive layer and the second conductive layer, the third insulating layer is disposed between the second conductive layer and the second semiconductor layer, the fourth insulating layer is disposed between the second semiconductor layer and the third conductive layer, the fifth insulating layer is disposed between the third conductive layer and the fourth conductive layer, and the sixth insulating layer and the first planarization layer are disposed between the fourth conductive layer and the fifth conductive layer.

[0328] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations: forming a second planarization layer pattern, wherein at least an anode via is provided on the second planarization layer; forming an anode pattern (i.e., an anode conductive layer), wherein the anode is connected to the anode connecting electrode through the anode via; forming an anode pixel definition layer, wherein a pixel opening is provided on the pixel definition layer, and the pixel opening exposes the anode; forming an organic light-emitting layer using a vapor deposition or inkjet printing process, wherein a cathode is formed on the organic light-emitting layer; and forming an encapsulation layer, wherein the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, wherein the first and third encapsulation layers may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0329] In an exemplary embodiment, the first conductive layer, second conductive layer, third conductive layer, fourth conductive layer, and fifth conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, and fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers.

[0330] In an exemplary embodiment, a sub-pixel in the display area (AA) consists of one sub-pixel row and one sub-pixel column, and the pixel driving circuit employs... Figure 5b Taking the 6T2C structure shown as an example, the fabrication process of the display substrate may include steps (101), (103) to (112) as described above. Figure 5b The fabrication process of the 6T2C pixel driving circuit shown did not include the first semiconductor layer and the first insulating layer, meaning step (102) was not performed. Figure 5b The fabrication process of the 6T2C pixel driving circuit shown differs from steps (101), (103) to (112) above as follows:

[0331] The first conductive layer formed in step (103) above can be as follows: Figure 17 As shown, Figure 17 This is a planar structure diagram of a sub-pixel after the formation of the first conductive layer. Figure 17 The first conductive layer shown is Figure 9b The difference in the first conductive layer shown is: Figure 17 In the first conductive layer shown, the first light-emitting control line EM1 is not provided, and the first electrode plate C21 of the second capacitor C2 is not provided with the second connection part CL2.

[0332] The second conductive layer formed in step (104) above can be as follows: Figure 18a and Figure 18b As shown, 18a is a planar structure diagram of a sub-pixel after the formation of the second conductive layer. Figure 18b for Figure 18a A schematic diagram of the planar structure of the second conductive layer. Figure 18b The second conductive layer shown is Figure 10b The difference in the second conductive layer shown is: Figure 18b In the second conductive layer shown, a second shielding line BL2 is provided, and an opening K11 is provided on the second electrode plate C22 of the second capacitor C2. The outline of the opening K11 is roughly rectangular, and the opening K11 exposes the surface of the first electrode plate C21 of the second capacitor C2. The shape of the second shielding line BL2 is roughly a strip or a broken line extending along the first direction X. In the same sub-pixel, the second shielding line BL2 can be located on the side of the second capacitor C2 away from the first capacitor C1.

[0333] The second semiconductor layer formed in step (105) above can be as follows: Figure 19a and Figure 19b As shown, 19a is a planar structure diagram of a sub-pixel after the formation of the second conductive layer. Figure 19b for Figure 19a A schematic diagram of the planar structure of the second semiconductor layer. Figure 19b The second semiconductor layer shown is Figure 11bThe difference in the second semiconductor layer shown is that: Figure 19b In the second semiconductor layer shown, an active layer AT5 of the fifth transistor T5 is provided. The active layer AT5 of the fifth transistor T5 can be in the shape of an "I" or a strip extending along the second direction Y. In the same sub-pixel, in the second direction Y, the active layer AT5 of the fifth transistor T5 can be located on the side of the active layer AT3 of the third transistor T3 away from the active layer AT6 of the sixth transistor T6. The first region AT51 of the active layer AT5 of the fifth transistor T5 can be set separately, and the second region AT52 of the active layer AT5 of the fifth transistor T5 can be used as the first region AT31 of the active layer AT3 of the third transistor T3.

[0334] The third conductive layer formed in step (106) above can be as follows: Figure 20a and Figure 20b As shown, 20a is a planar structure diagram of a sub-pixel after the formation of the third conductive layer. Figure 20b for Figure 20a A schematic diagram of the planar structure of the third conductive layer. Figure 20b The second conductive layer shown is Figure 10b The difference in the third conductive layer shown is: Figure 20b In the third conductive layer shown, a first light-emitting control line EM1 is provided. The shape of the first light-emitting control line EM1 is approximately a strip or a broken line extending along the first direction X. In the same sub-pixel, the first light-emitting control line EM1 can be located on the side of the second capacitor C2 away from the first capacitor C1. The orthographic projection of the first light-emitting control line EM1 on the substrate can at least partially overlap with the orthographic projection of the second occlusion line BL2 on the substrate. For example, the orthographic projection of the first light-emitting control line EM1 on the substrate can be located within the range of the orthographic projection of the second occlusion line BL2 on the substrate.

[0335] The fifth insulating layer formed in step (107) above can be as follows: Figure 21 As shown, Figure 21 The pattern of the fifth insulating layer shown is similar to Figure 13 The difference in the fifth insulating layer pattern shown is: Figure 21 In the fifth insulating layer pattern shown, the ninth via V9 and the twenty-second via V22 are not provided, which reduces the number of vias and thus reduces the occurrence of via defects. In the eighth via V8, the fifth and fourth insulating layers are etched away to expose the first region AT51 of the active layer AT5 of the fifth transistor T5. The thirteenth via V13 is located within the opening K11.

[0336] The fourth conductive layer formed in step (108) above can be as follows: Figure 22a and Figure 22b As shown, Figure 22a This is a planar structure diagram of a sub-pixel after the fourth conductive layer has been formed. Figure 22b for Figure 22a A planar schematic diagram of the fourth conductive layer. Figure 22b The pattern of the fourth conductive layer shown is similar to Figure 14b The difference in the pattern of the fourth conductive layer shown is: Figure 22b In the fourth conductive layer pattern shown, the seventh connecting electrode L7 is not provided, and a first power connection line VDDL is added. The sixth connecting electrode L6 is not electrically connected to the first region of the active layer AT5 of the fifth transistor T5. The first power connection line VDDL can be a strip or a broken line extending along the first direction X. The first power connection line VDDL can be connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 in the same row of sub-pixels through the eighth via V8 in the row of sub-pixels. In the second direction Y, in the same sub-pixel, the first power connection line VDDL can be located on the side of the fourth connecting electrode L4 and the sixth connecting electrode L6 away from the scan signal line Gate.

[0337] The fifth conductive layer formed in step (109) above can be as follows: Figure 23 As shown, Figure 23 To form a planar structure diagram of a sub-pixel after the first flattening layer, Figure 23 The patterns of the sixth insulating layer and the first planarization layer shown are consistent with... Figure 14b The difference between the patterns of the sixth insulating layer and the first planarization layer shown is as follows: Figure 23 In the pattern of the sixth insulating layer and the first planarization layer shown, a new twenty-seventh via V27 is added. The orthographic projection of the twenty-seventh via V27 on the substrate is within the range of the orthographic projection of the first power connection line VDDL on the substrate.

[0338] The patterns of the sixth insulating layer and the first planarization layer formed in step (110) above can be as follows: Figure 24a and 24b As shown, Figure 24a This is a planar structure diagram of a sub-pixel after the formation of the fifth conductive layer. Figure 24b for Figure 24a A schematic diagram of the planar structure of the fifth conductive layer. Figure 24a and 24b The fifth conductive layer shown is Figure 16a and Figure 16b The difference in the fifth conductive layer shown is: Figure 24a and 24b In the fifth conductive layer shown, the first power line VDD can be connected to the first power connection line VDDL through the twenty-seventh via V27. Multiple first power connection lines VDDL and multiple first power lines VDD are interconnected to form a grid structure, so that the signals received by adjacent sub-pixels from the first power line VDD are basically the same, which can reduce the voltage drop of the first power line VDD and improve the display uniformity of the display substrate.

[0339] In exemplary embodiments, the sub-pixel rows and sub-pixel columns described in this disclosure can be understood as the rows and columns of pixel driving circuits in a sub-pixel. The anode in a sub-pixel is connected to the pixel driving circuit in the corresponding sub-pixel, but the position of the anode of a sub-pixel does not necessarily correspond completely to the row and column of the pixel driving circuit it is connected to. For example, the orthographic projection of the anode AN3 of the third sub-pixel on the substrate may overlap with the orthographic projection of the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel on the substrate.

[0340] The structures and fabrication processes described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced as needed. The display substrates in this disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc. This disclosure does not limit them.

[0341] This disclosure also provides a display device, such as Figure 25 As shown, the display device may include the display substrate of any of the foregoing embodiments. The display device may be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0342] The display substrate and display device provided in the embodiments of this disclosure include a display substrate in which multiple transistors in the same pixel driving circuit include at least one first type transistor and at least one second type transistor. The first type transistor includes at least one of a top gate and a bottom gate, and the second type transistor includes a top gate and a bottom gate. By setting at least one transistor in the pixel driving circuit as a first type transistor, the bezel size of the display substrate can be reduced and the difficulty of narrowing the bezel can be reduced.

[0343] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0344] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0345] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit the scope of these embodiments. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, include: A substrate and a plurality of sub-pixels disposed on one side of the substrate, at least one sub-pixel including a pixel driving circuit, at least one pixel driving circuit including a plurality of transistors, the transistors including an active layer and at least one gate; In the same transistor, the at least one gate at least partially overlaps with the active layer, the at least one gate including at least one of a top gate and a bottom gate; in a direction perpendicular to the plane of the substrate, the bottom gate is located on the side of the active layer closer to the substrate, and the top gate is located on the side of the active layer away from the substrate; In the same pixel driving circuit, the plurality of transistors include at least one first type transistor and at least one second type transistor, wherein the first type transistor includes at least one of a top gate and a bottom gate, and the second type transistor includes a top gate and a bottom gate.

2. The display substrate according to claim 1, characterized in that, The plurality of transistors includes a third transistor as a driving transistor, a fifth transistor as a light-emitting control transistor, and a sixth transistor as a light-emitting control transistor. The first terminal of the third transistor is connected to the second terminal of the fifth transistor, and the second terminal of the third transistor is connected to the first terminal of the sixth transistor. The second type of transistor includes the third transistor.

3. The display substrate according to claim 2, characterized in that, The plurality of transistors further includes a first transistor as a reset transistor, a second transistor as a reset transistor, and a fourth transistor as a data write transistor, wherein one or more of the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are first type transistors; The second terminals of the first transistor and the fourth transistor are connected to the control terminal of the third transistor, and the second terminal of the second transistor is connected to the second terminal of the sixth transistor.

4. The display substrate according to claim 2, characterized in that, The pixel driving circuit also includes at least one capacitor, which includes a first plate and a second plate. In a direction perpendicular to the plane of the substrate, the display substrate includes: an active layer of a first type of transistor located on one side of the substrate, a top gate of a first type of transistor located on the side of the active layer of the first type of transistor away from the substrate, a bottom gate of a second type of transistor located on the side of the top gate of the first type of transistor away from the substrate, an active layer of a second type of transistor located on the side of the bottom gate of the second type of transistor away from the substrate, a top gate of a second type of transistor located on the side of the active layer of the second type of transistor away from the substrate, and a first electrode and a second electrode of a plurality of transistors located on the side of the top gate of the second type of transistor away from the substrate; The first plate of the capacitor is disposed on the same layer as the top gate of the first type of transistor, and the second plate of the capacitor is disposed on the same layer as the bottom gate of the second type of transistor.

5. The display substrate according to claim 4, characterized in that, The at least one capacitor includes a first capacitor and a second capacitor. The second type of transistor further includes a first transistor as a reset transistor, a second transistor as a reset transistor, and a fourth transistor as a data write transistor. The second terminal of the first transistor is connected to the first plate of the first capacitor. The second terminal of the second transistor is connected to the second terminal of the sixth transistor. The second terminal of the fourth transistor is connected to the first plate of the first capacitor and the top gate of the third transistor. The second terminal of the third transistor and the first terminal of the sixth transistor are connected to the second plate of the first capacitor and the second plate of the second capacitor. The first terminal of the fifth transistor is connected to the first plate of the second capacitor. In the same sub-pixel, the orthogonal projection of the second capacitor onto the substrate at least partially overlaps with the orthogonal projection of the third transistor onto the substrate. In a second direction, the first transistor and the fourth transistor are located on opposite sides of the third transistor, the fifth transistor is located on the side of the fourth transistor away from the third transistor, the sixth transistor is located on the side of the first transistor away from the third transistor, and the second transistor is located on the side of the sixth transistor away from the third transistor. At least a portion of the structure of the first capacitor is located between the third transistor and the sixth transistor. In a first direction, at least a portion of the structure of the first capacitor, the first transistor, and the fourth transistor are located on the same side of the second transistor, the third transistor, the fifth transistor, and the sixth transistor. In a plane parallel to the substrate, the first direction intersects the second direction.

6. The display substrate according to claim 5, characterized in that, It also includes a first reset control line, a second reset control line, and a scan signal line; the first reset control line, the second reset control line, and the scan signal line are disposed on the same layer as the first and second electrodes of the plurality of transistors; The first reset control line is connected to the top and bottom gates of the first transistor, the second reset control line is connected to the top and bottom gates of the second transistor, and the scan signal line is connected to the top and bottom gates of the fourth transistor; in the same sub-pixel, in the second direction, the first reset control line is located between the third transistor and the sixth transistor, the second reset control line is located on the side of the sixth transistor away from the third transistor, and the scan signal line is located between the third transistor and the fifth transistor.

7. The display substrate according to any one of claims 4 to 6, characterized in that, It also includes a first light-emitting control line and a second light-emitting control line. The first type of transistor includes the fifth transistor, and the second type of transistor also includes the sixth transistor. The region where the first light-emitting control line overlaps with the active layer of the fifth transistor serves as the top gate of the fifth transistor, and the region where the second light-emitting control line overlaps with the active layer of the sixth transistor serves as the top gate of the sixth transistor. The first light-emitting control line is disposed on the same layer as the top gate of the first type of transistor, and the second light-emitting control line is disposed on the same layer as the top gate of the second type of transistor; in the same sub-pixel, in the second direction, the first light-emitting control line and the fifth transistor are located on the same side of the third transistor, and the second light-emitting control line and the sixth transistor are located on the same side of the third transistor.

8. The display substrate according to claim 7, characterized in that, It also includes a first shielding line, which is disposed on the same layer as the bottom gate of the second type of transistor, and the orthographic projection of the first shielding line on the substrate at least partially overlaps with the orthographic projection of the second light-emitting control line on the substrate; The area where the first shielding line overlaps with the active layer of the sixth transistor serves as the bottom gate of the sixth transistor.

9. The display substrate according to any one of claims 2 to 6, characterized in that, The substrate includes a display area and a border area surrounding the display area. The plurality of sub-pixels are located in the display area. The border area located on at least one side of the display area is provided with a plurality of gate driving circuit groups. The plurality of gate driving circuits in the same gate driving circuit group are cascaded. The plurality of gate driving circuit groups include a first light-emitting gate driving circuit group and a second light-emitting gate driving circuit group. The plurality of sub-pixels form multiple rows. In at least one first light-emitting gate driving circuit in the first light-emitting gate driving circuit group, the same first light-emitting gate driving circuit is configured to be connected to the control electrode of the fifth transistor in at least two rows of sub-pixels. In at least one second light-emitting gate driving circuit in the second light-emitting gate driving circuit group, the same second light-emitting gate driving circuit is configured to be connected to the control electrode of the sixth transistor in at least two rows of sub-pixels.

10. The display substrate according to claim 9, characterized in that, The first light-emitting gate driving circuit of the nth level is configured to be connected to the control electrode of the fifth transistor in the sub-pixels of the (2n-1)th and (2n)th rows; the second light-emitting gate driving circuit of the nth level is configured to be connected to the control electrode of the sixth transistor in the sub-pixels of the (2n-1)th and (2n)th rows; where n is a positive integer greater than or equal to 1.

11. A display substrate, characterized in that, include: The display area and the border area surrounding the display area are provided. The display area is provided with a plurality of sub-pixels. At least one sub-pixel includes a pixel driving circuit. At least one pixel driving circuit includes a plurality of transistors. The border area located on at least one side of the display area is provided with a plurality of gate driving circuit groups. The plurality of gate driving circuits in the same gate driving circuit group are cascaded. In at least one of the plurality of gate driving circuit groups, the same gate driving circuit group is configured to be electrically connected to at least two transistors in the same pixel driving circuit.

12. The display substrate according to claim 11, characterized in that, The plurality of transistors includes a third transistor as a driving transistor, a first transistor as a reset transistor, a second transistor as a reset transistor, and a sixth transistor as a light-emitting control transistor; the second terminal of the first transistor is connected to the control terminal of the third transistor, the second terminal of the second transistor is connected to the second terminal of the sixth transistor, and the first terminal of the sixth transistor is connected to the second terminal of the third transistor. The control electrode of the first transistor and the control electrode of the second transistor are configured to be electrically connected to the same gate drive circuit group.

13. The display substrate according to claim 12, characterized in that, The plurality of gate driving circuit groups includes a second light-emitting gate driving circuit group, which is configured to be electrically connected to the control electrode of the first transistor, the control electrode of the second transistor, and the control electrode of the sixth transistor.

14. The display substrate according to claim 13, characterized in that, The plurality of sub-pixels form multiple rows. In the second light-emitting gate driving circuit group, the nth level second light-emitting gate driving circuit is connected to the control electrode of a plurality of first transistors in at least one row of sub-pixels, the (n+x)th level second light-emitting gate driving circuit is connected to the control electrode of a plurality of second transistors in the at least one row of sub-pixels, and the (n+y)th level second light-emitting gate driving circuit is connected to the control electrode of a plurality of sixth transistors in the at least one row of sub-pixels; wherein, n, x, and y are positive integers greater than or equal to 1, and y is greater than or equal to x.

15. The display substrate according to claim 14, characterized in that, The sixth transistor is a first type of transistor, and the first transistor, the second transistor, and the third transistor are second type of transistors; or, the first transistor and the second transistor are first type of transistors, and the third transistor and the sixth transistor are second type of transistors.

16. The display substrate according to claim 14, characterized in that, In the 2n-1 and 2n-1 row sub-pixels, the control electrodes of multiple first transistors are configured to be connected to the nth-level second light-emitting gate driving circuit, the control electrodes of multiple second transistors are configured to be connected to the n+x-level second light-emitting gate driving circuit, and the control electrodes of multiple sixth transistors are configured to be connected to the n+y-level second light-emitting gate driving circuit.

17. The display substrate according to claim 12, characterized in that, The plurality of gate drive circuit groups includes a first reset gate drive circuit group; The first reset gate drive circuit group is configured to be electrically connected to the control electrode of the first transistor and the control electrode of the second transistor.

18. The display substrate according to claim 17, characterized in that, The plurality of sub-pixels form multiple rows. In the first reset gate driving circuit group, the nth level first reset gate driving circuit is connected to the control electrode of a plurality of first transistors in at least one row of sub-pixels, and the n+bth level first reset gate driving circuit is connected to the control electrode of a plurality of second transistors in the at least one row of sub-pixels; wherein, n and b are positive integers greater than or equal to 1.

19. The display substrate according to claim 18, characterized in that, In the 2nth row of sub-pixels, the control electrodes of multiple first transistors are configured to be connected to the 2nth level first reset gate drive circuit, and the control electrodes of multiple second transistors are configured to be connected to the 2n+b level first reset gate drive circuit.

20. The display substrate according to any one of claims 12, 17 to 19, characterized in that, The plurality of gate driving circuit groups include a first light-emitting gate driving circuit group, and the plurality of transistors further include a fifth transistor as a light-emitting control transistor, wherein the second terminal of the fifth transistor is connected to the first terminal of the third transistor; The first light-emitting gate driving circuit group is configured to be electrically connected to the control electrode of the fifth transistor and the control electrode of the sixth transistor.

21. The display substrate according to claim 20, characterized in that, The multiple sub-pixels form multiple rows. In the first light-emitting gate driving circuit group, the nth level first light-emitting gate driving circuit is connected to the control electrode of multiple fifth transistors in at least one row of sub-pixels, and the (n+a)th level first light-emitting gate driving circuit is connected to the control electrode of multiple sixth transistors in the at least one row of sub-pixels; where n and a are positive integers greater than or equal to 1.

22. The display substrate according to claim 21, characterized in that, In the 2n-1 and 2n-a row sub-pixels, the control electrodes of multiple fifth transistors are configured to be connected to the nth-level first light-emitting gate driving circuit, and the control electrodes of multiple sixth transistors are configured to be connected to the n+a-level first light-emitting gate driving circuit.

23. The display substrate according to any one of claims 11 to 19, characterized in that, The plurality of sub-pixels form multiple rows, and in at least one of the plurality of gate driving circuit groups, the same gate driving circuit is configured to be electrically connected to at least two rows of sub-pixels.

24. The display substrate according to any one of claims 11 to 19, characterized in that, The frame area includes a third frame area and a fourth frame area. In a first direction, the third frame area and the fourth frame area are located on both sides of the display area. The plurality of gate driving circuit groups are located in the third frame area and the fourth frame area. The main body of the third frame area and the fourth frame area extends along a second direction. On a plane parallel to the display substrate, the first direction intersects with the second direction. In the frame region located on the same side of the display area in the first direction, multiple gate driving circuits are arranged along the extension direction of the frame region in the same gate driving circuit group.

25. A display device, characterized in that, It includes the display substrate as described in any one of claims 1 to 10, or the display substrate as described in any one of claims 11 to 24.

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