An MCTP implementation device, data transmission method, chip and control system

Abstract

The application provides an MCTP implementation device, which can be adapted to various PCIe controllers, and comprises an MCTP hardware module and an MCTP software module; the MCTP hardware module is connected with the PCIe controllers through an on-chip interconnection bus; the MCTP hardware module comprises a receiving path circuit and a sending path circuit; the MCTP software module is connected with the MCTP hardware module through a bus and an interrupt signal, and is used for performing protocol analysis and information screening. The MCTP implementation device has significantly reduced hardware complexity, greatly improved software flexibility and significantly enhanced compatibility. The application further discloses a data transmission method, a chip and a control system.

Description

Technical Field

[0001] This invention relates to the field of computer network communication technology, and in particular to an MCTP implementation device, data transmission method, chip, and control system. Background Technology

[0002] Management Component Transport Protocol (MCTP) is a media-independent transport layer protocol used for communication between intelligent devices within the platform management subsystem of a managed computer system. This protocol defines only the transport layer messages, independent of the physical and data link layers of the transport bus; that is, MCTP messages are encapsulated as data payloads within transport layer messages on other buses. Transmitting MCTP messages encapsulated in PCIe message packets (MCTP over PCIe) achieves faster transmission speeds and higher efficiency, and is therefore increasingly adopted by management controllers.

[0003] The Baseboard Management Controller (BMC), as an independent management processor in a computer system, is typically used for tasks such as monitoring and managing system hardware status, remote management, and control. It can perform firmware upgrades and monitor equipment even when the machine is powered off. In a computer system equipped with a BMC, the BMC communicates with the managed devices via physical channels such as out-of-band PCIe, undertaking the responsibility of monitoring the computer system hardware. The BMC can communicate with the hardware through the MCTP over PCIe path to obtain hardware information.

[0004] The existing MCTP over PCIe implementation solutions mainly include the following:

[0005] Mainstream MCTP solutions in the industry, such as Figure 1 As shown, in this architecture, the PCIe master controller and PCIe devices can be directly connected via the PCIe bus based on the Management Component Transport Protocol (MCTP); they can also be indirectly connected via PCIe bridges (such as PCIe switches or PCIe tri-mode controllers). Specifically, the PCIe master controller and the PCIe bridge are connected via PCIe_A (bus) based on the Management Component Transport Protocol (MCTP), and the PCIe bridge and the PCIe devices are connected via PCIe_B (bus) based on the Management Component Transport Protocol (MCTP).

[0006] The MCTP implementation is relatively straightforward and simple, and does not consume hardware resources. However, its drawback is that the MCTP implementation only reports link errors and other related information. The MCTP implementation is relatively specialized, and its hardware-software integration and flexibility are relatively low.

[0007] Chinese patent CN202211302999.6 discloses another solution, such as... Figure 2As shown, this solution can achieve more software and hardware interaction and obtain more firmware information, but MCTP functions are still largely carried out by hardware, and its flexibility is still insufficient.

[0008] Existing technology, Chinese patent CN202411011861.X, discloses another system architecture that includes MCTP, such as... Figure 3 As shown, this solution goes a step further in terms of hardware-software interaction, pre-setting more functions and related features. However, its drawbacks include the fact that the hardware implementation related to MCTP is largely reliant on the software, leading to increased logic complexity, hardware coding complexity, and system area. Furthermore, this implementation cannot support other Vendor define messages, resulting in insufficient system flexibility and versatility.

[0009] Therefore, the aforementioned existing technologies still have the following technical problems:

[0010] First, there is an imbalance in the division of responsibilities between hardware and software. In existing solutions, the hardware bears too much responsibility for protocol parsing and data processing. For example, in some existing solutions, the hardware needs to implement the complete MCTP protocol stack parsing, including identifying message types, extracting endpoint identifiers, and verifying message formats, resulting in complex hardware logic, large coding volume, and wasted chip area. Although some solutions adopt hardware-software co-design, the hardware is still responsible for packet reception and storage management, failing to achieve a fundamental restructuring of the boundaries of responsibilities.

[0011] Second, functional specialization leads to a lack of flexibility. Existing MCTP implementations are mostly customized for specific scenarios, only supporting standard MCTP messages and unable to handle vendor-defined messages (VDM). The reported information is fixed, and the scalability is limited. When new functions are needed, hardware design modifications are often required, resulting in long iteration cycles.

[0012] Third, protocol version compatibility is poor. The PCIe protocol has evolved from Gen1 to Gen6, with significant differences in maximum packet length, data bit width, and other parameters. For example, the maximum packet specifications differ between Gen3 and Gen6, and the AXI interface data bit width may also differ. Existing solutions lack parameterized design, requiring hardware redesign for each new version, resulting in poor design continuity. Summary of the Invention

[0013] To address the problems of high hardware complexity, poor flexibility, and weak compatibility in existing technologies, this invention provides an RDMA out-of-order reception and selective repeat method.

[0014] In a first aspect, the present invention provides an MCTP implementation device that is adaptable to a variety of PCIe controllers, including an MCTP hardware module and an MCTP software module. The MCTP hardware module is connected to a plurality of PCIe controllers via an on-chip interconnect bus. The MCTP hardware module includes a receiving path circuit and a transmitting path circuit. The MCTP software module is connected to the MCTP hardware module via a bus and an interrupt signal, and is used to perform protocol parsing and information filtering.

[0015] The receiving path circuit includes a format conversion unit, a message separation unit, a receiving buffer unit, and an interrupt triggering unit. The format conversion unit is connected to the on-chip interconnect bus and is used to perform endianness conversion and format rearrangement on the received message information. The message separation unit is connected to the format conversion unit and is used to separate the format-converted message into a message header (HDR) and a payload (PLD), wherein the HDR is fixed at 4 double-word DWs and the PLD is of variable length. The receiving buffer unit is connected to the message separation unit and is used to store the HDR and the PLD into corresponding HDR buffers and PLD buffers, respectively. The interrupt triggering unit is connected to the receiving buffer unit and is used to trigger an interrupt when the receiving buffer unit is not empty, notifying the MCTP software module to read the message.

[0016] The transmission path circuit includes a software interface unit, a transmission buffer unit, a message end detection unit, and a message transmission unit. The software interface unit is connected to the bus and is used to receive the HDR and PLD written by the MCTP software module through the bus. The transmission buffer unit is connected to the software interface unit and is used to buffer the HDR and PLD to be transmitted. The message end detection unit is connected to the transmission buffer unit and is used to determine the message end position according to the length information in the HDR. The message transmission unit is connected to the message end detection unit and is used to send the combined message to the target PCIe controller via the on-chip interconnect bus.

[0017] Specifically, the MCTP hardware module further includes a multicast control circuit connected to the transmission path circuit. This multicast control circuit supports sending the same message to multiple enabled PCIe controllers. The multicast control circuit includes a counting unit, a pointer control unit, and a message switching unit. The counting unit maintains a multicast counter, the value of which is the number of currently enabled PCIe controllers. The pointer control unit is connected to the counting unit and, when the transmission mode is multicast, repeatedly sends the same message multiple times, reverting the read pointer to the message start position after each transmission until the number of transmissions reaches the value of the multicast counter. The message switching unit is connected to the pointer control unit and switches to the next message after the number of transmissions reaches the value of the multicast counter.

[0018] Specifically, the MCTP hardware module further includes a flow control and discarding circuit. This circuit is located on the receiving path circuit side and connected to the format conversion unit. It is used to ensure that the on-chip interconnect bus is not blocked when the internal buffer is insufficient. The flow control and discarding circuit includes a first prefetch unit, a second prefetch unit, an alignment detection unit, a capacity judgment unit, and a discarding execution unit. The first prefetch unit is used to buffer HDR data from the AW channel; the second prefetch unit is used to buffer PLD data from the W channel; the alignment detection unit is connected to the first and second prefetch units and is used to start processing the current message when both the first and second prefetch units are not empty and the PLD of the previous message has been completely read; the capacity judgment unit is connected to the alignment detection unit and is used to determine whether the current message can be accommodated based on the length information in the message header and the remaining space in the internal buffer; the discarding execution unit is connected to the capacity judgment unit and is used to discard all data of the current message when the internal buffer is insufficient to accommodate it.

[0019] Specifically, the MCTP hardware module further includes a parameterized configuration circuit, which is connected to the receive path circuit and the transmit path circuit. This parameterized configuration circuit is used to adapt to the data bit width specifications and routing configurations of different PCIe systems, including a data bit width configuration unit and a routing address configuration unit. The data bit width configuration unit is used to adapt to the data bit width specifications of different PCIe systems through the AXI_DATA_WIDTH parameter. The routing address configuration unit is used to allocate a corresponding routing address to each PCIe controller through a configurable AWADDR register group. The routing address is used to implement routing in the on-chip interconnect bus.

[0020] Specifically, the MCTP hardware module further includes a VDM pass-through circuit, which is connected to the receiving path circuit and the sending path circuit to support the transmission of vendor-defined messages. The VDM pass-through circuit includes a message output unit and a no-data message processing unit. The message output unit is used to output all vendor-defined messages through the AXI Master interface. The no-data message processing unit is connected to the message output unit and is used to transmit vendor-defined messages without data payloads through a zero-byte write operation.

[0021] Specifically, the MCTP hardware module further includes the error detection circuit, which is connected to the receiving path circuit and the sending path circuit. This circuit detects and reports anomalies during message transmission. The MCTP hardware module also includes an error detection circuit comprising a protocol sequence detection unit, an enable state detection unit, a message length detection unit, an anomaly handling unit, an interrupt reporting unit, and an information reporting unit. The protocol sequence detection unit detects protocol sequence errors in received messages, including receiving HDR when PLD should be received, or receiving P when HDR should be received. LD; The enable status detection unit is used to detect whether the target PCIe controller for sending the message has been enabled; The message length detection unit is used to detect whether the length of the received message exceeds a preset threshold; The exception handling unit is connected to the protocol sequence detection unit, the enable status detection unit, and the message length detection unit, and is used to discard the current and subsequent messages when an exception is detected; The interrupt reporting unit is connected to the exception handling unit and is used to report the interrupt and the corresponding error code; The information reporting unit is connected to the enable status detection unit and is used to report the specific controller identifier that is not enabled for errors where the target controller is not enabled.

[0022] Secondly, the present invention also provides a data transmission method, comprising:

[0023] An MCTP hardware module is provided, which is connected to multiple PCIe controllers via an on-chip interconnect bus. The MCTP hardware module includes a receive path circuit and a transmit path circuit. The receive path circuit includes a format conversion unit, a message separation unit, a receive buffer unit, and an interrupt triggering unit. The transmit path circuit includes a software interface unit, a transmit buffer unit, a message end detection unit, and a message transmission unit.

[0024] The format conversion unit is provided to perform endianness conversion and format rearrangement on the received message information;

[0025] The message separation unit is provided to separate the format-converted message into a message header HDR and a payload PLD, wherein the HDR is fixed to 4 double-word DWs and the PLD is of variable length;

[0026] The receiving buffer unit is provided to store the HDR and the PLD into the corresponding HDR buffer and PLD buffer, respectively;

[0027] The interrupt triggering unit is provided to trigger an interrupt when the receive buffer unit is not empty, and notify the MCTP software module to read it;

[0028] An MCTP software module is provided, which responds to the interrupt, reads the HDR and PLD from the receive buffer unit, performs protocol parsing and information filtering on the read HDR and PLD, and writes the HDR and PLD to be sent to the software interface unit through the bus.

[0029] The software interface unit is provided to receive HDR and PLD data written by the MCTP software module via the bus;

[0030] The transmission buffer unit is provided to buffer the HDR and PLD to be transmitted;

[0031] The message end detection unit is provided to determine the message end position based on the length information in the HDR;

[0032] The message sending unit is provided to send the combined message to the target PCIe controller via the on-chip interconnect bus.

[0033] Specifically, the MCTP hardware module also includes a combination of one or more circuits such as a multicast control circuit, a flow control discarding circuit, a parameterized configuration circuit, a VDM pass-through circuit, and an error detection circuit.

[0034] The multicast control circuit is provided to maintain a multicast counter, the value of which is the number of currently enabled PCIe controllers. When the transmission mode is multicast, the same message is repeatedly transmitted multiple times, and after each transmission, the read pointer is backed to the beginning position of the message until the number of transmissions reaches the value of the multicast counter. When the number of transmissions reaches the value of the multicast counter, the system switches to the next message.

[0035] The flow control discarding circuit is provided to buffer HDR data from the AW channel and PLD data from the W channel, respectively. When both the HDR data and the PLD data are fully buffered and the PLD of the previous message has been completely read, the processing of the current message is started. Based on the length information in the message header and the remaining space in the internal buffer, it is determined whether the current message can be accommodated. When the internal buffer is insufficient to accommodate the current message, all data of the current message is discarded.

[0036] The parameterized configuration circuit is provided to adapt to the data bit width specifications of different PCIe systems through the AXI_DATA_WIDTH parameter, and to allocate a corresponding routing address to each PCIe controller through the configurable AWADDR register group. The routing address is used to implement routing in the on-chip interconnect bus.

[0037] The VDM pass-through circuit is provided to output all vendor-defined messages through the AXI Master interface. For vendor-defined messages without data payloads, they are transmitted through zero-byte write operations.

[0038] The error detection circuit is provided to detect protocol sequence errors in received messages, detect whether the target PCIe controller for sending messages has been enabled, detect whether the length of received messages exceeds a preset threshold, discard current and subsequent messages when an anomaly is detected, report the interrupt and the corresponding error code, and report the specific controller identifier that is not enabled for errors where the target controller is not enabled.

[0039] Thirdly, the present invention also provides a chip, including multiple PCIe controllers and an MCTP implementation device, wherein the MCTP implementation device is adapted to the multiple PCIe controllers; the MCTP implementation device includes an MCTP hardware module and an MCTP software module, wherein the MCTP hardware module is connected to the multiple PCIe controllers via an on-chip interconnect bus, and the MCTP hardware module includes a receive path circuit and a transmit path circuit; the MCTP software module is connected to the MCTP hardware module via a bus and an interrupt signal, and is used to perform protocol parsing and information filtering;

[0040] The receiving path circuit includes a format conversion unit, a message separation unit, a receiving buffer unit, and an interrupt triggering unit. The format conversion unit is connected to the on-chip interconnect bus and is used to perform endianness conversion and format rearrangement on the received message information. The message separation unit is connected to the format conversion unit and is used to separate the format-converted message into a message header (HDR) and a payload (PLD), wherein the HDR is fixed at 4 double-word DWs and the PLD is of variable length. The receiving buffer unit is connected to the message separation unit and is used to store the HDR and the PLD into corresponding HDR buffers and PLD buffers, respectively. The interrupt triggering unit is connected to the receiving buffer unit and is used to trigger an interrupt when the receiving buffer unit is not empty, notifying the MCTP software module to read the message.

[0041] The transmission path circuit includes a software interface unit, a transmission buffer unit, a message end detection unit, and a message transmission unit: the software interface unit is connected to the bus and is used to receive the HDR and PLD written by the MCTP software module through the bus; the transmission buffer unit is connected to the software interface unit and is used to buffer the HDR and PLD to be transmitted; the message end detection unit is connected to the transmission buffer unit and is used to determine the message end position according to the length information in the HDR; the message transmission unit is connected to the message end detection unit and is used to send the combined message to the target PCIe controller via the on-chip interconnect bus.

[0042] Fourthly, the present invention also provides a server management and control system, including a baseboard management controller, a chip, and multiple PCIe endpoint devices. The chip includes an MCTP implementation device and multiple PCIe controllers. The PCIe endpoint devices are connected to the PCIe controllers in the chip via a PCIe bus. The baseboard management controller communicates with the PCIe endpoint devices via the chip using MCTP messages. The MCTP implementation device includes an MCTP hardware module and an MCTP software module. The MCTP hardware module is connected to the multiple PCIe controllers via an on-chip interconnect bus. The MCTP hardware module includes a receive path circuit and a transmit path circuit. The MCTP software module is connected to the MCTP hardware module via a bus and an interrupt signal, and is used to perform protocol parsing and information filtering.

[0043] The receiving path circuit includes a format conversion unit, a message separation unit, a receiving buffer unit, and an interrupt triggering unit. The format conversion unit is connected to the on-chip interconnect bus and is used to perform endianness conversion and format rearrangement on the received message information. The message separation unit is connected to the format conversion unit and is used to separate the format-converted message into a message header (HDR) and a payload (PLD), wherein the HDR is fixed at 4 double-word DWs and the PLD is of variable length. The receiving buffer unit is connected to the message separation unit and is used to store the HDR and the PLD into corresponding HDR buffers and PLD buffers, respectively. The interrupt triggering unit is connected to the receiving buffer unit and is used to trigger an interrupt when the receiving buffer unit is not empty, notifying the MCTP software module to read the message.

[0044] The transmission path circuit includes a software interface unit, a transmission buffer unit, a message end detection unit, and a message transmission unit: the software interface unit is connected to the bus and is used to receive the HDR and PLD written by the MCTP software module through the bus; the transmission buffer unit is connected to the software interface unit and is used to buffer the HDR and PLD to be transmitted; the message end detection unit is connected to the transmission buffer unit and is used to determine the message end position according to the length information in the HDR; the message transmission unit is connected to the message end detection unit and is used to send the combined message to the target PCIe controller via the on-chip interconnect bus.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] 1. Significantly reduced hardware complexity. This invention restructures hardware and software responsibilities, with the MCTP hardware module only handling data format conversion, separate storage of HDR and PLD, and interrupt triggering, without undertaking any protocol parsing or information filtering functions. Compared to existing technologies that require complex protocol parsing state machines, this invention significantly simplifies hardware logic, reduces coding complexity, optimizes chip area, and effectively lowers R&D and manufacturing costs.

[0047] 2. Significantly enhanced software flexibility. Since the MCTP hardware module does not filter message content, all received HDR and PLD data is stored in a buffer for software retrieval. The MCTP software module can obtain all message information for flexible processing. Simultaneously, the software module supports parsing custom messages from any manufacturer, enabling functional expansion without hardware modifications, greatly improving system flexibility and scalability.

[0048] 3. Significantly enhanced compatibility. This invention uses parameterized configuration circuitry and the AXI_DATA_WIDTH parameter to adapt to the data bit width specifications of different PCIe systems. It assigns routing addresses to each PCIe controller through a configurable AWADDR register group. A single hardware design can simultaneously adapt to multiple PCIe versions such as Gen3 and Gen6, exhibiting excellent inheritability and scalability.

[0049] 4. High-efficiency multicast support. This invention utilizes a multicast control circuit, employing a multicast counter and pointer backoff mechanism to efficiently and repeatedly send the same message to all enabled PCIe controllers, avoiding the overhead of multiple software transmissions and improving broadcast communication efficiency.

[0050] 5. Comprehensive improvement in robustness. This invention incorporates an error detection circuit that can systematically detect various abnormal scenarios such as protocol sequence errors, target controller not being enabled, and excessively long messages. When an anomaly is detected, the erroneous message is promptly discarded and an interrupt and corresponding error code are reported. Combined with the flow control discarding circuit, it ensures that the bus is not blocked when the buffer is tight, effectively improving the stability and maintainability of the system. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0052] Figure 1 This is a schematic diagram of the framework structure of the mainstream MCTP solution in the industry in the existing technology;

[0053] Figure 2This is a schematic diagram of the connection structure of a system architecture that includes MCTP in the prior art;

[0054] Figure 3 This is a schematic diagram of the connection structure of another implementation of a system architecture that includes MCTP in the existing technology;

[0055] Figure 4 This is a connection diagram of the server management and control system provided in this application;

[0056] Figure 5 This is a schematic diagram of the modular structure connection in the chip provided in this application;

[0057] Figure 6 yes Figure 5 The block diagram of the MCTP implementation device shown is shown below;

[0058] Figure 7 This is a reference diagram of the message information format received and sent in the MCTP implementation device;

[0059] Figure 8 yes Figure 5 The diagram shows a structural block diagram of the MCTP hardware module in another embodiment of the MCTP implementation device shown.

[0060] Figure 9 yes Figure 8 The diagram shows the unit structure connection of the flow control discarding circuit. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0062] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0063] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0064] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0065] The terms “comprising” and “having,” and any variations thereof, are intended to cover but not exclude inclusion. For example, a product or device that includes a series of components is not necessarily limited to all components explicitly listed, but may include other components not explicitly listed or inherent to such product or device. The term “module” means any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0066] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0067] Please see Figure 4 and Figure 5 This invention provides a server management and control system, including a Baseboard Management Controller (BMC), a chip, and multiple PCIe endpoint devices. The chip includes an MCTP implementation device and multiple PCIe controllers. The MCTP implementation device includes an MCTP hardware module and an MCTP software module. The PCIe endpoint devices are connected to the PCIe controllers in the chip via a PCIe bus. The Baseboard Management Controller communicates with the PCIe endpoint devices via the chip using MCTP messages.

[0068] It should be noted that the PCIe controller can be different versions, such as Gen3 or Gen6, which are not limited here, and it is responsible for processing the PCIe protocol. PCIe endpoint devices can be network cards, NVMe hard drives, GPUs, RAID cards, etc., and are terminal devices on the PCIe bus. The baseboard management controller (BMC) communicates with the PCIe endpoint devices via MCTP messages through the chip. Specifically, the BMC, as the initiator of management messages, transmits signals with the chip through the management interface (PCIe / SMBus / MMBI, etc.), and encapsulates the MCTP message through the MCTP software module in the chip, sending it to the target PCIe endpoint device via the MCTP hardware module and the PCIe controller; the receiving direction is similar.

[0069] Please refer to the reference. Figure 5 , Figure 6 and Figure 7 The MCTP hardware module is connected to multiple PCIe controllers via an on-chip interconnect bus. The MCTP hardware module includes a receive path circuit and a transmit path circuit. The MCTP software module is connected to the MCTP hardware module via a bus and interrupt signals, and is used to perform protocol parsing and information filtering.

[0070] The receiving path circuit includes a format conversion unit, a message separation unit, a receive buffer unit, and an interrupt triggering unit. The format conversion unit is connected to the on-chip interconnect bus and is used to perform endianness conversion and format rearrangement on the received message information. The message separation unit is connected to the format conversion unit and is used to separate the format-converted message into a message header (HDR) and a payload (PLD), wherein the HDR is fixed at 4 double-word DWs, and the PLD is of variable length. The receive buffer unit is connected to the message separation unit and is used to store the HDR and PLD into corresponding HDR buffers and PLD buffers, respectively. The interrupt triggering unit is connected to the receive buffer unit and is used to trigger an interrupt when the receive buffer unit is not empty, notifying the MCTP software module to read the data.

[0071] The transmission path circuit includes a software interface unit, a transmission buffer unit, a message end detection unit, and a message transmission unit. The software interface unit is connected to the bus and is used to receive the HDR and PLD written by the MCTP software module through the bus. The transmission buffer unit is connected to the software interface unit and is used to buffer the HDR and PLD to be transmitted. The message end detection unit is connected to the transmission buffer unit and is used to determine the message end position based on the length information in the HDR. The message transmission unit is connected to the message end detection unit and is used to send the combined message to the target PCIe controller via the on-chip interconnect bus.

[0072] This application clarifies the boundaries of responsibilities between the MCTP implementation device by dividing it into an MCTP hardware module and an MCTP software module. The hardware module is only responsible for data format conversion and transmission, while the software module is responsible for protocol parsing and information filtering. This division of responsibilities significantly reduces hardware complexity and greatly improves software flexibility.

[0073] The receive path circuit is configured to process messages received from the PCIe controller, including a format conversion unit, a message separation unit, a receive buffer unit, and an interrupt triggering unit.

[0074] The format conversion unit is connected to the on-chip interconnect bus and is used to perform endianness conversion and format rearrangement on the received message information. In computer systems, different processor architectures may use different endianness formats, and the format conversion unit is responsible for converting the received data into a unified format used internally by the system. Format rearrangement, on the other hand, rearranges the data transmitted by NI-TOWER into a standard format according to the message format requirements of MCTPover PCIe.

[0075] The message separation unit is connected to the format conversion unit and is used to separate the format-converted message into a message header (HDR) and a payload (PLD). According to the MCTP over PCIe message format, the first 16 bytes (4 double-word DWs) constitute the message header (HDR), and the subsequent bytes constitute the payload (PLD). The message separation unit performs mechanical separation at a fixed length of 16 bytes, without considering the specific meaning of the message content.

[0076] The receive buffer unit is connected to the message separation unit and is used to store the HDR and PLD into their respective HDR buffers and PLD buffers. The HDR buffer capacity is fixed at 4 double-word DWs, while the PLD buffer capacity is configurable. The length field in the HDR indicates the corresponding number of PLD reads.

[0077] The interrupt triggering unit is connected to the receiving buffer unit and is used to trigger an interrupt when the receiving buffer unit is not empty, so as to notify the MCTP software module to read.

[0078] The receiving path circuit adopts an architecture that separates the storage of HDR and PLD, allowing the software module to process HDR and PLD independently, resulting in clearer processing logic. The hardware does not perform any parsing or filtering of the message content; all received HDR and PLD data is stored in a buffer for software to read. This design significantly reduces hardware complexity while providing the software with complete information for flexible processing.

[0079] The transmission path circuit is configured to process messages sent to the PCIe controller, including a software interface unit, a transmission buffer unit, a message end detection unit, and a message transmission unit.

[0080] The software interface unit is connected to the bus and is used to receive HDR and PLD data written by the MCTP software module through the bus. The software interface unit provides a register interface or a FIFO interface for the software module to write data to be transmitted.

[0081] The transmit buffer unit is connected to the software interface unit and is used to buffer the HDR and PLD to be transmitted. The transmit buffer unit adopts a variant FIFO structure and supports pointer backoff operation during multicast.

[0082] The message end detection unit is connected to the transmission buffer unit and is used to determine the message end position (EOP) based on the length information in the HDR. Specifically, the message end detection unit reads the length field from the HDR, calculates the message end position, and thus determines when a complete message transmission is finished.

[0083] The message sending unit is connected to the message end detection unit and is used to send the combined message to the target PCIe controller via the on-chip interconnect bus. The message sending unit combines HDR and PLD into a complete MCTP message and sends it to the designated PCIe controller via NI-TOWER.

[0084] The transmission path circuit does not perform protocol verification on the transmitted message content; it only determines the end position of the message based on the length information in the HDR before sending. This design simplifies the transmission path circuit structure and delegates the verification responsibility to the software module, maintaining consistency in the division of responsibilities between hardware and software.

[0085] Please see Figure 8 It should be noted that, in another embodiment, the MCTP hardware module further includes a combination of one or more circuits such as a multicast control circuit, a flow control dropping circuit, a parameterized configuration circuit, a VDM pass-through circuit, and an error detection circuit. In this embodiment, a combination of all circuits is preferred. All of the above circuits are optional enhancement components, and their quantity and type can be configured according to actual needs. The MCTP hardware module can be added as needed to enrich its functionality. Of course, the premise for adding settings is that the MCTP implementation device fully utilizes the advantages of hardware and software integration, optimizes the MCTP architecture, simplifies hardware implementation, and reduces the complexity and specialization of hardware implementation / coding, thereby enabling the expansion of more enhanced functions.

[0086] The MCTP hardware module may include a multicast control circuit connected to the transmission path circuit. This multicast control circuit supports sending the same message to multiple enabled PCIe controllers. The multicast control circuit includes a counting unit, a pointer control unit, and a message switching unit. The counting unit maintains a multicast counter, the value of which is the number of currently enabled PCIe controllers. The pointer control unit, connected to the counting unit, repeatedly sends the same message multiple times when the transmission mode is multicast. After each transmission, the read pointer is backed to the beginning of the message until the number of transmissions reaches the value of the multicast counter. The message switching unit, connected to the pointer control unit, switches to the next message after the number of transmissions reaches the value of the multicast counter. The MCTP implementation device, through the multicast control circuit, supports the efficient and repeated transmission of the same message to all enabled PCIe controllers. The multicast counter and pointer back-off mechanism ensure that each enabled controller receives the message, avoiding the overhead of multiple transmissions by the software module and improving broadcast communication efficiency.

[0087] The MCTP hardware module may further include a flow control and discarding circuit, which is located on the receiving path circuit side and connected to the format conversion unit. This circuit ensures that the on-chip interconnect bus is not blocked when the internal buffer is insufficient. The flow control and discarding circuit includes a first prefetch unit, a second prefetch unit, an alignment detection unit, a capacity determination unit, and a discarding execution unit. The first prefetch unit buffers HDR data from the AW channel, and the second prefetch unit buffers PLD data from the W channel. The alignment detection unit is connected to the first and second prefetch units and initiates processing of the current message when both units are not empty and the PLD of the previous message has been fully read. The capacity determination unit is connected to the alignment detection unit and determines whether the current message can be accommodated based on the length information in the message header and the remaining space in the internal buffer. The discarding execution unit is connected to the capacity determination unit and discards all data of the current message when the internal buffer is insufficient to accommodate it.

[0088] The flow-controlled drop circuit aligns the data in the AW and W channels by prefetching the FIFO, ensuring synchronized processing of HDR and PLD and avoiding state inconsistencies caused by partial writes. When the internal buffer is insufficient to hold the entire packet, the entire packet is discarded instead of being partially written, ensuring system stability and predictability. This circuit can be controlled by a software switch and is suitable for high-performance scenarios that allow for occasional packet loss.

[0089] Please refer to the following: Figure 9 The function of the flow control discard circuit will be further explained.

[0090] like Figure 9 As shown, two interface FIFOs are added to the flow control drop circuit: VMSG_HDR_INTF_PFIFO (prefetch FIFO) and VMSG_PLD_INTF_PFIFO. The main function of these two FIFOs is to align data from the AW Channel and W Channel. Data received from the AW and W channels is first written to VMSG_HD_INTF_PFIFO and VMSG_PLD_INTF_PFIFO respectively. Then, they are processed uniformly to avoid situations where one data arrives first and is written to the corresponding HDR_INNER FIFO / PLD_INNER FIFO (internal FIFO), while the corresponding INNER FIFO is full when the other arrives, leading to complex drop handling. The specific processing logic is as follows:

[0091] If VMSG_HDR_INTF_PFIFO is not empty, then check the state of VMSG_PLD_INTF_PFIFO. If VMSG_PLD_INTF_PFIFO is not empty, and the PLDs of the previous Message have already been read from VMSG_PLD_INTF_PFIFO, then start the process of reading the Head and Payload of a Message from the INTF_FIFO. When reading the Head, it is necessary to determine whether the two INNER_FIFOs can receive the Head and Payload of the current Message based on the length information in the Message Head and the remaining resources of the two INNER_FIFOs. If they can, all subsequent Head and Payloads should be written to the corresponding suffix INNER_FIFOs; otherwise, all Head and Payload data of this Message should be discarded.

[0092] Otherwise, either VMSG_PLD_INTF_PFIFO is empty, or the payload of the previous message has not yet been read from VMSG_PLD_INTF_PFIFO, continue to wait;

[0093] If VMSG_HDR_INTF_PFIFO is empty, it cannot be dequeued to the next level cache.

[0094] The MCTP hardware module may further include a parameterized configuration circuit, which is connected to the receiving path circuit and the transmitting path circuit to adapt to the data bit width specifications and routing configurations of different PCIe systems, including a data bit width configuration unit and a routing address configuration unit.

[0095] The data bit width configuration unit is used to adapt to the data bit width specifications of different PCIe systems through the AXI_DATA_WIDTH parameter. For example, the Gen3 system may use a smaller data bit width, while the Gen6 system uses a larger data bit width. By configuring the AXI_DATA_WIDTH parameter, one set of hardware code can be adapted to different versions.

[0096] The routing address configuration unit is used to assign a corresponding routing address to each PCIe controller through a configurable AWADDR register group. The routing address is used to implement routing in the on-chip interconnect bus.

[0097] The parameterized configuration circuitry gives the MCTP implementation device of this invention excellent compatibility and inheritability. Different PCIe versions are adapted through the AXI_DATA_WIDTH parameter, and multi-controller routing is supported through the configurable AWADDR register group. A single hardware design can be adapted to various PCIe systems from Gen1 to Gen6, greatly improving design reusability.

[0098] The MCTP hardware module may further include a VDM pass-through circuit, which is connected to the receiving path circuit and the transmitting path circuit to support the transmission of vendor-defined messages. The VDM pass-through circuit includes a message output unit and a no-data message processing unit. The message output unit is used to output all vendor-defined messages through the AXIMaster interface. The no-data message processing unit is connected to the message output unit and is used to transmit vendor-defined messages without data payloads through a zero-byte write operation.

[0099] The MCTP hardware module may further include the error detection circuit, which is connected to the receiving path circuit and the sending path circuit. This error detection circuit is used to detect and report anomalies during message transmission. The MCTP hardware module also includes an error detection circuit comprising a protocol sequence detection unit, an enable state detection unit, a message length detection unit, an anomaly handling unit, an interrupt reporting unit, and an information reporting unit. The protocol sequence detection unit is used to detect protocol sequence errors in received messages. Protocol sequence errors include receiving HDR when PLD should be received, or receiving PLD when HDR should be received. D; The enable status detection unit is used to detect whether the target PCIe controller for sending the message has been enabled; the message length detection unit is used to detect whether the length of the received message exceeds a preset threshold; the exception handling unit is connected to the protocol sequence detection unit, the enable status detection unit, and the message length detection unit, and is used to discard the current and subsequent messages when an exception is detected; the interrupt reporting unit is connected to the exception handling unit and is used to report the interrupt and the corresponding error code; the information reporting unit is connected to the enable status detection unit and is used to report the specific controller identifier that is not enabled for errors where the target controller is not enabled.

[0100] The data packets in the transmission path circuit are sent by software. If the data packets sent by the software contain errors in certain critical information, including but not limited to sending excessively long packets or sending packets destined for a disabled controller, unpredictable errors will occur. Therefore, to avoid this situation, the MCTP implementation device uses the following table to illustrate the correspondence between the error detection circuit in interrupt exception scenarios and the corresponding software and hardware processing actions:

[0101] Abnormal Scenario Description Software and hardware processing actions HDR was sent when PLD should have been sent, or PLD was sent when HDR should have been sent. 1. Hardware entry point is discarded, and subsequent packets are also discarded; 2. Hardware reports a fatal interrupt and the corresponding ERR_CODE ID, which correspond to ID0 and ID1 respectively; 3. Software obtains the information and initiates a soft reset; A packet indicating that the controller is not enabled was sent. 1. Hardware entry point is discarded, and subsequent packets are also discarded; 2. Hardware reports a fatal interrupt and its corresponding ERR_CODE ID; 3. Software acquires the information and initiates a soft reset; 4. When hardware reporting is required, it identifies which controller was disabled but sent a packet. An extra-long package was sent. 1. Hardware entry point is discarded, and subsequent packets are also discarded; 2. Hardware reports a fatal interrupt and its corresponding ERR_CODE ID; 3. Software obtains the information and initiates a soft reset; 4. Software needs to plan the packet length carefully. If it is necessary to send an excessively long packet, it needs to be split into multiple packets.

[0102] The error detection circuit systematically defines detection and handling mechanisms for various abnormal scenarios. When an anomaly is detected, error messages are promptly discarded to prevent error propagation; interrupts and detailed error codes are reported to facilitate rapid software problem localization; for errors where the target controller is not enabled, the specific controller identifier is also reported for easier debugging. Combined with the DFX counter, this significantly improves the system's robustness and maintainability.

[0103] In addition, this application also provides a data transmission method, including:

[0104] An MCTP hardware module is provided, which is connected to multiple PCIe controllers via an on-chip interconnect bus. The MCTP hardware module includes a receive path circuit and a transmit path circuit. The receive path circuit includes a format conversion unit, a message separation unit, a receive buffer unit, and an interrupt triggering unit. The transmit path circuit includes a software interface unit, a transmit buffer unit, a message end detection unit, and a message transmission unit.

[0105] The format conversion unit is provided to perform endianness conversion and format rearrangement on the received message information;

[0106] The message separation unit is provided to separate the format-converted message into a message header HDR and a payload PLD, wherein the HDR is fixed to 4 double-word DWs and the PLD is of variable length;

[0107] The receiving buffer unit is provided to store the HDR and the PLD into the corresponding HDR buffer and PLD buffer, respectively;

[0108] The interrupt triggering unit is provided to trigger an interrupt when the receive buffer unit is not empty, and notify the MCTP software module to read it;

[0109] An MCTP software module is provided, which responds to the interrupt, reads the HDR and PLD from the receive buffer unit, performs protocol parsing and information filtering on the read HDR and PLD, and writes the HDR and PLD to be sent to the software interface unit through the bus.

[0110] The software interface unit is provided to receive HDR and PLD data written by the MCTP software module via the bus;

[0111] The transmission buffer unit is provided to buffer the HDR and PLD to be transmitted;

[0112] The message end detection unit is provided to determine the message end position based on the length information in the HDR;

[0113] The message sending unit is provided to send the combined message to the target PCIe controller via the on-chip interconnect bus.

[0114] The data transmission method fully realizes the MCTP communication process with hardware and software collaboration. The hardware is only responsible for data format conversion and transmission, while the software is responsible for protocol parsing and information filtering, which reduces hardware complexity and ensures software flexibility.

[0115] The above description is merely an embodiment of the present invention. It should be noted that those skilled in the art can make improvements without departing from the inventive concept of the present invention, but these improvements all fall within the protection scope of the present invention.

Claims

1. An MCTP implementation device, adaptable to various PCIe controllers, characterized in that, include: An MCTP hardware module, wherein the MCTP hardware module is connected to multiple PCIe controllers via an on-chip interconnect bus, and the MCTP hardware module includes a receive path circuit and a transmit path circuit; and The MCTP software module is connected to the MCTP hardware module via a bus and interrupt signals, and is used to perform protocol parsing and information filtering. The receiving path circuit includes: The format conversion unit, connected to the on-chip interconnect bus, is used to perform endianness conversion and format rearrangement on the received message information; A message separation unit, connected to the format conversion unit, is used to separate the format-converted message into a message header HDR and a payload PLD, wherein the HDR is fixed to 4 double-word DWs and the PLD is of variable length. A receiving buffer unit, connected to the message separation unit, is used to store the HDR and the PLD into corresponding HDR buffers and PLD buffers, respectively; and An interrupt triggering unit, connected to the receiving buffer unit, is used to trigger an interrupt when the receiving buffer unit is not empty, so as to notify the MCTP software module to read. The transmission path circuit includes: A software interface unit, connected to the bus, is used to receive HDR and PLD written by the MCTP software module through the bus; A transmission buffer unit, connected to the software interface unit, is used to buffer the HDR and PLD to be transmitted; The message end detection unit, connected to the sending buffer unit, is used to determine the message end position based on the length information in the HDR; and The message sending unit, connected to the message end detection unit, is used to send the combined message to the target PCIe controller via the on-chip interconnect bus.

2. The MCTP implementation apparatus according to claim 1, characterized in that, The MCTP hardware module further includes a multicast control circuit, which is connected to the transmission path circuit and is used to support sending the same message to multiple enabled PCIe controllers. The multicast control circuit includes: A counting unit is used to maintain a multicast counter, the value of which is the number of currently enabled PCIe controllers; A pointer control unit, connected to the counting unit, is used to repeatedly send the same message multiple times when the sending mode is multicast. After each transmission, the read pointer is pushed back to the beginning position of the message until the number of transmissions reaches the value of the multicast counter. The message switching unit, connected to the pointer control unit, is used to switch to the next message when the number of transmissions reaches the value of the multicast counter.

3. The MCTP implementation apparatus according to claim 1, characterized in that, The MCTP hardware module further includes a flow control and discard circuit, which is located on the receiving path circuit side and connected to the format conversion unit. This circuit ensures that the on-chip interconnect bus is not blocked when the internal buffer is strained. The flow control and discard circuit includes: The first prefetch unit is used to buffer HDR data from the AW channel; The second prefetch unit is used to buffer PLD data from the W channel; An alignment detection unit, connected to the first prefetch unit and the second prefetch unit, is used to start processing the current message when both the first prefetch unit and the second prefetch unit are not empty and the PLD of the previous message has been completely read. A capacity determination unit, connected to the alignment detection unit, is used to determine whether the current message can be accommodated based on the length information in the message header and the remaining space in the internal buffer; and The discard execution unit, connected to the capacity judgment unit, is used to discard all data of the current message when the internal buffer is insufficient to hold the current message.

4. The MCTP implementation apparatus according to claim 1, characterized in that, The MCTP hardware module further includes a parameterized configuration circuit, which is connected to the receive path circuit and the transmit path circuit, and is used to adapt to the data bit width specifications and routing configurations of different PCIe systems, including: The data bit width configuration unit is used to adapt the data bit width specifications of different PCIe systems via the AXI_DATA_WIDTH parameter; and The routing address configuration unit is used to assign a corresponding routing address to each PCIe controller through a configurable AWADDR register group. The routing address is used to implement routing in the on-chip interconnect bus.

5. The MCTP implementation apparatus according to claim 1, characterized in that, The MCTP hardware module further includes a VDM pass-through circuit, which is connected to the receiving path circuit and the transmitting path circuit to support the transmission of vendor-defined messages. The VDM pass-through circuit includes: The message output unit is used to output all vendor-defined messages through the AXI Master interface; and A no-data message processing unit, connected to the message output unit, is used to transmit vendor-defined messages without data payloads via zero-byte write operations.

6. The MCTP implementation apparatus according to claim 1, characterized in that, The MCTP hardware module further includes an error detection circuit, which is connected to the receiving path circuit and the sending path circuit. This error detection circuit is used to detect and report anomalies during message transmission. The error detection circuit includes: A protocol sequence detection unit is used to detect protocol sequence errors in received messages, wherein the protocol sequence error includes receiving HDR when PLD should be received, or receiving PLD when HDR should be received; The enable status detection unit is used to detect whether the target PCIe controller for sending the message has been enabled. The message length detection unit is used to detect whether the length of the received message exceeds a preset threshold. An exception handling unit, connected to the protocol sequence detection unit, the enable state detection unit, and the message length detection unit, is used to discard the current and subsequent messages when an exception is detected. An interrupt reporting unit, connected to the exception handling unit, is used to report interrupts and their corresponding error codes; and The information reporting unit, connected to the enable status detection unit, is used to report the specific controller identifier that is not enabled when the target controller is not enabled.

7. A data transmission method, characterized in that, include: An MCTP hardware module is provided, which is connected to multiple PCIe controllers via an on-chip interconnect bus. The MCTP hardware module includes a receive path circuit and a transmit path circuit. The receive path circuit includes a format conversion unit, a message separation unit, a receive buffer unit, and an interrupt triggering unit. The transmit path circuit includes a software interface unit, a transmit buffer unit, a message end detection unit, and a message transmission unit. The format conversion unit is provided to perform endianness conversion and format rearrangement on the received message information; The message separation unit is provided to separate the format-converted message into a message header HDR and a payload PLD, wherein the HDR is fixed to 4 double-word DWs and the PLD is of variable length; The receiving buffer unit is provided to store the HDR and the PLD into the corresponding HDR buffer and PLD buffer, respectively; The interrupt triggering unit is provided to trigger an interrupt when the receive buffer unit is not empty, and notify the MCTP software module to read it; An MCTP software module is provided, which responds to the interrupt, reads the HDR and PLD from the receive buffer unit, performs protocol parsing and information filtering on the read HDR and PLD, and writes the HDR and PLD to be sent to the software interface unit through the bus. The software interface unit is provided to receive HDR and PLD data written by the MCTP software module via the bus; The transmission buffer unit is provided to buffer the HDR and PLD to be transmitted; The message end detection unit is provided to determine the message end position based on the length information in the HDR; The message sending unit is provided to send the combined message to the target PCIe controller via the on-chip interconnect bus.

8. The data transmission method according to claim 7, characterized in that, The MCTP hardware module also includes a combination of one or more circuits such as a multicast control circuit, a flow control discarding circuit, a parameterized configuration circuit, a VDM pass-through circuit, and an error detection circuit. The multicast control circuit is provided to maintain a multicast counter, the value of which is the number of currently enabled PCIe controllers. When the transmission mode is multicast, the same message is repeatedly transmitted multiple times, and after each transmission, the read pointer is pushed back to the beginning position of the message until the number of transmissions reaches the value of the multicast counter. When the number of transmissions reaches the value of the multicast counter, the system switches to the next message. The flow control discarding circuit is provided to buffer HDR data from the AW channel and PLD data from the W channel, respectively. When both the HDR data and the PLD data are fully buffered and the PLD of the previous message has been completely read, the processing of the current message is started. Based on the length information in the message header and the remaining space in the internal buffer, it is determined whether the current message can be accommodated. When the internal buffer is insufficient to accommodate the current message, all data of the current message is discarded. The parameterized configuration circuit is provided to adapt to the data bit width specifications of different PCIe systems through the AXI_DATA_WIDTH parameter, and to allocate a corresponding routing address to each PCIe controller through the configurable AWADDR register group. The routing address is used to implement routing in the on-chip interconnect bus. The VDM pass-through circuit is provided to output all vendor-defined messages through the AXI Master interface. For vendor-defined messages without data payload, they are transmitted through zero-byte write operations. and The error detection circuit is provided to detect protocol sequence errors in received messages, detect whether the target PCIe controller for sending messages has been enabled, detect whether the length of received messages exceeds a preset threshold, discard current and subsequent messages when an anomaly is detected, report the interrupt and the corresponding error code, and report the specific controller identifier that is not enabled for errors where the target controller is not enabled.

9. A chip, characterized in that, include: Multiple PCIe controllers; and The MCTP implementation apparatus according to any one of claims 1 to 6, wherein the MCTP implementation apparatus is adapted to a plurality of the PCIe controllers.

10. A server management and control system, characterized in that, include: Baseboard management controller; The chip as described in claim 9, wherein the chip includes an MCTP implementation device and a plurality of PCIe controllers; and Multiple PCIe endpoint devices, wherein the PCIe endpoint devices are connected to the PCIe controller in the chip via a PCIe bus; The baseboard management controller communicates with the PCIe endpoint device via MCTP messages through the chip.

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