Radio frequency front end module chip and preparation method thereof

Abstract

The application relates to the field of wireless communication technology and provides a radio frequency front end module chip and a preparation method thereof, the preparation method comprising the following steps: S1, providing a substrate, forming a plurality of substrate units on the substrate, and arranging the plurality of substrate units in an array; S2, connecting the circuit layer of each substrate unit to the ground layer of an adjacent substrate unit through a signal line; S3, performing chip packaging on the plurality of substrate units to obtain a packaged radio frequency front end module; S4, presetting a gap between two adjacent substrate units as a cutting channel, the signal line connecting the circuit layer and the ground layer of the two substrate units respectively passing through the cutting channel, the packaged radio frequency front end module being installed on a cutting platform in a vacuum adsorption mode, and the cutting channel between the two adjacent substrate units being sequentially cut off by a cutting blade of the cutting platform to realize the separation of single substrate units; and S5, obtaining a single-chip finished product. The application can improve the electrostatic protection and reliability of products.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a radio frequency front-end module chip and its fabrication method. Background Technology

[0002] As RF front-end module technology evolves towards advanced nodes, chip integration is continuously increasing, and device size is shrinking. This is especially true for RF chips, where the thickness of the internal gate oxide layer has been reduced to the nanometer level, significantly decreasing their tolerance to electrostatic discharge (ESD). ESD has become one of the main causes of RF chip failure. Industry research data shows that nearly 40% of integrated circuit failures originate from ESD / EOS (Electrical Over Stress) issues. RF chips, due to their inherent characteristics, are more sensitive to electrostatic shocks, resulting in a higher proportion of failures caused by ESD damage.

[0003] Electrostatic discharge (ESD) in chips originates from a wide range of sources, with the chip packaging process being a significant point of ESD introduction. During processes such as surface mounting, wire bonding / flip chip assembly, molding, ball bonding, substrate cutting and friction, charge accumulation due to the antenna effect of the metal layer, and charge transfer during robotic assembly, ESD can easily accumulate on and within the substrate, forming high-voltage ESD of several thousand volts. This ESD can be introduced into core sensitive circuits such as RF filters and power amplifiers through the connection structure between the substrate and the chip, causing irreversible damage such as gate oxide breakdown, PN junction burnout, metal interconnect meltdown, surface acoustic wave filter finger burnout, and bulk wave filter electrode damage. Ultimately, this can lead to abnormal chip function, performance degradation, or even complete failure.

[0004] Currently, radio frequency (RF) chips are widely used in consumer electronics, communication base stations, automotive RF modules, and other fields. Electrostatic discharge (ESD) protection under complex operating conditions has become a key indicator for measuring the reliability and core performance of RF chips. Therefore, suppressing ESD generation from the substrate preparation stage and improving the native ESD protection capability of RF chips are technical challenges that urgently need to be overcome in the field of RF front-end module manufacturing.

[0005] Currently, conventional electrostatic discharge (ESD) protection solutions in the industry mostly focus on the chip design stage (adding protective devices such as diodes, resistors, and power clamps to I / O ports) and the back-end packaging stage (using anti-static packaging materials and optimizing pin layout). There is insufficient reserve of ESD control technologies at the substrate fabrication stage, resulting in several inherent defects: First, the protection is not targeted enough to completely eliminate ESD problems at the source of packaging and substrate fabrication processes; second, traditional substrate fabrication processes themselves have potential ESD accumulation risks and are not adapted to ESD protection designs; third, existing protection solutions easily degrade the electrical performance of RF chips and have high production costs; fourth, latent ESD damage is difficult to predict, making it impossible to avoid the risk of latent chip failure in advance; and fifth, the technology has poor adaptability, the solution structure is simplistic, and it cannot meet the differentiated production needs of RF chips with different frequency bands, power levels, sizes, and materials, making it difficult to adapt to diverse fabrication scenarios in the industry.

[0006] In related technologies, such as Figure 1 The diagram illustrates a common manufacturing method for electrostatic discharge (ESD) protection measures in substrate fabrication. This method presents certain safety hazards. Multiple substrate chips 01 are included, each comprising a ground layer 011 and a circuit board layer 012. Each circuit board layer 012 is connected to the ground layer 011 of the substrate chip 01 via a metal wire 014, achieved by bending the metal wire 014. (The diagram shows a method for handling ESD protection measures in substrate fabrication.) Figure 1 The diagonal bars between two adjacent substrate chips 01 indicate the cutting path 013. This cutting path 013 is the cutting track along which the high-speed rotating blade moves during chip cutting, as set in the program. Because the cutting path 013 contains a significant amount of metal, the high-speed rotating blade experiences wear due to friction with the metal. Even with the more advanced laser cutting method, although it doesn't damage the equipment, metal shavings still fly during the cutting process, potentially damaging other equipment or chips, and causing issues such as cutting path 013 misalignment. Therefore, this easily leads to problems with poor electrostatic discharge protection and reliability during the current substrate chip 01 packaging and cutting process. Summary of the Invention

[0007] To address the shortcomings of the existing technologies, this invention proposes a method for fabricating radio frequency (RF) front-end module chips, which solves the problem of poor electrostatic discharge (ESD) protection performance and reliability during the packaging and cutting process of existing RF front-end module chips, thereby solving the problem of ESD loss during the packaging process and improving the ESD protection capability and reliability of the product.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0009] In a first aspect, embodiments of the present invention provide a method for fabricating a radio frequency (RF) front-end module chip, the method comprising the following steps: S1. A substrate is provided, on which a plurality of substrate units are formed and arranged in an array; wherein each substrate unit is used to form a chip, and the substrate unit includes a circuit layer and a ground layer; S2. Connect the circuit layer of each substrate unit to the ground layer of the adjacent substrate unit via signal lines; S3. The multiple substrate units are chip-packaged to obtain a packaged radio frequency front-end module assembly; S4. The gap between two adjacent substrate units is preset as a cutting channel. The signal lines connecting the circuit layer and the ground layer of the two substrate units pass through the cutting channel. The packaged RF front-end module is mounted on the cutting platform by vacuum adsorption. The cutting blade of the cutting platform cuts the cutting channel between the two adjacent substrate units in sequence to achieve the separation of a single substrate unit. S5. After completing the cutting and separation of all the substrate units, a single chip is obtained.

[0010] Preferably, in step S1, the signal line is a metal line and the ground layer is a copper layer.

[0011] Preferably, the packaging in step S3 specifically involves sequentially performing chip mounting, wire bonding, flip chip mounting, molding, and ball bonding on the substrate unit.

[0012] Preferably, the cutting blade cuts the edge of each substrate unit along a preset path.

[0013] Preferably, the substrate unit is rectangular, and each of the four sides of the circuit layer of the substrate unit is provided with a ground connection area, which is connected to the signal line.

[0014] Preferably, after step S5, the preparation method further includes sequentially performing cleaning, appearance inspection and electrical testing post-processing steps on the single chip product to finally obtain a qualified RF front-end module chip product.

[0015] Secondly, embodiments of the present invention provide a radio frequency front-end module chip, which is prepared by the above-described method for preparing a radio frequency front-end module chip.

[0016] Compared with related technologies, in the embodiments of the present invention, multiple substrate units are formed on a substrate and arranged in an array. Each substrate unit is used to form a chip. The substrate unit includes a circuit layer and a ground layer. The circuit layer of each substrate unit is connected to the ground layer of its adjacent substrate unit through signal lines. Multiple substrate units are packaged into a chip to obtain a packaged RF front-end module assembly. The gap between two adjacent substrate units is preset as a dicing channel. The signal lines connecting the circuit layer and ground layer of the two substrate units pass through the dicing channel. The packaged RF front-end module assembly is mounted on a dicing platform by vacuum adsorption. The dicing channel between two adjacent substrate units is cut sequentially by the dicing blades of the dicing platform to achieve the separation of a single substrate unit. After the dicing and separation of all substrate units is completed, a single chip product is obtained. This makes the packaging highly targeted and solves the problem of electrostatic damage to discrete devices caused by electrostatic discharge introduced during the packaging process of the RF module chip from the source. The number of metal wires entering the dicing channel is reduced, which facilitates cutting and has a high tolerance for cutting offset. In addition, the cross-section of the residual metal wires after cutting is reduced, which greatly improves the yield of the RF module chip. This improves the electrostatic protection capability and reliability of the product. Attached Figure Description

[0017] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 A schematic diagram of the structure of a radio frequency front-end module chip before cutting after packaging, provided for related technologies; Figure 2 A flowchart illustrating the fabrication method of the radio frequency front-end module chip provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the structure of the radio frequency front-end module chip before cutting after packaging, as provided in Embodiment 2 of the present invention; Figure 4 This is a schematic diagram of the structure of a single substrate unit after the radio frequency front-end module chip is cut according to Embodiment 2 of the present invention.

[0018] In the diagram, 200 is the RF front-end module chip, 1 is the substrate unit, 11 is the circuit layer, 12 is the ground layer, 2 is the cut track, and 3 is the signal line. Detailed Implementation

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0020] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example 1 Please see Figures 2-4 As shown, this embodiment of the invention provides a method for fabricating an RF front-end module chip, the method comprising the following steps: S1. A substrate is provided, on which multiple substrate units 1 are formed and arranged in an array. Each substrate unit 1 is used to form a chip, and the substrate unit 1 includes a circuit layer 11 and a ground layer 12. This substrate splicing wiring design and electrostatic discharge path construction effectively manages static electricity and reduces process damage. Circuit components are placed on the circuit layer 11, and the ground layer 12 is used for grounding and releasing static electricity. The array arrangement creates a stable conductive path for static electricity release in subsequent packaging and dicing stages, ensuring that static electricity can be quickly conducted to the ground layer 12. This significantly reduces the density and complexity of metal lines within the dicing kerf 2, reduces the amount of metal debris generated during dicing, and avoids physical damage to the internal circuitry of the chip and the dicing blade.

[0023] S2. Connect the circuit layer 11 of each substrate unit 1 to the ground layer 12 of the adjacent substrate unit 1 via signal lines 3. By connecting the signal lines 3 and the ground layer 12 on the substrate unit 1, the static electricity accumulated during the above operation can be transferred to the ground layer 12, thereby releasing the damage to the chip caused by the static electricity during the above process.

[0024] S3. Multiple substrate units 1 are chip-packaged to obtain a packaged RF front-end module assembly. This releases electrostatic charges generated during the packaging stage in advance, preventing electrostatic discharge from damaging sensitive discrete components inside the chip (such as RF components and analog circuits), and preventing device performance drift or permanent failure. The ground layer 12 connection structure of the substrate units 1 ensures a stable and reliable electrostatic discharge path with no risk of charge residue, improving device safety during the packaging process. At the same time, electrostatic discharge accumulated due to handling, mounting, bonding, and other operations is continuously transferred to the ground layer 12 and completely released through the conductive path of the pre-laid signal line 3 → adjacent ground layer 12.

[0025] S4. A pre-defined cleaving path 2 is established between two adjacent substrate units 1. Signal lines 3 connecting the circuit layer 11 and ground layer 12 of the two substrate units 1 pass through the cleaving path 2. The packaged RF front-end module assembly is mounted on the cutting platform via vacuum adsorption. The cutting blade of the cutting platform sequentially cuts the cleaving path 2 between two adjacent substrate units 1, achieving the separation of a single substrate unit 1. Throughout the packaging process, the neatly aligned signal line layout improves the cutting path accuracy and ensures the integrity of the chip unit edges. By firmly fixing the entire packaged substrate to the cutting platform of the cutting machine via vacuum adsorption, substrate displacement during cutting is prevented, ensuring cutting position accuracy. A high-speed rotating cutting blade moves along a pre-defined path (the edge of the substrate unit 1), sequentially cutting the signal lines 3 of the cleaving path 2 of two adjacent substrate units 1, achieving the physical separation of a single substrate unit 1. During the cutting process, the static electricity generated by the friction between the high-speed rotating blade and the substrate material is quickly conducted to the ground layer 12 of the adjacent substrate unit 1 through a briefly connected metal connection line, and the static charge is completely released into the ground layer 12.

[0026] Specifically, the signal line 3 of the substrate chip is connected to the ground layer 12 of the previous substrate, which allows for... Figure 2 As observed at cut track 2, compared to existing methods, there is significantly less metal in cut track 2, and it is also neatly aligned. This reduces damage to the chip and cutting tool during cutting, completely resolving the issue of electrostatic damage to discrete components during RF module chip packaging.

[0027] S5. After all the substrate units 1 are cut and separated, a single chip is obtained. The disconnected signal line 3 remains only in the waste area of ​​the cutting channel 2, without affecting the electrical function and signal integrity of the chip, thus obtaining a single chip.

[0028] Specifically, by providing a substrate, multiple substrate units 1 are formed on the substrate and arranged in an array; the circuit layer 11 of each substrate unit 1 is connected to the ground layer 12 of its adjacent substrate unit 1 via signal lines 3; the multiple substrate units 1 are chip packaged to obtain a packaged RF front-end module assembly; the gap between two adjacent substrate units 1 is preset as a cutting channel 2, and the signal lines 3 connecting the circuit layers 11 and ground layers 12 of the two substrate units 1 respectively pass through the cutting channel 2. The packaged RF front-end module assembly is mounted on a cutting platform by vacuum adsorption, and then sequentially cut by the cutting blade of the cutting platform. By cutting the cleaving channel 2 between two adjacent substrate units 1, the individual substrate unit 1 can be separated, reducing equipment safety hazards caused by metal sputtering. After all substrate units 1 are cut and separated, a single chip product is obtained. This allows for targeted packaging, addressing the electrostatic discharge (ESD) damage to discrete components (such as filters, RF switches, low-noise amplifiers, and power amplifiers) introduced during the packaging process of the RF module chip from the source. The number of metal interconnects entering the cleaving channel is reduced, facilitating cutting and increasing tolerance for cutting offset. In addition, the cross-sectional area of ​​the residual metal lines after cutting is reduced, greatly improving the yield of the RF module chip. This, in turn, improves the electrostatic discharge protection capability and reliability of the product.

[0029] In this embodiment, in step S1, the signal line 3 is a metal line, and the ground layer 12 is a copper layer. The metal signal line 3 has excellent conductivity, and the copper layer has low impedance and a large conductive area, enabling the construction of a low-resistance, high-speed electrostatic discharge channel. The electrostatic energy accumulated in each process of the substrate is quickly gathered to the ground layer 12 via the signal line 3, achieving charge orientation and rapid discharge. This results in low electrostatic conduction loss and high discharge efficiency, preventing charge accumulation in localized areas of the substrate, reducing the risk of high-voltage electrostatic discharge from the perspective of the pathway, and improving the overall electrostatic protection capability.

[0030] In this embodiment, the packaging in step S3 specifically involves sequentially performing die bonding, wire bonding, flip chip bonding, molding, and ball bonding on the substrate unit 1. This follows the heterogeneous integration process sequence of the RF module, first completing die bonding, then achieving high-density electrical interconnection between the chip and the substrate through wire bonding / flip chip bonding, followed by molding to protect internal precision components and interconnection structures, and finally ball bonding to form an external array of conductive terminals. Each process is designed to control secondary static electricity generated by friction, thermal processing, and mechanical contact, adapting to the requirements of multi-chip co-packaging in RF applications. This ensures the packaging process matches the integration characteristics of the RF module, reduces static electricity introduction and accumulation at each packaging stage, guarantees reliable chip electrical connections, protects the internal structure, and balances high-frequency RF performance with process anti-static capabilities.

[0031] In this embodiment, the high cutting sharpness and short cutting contact time of the blade in the high-speed range quickly cut the metal connection lines, significantly reducing the amount of secondary static electricity generated by friction between the blade and the substrate material. Simultaneously, the signal line 3 is quickly connected to the ground layer 12 discharge circuit, allowing the thousands of volts of static electricity accumulated in the substrate unit 1 to be instantly released through the ground layer 12. This suppresses the generation of static electricity during mounting and reflow soldering, accelerates the complete discharge of existing static electricity, avoids electrostatic discharge impacts on the RF sensitive core circuitry, effectively prevents gate oxide layer breakdown, PN junction burnout, and burnout of the surface acoustic wave filter fingers and damage to the bulk wave filter electrodes, significantly improving chip reliability.

[0032] In this embodiment, the cutting blade cuts the edge of each substrate unit 1 along a preset path. This limits the cutting path to the redundant cutting channel 2 area at the edge of the substrate unit 1, avoiding contact with the internal effective functional circuit layer 11 and the chip core area. The cutting stress and friction range are controllable, while reducing the generation of cutting dust. This avoids damage to the chip's functional structure caused by mechanical stress during cutting, reduces secondary frictional charging and surface contamination caused by cutting dust, ensures the integrity of each substrate unit 1 during segmentation, and improves process yield.

[0033] In this embodiment, the substrate unit 1 is rectangular, and each of the four sides of the circuit layer 11 of the substrate unit 1 is provided with a grounding connection area, which is connected to the signal line 3. The circular arrangement of grounding connection areas on the four sides of the rectangular substrate forms a multi-directional, symmetrical, global electrostatic discharge network. Charges accumulated at different locations on the substrate surface / interior and due to the antenna effect of the metal layer can be guided to the grounded copper layer through the surrounding signal line 3, eliminating dead zones in electrostatic discharge. This can evenly eliminate electrostatic accumulation in various areas of the substrate, suppress the collection of ionized charges by the antenna effect of the metal layer to form high-voltage electrostatic discharge, and comprehensively reduce the potential electrostatic hazards at the source of the substrate.

[0034] In this embodiment, after step S5, the preparation method further includes step S6: the single chip product is then sequentially subjected to cleaning, appearance inspection, and electrical testing post-processing steps to finally obtain a qualified RF front-end module chip product. The cleaning process removes cutting dust, residual impurities, and residual static charge on the surface; appearance inspection screens for physical defects such as cutting edge chipping, delamination, and structural damage; electrical testing verifies the RF circuit function, ESD tolerance parameters, and interconnect conductivity, accurately eliminating defective products with obvious / latent electrostatic damage; simultaneously, the layout of the cutting track 2 is optimized to reduce dust generation and tool wear from the source. The resulting chip is free of electrostatic damage, has a complete physical structure, and significantly improves device reliability; the optimized cutting track 2 layout reduces cutting dust and tool wear, extends the lifespan of the cutting blade, and improves production yield and efficiency.

[0035] Example 2 This invention provides an RF front-end module chip 200, which is fabricated using the aforementioned method. The technical effects of this RF front-end module chip are the same as those in Embodiment 1. This allows for targeted packaging, effectively addressing the electrostatic discharge (ESD) damage to discrete devices introduced during the packaging process. It also reduces material usage, saving costs and significantly improving the yield of the RF module chip. Ultimately, it enhances the product's ESD protection and reliability.

[0036] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A method for fabricating a radio frequency front-end module chip, characterized in that, The method for fabricating the radio frequency front-end module chip includes the following steps: S1. A substrate is provided, on which a plurality of substrate units are formed and arranged in an array; wherein each substrate unit is used to form a chip, and the substrate unit includes a circuit layer and a ground layer; S2. Connect the circuit layer of each substrate unit to the ground layer of the adjacent substrate unit via signal lines; S3. The multiple substrate units are chip-packaged to obtain a packaged radio frequency front-end module assembly; S4. The gap between two adjacent substrate units is preset as a cutting channel. The signal lines connecting the circuit layer and the ground layer of the two substrate units pass through the cutting channel. The packaged RF front-end module is mounted on the cutting platform by vacuum adsorption. The cutting blade of the cutting platform cuts the cutting channel between the two adjacent substrate units in sequence to achieve the separation of a single substrate unit. S5. After completing the cutting and separation of all the substrate units, a single chip is obtained.

2. The method for fabricating the radio frequency front-end module chip as described in claim 1, characterized in that, In step S1, the signal line is a metal line and the ground layer is a copper layer.

3. The method for fabricating the radio frequency front-end module chip as described in claim 1, characterized in that, The packaging process in step S3 specifically involves sequentially performing chip mounting, wire bonding, flip chip mounting, molding, and ball bonding on the substrate unit.

4. The method for fabricating the radio frequency front-end module chip as described in claim 1, characterized in that, The cutting blade cuts the edge of each substrate unit along a preset path.

5. The method for fabricating the radio frequency front-end module chip as described in claim 1, characterized in that, The substrate unit is rectangular, and each of the four sides of the circuit layer of the substrate unit is provided with a ground connection area, which is connected to the signal line.

6. The method for fabricating the radio frequency front-end module chip as described in claim 1, characterized in that, After step S5, the preparation method further includes sequentially performing cleaning, appearance inspection and electrical testing post-processing steps on the single chip product to finally obtain a qualified RF front-end module chip product.

7. A radio frequency front-end module chip, characterized in that, The radio frequency front-end module chip is prepared by the method described in any one of claims 1-6.

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