Register monitoring method, register monitoring device, register monitoring system, chip and chip module

Abstract

This application relates to a register monitoring method, apparatus, system, chip, and chip module. Applied to a register monitor located on a transmission port of an on-chip bus, the method includes: obtaining multiple access events of at least one target master device accessing a register from a cache queue of the on-chip bus; packaging the multiple access events according to a preset trace data structure to obtain a trace data stream; the trace data stream is used to monitor the register access behavior. This method enables register monitoring.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a register monitoring method, apparatus, register monitoring system, chip, and chip module. Background Technology

[0002] With the rapid development of mobile communication, artificial intelligence, and Internet of Things technologies, the functions of modern mobile phones and other electronic devices are becoming increasingly complex, and the number of integrated functional modules in their chips is also increasing. In such chips, multiple functional modules may access the same register resource.

[0003] However, when multiple functional modules access the same register resource, erroneous operations may occur, leading to serious problems such as data corruption and system crashes. Therefore, designing a mechanism to effectively monitor registers is crucial for improving chip reliability. Summary of the Invention

[0004] Therefore, it is necessary to provide a register monitoring method, device, system, chip, and chip module that can monitor registers to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a register monitoring method applied to a register monitor located on a transmission port of an on-chip bus. The method includes: obtaining multiple access events of at least one target master device accessing a register from a cache queue of the on-chip bus; packaging the multiple access events according to a preset trace data structure to obtain a trace data stream; and using the trace data stream to monitor register access behavior.

[0006] In one embodiment, the preset tracking data structure includes at least one data unit, which includes a header and a data section; the header is used to fill in the start identifier and global time base information of the data unit; the data section is used to fill in the data corresponding to multiple access events.

[0007] In one embodiment, the data unit includes multiple data packets corresponding one-to-one with multiple access events. The data packets include at least one of the following: on-chip bus type, channel set, timestamp, data packet type, address of the accessed register, empty slot, address of the target master device, etc.

[0008] In one embodiment, the method further includes: storing the trace data stream to a persistent storage area via a trace bus, so as to parse the trace data stream and find the access event that caused the chip abnormality when the chip where the register monitor is located is malfunctioning.

[0009] In one embodiment, when the register monitor is configured to monitor read behavior, the register monitor retrieves at least one multiple read events of a target master device accessing a register from the cache queue of the on-chip bus; when the register monitor is configured to monitor write behavior, the register monitor retrieves at least one multiple write events of a target master device accessing a register from the cache queue of the on-chip bus; and when the register monitor is configured to monitor read and write behavior, the register monitor retrieves at least one multiple read and write events of a target master device accessing a register from the cache queue of the on-chip bus.

[0010] In one embodiment, the target master control device includes at least one of the following:

[0011] The target master control device includes a master control device that accesses registers via the APB bus;

[0012] The target master control device includes a master control device that accesses registers via the AHB bus;

[0013] The target master control device includes a master control device that accesses registers via the AXI bus;

[0014] The target master control device includes the master control device that needs to be monitored.

[0015] Secondly, this application also provides a register monitoring device for use in a register monitor, the register monitor being located on a transmission port of an on-chip bus, the device comprising:

[0016] The acquisition module is used to acquire multiple access events of at least one target master device access register from the cache queue of the on-chip bus;

[0017] The packaging module is used to package multiple access events according to a preset tracking data structure to obtain a tracking data stream; the tracking data stream is used to monitor register access behavior.

[0018] In one embodiment, the preset tracking data structure includes at least one data unit, which includes a header and a data section; the header is used to fill in the start identifier and global time base information of the data unit; the data section is used to fill in the data corresponding to multiple access events.

[0019] In one embodiment, the data unit includes multiple data packets corresponding one-to-one with multiple access events. The data packets include at least one of the following: on-chip bus type, channel set, timestamp, data packet type, address of the accessed register, empty slot, address of the target master device, etc.

[0020] In one embodiment, the device further includes a storage module for storing the trace data stream to a persistent storage area via a trace bus, so as to parse the trace data stream and find the access event that caused the chip malfunction when the chip where the register monitor is located malfunctions.

[0021] In one embodiment, when the register monitor is configured to monitor read behavior, the register monitor retrieves at least one multiple read events of a target master device accessing a register from the cache queue of the on-chip bus; when the register monitor is configured to monitor write behavior, the register monitor retrieves at least one multiple write events of a target master device accessing a register from the cache queue of the on-chip bus; and when the register monitor is configured to monitor read and write behavior, the register monitor retrieves at least one multiple read and write events of a target master device accessing a register from the cache queue of the on-chip bus.

[0022] In one embodiment, the target master control device includes at least one of the following:

[0023] The target master control device includes a master control device that accesses registers via the APB bus;

[0024] The target master control device includes a master control device that accesses registers via the AHB bus;

[0025] The target master control device includes a master control device that accesses registers via the AXI bus;

[0026] The target master control device includes the master control device that needs to be monitored.

[0027] Thirdly, this application also provides a register monitoring system, which includes:

[0028] The on-chip bus is used to transmit multiple access events of multiple master devices accessing registers;

[0029] The on-chip bus cache queue is used to store multiple access events;

[0030] The register monitor is used to obtain multiple access events of at least one target master device accessing registers from the cache queue of the on-chip bus, and package the multiple access events according to a preset trace data structure to obtain a trace data stream; the trace data stream is used to monitor the register access behavior; wherein, the target master device is a device among multiple master devices.

[0031] In one embodiment, the register monitoring system further includes a trace bus, a cache queue for the trace bus, and a persistent storage area;

[0032] The register monitor is also used to transmit the trace data stream to the buffer queue of the trace bus;

[0033] The tracing bus is used to retrieve tracing data streams from the tracing bus's buffer queue, perform protocol conversion on the tracing data streams, and transmit the protocol-converted tracing data streams to the persistent storage area.

[0034] Persistent storage area is used to store the trace data stream after protocol conversion.

[0035] Fourthly, this application also provides a chip including a register monitor configured to cause the chip to perform the steps of the method described in any one of the first aspects above.

[0036] Fifthly, this application also provides a chip module, including a communication module, a power module, a storage module, and a chip, wherein:

[0037] The power module is used to provide power to the chip module;

[0038] The storage module is used to store data and instructions;

[0039] The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices.

[0040] The chip is used to perform the steps of the method described in any one of the first aspects above.

[0041] Sixthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any one of the first aspects above.

[0042] In a seventh aspect, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in any one of the first aspects above.

[0043] The aforementioned register monitoring method, device, system, chip, and chip module, with the register monitor located on the transmission port of the on-chip bus, obtains multiple access events of at least one target master device accessing registers from the cache queue of the on-chip bus, and then packages the multiple access events according to a preset trace data structure to obtain a trace data stream, thereby realizing the monitoring of register access behavior. Thus, when the chip where the register monitor is located malfunctions, parsing the trace data stream can reconstruct the access behavior of the registers, thereby finding the cause of the chip malfunction. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a flowchart illustrating a register monitoring method in one embodiment;

[0046] Figure 2 This is a schematic diagram of the register monitoring system in one embodiment;

[0047] Figure 3 This is a schematic diagram of a preset tracking data structure in one embodiment;

[0048] Figure 4 This is a structural block diagram of a register monitoring device in one embodiment;

[0049] Figure 5 This is an internal structure diagram of a chip module in one embodiment. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0051] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0052] With the rapid development of mobile communication, artificial intelligence, and the Internet of Things (IoT) technologies, the functions of modern mobile phones and other electronic devices are becoming increasingly complex, and the number of integrated functional modules in their chips is also increasing. These chips are called System-on-a-Chip (SoC). In such chips, multiple functional modules may access the same register resource. However, during this access, erroneous operations may occur, leading to data corruption, system crashes, and other serious problems. Currently, when a mobile phone freezes, methods such as logging and call stack analysis can only determine that the problem is due to abnormal register data, but cannot pinpoint when the abnormality occurred. Therefore, designing a mechanism to effectively monitor registers is crucial for improving chip reliability.

[0053] In one exemplary embodiment, such as Figure 1 As shown, a register monitoring method is provided, which is applied to a register monitor located on the transmission port of an on-chip bus. The register monitoring method includes steps 101 and 102. Wherein:

[0054] Step 101: Obtain at least one multiple access events of the target master device access register from the cache queue of the on-chip bus.

[0055] The on-chip bus can be an AMBA (Advanced Microcontroller Bus Architecture) bus, including at least one of the APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus), and AXI (Advanced eXtensible Interface) buses. In other words, the register monitor supports monitoring register access behavior via the AMBA bus.

[0056] The buffer queue can be an ASYNC FIFO (Asynchronous First-In First-Out) queue. Buffer queues are configured on the APB bus ports, AHB bus ports, and AXI bus ports. (See reference...) Figure 2 The register monitoring system shown.

[0057] A master control device refers to a functional module that accesses registers via the on-chip bus, such as a central processing unit, graphics processing unit, and display controller. It can be understood that there are multiple master control devices accessing registers via the on-chip bus, and the target master control device is one of these multiple master control devices.

[0058] In one possible implementation, the target master device includes at least one of the following: the target master device includes a master device that accesses registers via the APB bus; the target master device includes a master device that accesses registers via the AHB bus; the target master device includes a master device that accesses registers via the AXI bus; or the target master device includes a configured master device that needs to be monitored. In other words, the register monitor supports configuring the address of the master device and only monitors the access behavior of the configured target master device.

[0059] An access event is at least one of the following: the type of on-chip bus through which the target master device accesses the register, the specific channel of the on-chip bus through which it accesses the register, the time of access, the type of access event, the address of the accessed register, and the address of the target master device.

[0060] Access events include read events, write events, and read / write events. It's important to note that the register monitor also supports configuration to monitor read behavior, write behavior, or read / write behavior. For example, if the register monitor is configured to monitor read behavior, it retrieves multiple read events from the on-chip bus's cache queue indicating at least one target master device accessing a register; if configured to monitor write behavior, it retrieves multiple write events from the on-chip bus's cache queue indicating at least one target master device accessing a register; and if configured to monitor read / write behavior, it retrieves multiple read / write events from the on-chip bus's cache queue indicating at least one target master device accessing a register. In essence, read / write events include both read and write events.

[0061] Step 102: Package multiple access events according to the preset trace data structure to obtain a trace data stream; the trace data stream is used to monitor register access behavior.

[0062] The preset trace data structure is used to record access events. It can be understood that multiple access events are packaged according to the preset trace data structure. That is, for each access event, at least one of the following is filled into the corresponding position in the preset trace data structure: which type of on-chip bus the target master device used to access the register, which channel of the on-chip bus it used, the access time, the type of access event, the address of the accessed register, and the address of the target master device, thereby obtaining the trace data stream.

[0063] The aforementioned register monitoring method uses a register monitor located on the on-chip bus transmission port. By obtaining multiple access events of at least one target master device accessing a register from the on-chip bus cache queue, and then packaging these multiple access events according to a preset trace data structure to obtain a trace data stream, the method achieves monitoring of register access behavior. Thus, when the chip where the register monitor is located malfunctions, parsing the trace data stream can reconstruct the register access behavior, thereby identifying the cause of the chip malfunction.

[0064] In one exemplary embodiment, such as Figure 3 As shown, a preset tracking data structure is provided, which includes at least one data unit. The data unit includes a header and a package. The header is used to fill in the start identifier and global time base information of the data unit. The package is used to fill in the data corresponding to multiple access events.

[0065] The header includes a flag bit and a time bit. The flag bit can be 33 bits, and the time bit in the header can be 31 bits. The flag bit is used to fill in the starting identifier of the data unit, for example, it can be 33 ones. The time bit in the header is used to fill in global time base information, which can be a timestamp (TS).

[0066] The data section includes multiple data packets (pkg0, pkg1, pkg2, ...) that correspond one-to-one with multiple access events. Each data packet includes at least one of the following: bus type, channel set (Port_sel), timestamp (TS), data packet type (Pkg_type), address of the accessed register (address), available slot, and address (id) of the target master device.

[0067] The data section can be 32 bits; the on-chip bus type refers to the type of on-chip bus the target master device uses to access registers, and occupies 2 bits in the data section. Figure 3The timestamp in the data section is an offset time, occupying 8 bits. The timestamp in the data section is concatenated with the timestamp in the header to obtain the actual timestamp of the access event, thus reducing the data length in the data section. The data packet type refers to the type of access event (the type of behavior of the target master device accessing the register, including read, write, and read / write behavior), that is, the data packet type is read-only, write-only, or read / write package. The data packet type occupies 2 bits in the data section; for example, 00 represents read-only, 10 represents write-only, and 11 represents read / write. The address of the accessed register refers to the address of the register to be accessed by the target master device. Empty bits occupy 1 bit in the data section. Figure 3 The address of the target master device occupies 16 bits in the data section. It can be filled with 0s and can be used as an extension bit to record other data related to the access event.

[0068] The preset tracking data structure in this embodiment allows for a simple and clear recording of each access event.

[0069] In one embodiment, the method further includes: storing the trace data stream to a persistent storage area via a trace bus, so as to parse the trace data stream and find the access event that caused the chip abnormality when the chip where the register monitor is located is malfunctioning.

[0070] The trace bus can be an ATB bus (Advanced Trace Bus).

[0071] The persistent storage area is a non-power-loss storage space, which can be an ETB (Embedded Trace Buffer).

[0072] In one possible implementation, continue to refer to Figure 2 The register monitor sends the trace data stream to the trace bus's buffer queue. The trace bus retrieves the trace data stream from the trace bus's buffer queue, performs protocol conversion on the trace data stream, and transmits the protocol-converted trace data stream to the persistent storage area, where the persistent storage area stores the protocol-converted trace data stream.

[0073] In one possible scenario, the enable switches of IPs corresponding to multiple functional modules in the chip are stored in a register. When an enable switch is abnormally turned off, the illegal access behavior of the master control device that caused the abnormal turn off of the enable switch can be found by parsing and tracing the data stream. Furthermore, by tracing the timestamp in the header and the timestamp in the data section of the data stream, the specific time of this illegal access behavior can be obtained.

[0074] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0075] Based on the same inventive concept, this application also provides a register monitoring device for implementing the register monitoring method described above. This device can be applied to or integrated into a chip or chip module, for example. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more register monitoring device embodiments provided below can be found in the limitations of the register monitoring method described above, and will not be repeated here.

[0076] In one exemplary embodiment, such as Figure 4 As shown, a register monitoring device is provided, applied to a register monitor located on the transmission port of an on-chip bus. The register monitoring device 400 includes: an acquisition module 401 and a packetization module 402, wherein:

[0077] The acquisition module 401 is used to acquire multiple access events of at least one target master device access register from the cache queue of the on-chip bus;

[0078] Packaging module 402 is used to package multiple access events according to a preset tracking data structure to obtain a tracking data stream; the tracking data stream is used to monitor register access behavior.

[0079] In one embodiment, the preset tracking data structure includes at least one data unit, which includes a header and a data section; the header is used to fill in the start identifier and global time base information of the data unit; the data section is used to fill in the data corresponding to multiple access events.

[0080] In one embodiment, the data unit includes multiple data packets corresponding one-to-one with multiple access events. The data packets include at least one of the following: on-chip bus type, channel set, timestamp, data packet type, address of the accessed register, empty slot, address of the target master device, etc.

[0081] In one embodiment, the device further includes a storage module for storing the trace data stream to a persistent storage area via a trace bus, so as to parse the trace data stream and find the access event that caused the chip malfunction when the chip where the register monitor is located malfunctions.

[0082] In one embodiment, when the register monitor is configured to monitor read behavior, the register monitor retrieves at least one multiple read events of a target master device accessing a register from the cache queue of the on-chip bus; when the register monitor is configured to monitor write behavior, the register monitor retrieves at least one multiple write events of a target master device accessing a register from the cache queue of the on-chip bus; and when the register monitor is configured to monitor read and write behavior, the register monitor retrieves at least one multiple read and write events of a target master device accessing a register from the cache queue of the on-chip bus.

[0083] In one embodiment, the target master control device includes at least one of the following:

[0084] The target master control device includes a master control device that accesses registers via the APB bus;

[0085] The target master control device includes a master control device that accesses registers via the AHB bus;

[0086] The target master control device includes a master control device that accesses registers via the AXI bus;

[0087] The target master control device includes the master control device that needs to be monitored.

[0088] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0089] Based on the same inventive concept, this application also provides a register monitoring system for implementing the register monitoring method described above. This register monitoring system can be applied to or integrated into a chip or chip module, for example. The solution provided by this register monitoring system is similar to the implementation scheme described in the above method; therefore, the specific limitations of one or more register monitoring system embodiments provided below can be found in the limitations of the register monitoring method above, and will not be repeated here.

[0090] In one exemplary embodiment, reference is made to Figure 2 As shown, the register monitoring system includes: an on-chip bus for transmitting multiple access events from multiple master devices accessing registers;

[0091] The on-chip bus cache queue is used to store multiple access events;

[0092] The register monitor is used to obtain multiple access events of at least one target master device accessing registers from the cache queue of the on-chip bus, and package the multiple access events according to a preset trace data structure to obtain a trace data stream; the trace data stream is used to monitor the register access behavior; wherein, the target master device is a device among multiple master devices.

[0093] In one embodiment, continue to refer to Figure 2 As shown, the register monitoring system also includes a trace bus, a cache queue for the trace bus, and a persistent storage area;

[0094] The register monitor is also used to transmit the trace data stream to the buffer queue of the trace bus;

[0095] The tracing bus is used to retrieve tracing data streams from the tracing bus's buffer queue, perform protocol conversion on the tracing data streams, and transmit the protocol-converted tracing data streams to the persistent storage area.

[0096] Persistent storage area is used to store the trace data stream after protocol conversion.

[0097] Based on the same inventive concept, this application also provides a chip, including a register monitor and a communication interface; the communication interface is used to receive or send data; the register monitor is configured to cause the chip to perform the steps of the method described in the above method embodiments.

[0098] It is understood that the chip involved in the embodiments of this application may be a field-programmable gate array (FPGA), may be an application-specific integrated circuit (ASIC), may be a system on chip (SoC), may be a central processor unit (CPU), may be a network processor (NP), may be a digital signal processor (DSP), may be a microcontroller unit (MCU), may be a programmable logic device (PLD), or other integrated chips, etc.

[0099] Based on the same inventive concept, this application also provides a chip module, such as... Figure 5 As shown, the chip module includes a communication module, a power module, a storage module, and a chip. Among them:

[0100] The power module is used to provide power to the chip module; the storage module is used to store data and instructions; the communication module is used for internal communication within the chip module, or for communication between the chip module and external devices; this chip corresponds to the chip in the above chip embodiment.

[0101] The implementation method of this chip module can be found in the relevant content of the above chip embodiment, and will not be repeated here.

[0102] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the above method embodiment.

[0103] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method described in the above method embodiments.

[0104] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0106] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A register monitoring method, characterized in that, Applied to a register monitor located on a transmission port of an on-chip bus, the method includes: Obtain at least one multiple access events of the target master device access register from the cache queue of the on-chip bus; The multiple access events are packaged according to a preset tracking data structure to obtain a tracking data stream; the tracking data stream is used to monitor the register access behavior.

2. The method according to claim 1, characterized in that, The preset tracking data structure includes at least one data unit, and the data unit includes a header and a data section; The header is used to fill in the start identifier and global time base information of the data unit; The data section is used to populate the data corresponding to the multiple access events.

3. The method according to claim 2, characterized in that, The data unit includes multiple data packets corresponding one-to-one with the multiple access events. Each data packet includes at least one of the following: the type of the on-chip bus, the channel set, the timestamp, the data packet type, the address of the accessed register, the available slot, and the address of the target master device.

4. The method according to any one of claims 1-3, characterized in that, The method further includes: The trace data stream is stored in the persistent storage area via the trace bus so that when the chip where the register monitor is located malfunctions, the trace data stream can be parsed and the access event that caused the chip malfunction can be found.

5. The method according to claim 1, characterized in that, When the register monitor is configured to monitor read behavior, the register monitor retrieves multiple read events from the cache queue of the on-chip bus indicating that at least one target master device accesses a register. When the register monitor is configured to monitor write behavior, the register monitor retrieves multiple write events of at least one target master device accessing the register from the cache queue of the on-chip bus. When the register monitor is configured to monitor read and write behavior, the register monitor retrieves multiple read and write events of at least one target master device accessing the register from the cache queue of the on-chip bus.

6. The method according to claim 1, characterized in that, The target master control device includes at least one of the following: The target master control device includes a master control device that accesses the registers via the APB bus; The target master control device includes a master control device that accesses the registers via the AHB bus; The target master control device includes a master control device that accesses the registers via the AXI bus; The target master control device includes the master control device that needs to be monitored.

7. A register monitoring system, characterized in that, The register monitoring system includes: The on-chip bus is used to transmit multiple access events of multiple master devices accessing registers; The on-chip bus cache queue is used to store multiple access events; A register monitor is used to obtain multiple access events of at least one target master device accessing a register from the cache queue of the on-chip bus, and to package the multiple access events according to a preset trace data structure to obtain a trace data stream; the trace data stream is used to monitor the register access behavior; wherein, the target master device is one of the multiple master devices.

8. The register monitoring system according to claim 7, characterized in that, The register monitoring system also includes a trace bus, a cache queue for the trace bus, and a persistent storage area; The register monitor is also used to transmit the trace data stream to the buffer queue of the trace bus; The tracing bus is used to obtain the tracing data stream from the tracing bus's cache queue, perform protocol conversion on the tracing data stream, and transmit the protocol-converted tracing data stream to the persistent storage area. The persistent storage area is used to store the tracking data stream after the protocol conversion.

9. A chip, characterized in that, Includes a register monitor configured to cause the chip to perform the steps of the method described in any one of claims 1 to 6.

10. A chip module, characterized in that, This includes communication modules, power modules, storage modules, and chips, among which: The power module is used to provide power to the chip module; The storage module is used to store data and instructions; The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices. The chip is used to perform the steps of the method according to any one of claims 1 to 6.

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