Wide-narrow integrated low sidelobe multi-mode beam control system and method
By implementing a hierarchical control system and ping-pong storage management, the complexity and storage difficulties of multi-frequency and multi-bandwidth switching in the space-based radar beam control system have been solved, achieving efficient and flexible beam control and supporting high-precision, wide-range space-based radar applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING RES INST OF ELECTRONICS TECH
- Filing Date
- 2026-05-14
- Publication Date
- 2026-06-12
AI Technical Summary
Existing space-based radar beam control systems, under limited computing and storage resources, struggle to achieve flexible and rapid switching between multiple frequencies, bandwidths, and beamforming weights, resulting in high control complexity, stringent time delay accuracy requirements, and limited storage space.
By adopting a hierarchical control system and a ping-pong storage management strategy, and through the coordinated work of the scheduling module, the monitoring and timing module, and the beam control sub-module, combined with the three-level compensation of the phase shifters of the large position delay line, the small position delay line, and the T/R channel, and utilizing a two-layer FLASH+BRAM storage architecture, the flexibility of beam control and the improvement of storage efficiency are achieved.
It achieves efficient task scheduling and precise low-level execution, solves the problem of precise phase control under different bandwidths, ensures the system's orderly real-time response capability and flexibility, and supports high-precision, wide-range multi-mode space-based radar beam control.
Smart Images
Figure CN122204152A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of spaceborne microwave radar technology, and more specifically, to a wide and narrow integrated low sidelobe multimode beam control system and method. Background Technology
[0002] In space-based radar systems, the beam pointing control performance of phased array antennas is crucial, relying on the high-precision coordinated operation of the entire beam control architecture. As space-based radar evolves towards multi-mode integration, more stringent requirements are placed on the frequency adaptability, bandwidth adaptability, and flexibility of beamforming weighting forms of the beam control system.
[0003] Currently, under the limited computing and storage resources of beam control systems, achieving flexible and rapid switching between multiple frequencies, bandwidths, and beamforming weights has become one of the key bottlenecks restricting the application potential of space-based radar in high-precision, wide-area coverage fields. Traditional space-based radar beam control generally suffers from a series of technical challenges, including high control complexity, significant differences in beam control under different frequency / bandwidth / sidelobe requirements, strict requirements for time delay accuracy, and limited storage space in the beam control system. Therefore, an innovative solution is urgently needed to overcome these difficulties and achieve more efficient and flexible space-based radar beam control. Summary of the Invention
[0004] This invention aims to optimize the beam control architecture and storage management strategy, thereby effectively solving the problems of high latency requirements and limited storage space. A further objective is to leverage the architecture's integrated compatibility with both wide and narrow beams and its multi-mode support capabilities to significantly improve the flexibility and storage efficiency of the beam control system, ultimately providing key technical support for achieving high-precision, wide-range space-based radar beam control.
[0005] To achieve the above objectives, this invention proposes a wide-band and narrow-band integrated low-sidelobe multi-mode beam control system and method. The beam control system is designed as a hierarchical integrated control system, with scheduling software performing top-level control, monitoring timing for frame-by-frame control, and beam control modules for distribution control. To address the magnitude of the wide-band and narrow-band phase compensation, a three-stage compensation system is designed, consisting of a large-position delay line, a small-position delay line, and a phase shifter for the T / R channel. Furthermore, to address the issue of large beam control code data volume, a ping-pong storage method is designed in the BRAM to enable agile switching between different frequency points, solving the problem of large beam control code data volume and difficult BRAM storage. The specific technical solutions adopted are as follows:
[0006] A wide-narrow integrated low-sidelobe multi-mode beam control system includes:
[0007] The scheduling module serves as the top-level control unit, the monitoring and timing module serves as the intermediate control layer, and the wave control sub-module serves as the bottom-level execution unit.
[0008] The scheduling module integrates information interaction, task pre-scheduling and parameter calculation. It first receives the working instructions of the radar payload, and plans the subsequent task sequence based on these instructions. At the same time, it calculates the various working parameters required to execute the tasks.
[0009] The monitoring timing module serves as the timing reference for the radar system and is responsible for coordinating the operation of the entire system. It receives scheduling instructions and generates various timing pulses and operating instructions based on the system clock provided by the integrated radio frequency, and distributes them to each sub-unit to ensure that all units operate in strict accordance with the preset timing sequence.
[0010] The beam control sub-module adopts a centralized three-level architecture, consisting of a computation and distribution module, a beam control unit, and a component controller. The computation and distribution module serves as the control core, completing beam calculation and command generation; the beam control unit acts as a relay, serially distributing commands to the active subarrays; and the component controller acts as the execution terminal, completing the final control of the T / R components.
[0011] As a preferred structure of the present invention, the scheduling module is composed of an FPGA chip and a DDR memory; the monitoring and timing module is composed of a FLASH memory and an FPGA; the scheduling module, the monitoring and timing module, and the operation and distribution module are located inside the cabin, and the beam control unit and the component controller are located on the active subarray of the antenna array; the beam control unit is composed of an ASIC interface chip, and the component controller is located between the radar antenna and the beam control unit.
[0012] In a preferred embodiment of the present invention, the computation and distribution module is connected to the wave control unit via an RS422 differential line to transmit control information; the wave control unit is connected to the component controller via a digital integrated circuit to transmit wave control information.
[0013] As a preferred structure of the present invention, the component controller includes a subarray-level large-position delay, a T / R component-level small-position delay, and a T / R channel-level phase shifter.
[0014] The present invention also employs a beam control method based on the above system, comprising:
[0015] The scheduling module receives instructions and completes task planning and parameter calculation.
[0016] The timing module generates the overall timing sequence and distributes the instructions containing the beam control parameters to the beam control sub-module.
[0017] The beam control module adopts a centralized three-level architecture to issue commands step by step. Finally, the component controller completes the control of the large position delay, small position delay and phase shifter to achieve beamforming.
[0018] As a preferred method of the present invention, when the beam control module performs the delay, it calculates the subarray-level large position delay and the component-level small position delay based on the signal bandwidth, antenna array length and scanning angle, and calculates the phase difference of the phase shifter at the T / R channel level based on the operating frequency, array element spacing and scanning angle.
[0019] As a preferred method of the present invention, the calculation method for the subarray-level large-bit delay and the component-level small-bit delay is as follows:
[0020] ;
[0021] Where B is the signal bandwidth, k is a coefficient, and L is the antenna array length. Let be the scanning angle, and c be the speed of light.
[0022] As a preferred method of the present invention, the method for calculating the phase difference of the phase shifter in the T / R channel stage is as follows:
[0023] ;
[0024] in The phase difference between adjacent array elements. λ is the wavelength, and d is the spacing between array elements. The scanning angle.
[0025] As a preferred method of the present invention, when storing and switching wave control codes, multiple bandwidths of wave control codes with weak frequency dependence are stored together in one group, or compressed into one-dimensional codes for storage; before frequency switching, the wave control parameters of the next frequency point are preloaded from FLASH to the free partition of BRAM through a ping-pong operation to achieve fast switching; specifically including:
[0026] When performing beam control, the radar antenna is designed with various shaping codes, including the ground state code, the large position delay compensation code, the small position delay compensation code, and the TR channel-level phase shifter compensation code.
[0027] The computation and distribution module adopts a two-layer FLASH+BRAM storage and computation architecture for storing beam control codes. During beam control, all beam control parameters are compressed and stored in FLASH according to frequency points and usage requirements.
[0028] For wave control codes that are weakly related to frequency points, all bandwidths share a single set;
[0029] For wave control codes with weak frequency relationship, such as large-position delay compensation codes, small-position delay compensation codes, and phase shifter compensation codes at the T / R channel level, the codes are compressed into one-dimensional codes for storage and then expanded to two dimensions during calculation.
[0030] When calculating the wave position parameters, the parameters required for the current frame are read from FLASH into BRAM. BRAM is partitioned according to frequency points, and switching between different frequency points is completed through ping-pong storage and pre-switching frequency points.
[0031] Compared with the prior art, the technical solution adopted in this invention has the following technical effects:
[0032] This invention achieves efficient task scheduling and precise low-level execution through a hierarchical control system, significantly improving control efficiency and coordination. For both broadband and narrowband signals, a three-level compensation mechanism is employed to effectively solve the challenge of precise phase control under different bandwidths. Crucially, an innovative BRAM ping-pong storage design addresses the problem of large data volume and storage difficulties in wave control codes, enabling agile switching between different frequency points. This method ensures both frequency switching and the system's orderly real-time response capability and flexibility. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of a wide and narrow integrated low sidelobe multimode beam control system architecture in this embodiment.
[0034] Figure 2 This is a schematic diagram of the centralized three-level architecture of the wave control sub-module in this embodiment.
[0035] Figure 3 This is a schematic diagram of aperture crossing in this embodiment.
[0036] Figure 4 This is a schematic diagram of the frequency switching timing in this embodiment. Detailed Implementation
[0037] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0038] The embodiments provided by the present invention will be described in detail below:
[0039] Example 1: System Architecture and Workflow
[0040] This embodiment proposes a wide and narrow beamwidth integrated low sidelobe multi-mode beam control system. Through a multi-level control architecture and a ping-pong memory management strategy, this system effectively solves the problems of high beam control latency requirements and limited storage space. Simultaneously, the system possesses wide and narrow beamwidth compatibility and multi-mode support capabilities, significantly improving the flexibility and storage efficiency of the beam control system, and providing support for achieving high-precision, wide-range, multi-mode space-based radar beam control.
[0041] like Figure 1 As shown, the beam control architecture of the present invention includes a scheduling module, a monitoring and timing module, and a beam control sub-module.
[0042] The scheduling module is located in the cabin's electronic equipment and consists of an FPGA chip and DDR. Resource scheduling software is installed within the FPGA chip.
[0043] The monitoring timing module is located in the cabin's electronic equipment and consists of a FLASH memory and an FPGA.
[0044] The beam control submodule consists of a computation and distribution module, a beam control unit, and a component controller. The computation and distribution module is located in the cabin electronics, while the beam control unit and component controller are located on the antenna array.
[0045] The beam control workflow based on this architecture is completed collaboratively by the scheduling module, the monitoring and timing module, and the beam control sub-module.
[0046] The core functions of the scheduling module integrate information exchange, task pre-scheduling, and parameter calculation. It first receives the radar payload's operational instructions, then plans the subsequent task sequence based on these instructions, while simultaneously calculating the various operational parameters required to execute the tasks.
[0047] The monitoring and timing module serves as the timing reference for the radar system, responsible for coordinating the operation of the entire system. It receives scheduling commands and, based on the system clock provided by the integrated radio frequency, generates various timing pulses and operating instructions, distributing them to each sub-unit to ensure all units operate collaboratively according to the preset timing sequence. Furthermore, this module integrates beam control functionality, achieving precise beam control through real-time calculation of antenna array parameters.
[0048] The beam control module adopts a centralized three-level architecture to achieve the hierarchical distribution of beam control commands. The computation and distribution module, as the control core, completes beam calculation and command generation; the beam control unit, as a relay, serially distributes commands to the active subarrays; and the component controller, as the execution terminal, completes the final control of the T / R components. The three-level control architecture is as follows: Figure 2 As shown.
[0049] When performing delay control, the beam control module works in concert with the computation distribution module, the beam control unit, and the component controller to form a centralized three-level beam control system.
[0050] The computing and distribution module is located in the cabin's electronic equipment and consists of an FPGA, storage, and interface chips.
[0051] The beam control unit is located on the active subarray of the antenna array and is composed of ASIC interface chips.
[0052] The component controller is located on the active subarray of the antenna array, between the radar antenna and the beam control unit. The component controller consists of subarray-level large position delay, T / R component-level small position delay, and T / R channel-level phase shifter.
[0053] The beam control of the phased array antenna array adopts multi-component joint control, which is achieved through the cooperation of subarray-level large position delay, T / R component-level small position delay, and T / R channel-level phase shifter.
[0054] The beam control system consists of one computation and distribution module, 40 beam control units, 80 subarray-level large-position delays, 1920 T / R component-level small-position delays, and 7680 T / R channel-level phase shifters. One computation and distribution module controls all 40 beam control units on the entire array, and each beam control unit controls the beam positions of two subarrays.
[0055] The operation and distribution module is connected to the wave control unit via an RS422 differential line to complete the transmission of control information. The wave control unit is connected to the component controller via a digital integrated circuit to complete the transmission of wave control information.
[0056] The workflow of this system is as follows: the scheduling module performs task pre-scheduling and parameter calculation; the monitoring and timing module uniformly generates timing sequences and executes real-time wave control calculations; the wave control sub-module adopts a centralized three-level architecture to realize the hierarchical distribution of instructions: calculation distribution -> instruction relay distribution -> terminal execution, and finally the component controller completes the precise control of the T / R component.
[0057] Example 2: Multi-component joint delay control
[0058] This embodiment focuses on the three-layer time delay compensation mechanism. Phased array antenna beam control requires precise compensation for aperture transit time and phase difference between array elements.
[0059] First, before controlling the component controller, it is necessary to calculate the subarray level large position delay, T / R component level small position delay, and TR channel level phase shifter displacement based on the aperture transit time and the phase difference between adjacent array elements.
[0060] The aperture transit time should be less than 1 / k times the pulse width of the compressed signal. The required delay for the phased array antenna is calculated based on the scanning angle, antenna array length, and scanning bandwidth. The calculation method is as follows:
[0061]
[0062] Where B is the signal bandwidth, k is a coefficient, and L is the antenna array length. Where c is the scanning angle and c is the speed of light, the aperture transit diagram is shown below. Figure 3 As shown.
[0063] Taking an antenna array with an azimuth length of 4.8m, an operating center frequency of 8GHz, and a scanning angle of 30 degrees as an example, the calculated wavelength is 0.0375m. The required wavelength for fully compensated aperture crossing is... The required subarray level large-bit delay is... The small-bit delay at the T / R component level is .
[0064] The phase difference between adjacent elements of the phased array is calculated based on the operating frequency, element spacing, and beam scanning angle. The phase shifters of each T / R channel are then adjusted to perform phase adjustment. The calculation method is as follows.
[0065]
[0066] in The phase difference between adjacent array elements. λ is the wavelength, and d is the spacing between array elements. The scanning angle.
[0067] The antenna array has an azimuth length of 4.8m, an operating center frequency of 7.5GHz, and an element spacing of 0.5m. Taking a scanning angle of 30 degrees as an example, with a wavelength of 0.04m and an element spacing of 0.02m, the phase of the first element (element 0) is taken as the reference (set to 0°). Then the phase of the second element (element 1) should be 0° - 90° = -90°. The phase of the third element (element 2) should be -90° - 90° = -180°. The phase of the fourth element (element 3) should be -180° - 90° = -270° (equivalent to +90°). And so on, the phase of the Nth element is... .
[0068] Example 3: Ping-Pong Storage and Agile Switching
[0069] This embodiment focuses on resolving the contradiction between the large amount of wave control code data and the limited storage space of the FPGA's internal BRAM.
[0070] The beam control system needs to store various type codes, including the ground state code, large / small bit delay compensation code, and phase shifter compensation code. Among them, the compensation code, which is strongly correlated with the frequency point, has a huge amount of data and is difficult to store entirely in the limited BRAM (e.g., 5Mb).
[0071] This invention employs a two-level storage and computation architecture of FLASH + BRAM. All beam control parameters are compressed according to frequency points and usage requirements and stored in a large-capacity FLASH (e.g., 256Mb). Optimization strategies include: sharing a single set of beam control codes with weak frequency point correlation across all bandwidths; compressing broadened codes, low sidelobe weighted codes, etc., into one-dimensional codes for storage, and then expanding them into two-dimensional codes in real time during calculation.
[0072] During system operation, based on the timing requirements of frequency switching, the beam control parameters required for the next operating frequency are pre-loaded from FLASH into BRAM for pre-switching. For example... Figure 4 As shown, the BRAM is internally partitioned by frequency point, using a ping-pong operation: when data from one BRAM partition is used in the current frame, the data for the required frequency point in the next frame has already been pre-loaded into another partition, thus achieving agile and seamless switching between different frequency points. Specifically:
[0073] When performing beam control, radar antennas are designed with various shaping codes, including ground state codes, large-position delay compensation codes, small-position delay compensation codes, and TR channel-level phase shifter compensation codes.
[0074] The ground state code has a weak correlation with the frequency point, while the large-position delay compensation code, small-position delay compensation code, and T / R channel-level phase shifter compensation code have a strong correlation with the frequency point. Different frequency points require different wave control codes, resulting in a large amount of data. The wave control code is implemented using an FPGA, but the FPGA's BRAM has limited storage space and cannot store compensation codes for multiple frequency points.
[0075] To address the issue of excessively large wave control parameters and limited BRAM storage space, the computation and distribution module employs a two-layer storage architecture of FLASH + BRAM for storing wave control codes. The FLASH memory, located within the computation and distribution module, has a larger capacity, while the BRAM memory, located within the FPGA of the computation and distribution module, has a smaller capacity.
[0076] For example, the storage space of a conventional FLASH memory on a satellite is 256Mb, while the storage space of the BRAM used for computation is approximately 5Mb.
[0077] During beam control, all required parameters (frequency points, wave positions) are compressed and stored in FLASH according to the characteristics of the frequency points and usage requirements.
[0078] Waveguide codes that are less related to frequency points can be shared across all bandwidths, eliminating the need for frequency-specific storage and saving space.
[0079] Wave control codes that are weakly related to frequency points, such as large-position delay compensation codes, small-position delay compensation codes, and phase shifter compensation codes at the T / R channel level, are compressed into one-dimensional codes for storage and then expanded to two dimensions during calculation, saving FLASH storage space.
[0080] When calculating wavelet parameters, the parameters required for the current frame are read from FLASH into BRAM. BRAM is partitioned according to frequency points, and agile switching between different frequency points is achieved through ping-pong storage and pre-switching of frequency points. A schematic diagram of frequency point switching is shown below. Figure 4 As shown.
[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A wide-narrow integrated low-sidelobe multi-mode beam control system, characterized in that, include: The scheduling module serves as the top-level control unit, the monitoring and timing module serves as the intermediate control layer, and the wave control sub-module serves as the bottom-level execution unit. The scheduling module integrates information interaction, task pre-scheduling and parameter calculation. It first receives the working instructions of the radar payload, and plans the subsequent task sequence based on these instructions. At the same time, it calculates the various working parameters required to execute the tasks. The monitoring timing module serves as the timing reference for the radar system and is responsible for coordinating the operation of the entire system. It receives scheduling instructions and generates various timing pulses and operating instructions based on the system clock provided by the integrated radio frequency, and distributes them to each sub-unit to ensure that all units operate in strict accordance with the preset timing sequence. The beam control sub-module adopts a centralized three-level architecture, consisting of a computation and distribution module, a beam control unit, and a component controller. The computation and distribution module serves as the control core, completing beam calculation and command generation; the beam control unit acts as a relay, serially distributing commands to the active subarrays; and the component controller acts as the execution terminal, completing the final control of the T / R components.
2. The system according to claim 1, characterized in that, The scheduling module consists of an FPGA chip and a DDR memory; the monitoring and timing module consists of a FLASH memory and an FPGA; the scheduling module, the monitoring and timing module, and the operation and distribution module are located inside the cabin, and the beam control unit and the component controller are located on the active subarray of the antenna array; the beam control unit consists of an ASIC interface chip, and the component controller is located between the radar antenna and the beam control unit.
3. The system according to claim 2, characterized in that, The computation and distribution module is connected to the wave control unit via an RS422 differential line to complete the transmission of control information; the wave control unit is connected to the component controller via a digital integrated circuit to complete the transmission of wave control information.
4. The system according to claim 1, characterized in that, The component controller includes a subarray-level large-bit delay, a T / R component-level small-bit delay, and a T / R channel-level phase shifter.
5. A beam control method based on the system described in any one of claims 1-4, characterized in that, include: The scheduling module receives instructions and completes task planning and parameter calculation. The timing module generates the overall timing sequence and distributes the instructions containing the beam control parameters to the beam control sub-module. The beam control module adopts a centralized three-level architecture to issue commands step by step. Finally, the component controller completes the control of the large position delay, small position delay and phase shifter to achieve beamforming.
6. The method according to claim 5, characterized in that, When performing delay, the beam control module calculates the subarray-level large-position delay and the component-level small-position delay based on the signal bandwidth, antenna array length, and scanning angle, and calculates the phase difference of the phase shifter at the T / R channel level based on the operating frequency, array element spacing, and scanning angle.
7. The method according to claim 6, characterized in that, The calculation methods for the subarray-level large-bit delay and the component-level small-bit delay are as follows: ； Where B is the signal bandwidth, k is a coefficient, and L is the antenna array length. Let be the scanning angle, and c be the speed of light.
8. The method according to claim 6, characterized in that, The method for calculating the phase difference of the phase shifter in the T / R channel stage is as follows: ； in The phase difference between adjacent array elements. λ is the wavelength, and d is the spacing between array elements. The scanning angle.
9. The method according to claim 5, characterized in that, When storing and switching beam control codes, multiple bandwidths of beam control codes that are weakly related to the frequency point share a set of storage, or are compressed into one-dimensional code storage; before switching the frequency point, the beam control parameters of the next frequency point are preloaded from FLASH to the idle partition of BRAM through ping-pong operation to achieve fast switching.
10. The method according to claim 9, characterized in that, Specifically, it includes: When performing beam control, the radar antenna is designed with various shaping codes, including the ground state code, the large position delay compensation code, the small position delay compensation code, and the TR channel-level phase shifter compensation code. The computation and distribution module adopts a two-layer FLASH+BRAM storage and computation architecture for storing beam control codes. During beam control, all beam control parameters are compressed and stored in FLASH according to frequency points and usage requirements. For wave control codes that are weakly related to frequency points, all bandwidths share a single set; For wave control codes with weak frequency relationship, such as large-position delay compensation codes, small-position delay compensation codes, and phase shifter compensation codes at the T / R channel level, the codes are compressed into one-dimensional codes for storage and then expanded to two dimensions during calculation. When calculating the wave position parameters, the parameters required for the current frame are read from FLASH into BRAM. BRAM is partitioned according to frequency points, and switching between different frequency points is completed through ping-pong storage and pre-switching frequency points.