Data shift operation method and device, electronic equipment, and storage medium

Abstract

This disclosure provides a data shifting operation method, apparatus, electronic device, and storage medium, relating to the field of data operation technology. The method includes: splitting a source operand into multiple sub-operands according to its bit width, determining the shift direction based on the shift type, and determining the segmented shift processing method based on the target shift amount, so that multiple shifting operation units perform shift operations on each sub-operand respectively; further, combining and concatenating the shift results across segments to obtain the target shift result. This technical solution, by transforming the shifting of high-bit-width data into a collaborative processing process of multiple low-bit-width data, and employing differentiated processing paths under different shift ranges, can reduce circuit implementation complexity, reduce hardware resource consumption, improve the reusability of shifting operation units, and enhance the flexibility and adaptability of the system structure while ensuring the consistency of shift semantics.

Description

Technical Field

[0001] This disclosure relates to the field of data processing technology, and more specifically, to a data shifting operation method and apparatus, electronic device, and storage medium. Background Technology

[0002] In computer architecture and integrated circuit design, shift operations are a common type of data processing operation used to move the binary bits of operands as a whole to achieve functions such as data alignment, accelerated multiplication and division, and bit field processing. In practical applications, as data processing demands increase, systems typically need to support data shift operations with larger bit widths and be able to adapt to different shift types and variable shift amounts.

[0003] However, in related technologies, in order to support shift operations with large bit widths, it is usually necessary to construct a relatively complex shift circuit structure, which leads to problems such as large circuit size, complex logic structure and low resource utilization efficiency in the implementation process. At the same time, in some application scenarios, the frequency of use of large bit width shift operations is relatively low, and configuring a complete implementation structure for it can easily lead to a waste of hardware resources.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a data shifting operation method, apparatus, electronic device, and storage medium, which can reduce circuit implementation complexity, reduce hardware resource consumption, improve the reusability of shifting operation units, and enhance the flexibility and adaptability of system structure while ensuring the consistency of shifting semantics.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to a first aspect of the present disclosure, a data shifting operation method is provided, applied to an electronic device having at least two shifting operation units, wherein the maximum data bit width processed by the shifting operation units is less than a first data bit width and greater than or equal to a second data bit width, the method comprising: Obtain the source operand to be processed, and split the source operand into at least two sub-operands; wherein the source operand has the first data bit width, and each of the sub-operands has the second data bit width; Based on the shift type and target shift amount corresponding to the source operand, control the at least two shift operation units to perform corresponding shift operations on the at least two sub-operands respectively, and obtain the shift results of at least two operands; The shift results of the at least two operands are combined across segments, and the combined results are then concatenated to obtain the target shift result corresponding to the source operand. The cross-segment data combination process refers to the process of reconstructing the data between the shift results of the operands after segmented shifting.

[0008] In some example embodiments of this disclosure, based on the foregoing scheme, controlling the at least two shift operation units to perform corresponding shift operations on the at least two sub-operands according to the shift type and target shift amount corresponding to the source operand, to obtain the shift result of at least two operands, includes: The shift direction is determined according to the shift type corresponding to the source operand, and the segmented shift processing method corresponding to the source operand is determined according to the target shift amount corresponding to the source operand. The segmented shift processing method is used to enable the at least two shift operation units to cooperate in completing the overall shift operation of the source operand. Based on the shift direction, the target shift amount, and the segmented shift processing method, the at least two shift operation units are controlled to perform corresponding shift operations on the at least two sub-operands respectively, so as to obtain the shift results of at least two operands.

[0009] In some example embodiments of this disclosure, based on the foregoing scheme, the segmented shift processing method includes a first processing method and a second processing method. The first processing method is used to select a data processing path in which each operand is shifted independently and combined across segments when the target shift amount does not cross the boundary of the complete data segment. The second processing method is used to select a data processing path in which some operands are shifted and filled when the target shift amount crosses the boundary of the complete data segment. The step of determining the segmented shift processing method corresponding to the source operand based on the target shift amount corresponding to the source operand includes: Compare the target shift amount with the second data bit width; If the target shift amount is less than the second data bit width, then the first processing method is determined to be used; If the target shift amount is greater than or equal to the second data bit width, then the second processing method is determined to be used.

[0010] In some example embodiments of this disclosure, based on the foregoing scheme, the at least two sub-operands include a first operand and a second operand, and the shift result of the at least two operands includes the shift result of the first operand and the shift result of the second operand; When the first processing method is adopted, controlling the at least two shift operation units to perform corresponding shift operations on the at least two sub-operands respectively, and obtaining the shift results of at least two operands, includes: According to the shift direction, a shift operation with a shift amount equal to the target shift amount is performed on the first operand and the second operand respectively to obtain the shift result of the first operand and the shift result of the second operand.

[0011] In some example embodiments of this disclosure, based on the foregoing scheme, the step of performing cross-segment data combination processing on the shift results of the at least two operands, and concatenating the combined results to obtain the target shift result corresponding to the source operand, includes: A cross-shift operation is performed on the first operand shift result and the second operand shift result, and the result of the cross-shift operation is logically combined with the first operand shift result and the second operand shift result respectively according to the shift direction to generate the high-order operand and the low-order operand of the shift result; The high-order operands and low-order operands of the shift result are concatenated to obtain the target shift result corresponding to the source operand.

[0012] In some example embodiments of this disclosure, based on the foregoing scheme, when the shift direction is left shift, the step of performing a cross-shift operation on the first operand shift result and the second operand shift result, and logically combining the result of the cross-shift operation with the first operand shift result and the second operand shift result respectively according to the shift direction, includes: The second operand shift result is shifted to the right by a first shift amount to obtain a first cross value, where the first shift amount is the difference between the second data bit width and the target shift amount; Perform a bitwise OR operation on the first cross value and the shift result of the first operand to obtain the high-order operand of the shift result; The result of shifting the second operand is used as the lower operand of the shift result.

[0013] In some example embodiments of this disclosure, based on the foregoing scheme, when the shift direction is right shift, the step of performing a cross-shift operation on the first operand shift result and the second operand shift result, and logically combining the result of the cross-shift operation with the first operand shift result and the second operand shift result respectively according to the shift direction, includes: The first operand shift result is shifted to the left by a first shift amount to obtain the second cross value, where the first shift amount is the difference between the second data bit width and the target shift amount; Perform a bitwise OR operation on the second cross value and the shift result of the second operand to obtain the low-order operand of the shift result; The result of shifting the first operand is used as the high-order operand of the shift result.

[0014] In some example embodiments of this disclosure, based on the foregoing scheme, the at least two sub-operands include a first operand and a second operand, and the shift result of the at least two operands includes the shift result of the first operand and the shift result of the second operand; When the second processing method is adopted, the control of the at least two shift operation units to perform corresponding shift operations on the at least two sub-operands respectively, to obtain the shift results of at least two operands, including: According to the shift direction, a target operand is determined from the first operand and the second operand, and a shift operation with a shift amount of the second shift amount is performed on the target operand to obtain a target shift value, wherein the second shift amount is the difference between the target shift amount and the second data bit width; Set the shift result corresponding to the other operand to the preset padding value; Wherein, one of the first operand shift result and the second operand shift result is the target shift value, and the other is the preset fill value.

[0015] In some example embodiments of this disclosure, based on the foregoing scheme, the step of performing cross-segment data combination processing on the shift results of the at least two operands, and concatenating the combined results to obtain the target shift result corresponding to the source operand, includes: When the shift direction is left shift, the target shift value is used as the high-order operand of the shift result, and the preset fill value is used as the low-order operand of the shift result; or When the shift direction is right shift, the preset fill value is used as the high-order operand of the shift result, and the target shift value is used as the low-order operand of the shift result. The high-order operands and low-order operands of the shift result are concatenated to obtain the target shift result corresponding to the source operand.

[0016] In some example embodiments of this disclosure, based on the foregoing scheme, determining the target operand from the first operand and the second operand according to the shift direction includes: When the shift direction is left shift, the second operand is used as the target operand; or When the shift direction is right shift, the first operand is used as the target operand.

[0017] In some example embodiments of this disclosure, based on the foregoing scheme, the preset fill value is determined according to the shift direction and the shift type: When the shift direction is leftward, the preset fill value is zero; When the shift direction is right shift and the shift type is logical right shift, the preset fill value is zero; When the shift direction is right shift and the shift type is arithmetic right shift, the preset fill value is the extension value of the sign bit of the first operand.

[0018] In some example embodiments of this disclosure, based on the foregoing scheme, the shift type includes at least logical left shift, logical right shift, and arithmetic right shift; determining the shift direction according to the shift type corresponding to the source operand includes: If the shift type is logical left shift, then the shift direction is determined to be left shift; If the shift type is a logical right shift or an arithmetic right shift, then the shift direction is determined to be a right shift.

[0019] In some example embodiments of this disclosure, based on the foregoing scheme, the at least two shift operation units include two shifters arranged in parallel, and the data bit width processed by each shifter is the second data bit width; the first data bit width is 64 bits, and the second data bit width is 32 bits.

[0020] According to a second aspect of the present disclosure, a data shifting operation apparatus is provided, comprising: An input processing unit is configured to acquire a source operand to be processed and split the source operand into at least two sub-operands; wherein the source operand has a first data bit width and each of the sub-operands has a second data bit width; A shift control unit is used to acquire the shift type and target shift amount corresponding to the source operand, determine the shift direction according to the shift type, and determine the segmented shift processing method according to the target shift amount; At least two shift operation units, each shift operation unit processing data with a data bit width of the second data bit width, are used to perform shift operations on the at least two sub-operands respectively under the control of the shift control unit; The data combination unit includes a multiplexer and a logic combination circuit. The multiplexer and the logic combination circuit are used to perform cross-segment data combination and concatenation on at least two shifted suboperands to obtain the target shift result corresponding to the source operand. The shift control unit is configured to enable the at least two shift operation units to collaboratively perform shift operations on the source operands of the first data bit width.

[0021] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory storing computer-readable instructions, which, when executed by the processor, implement the data shifting operation method of the first aspect.

[0022] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the data shifting operation method of the first aspect.

[0023] The technical solutions provided in this disclosure may have the following beneficial effects: The data shifting operation method in the example embodiments of this disclosure, on the one hand, splits the source operand into multiple sub-operands according to the bit width, and performs corresponding shift operations on each sub-operand based on the shift type and shift amount. This transforms the shifting process originally designed for overall high-bit-width data into a segmented processing process for multiple smaller-bit-width data, thereby avoiding direct dependence on high-bit-width shifting circuits. Under the premise of achieving the same shift semantics, it reduces the use of multi-level selection structures and complex combinational logic, which can reduce circuit implementation complexity and logic resource consumption. On the other hand, by performing cross-segment data combination processing on the shift results of each sub-operand, it enables the formation of effective data connection relationships between different data segments and achieves unified data processing adaptation in different shifting scenarios. This enhances the adaptability of the circuit structure to different bit-width requirements and application scenarios while ensuring the consistency of the overall shift semantics, thereby improving the flexibility and scalability of the system structure.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0026] Figure 1 The diagram illustrates a data shifting operation method according to some embodiments of the present disclosure.

[0027] Figure 2 The illustration shows a schematic diagram of a process path selection by shift amount according to some embodiments of the present disclosure.

[0028] Figure 3The illustration shows a flowchart of determining the target shift result corresponding to the source operand in a first processing mode according to some embodiments of the present disclosure.

[0029] Figure 4 The illustration shows a flowchart of implementing the first processing method in a left-shifting scenario according to some embodiments of the present disclosure.

[0030] Figure 5 The illustration shows a flowchart of implementing the first processing method in a right-shifting scenario according to some embodiments of the present disclosure.

[0031] Figure 6 The illustration schematically shows a flow diagram of data shifting of a 64-bit source operand according to some embodiments of the present disclosure.

[0032] Figure 7 A schematic diagram of a data shifting operation apparatus according to some embodiments of the present disclosure is shown.

[0033] Figure 8 The schematic diagram illustrates the structural schematic of a computer system of an electronic device according to some embodiments of the present disclosure.

[0034] Figure 9 A schematic diagram of a computer-readable storage medium according to some embodiments of the present disclosure is shown.

[0035] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0037] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0038] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0039] Furthermore, the accompanying drawings are for illustrative purposes only and are not necessarily drawn to scale. The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0040] In this example embodiment, a data shifting operation method is first provided. This data shifting operation method can be applied to an electronic device having at least two shifting operation units. The maximum data bit width that the shifting operation unit can process is less than the first data bit width and greater than or equal to the second data bit width.

[0041] Figure 1 A schematic flowchart illustrating a data shifting operation method according to some embodiments of the present disclosure is shown. (Reference) Figure 1 As shown, the data shifting operation method may include the following steps: Step S110: Obtain the source operand to be processed and split the source operand into at least two sub-operands; wherein the source operand has the first data bit width, and each of the sub-operands has the second data bit width; Step S120: Based on the shift type and target shift amount corresponding to the source operand, control the at least two shift operation units to perform corresponding shift operations on the at least two sub-operands respectively, to obtain the shift result of at least two operands; Step S130: Perform cross-segment data combination processing on the shift results of the at least two operands, and splice the combined results to obtain the target shift result corresponding to the source operand. The cross-segment data combination processing refers to the process of reconstructing the data between the shift results of the operands after segmented shifting.

[0042] According to the data shifting operation method in this example embodiment, on the one hand, by splitting the source operand into multiple sub-operands according to the bit width, and performing corresponding shift operations on each sub-operand based on the shift type and shift amount, the shifting process originally targeting the overall high bit width data can be transformed into a segmented processing process of multiple smaller bit width data. This avoids direct dependence on high bit width shifting circuits, reduces the use of multi-level selection structures and complex combinational logic while achieving the same shift semantics, thereby reducing circuit implementation complexity and logic resource consumption. On the other hand, by performing cross-segment data combination processing on the shift results of each sub-operand, effective data connection relationships can be formed between different data segments, and unified data processing adaptation can be achieved in different shifting scenarios. This enhances the adaptability of the circuit structure to different bit width requirements and application scenarios while ensuring the overall shift semantic consistency, thereby improving the flexibility and scalability of the system structure.

[0043] The data shifting operation method in this example embodiment will be further explained below.

[0044] In step S110, the source operand to be processed is obtained, and the source operand is split into at least two sub-operands; wherein the source operand has the first data bit width, and each of the sub-operands has the second data bit width.

[0045] In one example embodiment of this disclosure, the source operand refers to the data object involved in the shift operation. It can be data from a register, cache unit, or input terminal of an arithmetic logic unit (ALU) in the processor. For example, the source operand can be a set of consecutive bit sequences organized according to a first data bit width, such as 64-bit data.

[0046] Each suboperand refers to multiple sub-data segments obtained based on the source operand. Each suboperand can correspond to different bit segments of the source operand. For example, a suboperand can include the high-order data segment and the low-order data segment of the source operand. Each suboperand has a second data bit width. For example, if the first data bit width of the source operand is 64 bits, then the second data bit width can be 32 bits. In this case, the source operand can be split into two suboperands, corresponding to the high 32-bit data segment and the low 32-bit data segment, respectively. By dividing the source operand into two suboperands, the data processing is made symmetrical and segmentable.

[0047] Understandably, the source operand can also be split into multiple sub-operands according to the bit width. For example, the number of sub-operands obtained by splitting can be 4, 8, etc. This embodiment does not make a special limitation on the number of sub-operands obtained by splitting. Multiple sub-operands are processed by multiple shift operation units in concert. For example, the bit width of the source operand can be 128 bits, which can be divided into 4 sub-operands with a data bit width of 32 bits, and the overall shift operation is completed based on the corresponding number of 32-bit shift operation units. This embodiment does not limit this.

[0048] In specific implementations, the splitting of the source operand can be achieved through bit selection circuits. For example, the high-order bits can be output as the first operand and the low-order bits as the second operand through wiring. Alternatively, it can be achieved through bit masking and shift operations. For example, the first operand can be obtained by right shifting the source operand and performing a bitwise AND operation with the high-order bit mask, and the second operand can be obtained by performing a bitwise AND operation with the low-order bit mask. Of course, it can also be achieved through register mapping, that is, reading the high-order register and the low-order register from the register file as the first operand and the second operand respectively. This embodiment does not impose any special limitations on the splitting method of the source operand.

[0049] By splitting the source operand into multiple sub-operands according to the bit width, and performing corresponding shift operations on each sub-operand based on the shift type and shift amount, the shift processing originally designed for high-bit-width data can be transformed into a segmented processing process for multiple smaller-bit-width data. This avoids direct dependence on high-bit-width shift circuits, reduces the use of multi-level selection structures and complex combinational logic while achieving the same shift semantics, thereby reducing circuit implementation complexity and logic resource consumption.

[0050] In step S120, based on the shift type and target shift amount corresponding to the source operand, the at least two shift operation units are controlled to perform corresponding shift operations on the at least two sub-operands respectively, so as to obtain the shift results of at least two operands.

[0051] In one example embodiment of this disclosure, shift type refers to control information used to describe the behavior of shift operations. For example, shift type may include logical left shift (LSL), logical right shift (LSR), and arithmetic right shift (ASR), wherein logical left shift and logical right shift do not involve sign bit extension, while arithmetic right shift requires sign bit extension.

[0052] In this embodiment, the shift direction can be determined according to the shift type. For example, when the shift type is logical left shift, the shift direction is left shift; when the shift type is logical right shift or arithmetic right shift, the shift direction is right shift.

[0053] The target shift amount refers to the number of bits that the source operand needs to be shifted. It can be derived from the instruction decoding result, register input value, or external control signal. For example, the shift amount can be an integer between 0 and the first data bit width minus one.

[0054] A shift operation unit refers to a hardware circuit module used to perform shift operations. For example, a shift operation unit can be a barrel shifter, a shift structure based on a shift register chain, or a shift network composed of multiplexers (MUX). In specific implementations, the electronic device can obtain the shift type and target shift amount through the shift control unit, and generate corresponding control signals based on the shift type and target shift amount to control each shift operation unit to perform the corresponding shift operation on each sub-operand. For example, when a 64-bit source operand is split into a high 32-bit sub-operand and a low 32-bit sub-operand, two 32-bit shift operation units can be used to shift the high 32-bit sub-operand and the low 32-bit sub-operand respectively, thereby obtaining the corresponding operand shift result. The operand shift result can be an intermediate result formed by each sub-operand under the corresponding shift direction and shift amount. This intermediate result can be directly sent to the subsequent data combination unit, or it can be temporarily stored in an intermediate register before participating in subsequent processing.

[0055] By controlling multiple shift operation units to perform shift operations on suboperands according to the shift type and target shift amount, the overall shift operation can be decomposed into multiple smaller bit-width data paths, thereby reducing the dependence on complete high-bit-width shift circuits and improving the reuse of existing shift operation units.

[0056] In step S130, the shift results of the at least two operands are subjected to cross-segment data combination processing, and the combined results are spliced ​​together to obtain the target shift result corresponding to the source operand. The cross-segment data combination processing refers to the process of reconstructing the data between the shift results of the operands after segmented shifting.

[0057] In one example embodiment of this disclosure, cross-segment data combination processing refers to the process of reconstructing the boundary data between different data segments after segment shifting. Its core is to ensure the correct transmission of cross-segment data during the shifting process. For example, when the shift direction is left, some high-order data in the operand shift result of the low-order suboperand can be obtained by compensating shift to obtain cross data, and the cross data is combined with the operand shift result of the high-order suboperand by bitwise OR operation to form a new high-order part, while the operand shift result of the low-order suboperand is used as the low-order part; when the shift direction is right, some low-order data in the operand shift result of the high-order suboperand can be obtained by compensating shift to obtain cross data, and bitwise OR operation is performed with the operand shift result of the low-order suboperand to form a new low-order part, while the operand shift result of the high-order suboperand is used as the high-order part.

[0058] When the shift amount is large, one operand can be selected as the target operand, and the other operand can be padded with values, such as zeros or sign bit extension, to ensure the correctness of the shift result. In specific implementation, the above-mentioned cross-segment data combination can be implemented by logic combinational circuits, such as constructing data paths through bitwise logic operation circuits and multiplexers; the splicing process can be implemented by data bus splicing or bit segment combination during register write-back. This embodiment does not impose special limitations on the combination and splicing methods.

[0059] Understandably, in this embodiment, reconstruction refers to the recombination, compensation, or correction of data that needs to be transferred across segments between the shift results of different sub-operands after each sub-operand has been shifted, so that each data segment can form a high-bit part and a low-bit part that conforms to the overall shift semantics. In other words, reconstruction focuses on whether the content within each data segment is correct, especially whether the bits that cross from one data segment to another during the shift process are correctly padded. For example, after splitting a 64-bit source operand into a high 32-bit sub-operand and a low 32-bit sub-operand, if a left shift is performed and the target shift amount is less than 32 bits, some high-bit bits in the low 32-bit sub-operand will enter the high 32-bit region in the overall 64-bit left shift result. At this point, simply concatenating the results of the left shift of the high 32-bit sub-operand and the low 32-bit sub-operand will not yield the correct result. It is also necessary to extract the bits that cross into the high-bit region from the low 32-bit sub-operand and logically combine them with the shift result of the high 32-bit sub-operand. This process constitutes reconstruction.

[0060] In this embodiment, the splicing is performed after reconstruction, connecting the high-order and low-order parts of the already formed shift result in bit segment order to form a complete target shift result. In other words, splicing focuses on how the processed data segments are synthesized into a whole data in high-low bit order, and it usually does not change the bit content within each data segment.

[0061] As is easily understood, reconstruction involves recombining the valid data in the shift results of each suboperand. For example, it might involve padding the bits that should have entered the higher-order region of the lower-order suboperands into the higher-order result, or generating a padding value based on the sign bit during an arithmetic right shift. Concatenation, on the other hand, involves joining the obtained higher-order and lower-order results in bit-width order after reconstruction to form the complete target shift result. Reconstruction changes or supplements the content of each segment, while concatenation simply connects the processed segments together.

[0062] By performing cross-segment data combination processing on the shift results of each suboperand, an effective data connection relationship can be formed between different data segments, and unified data processing adaptation can be achieved in different shift scenarios. This enhances the adaptability of the circuit structure to different bit width requirements and application scenarios while ensuring the overall shift semantic consistency, thereby improving the flexibility and scalability of the system structure.

[0063] The data shifting operation method in steps S110 to S130 will be described in detail below.

[0064] In one example embodiment of this disclosure, the following steps can be used to control at least two shift operation units to perform corresponding shift operations on at least two sub-operands according to the shift type and target shift amount of the source operand, so as to obtain the shift result of at least two operands. Specifically, this may include: The shift direction can be determined based on the shift type corresponding to the source operand, and the segmented shift processing method corresponding to the source operand can be determined based on the target shift amount corresponding to the source operand. The segmented shift processing method is used to enable at least two shift operation units to collaboratively complete the overall shift operation of the source operand. Based on the shift direction, target shift amount, and segmented shift processing method, at least two shift operation units are controlled to perform corresponding shift operations on at least two sub-operands respectively to obtain the shift results of at least two operands.

[0065] The segmented shift processing method refers to a processing strategy determined based on the relationship between the shift amount and the second data bit width. For example, when the shift amount is less than the second data bit width, a first processing method can be used to handle data that spans a segment but is not completely crossed. When the shift amount is greater than or equal to the second data bit width, a second processing method can be used to handle data that spans a complete data segment. In specific implementations, a comparator circuit can be used to compare the shift amount with the second data bit width and generate a control signal based on the comparison result. Alternatively, a look-up table (LUT) or control logic can be used to select the segmented strategy. This embodiment does not impose any special limitations on the implementation form of the segmented shift processing method. By making different shift ranges correspond to different data processing paths, the system's adaptability to various shift scenarios can be improved.

[0066] After determining the shift direction, target shift amount, and segmented shift processing method, the shift control unit can output corresponding control signals to each shift operation unit, enabling each shift operation unit to operate according to the corresponding data path and shift amount. For example, when the target shift amount is less than the second data bit width, each shift operation unit can be controlled to perform the shift operation corresponding to the target shift amount on the sub-operands to obtain the local shift result of each sub-operand; when the target shift amount is greater than or equal to the second data bit width, the target sub-operand can be determined according to the shift direction, and the corresponding shift operation unit can be controlled to perform the shift operation corresponding to the remaining shift amount on the target sub-operand, while controlling another result segment to participate in the result construction using a preset padding value.

[0067] By determining the segmented shift processing method based on the shift amount and adopting differentiated data processing paths under different shift ranges, each sub-operand can complete the coordinated shift under unified control. The overall data relationship can be restored by combining cross-segment data, thereby completing the shift operation without configuring a complete high-bit-width shift structure. This can improve the reuse of existing shift operation units and reduce additional hardware resource investment, thereby improving hardware resource utilization.

[0068] In one example embodiment of this disclosure, the segmented shift processing method may include a first processing method and a second processing method. The segmented shift processing method refers to a differentiated data processing strategy adopted for the source operand under different shift ranges. Essentially, it involves dividing the overall shift process into intervals based on the relationship between the shift amount and the second data bit width, so as to achieve adaptation to different shift scenarios under a unified architecture. The first processing method can be understood as being used to handle shift scenarios where the shift amount does not cross the bit width range of a single sub-operand. In this scenario, data is only partially transferred across segments between the first and second operands. The second processing method can be understood as being used to handle shift scenarios where the shift amount crosses or is equal to the bit width range of a single sub-operand. In this scenario, the data as a whole crosses a sub-operand boundary, resulting in the complete shifting out of the data of one sub-operand and being replaced by another sub-operand or a padding value.

[0069] It can be done Figure 2 The steps in the document determine the segmented shift processing method corresponding to the source operand based on the target shift amount corresponding to the source operand. (Refer to...) Figure 2 As shown, it can specifically include: Step S210: Compare the target shift amount with the second data bit width; Step S220: If the target shift amount is less than the second data bit width, then it is determined that the first processing method is adopted; Step S230: If the target shift amount is greater than or equal to the second data bit width, then the second processing method is determined to be adopted.

[0070] The comparison operation is a crucial process for determining whether the current shift operation crosses a data segment boundary. By comparing the target shift amount with the second data bit width, the shift operation can be divided into two categories: when the target shift amount is less than the second data bit width, it indicates that the shift operation is still within a single segment or partially spans a segment; when the target shift amount is greater than or equal to the second data bit width, it indicates that the shift operation has crossed a complete data segment boundary. In optional implementations, this comparison operation can be implemented using a digital comparator. For example, a subtractor and a sign bit determination circuit can be used to determine whether the target shift amount has reached a threshold; it can also be implemented using high-order bit detection logic, such as detecting whether the high-order bits of the target shift amount are non-zero; or the comparison result can be directly output using a lookup table. This embodiment does not specifically limit the specific implementation of the comparison circuit. By introducing this comparison process, shift operations can be classified at the hardware level.

[0071] When the target shift amount is less than the second data bit width, the first processing method can be adopted, that is, when the shift does not cross the boundary of the complete data segment, a data processing path based on cross-segment combination is selected. In this scenario, the high-order and low-order parts of the source operand still have data interaction relationships during the shift process. For example, some low-order data needs to be supplemented into the high-order result, or some high-order data needs to be supplemented into the low-order result. Therefore, it is necessary to achieve the overall shift through cross shift and logical combination. For example, in the implementation of splitting 64-bit data into high 32 bits and low 32 bits, when the target shift amount N satisfies 0≤N<32, a complete 64-bit shift result can be formed by performing shift operations on the first operand and the second operand respectively, and by shifting the low-order part to the right to supplement the high-order part, or shifting the high-order part to the left to supplement the low-order part.

[0072] In optional implementations, determining the first processing method can be achieved by enabling the cross-shift path with control signals, for example, by enabling combinational logic circuits to participate in the operation; alternatively, a multiplexer can be used to select the cross-segment combination result as the output; or a pipelined structure can be used to complete data fusion in the subsequent combination stage. This embodiment does not impose any special limitations on this. By employing the first processing method in small displacement scenarios, it can be ensured that the source operands can still correctly express the overall shift semantics even in cases of partial cross-segment operations, thereby improving the accuracy of the results.

[0073] When the target shift amount is greater than or equal to the second data bit width, the second processing method can be determined. That is, when the shift has crossed the boundary of the complete data segment, a data processing path based on single-segment shift and padding is selected. In this scenario, one sub-data segment of the source operand becomes the main data source of the result after shifting, while the result part corresponding to the other sub-data segment is no longer directly composed of the original data, but is generated through preset padding values. For example, in the implementation of splitting 64-bit data into two 32-bit data segments, when the target shift amount N satisfies 32≤N<64, the remaining shift amount M=N-32 can be calculated first. Then, the target operand is selected according to the shift direction, and M shift is performed on it to obtain the target shift value. At the same time, the result corresponding to the other data segment is set to zero or a sign extension value, thereby constructing the complete result.

[0074] In optional implementations, determining whether to adopt the second processing method can be achieved by disabling the cross-combination path and enabling the target operand selection path and the padding path through control logic; alternatively, a multiplexer can be used to directly send the target shift value and the padding value into the high-order and low-order segments of the result, respectively; or a state machine can be used to switch the data path structure. This embodiment does not impose any special limitations on this approach. By adopting the second processing method in large displacement scenarios, cross-segment combination calculations can be reduced, thereby reducing logical complexity and improving hardware resource utilization efficiency.

[0075] By dividing the segmented shift processing into a first processing method and a second processing method, and selecting the processing method based on the relationship between the target shift amount and the second data bit width, different shift ranges correspond to different data processing paths. This allows the shift control logic to adopt more suitable data processing strategies for small and large shift scenarios, avoiding redundant logic participation under a unified processing method. The first processing method is used when the target shift amount is less than the second data bit width, and the second processing method is used when the target shift amount is greater than or equal to the second data bit width. This allows the shift operation path to switch with the shift range, thereby reducing unnecessary data combination complexity and improving the targeting and execution efficiency of the shift processing path.

[0076] In one example embodiment of this disclosure, at least two sub-operands may include a first operand and a second operand, and the shift result of at least two operands may include the shift result of the first operand and the shift result of the second operand. The first operand and the second operand refer to two sub-data units obtained based on the source operand. The first operand may correspond to the high-order data segment of the source operand, and the second operand may correspond to the low-order data segment of the source operand. Both have a second data bit width. For example, if the first data bit width of the source operand is 64 bits, then the second data bit width can be 32 bits, meaning both the first operand and the second operand are 32-bit data. By making the first data bit width twice the second data bit width, the source operand can be equally divided into two sub-operands, thereby enabling data processing to possess symmetry and segmentability.

[0077] When the first processing method is adopted, the following steps can be used to control at least two shift operation units to perform corresponding shift operations on the first operand and the second operand respectively, so as to obtain the shift result of the first operand and the shift result of the second operand. Specifically, this may include: The first operand and the second operand can be shifted according to the shift direction, and the shift result of the first operand and the shift result of the second operand can be obtained.

[0078] The shift direction can be understood as a control parameter that controls the overall migration direction of each valid bit in the source operand. It can be determined by the shift type; for example, logical left shift corresponds to the left shift direction, and logical right shift and arithmetic right shift correspond to the right shift direction. Performing a shift operation according to the shift direction means that the corresponding shift path is selected within the shift operation unit according to the direction control signal. For example, in a left shift path, the data is moved to the higher-order bits through a left shift network, and in a right shift path, the data is moved to the lower-order bits through a right shift network.

[0079] For the first operand, the shift operation can be understood as performing a displacement in the corresponding direction on the higher-order data segment; for the second operand, the shift operation can be understood as performing the same displacement on the lower-order data segment. In optional implementations, the shift operation can be completed within a single cycle using a barrel shifter, for example, by using a multi-stage selection network to achieve a shift of any number of bits at once; it can also be achieved by shifting step-by-step using multi-stage shift registers, for example, by gradually completing the shift through cascaded shift stages; or it can achieve an equivalent shift using a bit rearrangement network, which is not specifically limited in this embodiment. By performing shift operations with the same shift amount on the first and second operands respectively, the two sub-data segments can form local results consistent with the overall shift within their respective ranges, thereby ensuring the correctness of the shift operation under segmented processing.

[0080] The first operand shift result refers to the data result obtained after the first operand performs a shift operation corresponding to the shift direction and the target shift amount. It corresponds to the shift result of the high-order part of the source operand within a local range. The second operand shift result refers to the data result obtained after the second operand performs the same shift operation. It corresponds to the shift result of the low-order part of the source operand within a local range.

[0081] In the first processing method, both shift results are intermediate results and cannot directly constitute the final target shift result. They need to be merged through subsequent cross-segment data combination processing. For example, in the implementation where the first data bit width is 64 bits and the second data bit width is 32 bits, when the target shift amount N satisfies 0≤N<32, the first operand shift result can be represented as the result after shifting the high 32 bits of the data segment, and the second operand shift result can be represented as the result after shifting the low 32 bits of the data segment. In subsequent processing, the cross relationship between these two results also needs to be used to combine them to restore the overall 64-bit shift semantics.

[0082] In optional implementations, the first operand shift result and the second operand shift result can be temporarily stored in a register and then sent to the data combination unit, or they can be directly transmitted to the combinational logic circuit through the data path; alternatively, these intermediate results can be passed through different stages using a pipeline structure, which is not specifically limited in this embodiment. By generating the first operand shift result and the second operand shift result, necessary intermediate data can be provided for subsequent cross-segment data combination, thereby ensuring that the correct overall shift result can still be constructed under segmented processing conditions.

[0083] By performing shift operations with the same target shift amount on the first and second operands according to the shift direction under the first processing method, the two sub-data segments form local shift results consistent with the overall shift within their respective ranges, providing a unified basis for subsequent cross-segment data combination. Since the two sub-data segments are processed synchronously under the same shift amount, data alignment deviations caused by inconsistent processing between different data segments can be avoided, thereby improving the consistency of local shift results and providing stable input for subsequent combination processes, which in turn improves the accuracy of the overall shift result.

[0084] In one example embodiment of this disclosure, it can be achieved through Figure 3 The steps described in the document involve performing cross-segment data combination processing on the shift results of the first operand and the second operand, and then concatenating the combined results to obtain the target shift result corresponding to the source operand. (Refer to...) Figure 3 As shown, it can specifically include: Step S310: Perform a cross-shift operation on the first operand shift result and the second operand shift result, and logically combine the result of the cross-shift operation with the first operand shift result and the second operand shift result respectively according to the shift direction to generate the high-order operand and the low-order operand of the shift result; Step S320: Concatenate the high-order operands and low-order operands of the shift result to obtain the target shift result corresponding to the source operands.

[0085] The first operand shift result and the second operand shift result can be understood as intermediate result data formed by at least two shift operation units shifting the first operand and the second operand according to the target shift amount, respectively, under the first processing method. Since logical left shift, logical right shift, and arithmetic right shift are all basic operations of bitwise shifting of register values ​​in the instruction system, and arithmetic right shift requires maintaining sign bit extension compared to logical right shift, after splitting the source operand into two sub-data segments, only obtaining the independent first operand shift result and second operand shift result is usually not enough to directly restore the complete bit order relationship after the overall data shift. Further processing is needed to address the cross-segment bit migration problem that occurs at the boundary between the two sub-data segments.

[0086] Cross-shifting refers to performing a segment-width-related compensatory shift operation on bits located near segment boundaries in the first and second operand shift results that need to be redistributed across two sub-data segments. This extracts the cross-data used for cross-segment filling. The essence of this cross-shifting operation is not to redefine the original shift semantics, but rather to reposition a portion of the valid bits based on the already formed first and second operand shift results. This ensures that boundary bits that should have moved from the lower-order data segment to the higher-order data segment, or vice versa, are accurately sent to the corresponding result segments. In scenarios where the target shift amount is less than the second data bit width, although the overall data has not yet crossed the complete sub-data segment boundary, some bits have already flowed from one sub-data segment to another. Therefore, cross-shifting is needed to construct this portion of cross-segment data. In other words, the cross-shift operation can be understood as generating an additional intermediate data for boundary compensation in addition to the original sub-data segment shift result, so as to restore the continuity between the overall high-order part and the overall low-order part when combining logic in subsequent operations.

[0087] In specific implementations, the cross-shift operation can be performed by a separate compensation shift circuit, or it can reuse part of the capabilities of an existing shift operation unit. For example, after the first operand shift result and the second operand shift result are output, a multiplexer can be used to select one as the input for the cross-shift, and then the direction and number of bits for compensation shift can be selected according to the shift direction. Alternatively, a bypass data path can be added inside the shift operation unit so that the first operand shift result and the second operand shift result pass through a configurable compensation shift path before being output to the logic combinational circuit. Of course, combinational logic networks can also be used to directly rearrange the boundary bits, for example, by combining bit selection lines, wire crossings, and gate circuits to achieve an equivalent cross-shift effect, as long as the repositioning of cross-segment bits can be achieved. This embodiment does not impose any special limitations on this.

[0088] After obtaining the corresponding cross data through the cross-shift operation, the result of the cross-shift operation can be logically combined with the first operand shift result and the second operand shift result, respectively, according to the shift direction. Logical combination refers to fusing the result of the cross-shift operation with the corresponding first operand shift result or second operand shift result bit by bit according to predetermined rules to generate the high-order operand and low-order operand of the shift result. The purpose of this logical combination is to synthesize the valid data retained after shifting within each sub-data segment and the compensation data migrated from adjacent sub-data segments into a new segment result. This ensures that the high-order and low-order operands of the shift result are no longer isolated local shift results, but rather can jointly represent the complete data of the high and low halves of the overall source operand after shifting.

[0089] In an optional implementation, the logic combination can be implemented using bitwise OR operation, because the cross data after compensated shift and the corresponding first operand shift result or second operand shift result are usually complementary in the effective bit interval. The two parts of data can be merged into the same result segment by bitwise OR operation. Of course, it can also be implemented by a selection merging method after mask control. For example, invalid bits are first cleared by masking, and then bitwise synthesis is performed by OR operation, XOR operation or multiplexer. As long as the shift result high bit operand and shift result low bit operand that conform to the overall shift semantics can be generated, this embodiment does not make special restrictions on the specific gate-level form of the logic combination.

[0090] The high-order operand of the shift result refers to the data result located in the high-order segment of the final target shift result, and the low-order operand of the shift result refers to the data result located in the low-order segment of the final target shift result. It is understood that the high-order and low-order operands of the shift result are not simply a preservation of the shift results of the first and second operands, but rather a reconstructed result after cross-shifting operations and logical combination. In optional implementations, the logic for generating the high-order and low-order operands of the shift result can be located after the shift operation unit and completed by a dedicated data combination unit; it can also be integrated into the subsequent result forming circuit controlled by the shift controller, with a unified control signal selecting whether to output a partial shift result or a combined segment result; or it can be implemented using a two-stage pipeline, with the first stage generating the shift results of the first and second operands, and the second stage performing cross-shifting operations and logical combination. This embodiment does not impose special limitations on the generation timing and circuit location of the high-order and low-order operands of the shift result. This step allows the shift results of the first and second operands, which were originally executed in segments, to re-establish a data continuity relationship at the segment boundary, thereby improving the semantic consistency of the overall shift result.

[0091] Concatenation refers to the process of placing the high-order operands of the shift result in the high-order segment of the result data and the low-order operands of the shift result in the low-order segment of the result data according to a predetermined bit order, thereby reconstructing a complete result data with a first data bit width.

[0092] The target shift result refers to the final output result that should be obtained after the source operands are shifted as a whole under the corresponding shift type and target shift amount. Since the high-order and low-order operands of the shift result already carry the semantics of the high-order and low-order parts of the target shift result, the complete data form can be restored simply by combining the two into the same result word according to the bit width correspondence, without having to perform a high-order bit width overall shift again.

[0093] In one optional implementation, concatenation can be achieved directly via the data bus, for example, by connecting the high-order operand of the shift result to the high-order bit line of the result bus and the low-order operand of the shift result to the low-order bit line of the result bus; it can also be achieved through bit field writing in the register write-back stage, for example, by first writing the high-order operand of the shift result to the high-order field of the target register and then writing the low-order operand of the shift result to the low-order field of the target register; of course, equivalent concatenation can also be achieved through combinational logic, for example, by first extending the high-order operand of the shift result to the high-order position and then performing a bitwise OR operation with the low-order operand of the shift result to form the complete target shift result, as long as it is ultimately equivalent to combining the high-order operand and the low-order operand of the shift result according to the original bit order to form the first data bit width result, this embodiment does not impose any special limitations on this. For implementations using parallel shift operation units, splicing can be completed consecutively with logic combination steps within the same clock cycle; for implementations using a pipelined approach, splicing can also be completed in the next pipeline stage to meet timing constraints under different frequency targets.

[0094] By concatenating the high-order and low-order operands of the shift result, the segment result, which has already undergone cross-segment compensation and logical combination in the previous stage, can be unified back into a complete target shift result. This ensures that the target shift result is consistent with the result that should be obtained after directly shifting the source operands as a whole in terms of data width, bit order, and shift semantics. On the one hand, this avoids directly constructing a complete high-width shift network in hardware; on the other hand, it ensures that the segment result formed by the shift result of the first operand, the shift result of the second operand, the cross shift operation, and the logical combination is ultimately restored to standard result data that can be directly used by the subsequent execution unit, register write-back unit, or bus interface. This improves the compatibility of the entire segmented shift implementation scheme with existing processor or dedicated circuit data paths.

[0095] By performing cross-shift operations on the shift results of the first and second operands, and logically combining them according to the shift direction to generate high-order and low-order operands of the shift result, the data that was originally processed independently in segments can be re-established at the cross-segment level, thereby restoring the semantic relationship of the overall bit-width shift. Furthermore, by concatenating the high-order and low-order operands, the data after cross-segment combination can be re-formed into a complete bit-width result. Thus, an equivalent overall shift function can be achieved without constructing an overall shift circuit, and the ability of the segmented processing scheme to restore the semantics of large bit-width shifts can be improved.

[0096] In one example embodiment of this disclosure, when the shift direction is leftward, it can be achieved through... Figure 4The steps described in the document implement a cross-shift operation on the shift results of the first and second operands, and logically combine the result of the cross-shift operation with the shift results of the first and second operands respectively, according to the shift direction. (Refer to...) Figure 4 As shown, it can specifically include: Step S410: Shift the second operand shift result to the right by a first shift amount to obtain a first cross value, where the first shift amount is the difference between the second data bit width and the target shift amount; Step S420: Perform a bitwise OR operation on the first cross value and the shift result of the first operand to obtain the high-order operand of the shift result; Step S430: The shift result of the second operand is used as the low-order operand of the shift result.

[0097] In the first processing method, the target shift amount is less than the second data bit width. When the shift direction is left, it does not directly cross the boundary of the complete sub-data segment. Instead, a portion of the bits in the second operand shift result needs to cross segments to enter the higher-order part. Correspondingly, the second operand shift result itself still retains the main body of the lower-order segment result. It is based on this data migration relationship of locally sending boundary bits from the lower-order segment to the higher-order segment that it is necessary to generate a first cross value around the second operand shift result and logically combine it with the first operand shift result.

[0098] The second operand shift result is the intermediate result data formed after the second operand has been left-shifted according to the target shift amount under the first processing method. Since the second operand shift result has completed the left shift towards its own low-order segment, but the valid bits near the high-order boundary still need to be extracted to compensate for the low-order gaps in the high-order operands of the shift result, a compensatory right shift related to the segment width needs to be performed on the second operand shift result again.

[0099] The first shift amount refers to the difference between the second data bit width and the target shift amount. Essentially, it represents the number of bits remaining within a complete sub-data segment width that need to be reverse-aligned, excluding the portion where the target shift amount has already been shifted to the left. For example, in a scenario where a 64-bit source operand is split into two 32-bit sub-data segments, if the target shift amount is N and satisfies 0 ≤ N < 32, then the first shift amount essentially corresponds to 32 - N.

[0100] In principle, shifting the result of the second operand to the right by a first shift amount to obtain the first cross value is not a new independent shift operation on the second operand's shift result. Instead, it's based on the already left-shifted result, realigning the bits that should have crossed the sub-data segment boundary into the high-order segment to their combinable positions, thus forming the first cross value. The first cross value can be understood as a boundary compensation value used to fill the low-order region of the high-order operand in the shift result. In specific implementation, shifting the result of the second operand to the right by a first shift amount can be accomplished by a compensation shift circuit. This compensation shift circuit can be an independent shifter or can reuse the bypass capability of an existing shift operation unit. For example, a multiplexer can be used to send the second operand's shift result into a dedicated right-shift compensation path, with the first shift amount used as a control input; alternatively, combinational logic can be used to rearrange the bit lines to achieve bit extraction and alignment equivalent to shifting to the right by a first shift amount. In an optional implementation, the first shift amount can be calculated in real time by the subtractor, or it can be looked up in a lookup table based on the target shift amount, as long as the final compensation bit width is consistent with the second data bit width minus the target shift amount. By extracting and aligning the boundary bits that need to cross segments into the higher bit segment in the second operand shift result separately, accurate compensation data can be provided for the subsequent generation of the higher bit operands of the shift result, thereby improving the integrity of cross-segment data transmission in the left shift scenario.

[0101] The first operand shift result retains the valid bits of the original high-order data segment that remain in the high-order half after the left shift; the first cross value provides the boundary bits that should have been filled into the high-order half by the second operand shift result. Therefore, logically, they correspond to the two sources of the high-order operand of the shift result: the first operand shift result is the portion remaining in the high-order segment after the original high-order segment is shifted left, and the first cross value is the portion that overflows into the high-order segment after the original low-order segment is shifted left. Since these two parts of data are usually complementary in the valid bit range, they should not carry different valid values ​​at the same position. Therefore, a bitwise OR operation can be used to combine them into a complete high-order operand of the shift result. By performing a bitwise OR operation between the first cross value and the first operand shift result, the local left shift result and the cross-segment compensation result can be combined into a single high-order segment result. This allows the high-order operand of the shift result to retain the valid content of the high-order data segment itself after the left shift, while accurately absorbing the cross-segment bits from the low-order data segment, thereby improving the integrity and correctness of the high-order half of the left shift result.

[0102] In scenarios where the shift direction is left and the target shift amount is less than the width of the second data bit, the lower operand of the shift result corresponds to the lower half of the overall result. The main source of data for this lower half is the retained result after the left shift of the second operand. It's easy to understand that when the overall data is left-shifted, the lower half does not receive reverse compensation data from the first operand. Instead, the lower half only generates empty bits filled with zeros on the lower side due to the left shift. Therefore, the shift result of the second operand itself already fully expresses the content required by the lower half of the overall left-shift result, and there is no need to combine it with the crossover data from the first operand. In practical implementation, using the shift result of the second operand as the low-order operand of the shift result can be manifested by directly connecting the shift result of the second operand to the low-order half of the result bus, or by writing the shift result of the second operand into the low-order field in the write-back path of the result register. Of course, a multiplexer can also be used to select the shift result of the second operand from several candidate low-order results, as long as it ultimately occupies the low-order half of the output position. This embodiment does not impose any special limitations on the data path form for implementing this transmission relationship. By directly using the shift result of the second operand as the low-order operand of the shift result, it is possible to avoid introducing additional redundant combinational logic into the low-order half in the scenario of small left shift, thereby making the formation process of the low-order operand of the shift result more direct and helping to simplify the result construction path.

[0103] By right-shifting the result of the second operand in the left-shift scenario to form the first cross value, and performing a bitwise OR operation with the result of the first operand shift, the low-order data can be supplemented into the high-order result during the segment crossing process, thereby restoring the effect of low-order data migration to high-order in the left-shift operation; at the same time, the result of the second operand shift is directly used as the low-order result, so that the low-order part maintains local shift consistency, thereby improving the accuracy of segment data compensation in the left-shift scenario and ensuring the integrity of the high-order result construction.

[0104] In one example embodiment of this disclosure, when the shift direction is rightward, it can be achieved through... Figure 5 The steps described in the document implement a cross-shift operation on the shift results of the first and second operands, and logically combine the result of the cross-shift operation with the shift results of the first and second operands respectively, according to the shift direction. (Refer to...) Figure 5 As shown, it can specifically include: Step S510: Shift the first operand shift result to the left by a first shift amount to obtain a second cross value. The first shift amount is the difference between the second data bit width and the target shift amount. Step S520: Perform a bitwise OR operation on the second cross value and the shift result of the second operand to obtain the low-order operand of the shift result; Step S530: The shift result of the first operand is used as the high-order operand of the shift result.

[0105] In the case where the shift direction is right and the target shift amount is less than the second data bit width, although the overall data has not yet crossed the complete data segment boundary, some valid bits that were originally located on the low side of the high data segment have the conditions to migrate to the low data segment. The shift results of the first operand and the second operand alone cannot completely restore the bit order relationship after the overall right shift. Therefore, it is necessary to perform further compensatory shift processing on the shift results of the first operand.

[0106] The second cross value can be understood as boundary compensation data extracted from the shift result of the first operand, which should be filled into the lower-order result across segments. Its purpose is to realign the bits that originally belonged to the higher-order data segment but should have entered the lower-order data segment under the overall right shift semantics to a suitable position for combination. The first shift amount is the compensation bit number used to complete this alignment process. It is obtained from the difference between the second data bit width and the target shift amount. Essentially, it represents the number of bits that need to be reverse-compensated within the width of a complete sub-data segment, in addition to the right shift bits already completed, so that the boundary bits can fall into the corresponding positions of the lower-order data segment. For example, in the scenario where a 64-bit source operand is split into two 32-bit sub-data segments, when the target shift amount is N and satisfies 0≤N<32, the first shift amount can be 32-N.

[0107] The left shift of the first operand shift result can be achieved by a dedicated compensation shift circuit. For example, the left shift of the first operand shift result can be performed again by the bypass path of the shift operation unit, or an equivalent left shift compensation can be achieved by a multiplexer and a bit line rearrangement circuit. Of course, combinational logic can also be used to rewire the valid bits located near the boundary in the first operand shift result, as long as the alignment result with the same left shift amount can be formed. This example embodiment does not impose any special limitations on this.

[0108] The second operand shift result represents the valid content of the low-order data segment of the source operand that remains in the low-order side after the right shift; the second cross value represents the compensation data migrated across segments from the first operand shift result. In other words, under the overall right shift semantics, the low-order operand of the shift result is not simply composed of the second operand shift result independently, but is composed of the part of the low-order data segment that remains in the low-order segment after the right shift and the part of the high-order data segment that should be filled into the high-order side of the low-order segment after the right shift. The second cross value and the second operand shift result are usually complementary in the valid bit interval, so the two data can be combined bit by bit into a complete shift result low-order operand through a bitwise OR operation. Bitwise OR can be understood as a bitwise logical combination method. It performs a logical judgment on two input bits at the same position, and if either input bit is 1, the output result is 1. It's easy to understand that the second cross value mainly carries the data of the cross-segment compensation area, and the second operand shift result mainly carries the data of the original low-order data segment retention area. After the two are combined through a bitwise OR operation, the complete bit distribution of the low-order half segment in the overall right shift result can be restored. In specific implementation, this bitwise OR operation can be implemented through a parallel OR gate array, that is, performing a logical OR on each bit of the second cross value and the second operand shift result simultaneously; alternatively, invalid bits can be cleared through a mask in the data path before performing the bitwise OR operation; of course, equivalent combinational logic to the bitwise OR operation can also be implemented through multiplexers, gated bit selection circuits, or lookup tables, as long as the final data result is consistent with the result obtained by performing a bitwise OR operation on the second cross value and the second operand shift result. This example embodiment does not impose any special limitations on this. By performing a bitwise OR operation between the second cross value and the shift result of the second operand, the lower operand of the shift result can simultaneously retain local data and cross-segment migration data, thereby improving the integrity and semantic consistency of the lower half of the overall right shift result.

[0109] In scenarios where the shift direction is right and the target shift amount is less than the width of the second data bit, the high-order part formed by the overall right shift operation does not need to receive reverse compensation data from the second operand. This is because during a right shift, the data shifts towards the lower order, and the empty bit positions on the high-order side are filled with zeros in logical right shift scenarios and with sign bit expansion in arithmetic right shift scenarios. This high-order semantics is already reflected in the formation process of the first operand shift result. In other words, for small right shifts, the first operand shift result itself already fully represents the effective data content of the high-order half of the overall right shift result. Therefore, there is no need to perform additional cross-segment combination processing on it, and the first operand shift result can be directly used as the high-order operand of the shift result. By directly using the first operand shift result as the high-order operand of the shift result, unnecessary combinational logic can be avoided in the high-order part in small right shift scenarios, thereby simplifying the formation path of the high-order operand of the shift result and helping to reduce the implementation complexity of the result construction process.

[0110] By shifting the first operand's shift result to the left to form the second cross value in the right-shift scenario, and performing a bitwise OR operation with the second operand's shift result, the high-order data can be supplemented into the low-order result during the segment crossing process, thereby restoring the effect of high-order data migrating to low-order data in the right-shift operation. At the same time, using the first operand's shift result as the high-order result ensures that the high-order part maintains local shift consistency, thereby improving the accuracy of segment crossing data compensation in the right-shift scenario and ensuring the integrity of the low-order result construction.

[0111] In an example embodiment of this disclosure, when the second processing method is adopted, the following steps can be used to control at least two shift operation units to perform corresponding shift operations on the first operand and the second operand respectively, so as to obtain the shift result of the first operand and the shift result of the second operand. Specifically, this may include: The target operand can be determined from the first operand and the second operand according to the shift direction, and a shift operation with a shift amount equal to the second shift amount can be performed on the target operand to obtain the target shift value. The second shift amount is the difference between the target shift amount and the second data bit width. The shift result corresponding to the other operand is set as a preset padding value. Among them, one of the shift results of the first operand and the shift result of the second operand is the target shift value, and the other is the preset padding value.

[0112] The target operand refers to the operand that still provides the main valid data for the target shift result after the overall shift. Since the shift direction determines the migration direction of data within the overall bit width, the selection of the target operand needs to match the shift direction. When the shift direction is left, the low-order data in the source operand moves to the high-order direction, and the data in the original second operand will cross the segment boundary to enter the high-order side. Therefore, the second operand can be determined as the target operand. When the shift direction is right, the high-order data in the source operand moves to the low-order direction, and the data in the original first operand will cross the segment boundary to enter the low-order side. Therefore, the first operand can be determined as the target operand. This determination process can be implemented through control logic, for example, by outputting a selection signal through the shift control unit and having a multiplexer select between the first and second operands; or by pre-setting different input channels in the data path and directly selecting the corresponding data path according to the shift direction; or by generating control codes in the instruction decoding stage at the microarchitecture control layer to directly instruct subsequent data paths to select the corresponding operand. This embodiment does not limit the specific control method used for selecting the target operand. By clearly defining the target operands in large displacement scenarios, the range of data involved in the actual shift operation can be more concentrated, thereby reducing unnecessary data participation and data movement, and improving computational efficiency.

[0113] The second shift amount refers to the remaining shift amount that still needs to be performed within the target operand after the overall shift amount has already crossed a complete second data bit width. It can be obtained by the difference between the target shift amount and the second data bit width. For example, in a scenario where a 64-bit source operand is split into two 32-bit sub-data segments, when the target shift amount is N and N is greater than or equal to 32, the second shift amount can be N-32. In specific implementations, the shift operation of performing the second shift amount on the target operand can be completed by a shift operation unit. For example, a barrel shifter can be used to complete the shift operation of the corresponding number of bits in a single clock cycle, or a multi-stage shift structure can be used to complete the shift step by step; an equivalent shift function can also be achieved by combining shift control logic with bit line rearrangement circuitry. This embodiment does not limit the implementation structure of the shift operation.

[0114] The other operand refers to the operand that was not selected as the target operand. In the scenario corresponding to the second processing method, this operand no longer contributes the main data after the overall shift, and its corresponding result segment needs to be filled according to the shift semantics.

[0115] The preset fill value can be understood as the fill value used to fill empty bits during the shift process, and its specific value can be determined according to the shift direction and shift type. For example, in the case of logical left shift and logical right shift, an all-zero value can be used as the preset fill value; in the case of arithmetic right shift, a sign bit extension value can be used as the preset fill value, that is, the high-order sign bit is copied and extended to the entire result segment. In specific implementation, a fixed zero value can be output by a constant generation circuit, or the sign bit of the target operand can be extracted by a sign extension module and extended to generate a fill value; the corresponding fill value can also be dynamically generated by a lookup table or combinational logic. This embodiment does not limit the generation method of the preset fill value. By filling the result segment corresponding to another operand, it can be ensured that the final result conforms to the bit filling rules under different shift types, while avoiding redundant operations on invalid data.

[0116] When one of the first operand shift result and the second operand shift result is used as the target shift value, and the other as the preset padding value, it can be understood as assigning roles to the two result segments. One result segment carries the target shift value after the target operand has been processed by the second shift amount, and the other result segment carries the preset padding value. Specifically, in the left shift scenario, the target shift value can be used as the high-order result segment, and the preset padding value as the low-order result segment; in the right shift scenario, the preset padding value can be used as the high-order result segment, and the target shift value as the low-order result segment. In implementation, the target shift value and the preset padding value can be routed to their respective data output terminals through result selection logic. For example, a multiplexer can be used to selectively output the target shift value to either the high-order or low-order result path, while outputting the preset padding value to the other path; alternatively, during the result register write stage, both can be written to their respective high-order and low-order fields. This embodiment does not limit the specific mapping method of the result segments. By reasonably allocating the target shift value and the preset fill value, a complete result structure that conforms to the shift semantics can be formed in large displacement scenarios, thereby improving the accuracy and consistency of the shift result construction.

[0117] By determining the target operand based on the shift direction in the second processing method and performing the shift operation corresponding to the second shift amount, valid data after crossing the complete data segment can directly participate in the result construction. At the same time, by setting the result corresponding to the other operand to a preset fill value, invalid data segments do not need to participate in complex combination processing, thereby reducing the involvement of cross-segment combination logic. Furthermore, by dividing the result into two parts, the target shift value and the fill value, the data processing path in large displacement scenarios is further simplified, thereby reducing logical complexity and improving the execution efficiency of shift operations.

[0118] In an optional embodiment of this disclosure, the shift results of the first operand and the shift results of the second operand can be combined across data segments through the following steps, and the combined results can be concatenated to obtain the target shift result corresponding to the source operand. Specifically, this may include: When the shift direction is left, the target shift value can be used as the high-order operand of the shift result, and the preset padding value can be used as the low-order operand of the shift result; or when the shift direction is right, the preset padding value can be used as the high-order operand of the shift result, and the target shift value can be used as the low-order operand of the shift result; the high-order operand and the low-order operand of the shift result are concatenated to obtain the target shift result corresponding to the source operand.

[0119] In the left shift scenario, the target operand can be the second operand. The target shift value essentially represents the result data after the original low-order data segment crosses the segment boundary and continues to move towards the higher order. For example, in an implementation where the first data bit width is 64 bits and the second data bit width is 32 bits, when the target shift amount is N and satisfies 32 ≤ N < 64, the second shift amount M = N - 32 can be determined first, and then the second operand can be shifted left by M bits to obtain the target shift value. This target shift value can then be used as the higher order part of the final result. Correspondingly, the higher order operand of the shift result is the data result located in the higher half of the target shift result. It bears the responsibility of representing the effective information on the higher order side after the overall shift. Therefore, in this scenario, using the target shift value directly as the higher order operand of the shift result ensures that the higher half of the result maintains consistency with the semantics of the overall left shift.

[0120] In a left shift scenario, using a preset padding value as the low-order operand of the shift result is easy to understand. After the overall data has moved up a full second data bit width, the low-order side of the original result no longer retains the valid data body from the target operand, but instead consists of padding values ​​according to the left shift semantics. In a left shift scenario, this preset padding value can usually be zero to match the requirement of filling low-order empty spaces with zeros during logical left shifts. The low-order operand of the shift result is the data result in the low-order half of the target shift result. In this scenario, it corresponds to the low-order result segment that becomes empty after the overall data shifts upwards after the overall left shift. Therefore, using the preset padding value as the low-order operand of the shift result ensures that the output of the low-order half conforms to the left shift semantics.

[0121] In a right-shift scenario, since the overall right shift moves the valid bits from the original high-order segment to the low-order segment, using the target shift value as the low-order operand of the shift result allows the low-order result to directly carry the valid data information after the overall right shift. For example, in an implementation where the first data bit width is 64 bits and the second data bit width is 32 bits, when the target shift amount is N and satisfies 32 ≤ N < 64, the second shift amount M = N - 32 can be calculated first, and then the first operand can be right-shifted by M bits to obtain the target shift value, which can then be output as the low-order result.

[0122] In right-shift scenarios, the preset padding value is used as the high-order operand of the shift result. This is easily understood because after the overall data has crossed a full second data bit width towards the lower bits, the high-order side of the shift result is no longer directly composed of the original valid data body. Instead, it needs to be generated according to the high-order padding rules corresponding to the current shift type. The preset padding value here is still used to fill the data content in empty bit segments, but in right-shift scenarios, its value can differ depending on the shift type. For example, when the shift type is logical right shift, the high-order empty bits can be filled with zero; when the shift type is arithmetic right shift, the high-order empty bits can be filled with a sign bit extension value, that is, the most significant bit of the first operand is used as the sign bit and copied and extended to the entire high-order result segment. The high-order operand of the shift result is the data result located in the high-order half of the target shift result. In this scenario, it no longer undertakes the main function of moving valid data, but rather the semantic padding function of the high-order side of the result.

[0123] The high-order and low-order operands of the shift result correspond to the high-order and low-order halves of the target shift result, respectively. They can be allocated according to the shift direction and the role of the result segment; one part is formed by the target shift value, and the other part is formed by a preset padding value. Concatenation refers to placing the high-order operand of the shift result in the high-order segment and the low-order operand in the low-order segment according to their bit order, thereby reconstructing a complete result data with the first data bit width. For example, in a 64-bit source operand scenario, the high-order operand of the shift result can be used as Res_hi, and the low-order operand as Res_lo, forming Result=(Res_hi<<32)|Res_lo, thus obtaining the complete target shift result.

[0124] By mapping the target shift value and the preset fill value to the high-order operand and low-order operand of the shift result respectively according to the shift direction in the second processing method, the result construction process in large displacement scenarios can be directly allocated according to the shift direction, thereby avoiding complex cross-segment combination operations; furthermore, by concatenating the high-order operand and the low-order operand, the result can be quickly restored to the complete bit-width data, thereby improving the efficiency of result generation in large displacement scenarios and reducing data path complexity.

[0125] In one optional embodiment of this disclosure, when the shift direction is left, the second operand can be used as the target operand; or when the shift direction is right, the first operand can be used as the target operand. The specific reasons have been explained in other embodiments and will not be repeated here.

[0126] By using the second operand as the target operand in the left shift scenario and the first operand as the target operand in the right shift scenario, the selection of the target operand is kept consistent with the actual data migration direction, thereby making the data source for subsequent shift operations more accurate. Furthermore, by concentrating effective data processing on a single sub-data segment, unnecessary data participation can be reduced, thereby improving data path utilization efficiency and reducing computational redundancy.

[0127] In one optional embodiment of this disclosure, the preset fill value can be determined according to the shift direction and shift type: when the shift direction is left shift, the preset fill value is zero; when the shift direction is right shift and the shift type is logical right shift, the preset fill value is zero; when the shift direction is right shift and the shift type is arithmetic right shift, the preset fill value is the extension value of the sign bit of the first operand. The specific reasons have been explained in other embodiments and will not be repeated here.

[0128] By determining the preset padding value based on the shift direction and shift type, the padding value can be consistent with the semantics of logical left shift, logical right shift, and arithmetic right shift, thereby ensuring the correctness of the result under different shift types. Zero padding is used in left shift and logical right shift scenarios, and sign bit extension is used in arithmetic right shift scenarios, so that the result can correctly express the shift behavior of unsigned and signed data, thereby improving the semantic consistency of shift results and avoiding data distortion caused by padding errors.

[0129] In one example embodiment of this disclosure, the shift type may include at least logical left shift, logical right shift, and arithmetic right shift. If the shift type is logical left shift, the shift direction is determined to be left shift; if the shift type is logical right shift or arithmetic right shift, the shift direction is determined to be right shift.

[0130] By mapping shift types to shift directions, different shift types can be processed under a unified direction control framework, thereby achieving the separation of direction control and padding semantic control. By mapping logical left shift to left shift direction and logical right shift and arithmetic right shift to right shift direction, data migration paths can be uniformly controlled, which simplifies the control logic structure and improves the reusability of different shift types on the same hardware path.

[0131] In an optional embodiment of this disclosure, at least two shift operation units include two shifters arranged in parallel, each shifter being capable of processing data with a second data width, the first data width being 64 bits, and the second data width being 32 bits.

[0132] Among them, the two parallel shifters can be understood as two shift operation units arranged in the form of parallel data paths in the hardware structure. They respectively undertake the shift processing tasks of the first operand and the second operand. Parallel setting not only refers to the parallel arrangement in physical structure, but also includes the ability to perform shift operations on different input data simultaneously in the same clock cycle in terms of timing.

[0133] By configuring two shifters in parallel, the source operands, after being split into first and second operands, can be shifted simultaneously in independent data paths, thus avoiding the increased latency caused by serial processing. For example, in a traditional single-shifter structure, if two data segments need to be processed, the shift operation usually needs to be performed in two separate cycles. However, by configuring two shifters in parallel, the shifting of the two data segments can be completed simultaneously in one cycle, thereby improving the overall processing efficiency. In specific implementations, the two parallel shifters can be connected to different data input ports, for example, one shifter receives the first operand and the other receives the second operand; alternatively, different operands can be loaded in different time slices by sharing an input bus and coordinating with data distribution logic; or flexible data path mapping can be achieved through a crossbar network, as long as it can be ensured that the two shifters can process the corresponding operands simultaneously when needed. This implementation does not impose special limitations on whether the shifters share some control logic or some data paths.

[0134] By employing two parallel shifters, with each shifter processing data of the second data bit width, large-bit-width data shifting can be completed collaboratively by multiple small-bit-width shifters, thus avoiding the complex circuit structure resulting from designing a complete large-bit-width shifter. Furthermore, by setting the first data bit width to twice the second data bit width, the data can be evenly divided and processed in parallel, thereby reducing hardware implementation complexity and improving the parallelism and resource utilization efficiency of shift operations.

[0135] In one embodiment, a 64-bit data shift operation is used as an example. For example, assume the source operand is... It is 64-bit binary data, which can be represented as a combination of high-order and low-order bits, i.e. .in, This represents the high 32 bits of data. This represents the lower 32 bits of data; both have a bit width of 32 bits. By analyzing... By splitting the data, the original 64-bit data processing can be transformed into parallel processing of two 32-bit data segments, i.e., the first operand Second operand .

[0136] During the processing, the target displacement amount is obtained. ,in This indicates the number of bits to shift the data, and its value can be an integer between 0 and 63. It also retrieves the shift type, which can be logical left shift, logical right shift, or arithmetic right shift. The shift direction can be determined based on the shift type: when the shift type is logical left shift, the shift direction is left; when the shift type is logical right shift or arithmetic right shift, the shift direction is right.

[0137] Based on the target shift amount The size of the value determines the shifting process into two processing methods, namely when... When the shift does not cross the boundary of a complete 32-bit data segment, the first processing method is used; when When the shift has crossed the boundary of a complete 32-bit data segment, the second processing method is adopted. Through this division, different shift ranges correspond to different data processing paths.

[0138] When the first processing method is used, for and Perform shifts of respectively The shift operation can yield intermediate results. and .in, This represents the result of shifting the first operand after shifting the high-order data segment. This indicates the result of shifting the second operand after shifting the lower-order data segment.

[0139] If the shift direction is left shift, it can be represented as: , .

[0140] If the shift direction is to the right, it can be represented as: , .

[0141] After obtaining the above intermediate results, cross-segment data combination processing can be performed on the two data segments. In the left-shift scenario, cross-compensation is introduced. In the left-shift scenario, this is the first crossover value, which represents the portion supplemented from the lower-order data segment to the higher-order data segment. This can be achieved by... The first shift amount is obtained by shifting to the right by the first shift amount, which can be expressed as: The first cross value can be represented as: Then, a bitwise OR operation is performed between the first crossover value and the high-order shift result to obtain the high-order operand of the shift result, which is the new high-order part of the source operand after shifting: Meanwhile, keeping the lower-order part as the lower-order operand of the shift result, can be represented as: Through the above processing, the portion of the low-order data that overflowed during the shift process can be added to the high-order bits, thereby restoring the overall 64-bit left shift semantics.

[0142] In the right-shift scenario, cross compensation is introduced. In the right-shift scenario, this is the second crossover value: This cross-compensation amount represents the portion added from the high-order data segment to the low-order data segment. A bitwise OR operation is then performed to obtain the low-order operands of the shift result, which are the new low-order portions of the source operands after shifting. At the same time, keeping the high-order bits as the high-order operands of the shift result, it can be represented as: This process allows the overflow of high-order data during the right shift to be added to the low-order bits, thus restoring the overall right shift semantics. Ultimately, this will... and By splicing, a complete 64-bit shift result is obtained. Specifically, the splicing process can be represented as follows: .

[0143] When the second processing method is used, the second shift amount is calculated first. ,in This indicates the amount of shift required after traversing a complete 32-bit data segment. The data segment to be processed can then be determined based on the shift direction. In a left shift scenario, the selected... As the primary data segment involved in the calculation; in the right-shift scenario, select As the main data segment involved in the calculation.

[0144] In a left-shift scenario, it is possible to... Perform left shift Bitwise operations yield: At the same time, set the lower-order bits to zero: This process moves the low-order data to the high-order bits, padding the low-order bits with zeros to form a complete result.

[0145] In a right-shift scenario, if it's a logical right shift, then... Perform right shift Bitwise operations yield: At the same time, set the high-order part to zero: .

[0146] If it's an arithmetic right shift, then sign extension needs to be considered. Let... for The highest bit can be used to construct a high-bit padding value that is the data obtained by extending the sign bit, that is: Meanwhile, the lower part is: .in, This indicates that the sign bit will be copied and extended to a width of 32 bits. Finally, and By splicing the results, we obtain the final 64-position displacement result. Specifically, the splicing process can be represented as follows: .

[0147] Through the above implementation method, 64-bit data shifting can be completed by using two 32-bit shifting units in collaboration without constructing a 64-bit shifting circuit. Different processing paths can be selected according to different shift ranges, thereby achieving more efficient data shifting operations while ensuring the correctness of shift semantics.

[0148] Figure 6 The illustration schematically shows a flow diagram of data shifting of a 64-bit source operand according to some embodiments of the present disclosure.

[0149] refer to Figure 6 As shown, the process begins; Step S601: Obtain the 64-bit source operand to be processed and its associated shift operation; Step S602: Split the 64-bit source operand into a 32-bit high-order first operand val_hi and a 32-bit low-order second operand val_lo; Step S603: Analyze the shift direction and shift amount N corresponding to the shift operation; Step S604: Determine whether the shift amount N is in the interval 0 ≤ N < 32. If the shift amount N is in the range 0 ≤ N < 32, the high-order operand and low-order operand of the shift result can be determined according to the shift direction. Specifically, when the shift direction is a left shift (logical left shift or arithmetic left shift), step S605 is executed, and the high-order operand of the shift result res_hi = (val_hi << N) | (val_lo >> (32 - N)), and the low-order operand of the shift result res_lo = val_lo << N; when the shift direction is a logical right shift, step S606 is executed, the high-order operand of the shift result res_hi = val_hi >> N, and the low-order operand of the shift result res_lo = (val_lo >> N) | (val_hi << (32 - N)); when the shift direction is an arithmetic right shift, step S607 is executed, the high-order operand of the shift result res_hi = (int32_t)val_hi >> N, and the low-order operand of the shift result: res_lo = (val_lo >> N) | (val_hi << (32 - N)).

[0150] If the shift amount N is in the range 32 ≤ N < 64, the high-order operand and low-order operand of the shift result can be determined according to the shift direction. Specifically, when the shift direction is a left shift (logical left shift or arithmetic left shift), step S608 is executed, the high-order operand of the shift result res_hi = val_lo << (N - 32), and the low-order operand of the shift result: res_lo = 0; when the shift direction is a logical right shift, step S609 is executed, the high-order operand of the shift result res_hi = 0; the low-order operand of the shift result res_lo = val_hi >> (N - 32); when the shift direction is an arithmetic right shift, step S610 is executed, the high-order operand of the shift result res_hi = (val_hi & 0x80000000)? 0xFFFFFFFF:0x00000000, where 0x80000000 represents the highest bit mask in a 32-bit data, and its binary form is that the highest bit is 1 and the rest of the bits are 0, which is used to extract the sign bit. By performing the bitwise AND operation (val_hi & 0x80000000), it can be determined whether the highest bit (i.e., the sign bit) of val_hi is 0 or 1. "?0xFFFFFFFF:0x00000000" can represent an assignment using a conditional expression. If the sign bit is 1, res_hi is assigned 0xFFFFFFFF, that is, all bits are 1. If the sign bit is 0, res_hi is assigned 0x00000000, that is, all bits are 0. The low-order operand of the shift result res_lo = (int32_t)val_hi >> (N - 32).

[0151] After obtaining the high-order operand res_hi and the low-order operand res_lo of the shift result, the shift result result = ((unit64_t)res_hi<<32)|res_lo can be concatenated through step S611; finally, the process ends. It should be understood that this embodiment is merely an illustrative example and should not impose any special limitations on this embodiment.

[0152] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0153] Furthermore, in this example embodiment, a data shifting operation apparatus is also provided. (Refer to...) Figure 7 As shown, the data shifting and arithmetic device 700 includes: The input processing unit 710 is used to acquire the source operand to be processed and split the source operand into a first operand and a second operand; wherein the source operand has a first data bit width, and the first operand and the second operand have a second data bit width; The shift control unit 720 is used to acquire the shift type and target shift amount corresponding to the source operand, determine the shift direction according to the shift type, and determine the segmented shift processing method according to the target shift amount; At least two shift operation units 730, each of which can process data bit widths equal to the second data bit width, are used to perform shift operations on the first operand and the second operand respectively under the control of the shift control unit; The data combination unit 740 includes a multiplexer 741 and a logic combination circuit 742. The multiplexer 741 and the logic combination circuit 742 are used to perform cross-segment data combination and splicing on the shifted first operand and second operand to obtain the target shift result corresponding to the source operand. The shift control unit 720 is configured to enable the at least two shift operation units to collaboratively perform the shift operation of the first data bit width data.

[0154] The specific details of each module in the above-mentioned data shifting operation device have been described in detail in the corresponding data shifting operation method, so they will not be repeated here.

[0155] It should be noted that although several modules or units of the data shifting operation apparatus have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0156] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described data shifting operation method is also provided.

[0157] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be embodied in the following forms: a completely hardware embodiment, a completely software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0158] The following reference Figure 8 To describe an electronic device 800 according to such an embodiment of the present disclosure. Figure 8 The electronic device 800 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0159] like Figure 8 As shown, the electronic device 800 is presented in the form of a general-purpose computing device. The components of the electronic device 800 may include, but are not limited to: at least one processing unit 810, at least one storage unit 820, a bus 830 connecting different system components (including storage unit 820 and processing unit 810), and a display unit 840.

[0160] The storage unit stores program code that can be executed by the processing unit 810, causing the processing unit 810 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, the processing unit 810 can perform actions such as... Figure 1In step S110, the source operand to be processed is obtained, and the source operand is split into at least two sub-operands; wherein the source operand has the first data bit width, and each of the sub-operands has the second data bit width; in step S120, according to the shift type and target shift amount corresponding to the source operand, the at least two shift operation units are controlled to perform corresponding shift operations on the at least two sub-operands respectively to obtain at least two operand shift results; in step S130, the shift results of the at least two operands are subjected to cross-segment data combination processing, and the combined results are spliced ​​to obtain the target shift result corresponding to the source operand. The cross-segment data combination processing refers to the process of reconstructing the data between the shift results of the operands after segmented shifting.

[0161] Storage unit 820 may include readable media in the form of volatile storage units, such as random access memory (RAM) 821 and / or cache memory (Cache) 822, and may further include read-only memory (ROM) 823.

[0162] The storage unit 820 may also include a program / utility 824 having a set (at least one) of program modules 825, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0163] Bus 830 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0164] Electronic device 800 can also communicate with one or more external devices 870 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 800, and / or with any device that enables electronic device 800 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 850. Furthermore, electronic device 800 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 860. As shown, network adapter 860 communicates with other modules of electronic device 800 via bus 830. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0165] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0166] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0167] refer to Figure 9 As shown, a program product 900 for implementing the above-described data shifting operation method according to an embodiment of the present disclosure is described. This product may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0168] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0169] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0170] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0171] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0172] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of this disclosure and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0173] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0174] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0175] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A data shifting operation method, characterized in that, An electronic device having at least two shift operation units, wherein the maximum data bit width processed by the shift operation units is less than a first data bit width and greater than or equal to a second data bit width, the method comprising: Obtain the source operand to be processed, and split the source operand into at least two sub-operands; wherein the source operand has the first data bit width, and each of the sub-operands has the second data bit width; Based on the shift type and target shift amount corresponding to the source operand, control the at least two shift operation units to perform corresponding shift operations on the at least two sub-operands respectively, and obtain the shift results of at least two operands; The shift results of the at least two operands are combined across segments, and the combined results are then concatenated to obtain the target shift result corresponding to the source operand. The cross-segment data combination process refers to the process of reconstructing the data between the shift results of the operands after segmented shifting.

2. The method according to claim 1, characterized in that, The step of controlling at least two shift operation units to perform corresponding shift operations on at least two sub-operands respectively, based on the shift type and target shift amount corresponding to the source operand, to obtain shift results for at least two operands, includes: The shift direction is determined according to the shift type corresponding to the source operand, and the segmented shift processing method corresponding to the source operand is determined according to the target shift amount corresponding to the source operand. The segmented shift processing method is used to enable the at least two shift operation units to cooperate in completing the overall shift operation of the source operand. Based on the shift direction, the target shift amount, and the segmented shift processing method, the at least two shift operation units are controlled to perform corresponding shift operations on the at least two sub-operands respectively, so as to obtain the shift results of at least two operands.

3. The method according to claim 2, characterized in that, The segmented shift processing method includes a first processing method and a second processing method. The first processing method is used to select a data processing path in which each operand is shifted independently and combined across segments when the target shift amount does not cross the boundary of the complete data segment. The second processing method is used to select a data processing path in which some operands are shifted and filled when the target shift amount crosses the boundary of the complete data segment. The step of determining the segmented shift processing method corresponding to the source operand based on the target shift amount corresponding to the source operand includes: Compare the target shift amount with the second data bit width; If the target shift amount is less than the second data bit width, then the first processing method is determined to be used; If the target shift amount is greater than or equal to the second data bit width, then the second processing method is determined to be used.

4. The method according to claim 3, characterized in that, The at least two sub-operands include a first operand and a second operand, and the shift result of the at least two operands includes the shift result of the first operand and the shift result of the second operand; When the first processing method is adopted, controlling the at least two shift operation units to perform corresponding shift operations on the at least two sub-operands respectively, and obtaining the shift results of at least two operands, includes: According to the shift direction, a shift operation with a shift amount equal to the target shift amount is performed on the first operand and the second operand respectively to obtain the shift result of the first operand and the shift result of the second operand.

5. The method according to claim 4, characterized in that, The step of performing cross-segment data combination processing on the shift results of the at least two operands, and concatenating the combined results to obtain the target shift result corresponding to the source operand, includes: A cross-shift operation is performed on the first operand shift result and the second operand shift result, and the result of the cross-shift operation is logically combined with the first operand shift result and the second operand shift result respectively according to the shift direction to generate the high-order operand and the low-order operand of the shift result; The high-order operands and low-order operands of the shift result are concatenated to obtain the target shift result corresponding to the source operand.

6. The method according to claim 5, characterized in that, When the shift direction is left shift, the step of performing a cross-shift operation on the shift results of the first operand and the second operand, and logically combining the result of the cross-shift operation with the shift results of the first operand and the second operand according to the shift direction, includes: The second operand shift result is shifted to the right by a first shift amount to obtain a first cross value, where the first shift amount is the difference between the second data bit width and the target shift amount; Perform a bitwise OR operation on the first cross value and the shift result of the first operand to obtain the high-order operand of the shift result; The result of shifting the second operand is used as the lower operand of the shift result.

7. The method according to claim 5, characterized in that, When the shift direction is right shift, the step of performing a cross-shift operation on the shift results of the first operand and the second operand, and logically combining the result of the cross-shift operation with the shift results of the first operand and the second operand according to the shift direction, includes: The first operand shift result is shifted to the left by a first shift amount to obtain the second cross value, where the first shift amount is the difference between the second data bit width and the target shift amount; Perform a bitwise OR operation on the second cross value and the shift result of the second operand to obtain the low-order operand of the shift result; The result of shifting the first operand is used as the high-order operand of the shift result.

8. The method according to claim 3, characterized in that, The at least two sub-operands include a first operand and a second operand, and the shift result of the at least two operands includes the shift result of the first operand and the shift result of the second operand; When the second processing method is adopted, the control of the at least two shift operation units to perform corresponding shift operations on the at least two sub-operands respectively, to obtain the shift results of at least two operands, including: According to the shift direction, a target operand is determined from the first operand and the second operand, and a shift operation with a shift amount of the second shift amount is performed on the target operand to obtain a target shift value, wherein the second shift amount is the difference between the target shift amount and the second data bit width; Set the shift result corresponding to the other operand to the preset padding value; Wherein, one of the first operand shift result and the second operand shift result is the target shift value, and the other is the preset fill value.

9. The method according to claim 8, characterized in that, The step of performing cross-segment data combination processing on the shift results of the at least two operands, and concatenating the combined results to obtain the target shift result corresponding to the source operand, includes: When the shift direction is left shift, the target shift value is used as the high-order operand of the shift result, and the preset fill value is used as the low-order operand of the shift result; or When the shift direction is right shift, the preset fill value is used as the high-order operand of the shift result, and the target shift value is used as the low-order operand of the shift result. The high-order operands and low-order operands of the shift result are concatenated to obtain the target shift result corresponding to the source operand.

10. The method according to claim 8, characterized in that, Determining the target operand from the first operand and the second operand according to the shift direction includes: When the shift direction is left shift, the second operand is used as the target operand; or When the shift direction is right shift, the first operand is used as the target operand.

11. The method according to claim 8 or 9, characterized in that, The preset fill value is determined based on the shift direction and the shift type: When the shift direction is leftward, the preset fill value is zero; When the shift direction is right shift and the shift type is logical right shift, the preset fill value is zero; When the shift direction is right shift and the shift type is arithmetic right shift, the preset fill value is the extension value of the sign bit of the first operand.

12. The method according to claim 2, characterized in that, The shift types include at least logical left shift, logical right shift, and arithmetic right shift; determining the shift direction based on the shift type corresponding to the source operand includes: If the shift type is logical left shift, then the shift direction is determined to be left shift; If the shift type is a logical right shift or an arithmetic right shift, then the shift direction is determined to be a right shift.

13. The method according to claim 1, characterized in that, The at least two shift operation units include two shifters arranged in parallel, and each shifter processes data with a data bit width of the second data bit width; the first data bit width is 64 bits, and the second data bit width is 32 bits.

14. A data shifting and arithmetic device, characterized in that, include: An input processing unit is configured to acquire a source operand to be processed and split the source operand into at least two sub-operands; wherein the source operand has a first data bit width and each of the sub-operands has a second data bit width; A shift control unit is used to acquire the shift type and target shift amount corresponding to the source operand, determine the shift direction according to the shift type, and determine the segmented shift processing method according to the target shift amount; At least two shift operation units, each shift operation unit processing data with a data bit width of the second data bit width, are used to perform shift operations on the at least two sub-operands respectively under the control of the shift control unit; The data combination unit includes a multiplexer and a logic combination circuit. The multiplexer and the logic combination circuit are used to perform cross-segment data combination and concatenation on at least two shifted suboperands to obtain the target shift result corresponding to the source operand. The shift control unit is configured to enable the at least two shift operation units to collaboratively perform shift operations on the source operands of the first data bit width.

15. An electronic device, characterized in that, include: processor; as well as A memory storing computer-readable instructions that, when executed by the processor, implement the data shifting operation method as described in any one of claims 1 to 13.

16. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the data shifting operation method as described in any one of claims 1 to 13.

Images