Radio frequency communication

Abstract

An apparatus can include a resonator configured to oscillate at a resonant frequency; and a first oscillator core and a second oscillator core coupled to the resonator in a parallel configuration; wherein the first oscillator core is configured to drive the resonator by providing a first drive signal and generate a first oscillator signal based on oscillation of the resonator; and wherein the second oscillator core is configured to drive the resonator by providing a second drive signal and generate a second oscillator signal based on oscillation of the resonator.

Description

Background Technology

[0001] In wireless communication networks based on various wireless communication technologies such as Wireless Local Area Networks (WLAN or Wi-Fi), Bluetooth, 4th Generation Long Term Evolution (LTE), and 5th Generation (5G) New Radio (NR), various approaches are employed to provide wireless data transmission with the required efficiency, speed, and reliability. These networks require robust design and implementation of radio frequency (RF) components to achieve the desired performance characteristics, including low power consumption, high bandwidth, and minimal interference. The successful development and operation of these technologies may depend on the design and implementation of the RF components.

[0002] One of the core elements associated with these RF components can be the generation of a reference clock, which may enable the operation of the communication device to be synchronized and stabilized with the generation of the RF signal. Specifically, RF communication circuits such as those supporting Wi-Fi, Bluetooth, and wide-area wireless networks may require precise clock signals for their functionality. These circuits may typically include components such as resonators (e.g., quartz crystal resonators) and oscillator cores to generate the necessary reference clock signal. The design and implementation of these components can affect the overall performance, cost, and complexity of the wireless system. Attached Figure Description

[0003] In the accompanying drawings, similar reference numerals throughout the different views generally refer to the same components. The drawings are not necessarily drawn to scale; rather, the emphasis is usually on illustrating the principles described herein. In the following description, various aspects are described with reference to the following drawings, wherein: Figure 1 and Figure 2 A general network and device architecture for wireless communication and / or sensing operations is described; Figure 3 Exemplary illustrations of various communication elements of a device for a wireless communication equipment are shown; Figure 4 An exemplary diagram of the transmission path of an RF transceiver is shown; Figure 5 A block diagram of a communication circuit including two transceivers is shown; Figure 6 A communication circuit for implementing a cascaded clock signal configuration is shown; Figure 7 An illustrative embodiment of a communication circuit according to various aspects described herein is shown; Figure 8 An illustrative embodiment of a circuit according to various aspects described herein is shown; Figure 9 A simplified equivalent circuit based on the various aspects described herein is shown; Figure 10An embodiment of a circuit configuration according to the various aspects described herein is shown; Figure 11 A schematic embodiment of the equivalent circuit configuration according to the various aspects described herein is shown; Figure 12 A multi-band wireless communication circuit is shown; Figure 13 This illustrates a multiple-input multiple-output (MIMO) communication circuit. Figure 14 An embodiment of the method is shown. Detailed Implementation

[0004] The following detailed description refers to exemplary details and accompanying drawings in which the aspects described herein can be practiced.

[0005] In wireless communication networks utilizing various wireless communication technologies, achieving the required efficiency, speed, and reliability for wireless data transmission is essential. These networks employ various methods to meet the growing demand for high-speed data transmission while maintaining low power consumption and minimal interference. RF communication circuitry forms the backbone of these networks, enabling the transmission and reception of wireless signals across different frequencies and bands. Specifically, circuitry including resonators such as quartz crystal resonators and multiple oscillator cores can be crucial for generating accurate reference clock signals. These reference clocks synchronize the operation of transceiver integrated circuits within the wireless system, ensuring accurate timing and coordination between various communication protocols.

[0006] Wireless systems similar to Wi-Fi, Bluetooth, and wide-area wireless networks may include multiple transceiver integrated circuits to support multi-link and / or multi-band operation. This configuration allows devices to handle multiple communication channels or frequencies simultaneously, improving data throughput and reliability. Furthermore, some wireless system implementations may include multiple transceiver integrated circuits supporting multiple-input multiple-output (MIMO) operation, where each integrated circuit can support a single spatial stream. MIMO technology enables the simultaneous transmission and reception of more than one data signal on the same wireless channel using multiple antennas and transceivers, thereby improving the capacity and performance of wireless communication systems.

[0007] Each transceiver integrated circuit (IC) typically requires a reference clock oscillator, which may demonstrably include a quartz crystal resonator connected to an active oscillator core that can be integrated within the transceiver IC. The quartz crystal resonator provides a stable frequency reference, while the oscillator core amplifies and sustains the oscillation. This combination ensures that the individual transceiver ICs are synchronized and operate with the necessary timing accuracy. However, including multiple transceiver ICs may require multiple quartz crystal resonators, each connected to its corresponding IC.

[0008] This requirement can lead to increased system cost and size. Each additional quartz crystal resonator can increase material costs and occupy physical space on the circuit board. In compact devices where space is critical, such as smartphones and wearables, minimizing the number and size of components can be crucial. Furthermore, it is sometimes necessary to synchronize the reference clocks of different transceiver integrated circuits for appropriate operation, especially in MIMO configurations. Synchronization ensures the coherent combination of multiple data streams sent and received by different integrated circuits to maximize the benefits of MIMO technology. To achieve this synchronization, utilizing separate quartz crystal resonators can add additional system complexity, increase implementation costs, and contribute to higher power consumption.

[0009] To address these challenges, one approach might involve defining a master reference clock generator (also known as a clock cascade) within one of the transceiver integrated circuits. This master IC is connected to a single crystal resonator and generates a reference clock signal. The clock signal is then cascaded or daisy-chained to other transceiver integrated circuits. This approach reduces the number of crystal resonators required; however, it introduces new complexities.

[0010] Another approach could involve connecting a quartz crystal resonator to multiple integrated circuits, where one of the integrated circuits acts as an oscillator and the other integrated circuits can use the signal as an external clock. This configuration eliminates the need for each integrated circuit to have its own quartz crystal resonator, potentially reducing cost and scalability. However, both approaches may have significant drawbacks that can impact system performance and efficiency.

[0011] Even when the main transceiver is deactivated for data processing, clock cascading may require activating the reference clock generator in the main transceiver IC. This necessity can increase system complexity in terms of power and control flow management. The system must ensure that the main IC remains powered and operates independently to provide clock signals to other ICs, which may not be efficient from a power consumption perspective. Especially when the main IC is not used in other ways, continued activation can lead to unnecessary energy expenditure.

[0012] Furthermore, clock cascading may require the addition of clock output buffers to drive the reference clock from the master transceiver IC to other transceiver ICs. These buffers can increase the pin count of the transceiver ICs, increase the complexity of the IC design, and potentially increase manufacturing costs. The additional pins and circuitry occupy more space on the ICs and circuit boards, which may be undesirable in compact device designs. Moreover, driving clock signals through buffers and via interconnects can degrade clock quality. Problems such as clock phase noise (jitter) may occur, and clock harmonic spurious emissions may be introduced as the clock is passed from one IC to another. These degradations can negatively impact the performance and reliability of wireless communication systems, potentially leading to data errors or reduced communication efficiency.

[0013] Connecting a quartz crystal resonator to an integrated circuit operating as an oscillator, while other integrated circuits use the signal as an external clock, presents several challenges. This setup can result in degraded phase noise performance compared to a single integrated circuit. This degradation can occur due to the higher parasitic capacitance load from connecting multiple integrated circuits to the same quartz crystal resonator. The increased load can affect the oscillator's ability to maintain a stable and accurate frequency. Furthermore, the oscillator core may not provide sufficient drive level to handle the increased load, potentially further compromising clock signal integrity. Insufficient drive level can lead to weaker oscillations, making the system more susceptible to interference and degrading overall signal quality.

[0014] These drawbacks may highlight the need for improvements that can reduce system cost and size without introducing significant complexity or performance degradation. Based on the aspects described herein, circuitry can be provided that includes multiple oscillator cores (e.g., transceiver integrated circuits) connected in parallel to multiple transceivers, with resonators (e.g., a single resonator, such as a single quartz crystal resonator). By activating one or more oscillator cores or transceivers, the circuitry can generate a shared and synchronized reference clock. This configuration allows for flexibility in system operation, enabling the individual activation of any transceiver while maintaining synchronization across the system. For practical reasons such as routing constraints and parasitic capacitance, the aspects described herein may work best in the case of two transceivers coupled to a resonator; however, this should not be considered a limitation. The physical layout of the circuit board can thus limit the feasibility of connecting more than two integrated circuits without introducing excessive parasitic effects. However, the aspects described herein can also be applied to more than two transceivers, especially in low-frequency oscillators and systems that may require moderate or compromised phase noise (jitter) performance. In applications where ultra-high precision may not be critical, extending the concept to multiple integrated circuits can provide acceptable performance while still offering the benefits of reduced cost and scale.

[0015] By connecting a quartz crystal resonator in parallel to multiple oscillator cores, the circuit can utilize the combined drive capability of the activated oscillator cores. Each additional activated oscillator core increases the drive level of the quartz crystal resonator, which can contribute to overcoming parasitic losses and maintaining clock quality, such as phase noise (jitter). The increased drive level enhances the oscillation amplitude, making the clock signal more robust to interference and ensuring stable operation across connected integrated circuits.

[0016] The aspects described herein can allow the use of a single rotator (e.g., a single quartz crystal oscillator) for multiple transceivers, potentially reducing overall solution cost and size. These aspects may not require additional pins to the transceivers, simplifying integrated circuit design and potentially reducing manufacturing costs. By avoiding extra pins and external buffers, the circuitry can maintain a compact form factor, which can be beneficial for space-constrained devices. Furthermore, the aspects described herein can potentially activate any transceiver independently of each other while minimizing overall system complexity, control flow, and power consumption. This independence allows for flexible system operation, where individual transceivers (e.g., transceiver ICs) can be powered down when not in use, saving energy without interrupting synchronized clock signals.

[0017] In some cases, the signal waveform at the interface port between the quartz crystal resonator and the oscillator core can be a clipped sine wave. Compared to the square wave clock, which is typically used for clock cascading between different transceiver integrated circuits, this waveform can have lower harmonic emissions and interference. Lower harmonic emissions reduce the potential for interference with other system components and improve the overall system's electromagnetic compatibility (EMC). By minimizing electromagnetic interference, the system can achieve better overall performance and reliability.

[0018] The aspects described herein can be particularly beneficial in implementations of devices such as mobile phones, tablets, and Internet of Things (IoT) devices where space and power consumption are critical considerations. In these applications, reducing the number of components and simplifying circuit design can provide significant advantages in manufacturing and user experience.

[0019] The apparatus and methods described herein can utilize or relate to wireless communication technologies. While some embodiments may refer to specific wireless communication technologies, the embodiments provided herein can also be applied to a variety of other existing and undeveloped wireless communication technologies, particularly where these technologies share similar features as disclosed with respect to the following embodiments. Various exemplary wireless communication technologies that can be utilized by the apparatus and methods described herein include, but are not limited to: Global System for Mobile Communications (“GSM”) wireless communication technology, General Packet Radio Service (“GPRS”) wireless communication technology, Enhanced Data Rate GSM Evolution (“EDGE”) wireless communication technology, and / or 3rd Generation Partnership Project (“3GPP”) wireless communication technologies, such as Universal Mobile Telecommunications System (“UMTS”), Freedom of Multimedia Access (“FOMA”), 3GPP Long Term Evolution (“LTE”), 3GPP Long Term Evolution-Advanced (“LTE-Advanced”), Code Division Multiple Access 2000 (“CDMA2000”), Cellular Digital Packet Data (“CDPD”), Mobitex, and 3GPP. (3G), Circuit Switched Data (“CSD”), High-Speed ​​Circuit Switched Data (“HSCSD”), Universal Mobile Telecommunications System (“3G”) (“UMTS(3G)”), Wideband Code Division Multiple Access (Universal Mobile Telecommunications System) (“W-CDMA(UMTS)”), High-Speed ​​Packet Access (“HSPA”), High-Speed ​​Downlink Packet Access (“HSDPA”), High-Speed ​​Uplink Packet Access (“HSUPA”), Enhanced High-Speed ​​Packet Access (“HSPA+”), Universal Mobile Telecommunications System-Time Division Duplex (“UMTS-TDD”), Time Division-Code Division Multiple Access (“TD-CDMA”), Time Division-Synchronous Code Division Multiple Access (“TD-CDMA”), 3GPP Version 8 (quasi-4G) (“3GPP”) 3GPP Rel.8 (Pre-4G), 3GPP Rel.9 (3rd Generation Partnership Project Version 9), 3GPP Rel.10 (3rd Generation Partnership Project Version 10), 3GPP Rel.11 (3rd Generation Partnership Project Version 11), 3GPP Rel.12 (3rd Generation Partnership Project Version 12), 3GPP Rel.13 (3rd Generation Partnership Project Version 13), 3GPP Rel.14 (3rd Generation Partnership Project Version 14), 3GPP Rel.15 (3rd Generation Partnership Project Version 15), 3GPP Rel.16 (3rd Generation Partnership Project Version 16), 3GPP Rel.17 (3rd Generation Partnership Project Version 17), 3GPP Rel.18 (Pre-4G), 3GPP Rel.19 (Pre-4G), 3GPP Rel.10 (Pre-4G), 3GPP Rel.11 (Pre-4G), 3GPP Rel.12 (Pre-4G), 3GPP Rel.13 (Pre-4G), 3GPP Rel.14 (Pre-4G), 3GPP Rel.15 (Pre-4G), 3GPP Rel.16 (Pre-4G), 3GPP Rel.17 (Pre-4G ...18 (Generation 3 Partnership Program Version 18), 3GPP 4G, 3GPP LTE Extra, LTE-Advanced Pro, LTE Licensed Assisted Access (“LAA”), MuLTEfire, UMTS Terrestrial Radio Access (“UTRA”), Evolved UMTS Terrestrial Radio Access (“E-UTRA”), Long Term Evolution (4th Generation) (“LTE Advanced (4G)”), cdmaOne (“2G”), Code Division Multiple Access 2000 (3rd Generation) (“CDMA2000 (3G)”), Evolved Data Optimized or Data-Only Evolution (“EV-DO”), Advanced Mobile Phone Systems (1st Generation) (“AMPS (1G)”), Total Access Communications Deployment / Extended Total Access Communications Deployment (“TACS / ETACS”), Digital AMPS (2nd Generation) (“D-AMPS (2G)”), Push-to-Talk (“PTT”), Mobile Phone Systems (“MTS”), Improved Mobile Phone Systems (“IMTS”), Advanced Mobile Phone Systems (“AMTS”), OLT (Norwegian “Offentlig Landmobil”) Telefoni (local public land mobile phone), MTD (abbreviation of Swedish "Mobiltelefonisystem D", or mobile phone system D), Public Automated Land Mobile ("Autotel / PALM"), ARP (Finnish "Autoradiopuhelin", "vehicle radiophone"), NMT (Nordic Mobile Telephone), NTT High Capacity Version ("Hicap"), Cellular Digital Packet Data ("CDPD"), Mobitex, DataTAC, Integrated Digital Enhanced Network ("iDEN"), Personal Digital Cellular ("PDC"), Circuit Switched Data ("CSD"), Personal Handheld Telephone System ("PHS"), Broadband Integrated Digital Enhanced Network ("WiDEN"), iBurst, Unlicensed Mobile Access ("UMA") (also known as 3GPP Universal Access Network or GAN standard), Zigbee. The Wireless Gigabit Alliance (“WiGig”) standard, general millimeter wave standards (wireless systems operating in the 10-300 GHz and above, such as WiGig, IEEE 802.11ad, IEEE 802.11ay, etc.), technologies operating in the 300 GHz and above and terahertz bands, vehicle-to-vehicle (“V2V”), vehicle-to-everything (“V2X”), vehicle-to-infrastructure (“V2I”) and infrastructure-to-vehicle (“I2V”) communication technologies (based on 3GPP / LTE or IEEE 802.11p and others), 3GPP cellular V2X, DSRC (Dedicated Short Range Communication) communication deployments such as intelligent transportation systems, and other existing, developing, or future wireless communication technologies.

[0020] The apparatus and methods described herein can utilize the wireless communication technology according to various spectrum management schemes, including but not limited to, dedicated licensed spectrum, unlicensed spectrum, (licensed) shared spectrum (such as licensed shared access in LSA = 2.3-2.4 GHz, 3.4-3.6 GHz, 3.6-3.8 GHz and other frequencies, and spectrum access systems in SAS = 3.55-3.7 GHz and other frequencies), and can use various spectrum bands, including but not limited to, IMT (International Mobile Telecommunications) spectrum (including 450-470 MHz, 690-960 MHz, 1710-2025 MHz, 2110-2200 MHz, 2300-2400 MHz, 2500-2690 MHz, 698-790 MHz, 610-790 MHz, 3400-3600 MHz, etc., wherein, Some frequency bands may be limited to specific regions and / or countries), IMT-Advanced spectrum, IMT-2020 spectrum (expected to include the 3600-3800MHz, 3.5GHz, 600MHz, and 24.25-86GHz bands, etc.), spectrum available under the FCC's "Spectrum Frontier" 4G initiative (including 27.5-28.35GHz, 29.1-29.25GHz, 31-31.3GHz, 37-38.6GHz, 38.6-40GHz, 42-42.5GHz, 47-64GHz, 64-71GHz, 61-76GHz, 81-86GHz, and 92-94GHz, etc.), 4.9GHz (typically 4.85-5.925GHz) and 63-64GHz ITS (Intelligent Transportation Systems) bands, such as WiGig The frequency bands currently allocated to WiGig, including Band 1 (57.24-59.40 GHz), WiGig Band 2 (59.40-61.56 GHz), WiGig Band 3 (61.56-63.72 GHz), and WiGig Band 4 (63.72-65.88 GHz); the 60.2 GHz-71 GHz band; any band between 65.88 GHz and 61 GHz; bands currently allocated to automotive radar applications, such as 66-81 GHz; and future bands including 94-300 GHz and above. Furthermore, the apparatus and methods described herein can also secondaryly employ wireless communication technologies in frequency bands such as TV vacant bands (typically below 690 MHz), where, for example, 400 MHz and 600 MHz are potential candidate bands. In addition to cellular applications, specific applications for vertical markets can be addressed, such as PMSE (Programming, Special Events), medical, healthcare, surgical, automotive, low-latency, and drone applications.Furthermore, the apparatus and methods described herein can also be used for hierarchical applications of wireless communication technologies based on priority access to the spectrum, such as by introducing a hierarchical architecture with priority for different types of users, for example, Level 1 users have the highest priority, followed by Level 2, then Level 3, and so on. The apparatus and methods described herein are also capable of using wireless communication technologies with different single-carrier or OFDM variants (CP-OFDM, SC-FDMA, SC-OFDM, filter bank-based multicarrier (FBMC), OFDMA, etc.) and, for example, 3GPP NR (New Radio) technologies that can include allocating OFDM carrier data bit vectors to corresponding symbol resources.

[0021] The wireless communication technologies described herein can be categorized as either short-range wireless communication technologies or cellular wide-area wireless communication technologies. Short-range wireless communication technologies may include Bluetooth, WLAN (e.g., conforming to any IEEE 802.11 standard), and other similar wireless communication technologies. Cellular wide-area wireless communication technologies may include Global System for Mobile Communications (“GSM”), Code Division Multiple Access 2000 (“CDMA2000”), Universal Mobile Telecommunications System (“UMTS”), Long Term Evolution (“LTE”), General Packet Radio Service (“GPRS”), Evolved Data Optimized (“EV-DO”), Enhanced Data Rate GSM Evolution (“EDGE”), High Speed ​​Packet Access (HSPA; including High Speed ​​Downlink Packet Access (“HSDPA”)), High Speed ​​Uplink Packet Access (“HSUPA”), Enhanced HSDPA (“HSDPA+”), and Enhanced HSUPA (“HSUPA+”), Global Microwave Access Interoperability (“WiMax”) (e.g., conforming to the IEEE 802.16 wireless communication standard, e.g., WiMax Fixed or WiMax Mobile), and other similar wireless communication technologies. Cellular wide-area wireless communication technology also includes "small cells" of this technology, such as microcells, femtocells, and picocells. Here, cellular wide-area wireless communication technology can often be referred to as "cellular" communication technology.

[0022] In the context of WLAN, the apparatus and methods described herein can be used in various wireless devices, including access points (APs) and wireless station devices (STAs), each equipped with radio frequency (RF) communication capabilities. These devices can integrate transmitting and receiving components designed to process RF signals within the specified bandwidths and channels described herein. The communication components typically include hardware elements and software implementations for signal processing, capable of modulation and demodulation according to specified communication protocols. These devices can be specifically configured to operate according to various wireless communication standards, including those developed by the Institute of Electrical and Electronics Engineers (IEEE) for Wi-Fi applications. The RF components, in conjunction with an antenna system, enable communication across multiple frequency bands. These bands may include the 2.4 GHz band supporting protocols such as IEEE 802.11b / g / n / ax, the 5 GHz band supporting IEEE 802.11n / ac / ax / be, and the 6 GHz band supporting newer standards like IEEE 802.11ax / be, as well as other bands. Additional operating frequencies can be extended to 60 GHz (supporting IEEE 802.11ad / ay) and 800 MHz (supporting IEEE 802.11ah) using antenna systems capable of operating at frequencies such as 28 GHz and 40 GHz. In addition to these specified standards, the device can support emerging Wi-Fi protocols and alternative wireless communication technologies. These alternative technologies may include, but are not limited to, Bluetooth, dedicated short-range communication systems, UHF applications (including IEEE 802.11af and IEEE 802.22), and white-band frequency utilization. The RF receiver chain typically integrates all necessary components configured to ensure effective wireless communication capabilities, such as low-noise amplifiers, signal amplification stages, analog-to-digital converters, data buffering mechanisms, and digital baseband processing units.

[0023] Figure 1 and Figure 2 A general network and / or device architecture for wireless communication and / or sensing operations is described. Specifically, Figure 1An exemplary wireless communication network 100 is illustrated, which may include terminal devices 102 and 104 and network access points 110 and 120 (e.g., wireless access nodes) according to some aspects. The wireless communication network 100 can communicate with terminal devices 102 and 104 via network access nodes 110 and 120 through the wireless access network. Each of terminal devices 102 and 104 or network access nodes 110 and 120 may be a sensing communication device capable of performing sensing operations as described herein. Although the specific embodiments described herein may be referenced to a specific wireless access network context (e.g., 6G, 5G NR, LTE, UMTS, GSM, other 3GPP networks, WLAN / WiFi, Bluetooth, millimeter wave, etc.), these embodiments are indicative and can therefore be readily applied to any other type or configuration of wireless access network. The number of network access nodes and terminal devices in the wireless communication network 100 is exemplary and can be scaled to any number.

[0024] In an exemplary cellular context, network access nodes 110 and 120 can be base stations (e.g., eNodeB, NodeB, Base Transceiver Station (BTS), gNodeB, or any other type of base station), while terminal devices 102 and 104 can be cellular terminal devices (e.g., Mobile Station (MS), User Equipment (UE), or any type of cellular terminal device). Therefore, network access nodes 110 and 120 can interface with (e.g., via a backhaul interface) a cellular core network, such as an evolved packet core network (EPC for LTE), a core network (CN for UMTS), or other cellular core networks that can also be considered part of the wireless communication network 100. The cellular core network can interface with one or more external data networks. In an exemplary short-range context, network access nodes 110 and 120 can be access points (APs, e.g., WLAN or WiFi APs), while terminal devices 102 and 104 can be short-range terminal devices (e.g., stations (STAs)). Network access nodes 110 and 120 can interface with one or more external data networks (e.g., via internal or external routers). Network access nodes 110 and 120 and terminal devices 102 and 104 may include one or more transmit / receive points (TRPs).

[0025] Network access nodes 110 and 120 (and optionally, Figure 1 Other network access nodes of the wireless communication network 100 (not explicitly shown in the text) can accordingly provide information to terminal devices 102 and 104 (and optionally, Figure 1Other terminal devices in the wireless communication network 100 (not explicitly shown) are provided with wireless access networks. In an exemplary cellular context, the wireless access networks provided by network access nodes 110 and 120 may enable terminal devices 102 and 104 to wirelessly access the core network via wireless communication. The core network may provide exchange, routing, and transmission of traffic data related to terminal devices 102 and 104, and may further provide access to various internal data networks (e.g., control nodes, routing nodes for transmitting information between other terminal devices on the wireless communication network 100, etc.) and external data networks (e.g., data networks providing voice, text, multimedia (audio, video, images), and other Internet and application data). Furthermore, terminal devices 102 and 104 and network access nodes 110 and 120 may perform sensing operations according to the JCAS architecture, specifically, performing radar sensing. In an exemplary short-range context, the wireless access network provided by network access nodes 110 and 120 can provide access to internal data networks (e.g., for transmitting data between terminal devices connected to wireless communication network 100) and external data networks (e.g., data networks providing voice, text, multimedia (audio, video, images), and other Internet and application data).

[0026] According to the various aspects described herein, network access nodes 110 and 120 and terminal devices 102 and 104 perform their respective sensing operations in a manner that allows each device to perform its respective sensing operation based on its respective sensing signal configuration. Accordingly, each of these devices can generate and transmit its respective sensing signal according to a corresponding configuration, which may include at least one of the following: frequency resources for transmitting the sensing signal, bandwidth of the sensing signal, transmission power of the sensing signal, and waveform shape of the sensing signal that the respective device can determine before generating and / or transmitting the sensing signal. In some embodiments, a central orchestrator (e.g., a sensing orchestrator) can determine the respective sensing signal configuration for each device and transmit information representing the respective sensing signal configuration to the respective device.

[0027] The radio access network and core network of wireless communication network 100 (e.g., if applicable in a cellular context) can be managed by a communication protocol that can be modified according to the specific circumstances of wireless communication network 100. This communication protocol can define the scheduling, formatting, and routing of user and control data traffic through wireless communication network 100, including defining the transmission and reception of this data through the radio access and core network domains of wireless communication network 100. Accordingly, terminal devices 102 and 104 and network access nodes 110 and 120 can transmit and receive data through the radio access network domain of wireless communication network 100 according to the defined communication protocol, while the core network can route data within and outside the core network according to the defined communication protocol. Exemplary communication protocols include any 6G, 5G NR, LTE, UMTS, GSM, WiMAX, Bluetooth, WiFi, millimeter wave, etc., that can be applied to wireless communication network 100.

[0028] Figure 2 An exemplary internal configuration of a communication device (e.g., a sensing communication device) according to the various aspects described herein is illustrated. The communication device may also include aspects of a wireless communication device (e.g., network access nodes 110, 120) or a mobile wireless communication device (e.g., terminal devices 102, 104). Communication device 200 may include an antenna system 202, a radio frequency (RF) transceiver 204, a baseband modem 206 (including a digital signal processor 208 and a protocol controller 210), an application processor 212, and a memory 214. Although... Figure 2 Unless explicitly stated otherwise, in some respects, the communication device 200 may include one or more additional hardware and / or software components, such as processors / microprocessors, controllers / microcontrollers, other dedicated or general-purpose hardware / processors / circuits, peripherals, memory, power supply, external device interfaces, user identity modules (SIMs), user input / output devices (displays, keyboards, touchscreens, speakers, external buttons, cameras, microphones, etc.), or other related components.

[0029] Communication device 200 can transmit and receive wireless signals on one or more wireless access networks. Baseband modem 206 can control this communication function of communication device 200 according to the communication protocol associated with each wireless access network, and can perform control via antenna system 202 and RF transceiver 204 to transmit and receive wireless signals according to formatting and scheduling parameters defined by each communication protocol. Although various practical designs may include separate communication components (e.g., separate antennas, RF transceivers, digital signal processors, and controllers) for each supported wireless communication technology, for the sake of brevity, Figure 2 The configuration of the communication device 200 shown represents only a single instance of this component.

[0030] Communication device 200 can transmit and receive wireless signals using antenna system 202. Antenna system 202 can be a single antenna or can include one or more antenna arrays, each containing multiple antenna elements. For example, antenna system 202 can include an antenna array located at the top of communication device 200 and a second antenna array located at the bottom of communication device 200. In some aspects, antenna system 202 may additionally include analog antenna combining and / or beamforming circuitry. In the receive (RX) path, RF transceiver 204 can receive analog radio frequency signals from antenna system 202 and perform analog and digital RF front-end processing on the analog radio frequency signals to generate digital baseband samples (e.g., in-phase / quadrature (IQ) samples) provided to baseband modem 206. RF transceiver 204 can include analog and digital receiving components including amplifiers (e.g., low noise amplifiers (LNAs)), filters, RF demodulators (e.g., RF IQ demodulators), and analog-to-digital converters (ADCs), which can be used to convert the received radio frequency signals into digital baseband samples. In the transmit (TX) path, RF transceiver 204 can receive digital baseband samples from baseband modem 206 and perform analog and digital RF front-end processing on the digital baseband samples to generate an analog radio frequency signal provided to antenna system 202 for wireless transmission. RF transceiver 204 may thus include analog and digital transmission components including amplifiers (e.g., power amplifiers (PA)), filters, RF modulators (e.g., RF IQ modulators), and digital-to-analog converters (DACs). RF transceiver 204 can utilize these analog and digital transmission components to mix the digital baseband samples received from baseband modem 206 and generate an analog radio frequency signal for wireless transmission through antenna system 202. In some aspects, baseband modem 206 can control the wireless transmission and reception of RF transceiver 204, including specifying the transmit and receive radio frequencies for the operation of RF transceiver 204.

[0031] Based on the various aspects provided herein, communication device 200 can perform sensing operations within wireless communication network 100. Indicatively, in addition to conventional communication processing, baseband modem 206 (e.g., digital signal processor 208) can be configured to perform sensing-related signal processing. For example, baseband modem 206 can be configured to implement techniques such as radar waveform generation, matched filtering for target detection, parameter evaluation of detected targets (e.g., range, rate, angle), and environment mapping. In some embodiments, baseband modem 206 (e.g., digital signal processor 208) can use its own hardware accelerators and parallel processing capabilities to efficiently handle the computationally intensive sensing algorithms associated with communication tasks.

[0032] Furthermore, the baseband modem 206 (e.g., protocol controller 210) can be configured to coordinate and / or manage the joint operation of communication and sensing functions. Indicatively, the baseband modem 206 can invoke sensing and communication operations, allocate resources (e.g., time / frequency resources, antenna bundles) between sensing and communication operations, and manage interference between sensing and communication operations. The baseband modem (e.g., protocol controller 210) can further implement sensing control protocols and interfaces to enable coordination with other network entities for the distributed sensing operations described herein.

[0033] Similar to its role in communicating data, in some embodiments, application processor 212 can be configured as both a source and a destination for sensed data. Application processor 212 can execute sensing applications configured to process and interpret sensed data received from baseband modem 206. Exemplarily, application processor 212 can use the sensed data to perform at least one of target detection and tracking, environment mapping, and / or situational awareness services. In some embodiments, application processor 212 can interface with external sensors (e.g., cameras, LiDAR) to fuse data from multiple sensing modalities to enhance sensing capabilities.

[0034] Correspondingly, in addition to communication signals, the RF transceiver 204 can further support the transmission and reception of sensing waveforms. Indicatively, the RF transceiver 204 can generate and transmit sensing signals (e.g., continuous waveforms for frequency modulation used in radar), and can process received sensing signals to extract target information. In some embodiments, the RF transceiver 204 can use the same analog and digital components (e.g., amplifiers, filters, modulators / demodulators, ADCs / DACs) for both sensing and communication operations, potentially utilizing additional hardware accelerators for specific sensing tasks. Indicatively, in some embodiments, the antenna system 202 can also utilize independent antenna arrays or shared arrays with beamforming capabilities to support communication and sensing functions. Depending on various aspects, the antenna system 202 can form narrow beams for extended sensing range or wide beams for rapid coverage, depending on sensing requirements and resource constraints. Techniques similar to MIMO and beamforming can be employed to enhance sensing performance and enable functions such as high-definition target parameter evaluation and interference mitigation.

[0035] like Figure 2As shown, the baseband modem 206 may include a digital signal processor 208 capable of performing physical layer (PHY, Layer 1) transmit and receive processing to prepare outgoing transmit data provided by the protocol controller 210 for transmission via the RF transceiver 204 in the transmit path, and to prepare incoming receive data provided by the RF transceiver 204 for processing by the protocol controller 210 in the receive path. The digital signal processor 208 may be configured to perform one or more of the following physical layer processing functions: error detection, forward error correction coding / decoding, channel coding and interleaving, channel modulation / demodulation, physical channel mapping, radio measurement and search, frequency and time synchronization, antenna diversity processing, power control and weighting, rate matching / dematching, retransmission processing, interference cancellation, and any other physical layer processing functions. Digital signal processor 208 can be structurally implemented as a hardware component (e.g., implemented as one or more digitally configured hardware circuits or field-programmable gate arrays (FPGAs)), a software-defined component (e.g., one or more processors configured to execute program code defining arithmetic, control, and I / Q instructions (e.g., software and / or firmware) stored in a non-transitory computer-readable storage medium), or a combination of hardware and software components. In some aspects, digital signal processor 208 may include one or more processors configured to retrieve and execute program code defining control and processing logic for physical layer processing operations. In some aspects, digital signal processor 208 may utilize software to perform processing functions via the execution of executable instructions. In some aspects, digital signal processor 208 may include one or more dedicated hardware circuits (e.g., application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and other hardware) digitally configured to specifically perform processing functions, wherein one or more processors of digital signal processor 208 can offload specific processing tasks to these dedicated hardware circuits, referred to as hardware accelerators. Exemplary hardware accelerators can include Fast Fourier Transform (FFT) circuits and encoder / decoder circuits. In some respects, the processor and hardware accelerator components of the digital signal processor 208 can be implemented as coupled integrated circuits.

[0036] Communication device 200 can be configured to operate according to one or more wireless communication technologies. Digital signal processor 208 can handle lower-layer processing functions (e.g., Layer 1 / PHY) of the wireless communication technology, while protocol controller 210 can handle upper-layer protocol stack functions (e.g., data link layer / Layer 2 and / or network layer / Layer 3). Protocol controller 210 can thus be responsible for controlling the wireless communication components of communication device 200 (antenna system 202, RF transceiver 204, and digital signal processor 208) according to the communication protocol of each supported wireless communication technology, and accordingly, can represent the access layer (AS) and non-access layer (NAS) of each supported wireless communication technology (also covering Layer 2 and Layer 3). Protocol controller 210 can be structurally embodied as a protocol processor configured to execute protocol stack software (retrieved from controller memory) and subsequently control the wireless communication components of communication device 200 to send and receive communication signals according to the corresponding protocol stack control logic defined in the protocol software. Protocol controller 210 may include one or more processors configured to retrieve and execute program code defining upper-layer protocol stack logic for one or more wireless communication technologies, capable of including data link layer / Layer 2 and network layer / Layer 3 functions. Protocol controller 210 may be configured to perform user plane and control plane functions according to the specific protocols of the supported wireless communication technologies to facilitate the transmission of application layer data to and from wireless communication device 200. User plane functions may include header compression and encapsulation, security, error checking and correction, channel multiplexing, calling, and prioritization, while control plane functions may include the establishment and maintenance of radio bearers. The program code retrieved and executed by protocol controller 210 may include executable instructions defining the logic of these functions.

[0037] The communication device 200 may also include an application processor 212 and a memory 214. The application processor 212 may be a CPU and may be configured to process layers above the protocol stack, including the transport layer and the application layer. The application processor 212 may be configured to execute various applications and / or programs of the communication device 200 at the application layer of the communication device 200, such as an operating system (OS), a user interface (UI) to support user interaction with the communication device 200, and / or various user applications. The application processor may interface with the baseband modem 206 and serve as a source (in the transmission path) and destination (in the reception path) of user data, such as voice data, audio / video / image data, message data, application data, basic Internet / web access data, etc. Therefore, in the transmission path, the protocol controller 210 may receive and process the outgoing data provided by the application processor 212 according to the specific functions of each layer of the protocol stack and provide the generated data to the digital signal processor 208. Then, the digital signal processor 208 can perform physical layer processing on the received data to generate digital baseband samples, which can then be provided to the RF transceiver 204. The RF transceiver 204 can then process the digital baseband samples to convert them into analog RF signals that can be wirelessly transmitted via the antenna system 202. In the receiving path, the RF transceiver 204 can receive analog RF signals from the antenna system 202 and process them to obtain digital baseband samples. The RF transceiver 204 can provide the digital baseband samples to the digital signal processor 208, which can perform physical layer processing on them. The digital signal processor 208 can then provide the generated data to the protocol controller 210, which can process the generated data according to the specific functions of the protocol stack layers and provide the generated incoming data to the application processor 212. The application processor 212 can then process the incoming data at the application layer, which can include executing one or more applications on the data and / or presenting the data to a user via a user interface.

[0038] Memory 214 may encompass the memory components of communication device 200, such as a hard drive or another permanent memory device. Although Figure 2 It is not explicitly described in the text. Figure 2 Each of the other components of the communication device 200 shown may additionally include integrated permanent and non-permanent memory components, such as those for storing software program code, buffering data, etc.

[0039] According to some wireless communication networks, terminal devices 102 and 104 can execute mobility procedures to connect to, disconnect from, and switch between available network access nodes of the wireless access network of wireless communication network 100. Since each network access node of wireless communication network 100 can have a specific coverage area, terminal devices 102 and 104 can be configured to select and reselect available network access nodes to maintain a stable wireless access connection with the wireless access network of wireless communication network 100. For example, terminal device 102 can establish a wireless access connection with network access node 110, while terminal device 104 can establish a wireless access connection with network access node 112.

[0040] If the current wireless access connection degrades, terminal device 102 or 104 can seek a new wireless access connection with another network access node in the wireless communication network 100. For example, terminal device 104 can move from the coverage area of ​​network access node 112 to the coverage area of ​​network access node 110. Therefore, terminal device 104 can detect that the wireless access connection with network access node 112 may have degraded via wireless measurements such as signal strength or signal quality measurements of network access node 112.

[0041] According to the mobility procedures defined in the appropriate network protocol for the wireless communication network 100, terminal device 104 may seek a new wireless access connection by performing wireless measurements on adjacent network access nodes to determine whether any adjacent network access node can provide a suitable wireless access connection (e.g., at terminal device 104 or triggered by the wireless access network). Since terminal device 104 can move to the coverage area of ​​network access node 110, terminal device 104 can identify network access node 110 (which may be selected by terminal device 104 or by the wireless access network) and switch to a new wireless access connection with network access node 110. This mobility procedure, including wireless measurements, cell selection / reselection, and handover, is established in various network protocols and can be adopted by terminal devices and wireless access networks to maintain a stable wireless access connection between each terminal device and the wireless access network across any number of different wireless access network scenarios.

[0042] Figure 3Exemplary illustrations of various communication elements of a device for a wireless communication apparatus (e.g., communication device 200) are shown. The device 300 may include processing circuitry 310 (e.g., baseband modem 206, application processor 212) that can lead and manage the communication operations of the device 300 according to one or more wireless communication protocols, and can control the transmission / reception of communication signals via one or more RF transceivers 320a-b through at least one or more antennas 322a-b. The processing circuitry 310 may include an interface to the RF transceivers 320a-b. In this embodiment, two RF transceivers are shown, namely a first RF transceiver 320a and a second RF transceiver 320b; however, the device 300 may include more than two RF transceivers. In embodiments, each RF transceiver described herein may be implemented by a corresponding integrated circuit (i.e., a transceiver integrated circuit). Depending on the aspects described herein, the device 300 may include the communication circuitry described herein, which may include the RF transceivers 320a-b.

[0043] Each RF transceiver 320a-b may include at least one RF chain to process communication signals associated with antennas 322a-b respectively. The device 300 may include first and second antennas 322a-b, or the device 300 may include antenna interfaces that can be coupled to these antennas 322a-b. It should be noted that the device 300 is described as being coupled to antennas 322a-b; however, the device 300 may be coupled to more than two antennas, and thus, each RF transceiver 320a-b may include multiple RF chains, each RF chain capable of processing communication signals for a corresponding antenna. The device 300 can use antennas 322a-b to transmit and receive wireless communication signals. The device 300 can be used as an RF transmitter (e.g., an RF transmitting circuit) to transmit wireless communication signals and the device 300 can also be used as an RF receiver (e.g., an RF receiving circuit) to receive wireless communication signals.

[0044] The processing circuitry 310 may include circuitry and / or logic configured to manage wireless communication operations, or may be partially or wholly implemented by circuitry and / or logic configured to manage wireless communication operations, such as a processor, memory circuitry and / or logic including circuitry and / or logic. The processing circuitry 310 may be configured to communicate with an external main processor (e.g., host processor, central processing unit, system-on-a-chip) of the wireless communication device including device 300 via a designated interface coupled to the main processor. In some embodiments, the processing circuitry 310 may be the main processor of the wireless communication device. The processing circuitry 310 may also access the main memory of the corresponding wireless communication device via a designated interface. The processing circuitry 310 may further include an interface to the RF transceivers 322a-b.

[0045] Processing circuitry 310 may include a digital signal processor (e.g., digital signal processor 208). Digital signal processor 208 may be configured to perform one or more of the following physical layer processing functions: error detection, forward error correction coding / decoding, channel coding and interleaving, channel modulation / demodulation, physical channel mapping, wireless measurement and search, frequency and time synchronization, antenna diversity processing, power control and weighting, rate matching / dematching, retransmission processing, interference cancellation, and any other physical layer processing functions.

[0046] Processing circuitry 310 may include a modem configured to process baseband signals received from / transmitted to antennas 322a-b via corresponding communication paths 325a-b including corresponding RF chains. In various embodiments, the interface of the RF transceiver 320a-b of processing circuitry 310 may be configured to couple processing circuitry 310 to communication path 325a-b. Accordingly, processing circuitry 310 may include media access control (MAC) circuitry and / or logic, physical layer (PHY) circuitry and / or logic, baseband (BB) circuitry and / or logic, baseband processor, baseband memory, application processor circuitry and / or logic, application processor, application processor memory, and / or any other circuitry and / or logic. For example, processing circuitry 310 may perform baseband processing on digital baseband signals to recover data included in wireless data transmission.

[0047] Processing circuitry 310 can control and / or arbitrate the transmit and / or receive functions of arbitration device 300, and perform one or more baseband processing functions (e.g., MAC, encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.). Processing circuitry 310 can be configured to provide control functions to RF transceivers 320a-b (e.g., providing control functions to the RF chain to control and / or arbitrate the transmission and / or reception of wireless communication signals). In various aspects, the functionality of processing circuitry 310 can be implemented in software and / or firmware running on one or more suitable programmable processors, and can be implemented in, for example, field-programmable gate arrays, application-specific integrated circuits, etc. In various embodiments, the interface of processing circuitry 310 to RF transceivers 320a-b can be configured to couple the processing circuitry to RF transceivers 320a-b to provide communication between the processing circuitry and RF transceivers 320a-b.

[0048] Each RF transceiver 320a-b can provide RF processing of communication signals transmitted via corresponding communication paths 325a-b within a corresponding RF chain, to transmit wireless communication signals via corresponding antennas based on signals (e.g., baseband communication signals, digital signals) received from processing circuitry 310 via the communication paths. Each RF transceiver 320a-b can provide RF processing of communication signals transmitted via corresponding communication paths 325a-b to receive wireless communication signals via corresponding antennas 322a-b and provide signals to processing circuitry 310 via corresponding communication paths 325a-b. Processing circuitry 310 can be configured to control the operation of RF transceivers 320a-b. Each RF transceiver 320a-b may include a receive path to provide RF processing for receiving wireless communication signals received from corresponding antennas 322a-b, and each RF transceiver 320a-b may include a transmit path to provide RF processing for transmitting wireless communication signals transmitted via corresponding antennas 322a-b.

[0049] In the receive (RX) path, each RF transceiver 320a-b can receive analog radio frequency signals from corresponding antennas 322a-b via corresponding communication paths 325a-b and perform analog and digital RF front-end processing on the analog radio frequency signals to generate digital baseband samples (e.g., in-phase / quadrature (IQ) samples) provided to the processing circuitry 310. In various embodiments, each antenna element of each RF transceiver 320a-b may include two RF chains, each of which may be specified for a specific polarization. Each RF transceiver 320a-b may include analog and digital receiving components including amplifiers (e.g., low-noise amplifiers (LNAs)), filters, RF demodulators (e.g., RF IQ demodulators), and analog-to-digital converters (ADCs), which can be used to convert the received radio frequency signals into digital baseband samples.

[0050] In the transmit (TX) path, each RF transceiver 320a-b can receive digital baseband samples from processing circuitry 310 and perform analog and digital RF front-end processing on the digital baseband samples to generate an analog radio frequency signal that is provided to the corresponding antenna 322a-b for wireless transmission via the corresponding communication path 325a-b. Thus, each RF transceiver 320a-b may include analog and digital transmission components including an amplifier (e.g., a power amplifier (PA)), a filter, an RF modulator (e.g., an RF IQ modulator), and a digital-to-analog converter (DAC). The RF transceiver 320 can utilize the analog and digital transmission components to mix the digital baseband samples received from processing circuitry 310 and generate a corresponding analog radio frequency signal for wireless transmission via the corresponding antenna 322a-b. In some aspects, processing circuitry 310 can control the wireless transmission and reception of RF transceivers 320a-b, including specifying transmit and receive radio frequencies for the operation of each RF transceiver 320a-b. In some embodiments, at least one amplifier may include the amplifier circuitry provided herein.

[0051] Figure 4 An exemplary diagram illustrating the transmission path configuration for an RF transceiver used in dual-frequency operation is shown. The RF transceiver is referred to herein as RF transceiver 320 and may be, according to… Figure 3 The first RF transceiver 320a or the second RF transceiver 320b is described herein. The RF transceiver 320, whose transmit path is shown here, can be configured for digital polarization TX in two different frequency bands. The RF transceiver 320 can be coupled to processing circuitry (e.g., processing circuitry 310, modem) via an interface. The interface may include a communication path designated to carry communication signals 410 between the processing circuitry and the antenna. In some embodiments, the interface may include another circuitry path providing communication between the RF transceiver 320 and the processing circuitry for control operation. The RF transceiver 320 may further include additional components and / or circuitry not described herein, such as additional filter circuitry, synthesizer circuitry, etc. The RF transceiver 320 may include various circuits and components deployed on the respective transmission paths.

[0052] RF transceiver 320 may include various circuits and components for processing communication signals and transmitting communication signals across two frequency bands. These components may include a digital front end (DFE) 420, digital time converters (DTC) 430a and 430b, digital power amplifiers (DPA) 440a and 440b, a coupler 450, and a duplexer 460.

[0053] Digital front-end 420 can receive communication signal 410 via an interface to which processing circuitry is coupled. Digital front-end 420 may include digital front-end processing circuitry and other components. Digital front-end 420 can be configured to convert communication signal 410 (e.g., in-phase / quadrature (IQ) signal) into a polarized signal comprising amplitude modulation (AM) signal (e.g., amplitude control code) and phase modulation (PM) signal (e.g., phase control code). The generated amplitude-modulated and phase-modulated signals can be provided to the corresponding transmission chain for further processing.

[0054] In a first transmission chain configured for a first frequency band, RF transceiver 320 may include a first digital time converter 430a. The first digital time converter 430a may be coupled to a digital front-end 420. The first digital time converter 430a may receive a phase modulation signal. The first digital time converter 430a may be further coupled to a local oscillator (LO) 435. The first digital time converter 430a may adjust polarization modulation parameters based on a PM signal provided by the digital front-end 420 to generate a modulated local oscillator signal for the first frequency band. By adjusting the polarization modulation parameters based on the PM signal, the first digital time converter 430a may output a modulated local oscillator (MOLO) signal in the first frequency band. In the first transmission chain, RF transceiver 320 may further include a first digital power amplifier 440a. The first digital power amplifier 440a may receive an amplitude modulation signal (e.g., amplitude control code) that sets the desired output power of the first digital power amplifier 440a. The first digital power amplifier 440a can further receive a modulated local oscillator signal of the first frequency band and provide an output RF signal of the first frequency band based on the received modulated local oscillator signal and amplitude modulation signal. The first digital power amplifier 440a may include dynamic power control or an RF capacitor-type digital-to-analog converter (RF-CDAC).

[0055] In the second transmission chain configured for the second frequency band, RF transceiver 320 may include a second digital time converter 430b. The second digital time converter 430b may be coupled to digital front end 420. The second digital time converter 430b may receive a phase modulation signal. The second digital time converter 430b may be further coupled to a local oscillator 435. The second digital time converter 430b may adjust polarization modulation parameters based on the phase modulation signal provided by digital front end 420 to generate a modulated local oscillator signal for the second frequency band. By adjusting the polarization modulation parameters based on the phase modulation signal, the second digital time converter 430b may output the modulated local oscillator signal in the second frequency band. In the second transmission chain, RF transceiver 320 may further include a second digital power amplifier 440b. The second digital power amplifier 440b may receive an amplitude modulation signal (e.g., amplitude control code) that sets the desired output power of the second digital power amplifier 440b. The second digital power amplifier 440b can further receive the modulated local oscillator signal of the second frequency band and provide the output RF signal of the second frequency band based on the received modulated local oscillator signal and amplitude modulation signal. The second digital power amplifier 440b may include dynamic power control or an RF capacitor-type digital-to-analog converter. Although only two transmission chains are shown in the figure, the RF transceiver may include multiple transmission chains, i.e., more than two transmission chains, such as 3, 4, 5, ..., N, where N is an integer.

[0056] Local oscillator 435 may include various components that generate a stable and continuous signal at one or more specified frequencies and may be used as a reference for frequency conversion, mixing, and other signal processing tasks. In an embodiment, local oscillator 435 may include an oscillator core. The oscillator core may generate a signal at a specified frequency. The oscillator core may include one or more voltage-controlled oscillators that can include an tunable resonator capable of adjusting its frequency by changing a control voltage. The oscillator core may include a crystal oscillator that may rely on the mechanical resonance of a quartz crystal. The oscillator core may include a dielectric resonator oscillator (DRO).

[0057] In some embodiments, the local oscillator 435 may include a resonator that determines or stabilizes the frequency of oscillation. The resonator may include a quartz crystal in a crystal oscillator or an LC circuit or dielectric resonator in a voltage controller oscillator. In some embodiments, the local oscillator 435 may further include a phase-locked loop (PLL) to synchronize the output of the local oscillator 435 with a reference signal to achieve high accuracy and stability with low phase noise. Indicatively, the PLL may include a reference oscillator, a phase detector, a low-pass filter, and a VCO or adjustable resonator. The local oscillator 435 may further include frequency control circuitry configured to adjust the output frequency of the local oscillator 435 via various methods such as manual tuning (e.g., a potentiometer), automatic frequency control (AFC), or digital control via a microcontroller or DSP (e.g., via digital front-end 420). According to the aspects described herein, the local oscillator 435 may operate using a resonator shared with another RF transceiver. Indicatively, return to reference. Figure 4 In an embodiment where RF transceiver 320 is the first RF transceiver 320a, the second RF transceiver 320b may also be the same as or similar to RF transceiver 320. A common resonator may be shared by the local oscillators of these RF transceivers (e.g., local oscillator 435).

[0058] RF transceiver 320 may further include coupler 450. Coupler 450 may include a dual-frequency transformer. Coupler 450 may be configured to process RF signals from a first transmission chain and a second transmission chain. Specifically, coupler 450 may couple RF signals received through a first end (e.g., input) of coupler 450, output from digital power amplifiers 440a and 440b, to a second end (e.g., output) of coupler 450 to another component of RF transceiver 320, which is coupled to the second end of the coupler while maintaining its respective frequency characteristics. Coupler 450 (e.g., dual-frequency transformer) may achieve appropriate impedance matching between the two frequency bands to optimize power transfer and minimize signal reflection.

[0059] In other words, a dual-frequency transformer can achieve impedance matching across two frequency bands to ensure that the output impedance of each in the first and second transmission chains is matched to subsequent components. A dual-frequency transformer can couple RF signals from two digital power amplifiers 440a and 440b to two different outputs corresponding to their respective frequency bands. For example, a signal from digital power amplifier 440a is routed to the first frequency band output and a signal from digital power amplifier 440b is routed to the second frequency band output. The dual-frequency transformer can operate across the first and second frequency bands by employing impedance transformation techniques tailored to each band.

[0060] RF transceiver 320 may further include a duplexer 460 coupled to the output of coupler 450. Duplexer 460 can combine RF signals from the first and second frequency band outputs of the coupler into a single RF signal for transmission via an antenna. In this architecture, duplexer 460 may include a first terminal at a first end capable of receiving the first frequency band output, a second terminal at a first end capable of receiving the second frequency band output, and a terminal at a second end providing the combined signal. This combined signal is routed to the antenna for transmission. Despite signal combination, duplexer 460 can also provide isolation between paths corresponding to different frequency bands to prevent interference or leakage between signals of different frequency bands during transmission.

[0061] It should be noted that although duplexer 460 is described as being used for transmission in this architecture, the duplexer can also support reception by routing incoming RF signals from the antenna back to the appropriate receive chain based on its frequency. In the receive RX path of the RF transceiver (e.g., RF transceiver 320), the duplexer can separate the incoming signals based on its frequency band and route the separated incoming signals to the appropriate RF chain for further processing. In this case, in the duplexer shown above, the duplexer can receive these incoming signals at a terminal located at the second end and separate the received incoming signals into two independent signals at two independent frequency bands. In this illustrative embodiment, the duplexer can provide a first signal at a first frequency band from a first terminal located at the first end and a second signal at a second frequency from a second terminal located at the second end. The duplexer can be a three-port passive RF device that uses filters (e.g., high-pass filters, low-pass filters, or band-pass filters) to divide the signal into different frequency bands. This functionality enables the RF transceiver to process multiple frequency bands simultaneously using a shared antenna.

[0062] Figure 5 A block diagram of a communication circuit including two transceivers labeled Transceiver 0 and Transceiver 1 is shown. Each transceiver includes a quartz crystal resonator, an oscillator core, multiple phase-locked loops, and functional blocks for the receiver and / or transmitter. The arrangement of the components reflects a typical design for generating the system clock signal and ensuring an independent clock for each transceiver. In summary, Figure 5 The system described in the paper illustrates a dual transceiver architecture, in which each transceiver operates independently using its own quartz crystal resonator.

[0063] Transceiver 0 is shown connected to a quartz crystal resonator (XTAL 0), which is coupled to the transceiver's oscillator core. XTAL 0 is a two-terminal quartz crystal with terminals labeled X1 and X2, providing a stable reference frequency to the oscillator core. The oscillator core amplifies and sustains the oscillation provided by XTAL 0 to generate a precise output frequency signal that is subsequently distributed to multiple phase-locked loops (PLLs). These PLLs, labeled PLL 1, PLL 2, and PLL N, operate to generate clock signals with frequencies derived from the output of the oscillator core. The output signals from the PLLs serve as the system clock for the various operations within the transceiver.

[0064] The receivers and / or transmitters associated with transceiver 0 are functionally connected to the phase-locked loop (PLL) and utilize the system clock generated by the PLL for communication tasks. These components handle modulation, demodulation, and the signal processing required for transmitting and receiving data over the radio frequency (RF) channel. The system clock ensures the precise timing and synchronization necessary for reliable communication.

[0065] Similarly, transceiver 1 is connected to a second quartz crystal resonator (XTAL 1) that is functionally identical to XTAL 0. XTAL 1 also has two terminals labeled X1 and X2, and XTAL 1 is connected to the oscillator core of transceiver 1. The oscillator core amplifies and stabilizes the oscillator signal generated by XTAL 1 to generate a reference frequency. This frequency is allocated to a set of phase-locked loops within transceiver 1, also labeled PLL 1, PLL 2, and PLL N. These PLLs process the input signal from the oscillator core to generate a clock signal tailored to the transceiver's operational requirements.

[0066] The receiver and / or transmitter in transceiver 1 utilizes a system clock generated by an associated phase-locked loop (PLL) for signal processing, RF transmission, and reception tasks. Similar to transceiver 0, the system clock in transceiver 1 provides the necessary timing and synchronization for efficient communication operation. The replication of the quartz crystal resonators XTAL 0 and XTAL 1 in this architecture ensures that each transceiver can operate independently using its own dedicated reference clock. However, this arrangement can present challenges. For example, the use of independent resonators may lead to increased system cost and size. Furthermore, if the oscillation frequencies of XTAL 0 and XTAL 1 are very similar but not perfectly matched, interference or "beating" may occur between the clocks generated by the two transceivers. This interference can degrade the quality of the communication signal and affect the overall system performance. The oscillator cores in both transceivers provide a stable basis for generating clock signals. Due to their ability to generate highly stable and accurate frequency signals, the oscillator cores in both transceivers can employ quartz crystal oscillators. These signals serve as the basis for the PLL to synchronize the multiple clock frequencies required by different functional blocks within each transceiver.

[0067] The receiver and / or transmitter in a transceiver may include analog and digital processing chains. These chains may include amplifiers, filters, and mixers for RF signal processing, and digital signal processors for modulation, demodulation, and error correction. A system clock provided by a phase-locked loop ensures that these processing operations occur at precise times, which is crucial for maintaining synchronization with external communication systems.

[0068] Figure 6 A communication circuit implementing a cascaded clock signal configuration is shown. In this architecture, transceiver 0 acts as a master reference clock generator, and transceiver 1 operates using a clock signal cascaded from transceiver 0. Figure 6 The architecture in the text represents a scheme to reduce component costs and system size by sharing a single quartz crystal resonator across multiple transceivers. This differs from... Figure 5 The configuration in this design eliminates the need for a separate quartz crystal resonator for transceiver 1, resulting in a reduction in component quantity and associated cost. However, the design introduces some additional components and dependencies between transceivers.

[0069] Transceiver 0 includes a quartz crystal resonator with terminals X1 and X2 that provides a stable reference frequency signal to an oscillator core. The oscillator core amplifies and stabilizes the oscillations generated by the resonator to generate the reference frequency signal. This signal is then provided to internal phase-locked loop blocks labeled PLL 1, PLL 2, through PLL N to generate a system clock tailored to the internal operation of transceiver 0. These clocks can be used to synchronize associated receivers and / or transmitters.

[0070] Furthermore, transceiver 0 includes a clock output buffer configured to drive a reference clock signal to transceiver 1. This buffer ensures that the signal strength and quality are sufficient for transmitting the clock signal through the interconnect between the two transceivers. However, including the buffer increases the design complexity of transceiver 0, requiring additional control and power management circuitry. Moreover, transceiver 0 must remain active to generate and transmit clock signals even when the receiver and / or transmitter of transceiver 0 is not in use.

[0071] In contrast, transceiver 1 does not include a separate quartz crystal resonator. Instead, its oscillator core receives a cascaded clock signal from transceiver 0 via a clock input buffer. The input buffer ensures proper signal reception and prevents signal degradation during transmission. The oscillator core processes this signal and provides the processed signal to an internal phase-locked loop (PLL) configured similarly to that in transceiver 0. The PLL generates the required system clock for the receiver and / or transmitter in transceiver 1, enabling synchronized operation across the two transceivers.

[0072] While cascaded configurations reduce hardware redundancy by using a single crystal resonator, they can introduce potential limitations. Operational constraints are imposed on the reliance on the master transceiver (transceiver 0) for clock generation, as any interrupt in transceiver 0 directly affects the function of transceiver 1. Furthermore, especially when transmitting clock signals over long distances or in noisy environments, including buffers in the clock output and input stages can increase overall power consumption and potentially degrade clock quality, such as through phase noise (jitter) or harmonic spurious emissions.

[0073] Figure 7 An illustrative embodiment of a communication circuit according to various aspects described herein is shown. The communication circuit may include a single resonator 701 to provide a synchronous reference clock across multiple transceivers. In embodiments, resonator 701 may include, or may be, a single quartz crystal resonator. Resonator 701 may be electrically coupled to oscillator cores in multiple transceivers in a parallel configuration. In this illustrative embodiment, the communication circuit includes two transceivers, namely transceiver 320a and transceiver 1320b. Indicatively, each transceiver 320a-b may be a corresponding transceiver integrated circuit. Each transceiver 320a-b may include an oscillator core, a set of phase-locked loops, and functional circuitry for transmitting and / or receiving communication signals.

[0074] Resonator 701 can oscillate at a certain resonant frequency when driven by one or more connected oscillator cores. The resonant frequency of resonator 701 can be defined by physical and electrical characteristics and can be a predefined resonant frequency that has been demonstrably selected relative to the design considerations and purposes of the communication device, including the communication circuitry. Resonator 701 can be coupled to oscillator core 711 of transceiver 0 320a and oscillator core 721 of transceiver 1 320b via electrical connections to terminals X1 and X2. This parallel configuration allows the two oscillator cores 711, 721 to share the same resonator 701, generating synchronized oscillator signals while maintaining the operational independence of each transceiver 320a-b. Parallel coupling eliminates the need for additional clock signal routing or cascading mechanisms.

[0075] The oscillator core 711 of the transceiver 0 320a (which may be referred to as the first oscillator core) can maintain oscillation by driving the resonator 711 with a first drive signal and can generate a first oscillator signal based on the generated oscillation. In an embodiment, the oscillator core 711 can provide the first oscillator signal as a system clock directly (i.e., without involving any phase-locked loop) to the transmitter and / or receiver circuitry 715 (which may also be referred to as the first communication circuitry) via a direct path 716. In an embodiment, the oscillator core 711 can deliver the first oscillator signal to a series of phase-locked loops, including PLL 1712, PLL 2 713, and PLL N 714. These phase-locked loops can process the input oscillator signal (i.e., the first oscillator signal) to generate additional clock signals tailored to the specific needs of the transmitter and / or receiver circuitry 715 to ensure accurate timing and synchronization for communication operations such as modulation, demodulation, encoding, and decoding.

[0076] Similarly, in transceiver 1 320b, oscillator core 721 (which may be referred to as the second oscillator core) can drive the same resonator 711 using the second drive signal. Oscillator core 721 can generate a second oscillator signal that can be used as input to PLL 1 722, PLL 2 723, and PLL N 724. These phase-locked loops can provide additional clock synchronization to the transmitter and / or receiver circuitry 725 (which may also be referred to as the second communication circuitry) that also performs the communication functions described for transceiver 0 320a. In an embodiment, oscillator core 721 can provide the second oscillator signal as the system clock directly (i.e., without involving any phase-locked loops) to transmitter and / or receiver circuitry 725 via direct path 726. The use of a shared resonator allows the clock signals in the two transceivers to remain synchronized and facilitates efficient and consistent operation in systems requiring multi-link or multi-band communication.

[0077] The controller of the communication circuit can be configured to individually control the operation of each oscillator core 711, 721, so that any oscillator core 711, 721 can be activated independently of the other. For example, when only one of the transceivers 320a-b is active, the corresponding oscillator core of the activated transceiver can individually drive the resonator 701 to generate a corresponding oscillator signal for the operation of that transceiver. In an embodiment, when both transceivers 320a-b are active, the combined drive signal from the oscillator cores, i.e., the first oscillator signal of oscillator core 711 and the second oscillator signal of oscillator core 721, can enhance the performance of resonator 701 by compensating for parasitic losses and maintaining clock quality. This flexibility can reduce unnecessary power consumption while ensuring reliable clock generation.

[0078] The transmitter and / or receiver circuits 715, 725 within each transceiver 320a-b can use corresponding clock signals for their respective transmit and receive tasks. These circuit blocks may include digital-to-analog converters, analog-to-digital converters, amplifiers, filters, and mixers. Specifically, these circuits may include, as per [specific clock signal description needed], [specific clock signal description needed]. Figure 4 The described components include digital power amplifiers and digital time converters. The transmitter and / or receiver circuits 715 and 725 in the corresponding transceivers 320a-b can be dependent on a clock signal used to manage various communication operations. These circuits can perform tasks such as digital modulation, signal amplification, filtering, and analog-to-digital conversion. A synchronous reference clock provided by a shared resonator ensures that these operations are performed with precise timing, supporting reliable data transmission and reception in complex communication scenarios.

[0079] Resonator 701, schematically a quartz crystal resonator, can be configured to oscillate a clipped sine wave at an interface comprising terminals X1 and X2, having oscillator cores 711 and 721. This waveform inherently reduces harmonic emissions compared to a square wave signal, thereby improving electromagnetic compatibility and reducing interference within the circuit. The clipped sine wave can further contribute to minimizing spurious emissions, improving the overall quality of the clock signal allocated to the transceiver.

[0080] The phase-locked loops (PLLs) in each transceiver 320a-b can be configured to process a corresponding received oscillator signal (either a first oscillator signal or a second oscillator signal). For example, PLL 1 712, PLL 2 713, and PLL N 714 in transceiver 0 320a can receive the first oscillator signal and use it to generate an additional clock signal with the specific frequency and / or phase required by the transmitter and / or receiver circuit 715. Similarly, PLL 1722, PLL 2 723, and PLL N 724 in transceiver 1 320b can process the second oscillator signal to generate an additional clock signal configured for the transmitter and / or receiver circuit 725. Each PLL may include a reference oscillator, a phase detector, a low-pass filter, and a voltage-controlled oscillator (VCO) for maintaining high stability and accuracy of the output clock signal. In this implementation, the parallel coupling of resonator 701 to multiple oscillator cores 711, 712 also facilitates scalability. Although Figure 7 The embodiment shown focuses on two transceivers, and the design can be expanded to include additional transceivers, especially in systems that operate at lower frequencies or have lenient phase noise requirements.

[0081] In an embodiment, resonator 701 may be a single quartz crystal resonator configured as a shared oscillation source for oscillator cores 711 and 721. Resonator 701 may exhibit a predefined resonant frequency determined by its physical dimensions and material properties to provide a reference clock signal, potentially with minimal frequency deviation over time and temperature. Parallel coupling of a single resonator 701 to the first oscillator core 711 of transceiver 0 320a and the second oscillator core 721 of transceiver 1 320b can be achieved by coupling both ends of resonator 701 to the same corresponding terminals coupled to the two oscillator cores 711 and 721. The two oscillator cores 711 and 721 may drive resonator 701 individually or concurrently to maintain its oscillation and may generate a first oscillator signal and a second oscillator signal, respectively.

[0082] In this embodiment, the first oscillator core 711 and the second oscillator core 721 can operate concurrently (i.e., simultaneously). The controller of the communication circuit can concurrently activate both oscillator cores 711 and 721. Each oscillator core can generate its corresponding oscillator signal, while the two oscillator cores 711 and 721 jointly provide their drive signal to maintain oscillation in the resonator 701. The concurrent operation of the oscillator cores 711 and 721 allows the communication circuit to maintain synchronization between transceivers even in multi-link or multi-band communication scenarios. For example, when both transceivers 320a-b are active, the oscillator cores 711 and 721 can jointly compensate for parasitic losses in the resonator 701, ensuring that the quality of the oscillator signal, including phase noise and jitter, remains within acceptable limits.

[0083] In some embodiments, the circuitry may include a core controller (not shown) configured to activate the operation of a first oscillator core 711 and a second oscillator core 721. This core controller may be implemented in communication circuitry as part of the processing circuitry managing the transceivers. The core controller may include logic circuitry or programmable elements to selectively activate either or both oscillator cores 711, 721 based on operational requirements. For example, when transceiver 1 320b is deactivated, the core controller may activate only oscillator core 711 in transceiver 0 320a to demonstratively reduce power consumption while still generating the necessary oscillator signal for transceiver activation. Conversely, when both transceivers are active, the core controller may activate both oscillator cores to ensure synchronized operation of resonator 701 and enhance performance. In some embodiments, the processor 310 of the digital front-end 420 may include the core controller. For example, the core controller may dynamically switch between activating one or both oscillator cores 711, 712 based on current communication requirements to optimize power efficiency while maintaining synchronization across transceivers 320a-b.

[0084] In one embodiment, a first oscillator core 711 may be electrically coupled to a resonator 701 at a first terminal and a second terminal, and a second oscillator core 721 may be electrically coupled to a resonator 701 at the same terminal. The first terminal may be connected to one end of the resonator 701, and the second terminal may be connected to the other end of the resonator 701. These terminals can serve as common connection points for the two oscillator cores, enabling a parallel coupling configuration. Each oscillator core 711, 721 can interact with the resonator 701 through these terminals to provide its corresponding drive signal and receive oscillations generated by the resonator 701.

[0085] The aspects described herein may include the communication circuit described herein, which may include a modular circuit comprising a resonator 701 and oscillator cores 711, 721 coupled to a first transceiver circuit via a first interface, wherein the first transceiver circuit includes PLLs 712-714, a system clock path 716, and a transmitter and receiver circuit 715. The modular circuit may also be coupled to a second transceiver circuit via a second interface, wherein the second transceiver circuit includes PLLs 722-724, a system clock path 726, and a transmitter and receiver circuit 725, constituting the communication circuit.

[0086] The transmitter and / or receiver circuit 715 can receive a first oscillator signal and / or the outputs of PLLs 712-714 based on the first oscillator signal and perform one or more tasks based on the first oscillator signal and / or these PLL outputs, such as modulation, demodulation, signal amplification, and filtering. Similarly, the transmitter and / or receiver circuit 725 can receive a second oscillator signal and / or the outputs of PLLs 722-724 based on the second oscillator signal and perform one or more tasks based on the second oscillator signal and / or these PLL outputs, such as modulation, demodulation, signal amplification, and filtering.

[0087] In an embodiment, the communication circuitry may further include a transceiver controller (not shown) configured to control transmitter and / or receiver circuitry 715 and transmitter and / or receiver circuitry 725. This transceiver controller may be implemented as part of processing circuitry to coordinate the operation of transmitter and / or receiver circuitry 715 and 725 based on communication requirements. For example, the transceiver controller may adjust the timing, frequency, or power level of the communication circuitry to optimize performance or adapt to changing network conditions. The transceiver controller may also interact with a core controller to ensure that the oscillator cores are activated and synchronized according to the operating state of the communication circuitry. In an embodiment, processor 310 may implement the transceiver controller. The transceiver controller may be able to provide dynamic and centralized control of transmitter and / or receiver circuitry 715, 725. For example, the transceiver controller may synchronize the operation of transmitter and / or receiver circuitry 715, 725 with corresponding oscillator signals generated by oscillator cores 711, 720 for consistent communication across transceivers 320a-b.

[0088] In this embodiment, PLLs 712-714, 722-724 can receive their respective oscillator signals as input signals, namely, a first oscillator signal from oscillator core 711 and a second oscillator signal from oscillator core 721. Each PLL 712-714, 722-724 can process the input oscillator signals to generate a corresponding phase-locked output signal with a specific frequency and phase configured for the operational requirements of the respective transmitter and / or receiver circuits 715, 725. Correspondingly, the phase-locked signals generated by PLLs 712-714, 722-724 can be used by the respective transmitter and / or receiver circuits 715, 725 in subsequent operations such as modulation, demodulation, etc. For example, PLL 1 712 can output a first clock signal optimized for high-frequency modulation of transmitter and / or receiver circuit 715, while PLL 2 713 can generate a second clock signal for low-frequency demodulation that is output to transmitter and / or receiver circuit 715. Similarly, the phase-locked loop (PLL) in transceiver 1320b can provide a specified clock signal to the transmitter and / or receiver circuit 725 for its specific communication task. This implementation highlights the ability of PLLs to enhance the flexibility and performance of transceiver circuitry.

[0089] In an embodiment, transmitter and / or receiver circuitry 715 may include a first radio frequency (RF) chain configured to modulate or demodulate one or more first communication signals based on phase-locked signals received from one or more of PLLs 712-714, and transmitter and / or receiver circuitry 725 may include a second RF chain configured to modulate or demodulate one or more second communication signals based on another phase-locked signal received from one or more of PLLs 722-724. Each RF chain may include components such as digital-to-analog converters, analog-to-digital converters, mixers, amplifiers, and filters, which rely on phase-locked signals generated by the respective phase-locked loops to perform their functions.

[0090] For example, the first RF chain in transmitter and / or receiver circuit 715 can use a phase-locked signal from PLL 1 712 to modulate outgoing communication signals for transmission (e.g., within the transmit path of RF transceiver 320). Similarly, the second RF chain in transmitter and / or receiver circuit 725 can use a phase-locked signal from PLL 1 722 to demodulate incoming communication signals.

[0091] In one embodiment, the circuit includes an integrated circuit and a package or printed circuit board, wherein the package or printed circuit board includes a resonator, and the integrated circuit includes a first oscillator core and a second oscillator core. In another embodiment, the integrated circuit may include transceivers 320a-b. For example, resonator 701 may be embedded within the package or printed circuit board housing transceivers 320a and 320b. Integration of the resonator into the package or printed circuit board can reduce the overall circuit footprint, simplify assembly, and improve reliability by minimizing external connections. In another embodiment, oscillator cores 711 and 721, and their corresponding phase-locked loops and transmitter and / or receiver circuitry, may be housed within the integrated circuits of transceivers 320a and 320b. These integrated circuits can be coupled to resonator 701 via terminals X1 and X2, allowing a shared resonator to effectively drive both oscillator cores.

[0092] Figure 8 An illustrative embodiment of a circuit according to the aspects described herein is shown. In the embodiment, according to Figure 7 The described communication circuit may include circuitry. The circuitry shown can be viewed as a more detailed implementation depicting the parallel coupling of oscillator cores 711, 721 included in transceiver 0 320a and transceiver 1320b to a shared resonator 701. The resonator 701, labeled XTAL, can be configured to oscillate at a predefined resonant frequency and electrically coupled to the first oscillator core 711 of transceiver 0 320a via terminals X01 and X02, and electrically coupled to the second oscillator core 721 of transceiver 1 320b via terminals X11 and X12.

[0093] In one embodiment, the first oscillator core 711 may include an inverting amplifier 815 and a shaper 816. The inverting amplifier 815 amplifies the oscillation received from the resonator 701 to generate a first drive signal (e.g., a sine wave signal), which can be fed back to the resonator via terminal X01. The shaper 816 processes the amplified first drive signal to convert it into a square-wave clock signal, labeled Out0, which can be used as the first oscillator signal. This first oscillator signal can be provided to subsequent components in transceiver 0 320a for further processing. Similarly, the second oscillator core may include an inverting amplifier 825 and a shaper 826. The inverting amplifier 825 amplifies the oscillation received from the resonator 701 to generate a second drive signal, which can be fed back to the resonator 701 via terminal X11. The shaper 826 converts the second drive signal into a square-wave clock signal, labeled Out1, which can be used as the second oscillator signal.

[0094] Arrows 811 and 812 represent the electrical coupling between resonator 701 and the first oscillator core 711 in transceiver 0 320a. Specifically, arrow 811 represents the path through which resonator 701 provides oscillation to the input of inverting amplifier 815. The oscillation can travel from resonator terminal X01 to the amplifier input. Arrow 812 represents the feedback path from the output of inverting amplifier 815 back to resonator terminal X02, delivering a first drive signal to maintain the oscillation in the resonator. Similarly, arrows 821 and 822 show the electrical coupling between resonator 701 and the second oscillator core 721 in transceiver 1. Arrow 821 represents the path through which the oscillation from resonator 701 is supplied to the input of second inverting amplifier 825 via terminal X11. Arrow 822 represents the feedback path from the output of inverting amplifier 825 to resonator terminal X12, delivering a second drive signal. These bidirectional paths can form the basis for the resonator oscillation behavior maintained by the combined or individual operation of the oscillator cores 711 and 721.

[0095] In this embodiment, each inverting amplifier 815, 825 can receive the oscillation from resonator 701 at its respective input terminal and provide an amplified signal at its respective output terminal. When both oscillator cores are active, the amplifiers can work together to maintain the oscillation of resonator 701, effectively doubling the drive strength provided to resonator 701. Despite parasitic losses, this cooperative operation allows resonator 701 to maintain a consistent oscillation.

[0096] In an embodiment, the circuit may further include tuning capacitors C01 and C02 for the first oscillator core 711 and tuning capacitors C11 and C12 for the second oscillator core 721. Also shown herein, these capacitors may be connected in parallel to the corresponding terminals of the inverting amplifier and the resonator. The tuning capacitors allow for precise adjustment of the resonant frequency of the resonator 701. When both oscillator cores 711 and 721 are active, the capacitance values ​​of C01 and C11 are summed together, and similarly, the capacitance values ​​of C02 and C12 are summed together, affecting the oscillation frequency. This cooperative tuning mechanism enables the two transceivers 320a-b to maintain a stable and consistent oscillation frequency.

[0097] In an embodiment, a capacitor controller may be included in the circuitry to manage the tuning capacitors. The capacitor controller may adjust the capacitances of C01, C02, C11, and C12 based on a determination of the frequency of the oscillator signal. For example, if a deviation from the desired resonant frequency is detected, the capacitor controller may fine-tune the capacitance values ​​to bring the frequency back into alignment. Furthermore, the capacitor controller may selectively disconnect one or more capacitors from any oscillator core to manage the frequency characteristics of each core individually. Indicatively, the processor 310 or digital front-end 420 may include the capacitor controller.

[0098] In an embodiment, the inverter controller may be further implemented to manage the operation of inverting amplifiers 815 and 825. The inverter controller can individually activate or deactivate each inverting amplifier. For example, when only transceiver 0 320a is active, the inverter controller can deactivate the second inverting amplifier 825 while keeping the first inverting amplifier 815 operational. In this scenario, the first inverting amplifier 815 can individually drive resonator 701 to generate a first oscillator signal. Conversely, when transceiver 1 320b is active, the inverter controller can deactivate the first inverting amplifier 815 and allow the second inverting amplifier 825 to drive resonator 701. Indicatively, processor 310 or digital front-end 420 may include the inverter controller.

[0099] In an embodiment, the circuit can be configured to allow shaper 816 to generate a first oscillator signal based on the signal received at terminal X02 when the first inverting amplifier 815 is deactivated. This function enables the circuit to maintain clock generation for transceiver 0 320a even when its inverting amplifier 815 is deactivated. Similarly, second shaper 826 can generate a second oscillator signal based on the signal received at terminal X12 when the second inverting amplifier 825 is deactivated.

[0100] The resonator 701, which can be used as a shared oscillation source, can operate using a clipped sine wave signal at the interface with terminals X01 and X11. Compared to conventional square wave signals, this clipped sine wave signal inherently reduces harmonic emissions and minimizes interference, improving the circuit's electromagnetic compatibility. The shared resonator configuration also eliminates the need for additional clock routing or cascading mechanisms, simplifying the overall design and reducing system complexity.

[0101] Figure 9 It shows the result of Figure 8The simplified equivalent circuit described herein focuses specifically on the combined operation of oscillator cores 711 and 721 in transceiver 0320a and transceiver 1 320b. Resonator 701 is configured as a shared oscillation source for the two transceivers 320a-b coupled via terminals X1 and X2. Resonator 701 can generate a synchronized clock signal by exhibiting a predefined resonant frequency determined by its physical and material properties. This simplified equivalent circuit configuration, when activated and operating concurrently, exhibits a combined (e.g., 2x) drive strength provided by the two oscillator cores 711 and 721.

[0102] In one embodiment, the inverting amplifier 815 of the first oscillator core 711 amplifies the oscillation received from terminal X1 of the resonator 701. The amplified output can be fed back to terminal X2 of the resonator 701 to maintain the oscillation. The second oscillator core 721 can have the same configuration, with its inverting amplifier also coupled between terminals X1 and X2 of the resonator. When both cores 711 and 721 are active, the inverting amplifiers 815 and 825 cooperate to effectively double the drive strength applied to the resonator 701.

[0103] The corresponding shaper circuits 816 and 826 of each oscillator core 711, 721 can be coupled to the output of its corresponding inverting amplifier 815, 825. For example, the shaper circuit 816 associated with the first oscillator core 711 converts the sinusoidal output of the inverting amplifier 815 into a square wave signal labeled Out0. Similarly, the shaper circuit 826 connected to the second oscillator core 721 can generate a square wave output signal Out1. These square wave signals can be used as oscillator signals to drive subsequent components within their respective transceivers.

[0104] In this embodiment, tuning capacitors connected to the input and output terminals of inverting amplifiers 815 and 825 define the oscillation frequency. The combined tuning capacitance, resulting from the summation of the individual capacitors (C01 and C11 at one terminal, C02 and C12 at the other), sets the oscillation frequency. When both oscillator cores 711 and 721 are active, the capacitances are added together, co-tuning the resonator 701, which facilitates synchronizing the oscillation frequency across the two transceivers 320a-b. For this purpose, the capacitor controller can dynamically adjust the capacitance values ​​of C01, C02, C11, and C12 based on the determination of the oscillator signal frequency. In this embodiment, if a frequency deviation is detected, the capacitor controller can fine-tune the capacitance to restore the desired frequency. Furthermore, the inverter controller can selectively activate or deactivate the inverting amplifiers 815 and 825 of the oscillator cores 711 and 721. For example, when only one transceiver is active, the corresponding inverting amplifier can drive the resonator 701 alone, while the other amplifier remains deactivated.

[0105] Figure 10 It shows the result of Figure 8 An embodiment of the circuit configuration available from the circuit described herein is depicted. A shared quartz crystal resonator 701 is depicted, coupled to two transceivers 320a and 320b via terminals X01, X02, X11, and X12. In this configuration, the circuit can be configured to operate in a scenario where only one inverting amplifier is active. Indicatively, the inverting amplifier 815 of transceiver 320a can be configured to actively drive the resonator 701, while the inverting amplifier 825 remains deactivated. This setup can highlight an energy-efficient mode of operation where the resonator 701 is driven by only a single inverting amplifier, oscillating at the desired frequency.

[0106] In this embodiment, the inverting amplifier 815 amplifies the oscillation received from the resonator 701 via terminal X01 and feeds back the amplified first drive signal to terminal X02. The feedback loop facilitates maintaining the oscillation at the resonant frequency of the resonator 701. A first shaper 816 connected to the output of the inverting amplifier 815 processes the sinusoidal signal into a square wave, which can be used as the first oscillator signal for the subsequent circuitry within transceiver 1 320a. Alternatively, as indicated by the stub connection at terminal X11, the inverting amplifier 325 of transceiver 1 320b can be deactivated. In this mode, transceiver 1320b can contribute passively to driving the resonator 701. However, the resonator's oscillation can still be delivered to the input of the second shaper 826 via terminal X12. The second shaper 826 processes these oscillations into a second square wave, which can be used as the second oscillator signal for transceiver 1 320b. Although the phase noise and jitter characteristics of Out1 may differ slightly from those of Out1 due to the deactivated state of the second inverting amplifier 825, the frequency of the signal can be kept synchronized with the master oscillator signal Out0.

[0107] Tuning capacitors C01 and C02 in transceiver 0 320a, and tuning capacitors C11 and C12 in transceiver 1 320b, can remain connected in parallel to resonator 701. The capacitance values ​​may collectively affect the oscillation frequency of the resonator. The sum of the capacitances at each terminal—C01 and C11 at X01, and C02 and C12 at X02—can define the effective tuning of the shared oscillator. When the inverting amplifier 825 is deactivated, its associated capacitors can remain passively contributing to the overall capacitance.

[0108] The capacitor controller can optionally dynamically adjust the capacitance value to fine-tune the oscillation frequency as needed. In an embodiment, the capacitor controller can disconnect the tuning capacitor of the inverting amplifier, as shown here, which has been deactivated. Similarly, the inverter controller can selectively activate or deactivate inverting amplifiers 815, 825. The ability to individually control the operational state of each transceiver further enhances the versatility and energy efficiency of the communication circuitry.

[0109] Figure 11 It shows the basis Figure 10 The schematic embodiment of the equivalent circuit configuration shown illustrates the operation of a single active inverting amplifier to reduce the parasitic load on resonator 701. In this configuration, the inverting amplifier 815 of transceiver 0 320a can actively drive resonator 701, while capacitors C11 and C12 associated with the inverting amplifier 825 of transceiver 1 320b can be disconnected. This disconnection minimizes the parasitic capacitance effect on resonator 701.

[0110] In this configuration, the inverting amplifier 815 can receive the oscillation from the resonator 701 at terminal X01, amplify the oscillation, and feed the amplified first drive signal back to the resonator via terminal X02. This feedback can maintain oscillation at the oscillation frequency of the resonator 701. A first shaper 816 coupled to the output of the inverting amplifier 815 can process the amplified sine wave into a square wave to provide the output of Out0. Compared to the second oscillator signal, the first oscillator signal can be used as a more accurate and lower phase noise reference clock for the subsequent circuitry within the transceiver 0 320a.

[0111] On the other hand, the inverting amplifier 825 of transceiver 1320b can be deactivated, and its capacitors C11 and C12 can be disconnected. This setting reduces the load on resonator 701 and allows the inverting amplifier 815 to maintain stable oscillation without interference from the deactivated amplifier. Although the inverting amplifier 825 is deactivated, the oscillation of the resonator can be delivered to the second shaper 826 via terminal X12. The second shaper 826 can convert the sinusoidal oscillation into a square wave to provide the output of Out1, which is used as the second oscillator signal of transceiver 1320b. Although Out1 may exhibit slightly different noise characteristics compared to Out0 due to the deactivated state of its corresponding amplifier, its frequency can be kept synchronized with Out0, ensuring consistent operation across the two transceivers.

[0112] In this configuration, tuning capacitors C01 and C02 in transceiver 0 320a can be used to set the oscillation frequency of resonator 701. Capacitors C11 and C12, disconnected from transceiver 1 320b, may no longer contribute to the effective capacitance at terminals X01 and X02, minimizing unwanted load effects on resonator 701 and facilitating frequency calibration via active capacitors. The capacitor controller can dynamically manage the connection or disconnection of the tuning capacitors based on the operational status of inverting amplifiers 815 and 825.

[0113] Figure 12 A multi-band wireless communication circuit is shown. The multi-band wireless communication circuit includes components according to... Figure 7 The described communication circuitry. Indicatively, the multi-band wireless communication circuitry can be an embodiment of a Wi-Fi tri-band dual-concurrent system operating across 2.4 GHz, 5–6 GHz, and 6–7 GHz frequency bands. The multi-band wireless communication circuitry employs communication circuitry with two transceivers 320a, 320b, including a shared single quartz crystal resonator 701, to provide a synchronous reference clock for effective communication across multiple frequency bands. The resonator 701 is coupled to the two transceivers 320a-320b in a parallel configuration. Oscillator cores 711, 721 within transceivers 320a-b can generate oscillator signals based on the oscillations of the resonators. In this embodiment, each transceiver 320a-b includes its corresponding phase-locked loop circuitry 712-714 and transmitter and receiver circuitry 725 including radio frequency (RF) chains 725-1, 725-2. The oscillator cores 711, 721 can drive the resonator 701.

[0114] The first transceiver circuit 320a may include a first RF chain 715-1 and a second RF chain 715-2, each configured to modulate or demodulate communication signals in the 2.4 GHz band and the 5–6 GHz band. These RF chains can receive input oscillator signals from phase-locked loops 712-714 that process the first oscillator signal generated by the first oscillator core 711. The phase-locked loops 712-714 may be implemented as low-frequency (LB) and high-frequency (HB) phase-locked loops, respectively, to provide corresponding phase-locked loop output signals to the RF chains 715-1 and 715-2.

[0115] Similarly, the second transceiver circuit 320b may include two RF chains, each configured for operation in the 5–7 GHz frequency band: a first RF chain 725-1 and a second RF chain 725-2. These RF chains 725-1 and 725-2 may utilize phase-locked outputs derived from a second oscillator signal generated by the second oscillator core 701, wherein the phase-locked outputs may be provided by phase-locked loops 722-724. Phase-locked loops 722-724 may be implemented as low-frequency (LB) and high-frequency (HB) phase-locked loops, respectively, to provide corresponding phase-locked loop output signals to RF chains 725-1 and 725-2.

[0116] Each first RF chain 715-1, 725-1 of the first and second transceivers 320a-b can be coupled to one or more first antennas via a corresponding filter, duplexer circuit, and coaxial cable. Similarly, each second RF chain 715-2, 725-2 of the first and second transceivers 320a-b can be coupled to one or more second antennas via another corresponding filter, duplexer circuit, and another coaxial cable for multi-band wireless communication operation. A shared resonator 701 may enable synchronization between the transceivers 320a-b to ensure that the oscillator signals across all frequency bands remain frequency-locked regardless of the operation of each RF chain. In this implementation, the resonant frequency of the resonator can be fine-tuned by its associated tuning capacitor in the respective oscillator cores 711, 721. The tuning process can achieve frequency accuracy across all frequency bands.

[0117] Figure 13 A multiple-input multiple-output (MIMO) communication circuit is shown. The MIMO communication circuit may include, according to... Figure 7 The described communication circuit. Indicatively, the MIMO communication circuit can be a Wi-Fi 2x2 multiple-input multiple-output system comprising two transceiver integrated circuits 320a-b sharing a single quartz crystal resonator 701. The quartz crystal resonator 701 can be used as a synchronization reference clock source for the two transceivers 320a-b to perform MIMO communication.

[0118] The first transceiver circuit, transceiver 320a, may include an oscillator core 711 electrically coupled to a resonator 701. The oscillator core 711 can generate a first oscillator signal processed by phase-locked loop circuits 712, 713, and 714. These phase-locked loops may correspond to LB, HB, and UHB frequencies, respectively, and provide phase-locked signals for the corresponding frequency bands to RF chains 715-3 and 715-4. For example, RF chain 715-3 may be configured for the 2.4 GHz band, while RF chain 715-4 may support operation in the 5–7 GHz band. Each RF chain may be connected to its corresponding filter and duplexer circuitry, which can be interfaced with an external antenna via a coaxial cable for communication tasks including transmission and reception.

[0119] The STEP (Serial Time Coding Protocol) circuit 715-1 can be configured for initial signal conditioning tasks, which may include amplification, filtering, and spatial processing techniques to encode and decode the serial data stream. This can optimize multiple data streams for MIMO operation to enhance signal quality and minimize interference. The time-domain circuit 715-2 facilitates time-domain processing, encodes digital information into time variables during transmission, and performs time-domain quantization during reception. The time-domain circuit 715-2 also supports space-time coding for spatial diversity in MIMO systems. Block 715-5 can represent a stage including modulation and demodulation, which may include intermediate frequency conversion. This stage may include a mixer and amplifier and can operate using signals provided by PLLs 712-714.

[0120] Similarly, transceiver 320b may include an oscillator core 721 coupled to a shared resonator 701 to generate a second oscillator signal. This signal can be processed by PLLs 722, 723, and 724 corresponding to the LB, HB, and UHB frequency ranges. Phase-locked loops can provide phase-locked signals for the corresponding frequency bands to RF chains 725-3 and 725-4 to manage communication in the 2.4 GHz and 5–7 GHz bands, respectively. These RF chains 725-3 and 725-4 can be connected to an antenna via filters, duplexer circuitry, and coaxial cables. Similar to its box in transceiver 320a, STEP box 725-1 in transceiver 320b performs signal conditioning, spatial processing, and interference cancellation. Time-domain box 725-2 facilitates time-domain coding and quantization. Box 725-5 also provides frequency conversion.

[0121] The shared resonator 701 facilitates clock synchronization between the two transceivers 320a-b, enabling frequency-locked operation across the entire frequency band. Tuning capacitors associated with oscillator cores 711 and 721 allow for fine-tuning of the resonator frequency. As shown here, this configuration supports efficient, concurrent operation of both transceivers, making it well-suited for complex MIMO communication scenarios.

[0122] Figure 14 An embodiment of the method is shown. The method may include: causing a resonator to oscillate at a resonant frequency 1401; driving the resonator using a first oscillator core by providing a first drive signal to the resonator and generating a first oscillator signal 1402 based on the oscillation of the resonator; and driving the resonator using a second oscillator core by providing a second drive signal to the resonator and generating a second oscillator signal 1403 based on the oscillation of the resonator.

[0123] The following embodiments relate to other aspects described herein.

[0124] Example 1 is the subject of an apparatus that may include: a resonator configured to oscillate at a resonant frequency; a first oscillator core and a second oscillator core coupled to the resonator in a parallel configuration; the first oscillator core being configured to drive the resonator by providing a first drive signal and to generate a first oscillator signal based on the oscillation of the resonator; and the second oscillator core being configured to drive the resonator by providing a second drive signal and to generate a second oscillator signal based on the oscillation of the resonator.

[0125] Example 2 may include the subject of Example 1, wherein the resonator is a single quartz crystal resonator.

[0126] Instance 3 may include the subject of Instance 1 or Instance 2, wherein the first oscillator core and the second oscillator core are configured to operate concurrently.

[0127] Example 4 may include the subject of any one of Examples 1 to 3, and may further include a core controller configured to activate the operation of the first oscillator core and the second oscillator core; wherein the core controller is further configured to, for example, activate one of the first oscillator cores or the second oscillator core individually, regardless of the activation state of the other of the first oscillator cores or the second oscillator cores.

[0128] Example 5 may include the subject matter of any one of Examples 1 to 4, wherein a first oscillator core is coupled to a resonator at a first terminal and a second terminal; wherein a second oscillator core is coupled to a resonator at a first terminal and a second terminal.

[0129] Example 6 may include the subject matter of any one of Examples 1 to 5, wherein the first oscillator core includes: a first inverting amplifier configured to amplify the oscillation of a resonator received from a first terminal to obtain a first drive signal, wherein the output of the first inverting amplifier is coupled to a second terminal to provide the first drive signal to the resonator; and a first shaper coupled to the output of the first inverting amplifier and configured to generate a first oscillator signal based on the first drive signal.

[0130] Example 7 may include the subject matter of Example 6, wherein the first inverting amplifier includes an input configured to receive an oscillation of a resonator; wherein the core of the first oscillator further includes a first tuning capacitor coupled to the input of the first inverting amplifier and a second tuning capacitor coupled to the output of the first inverting amplifier.

[0131] Example 8 may include the subject matter of Example 7, wherein the second oscillator core includes: a second inverting amplifier configured to amplify the oscillation of the resonator received from the first terminal to obtain a second drive signal, wherein the output of the second inverting amplifier is coupled to the second terminal to provide the second drive signal to the resonator; and a second shaper coupled to the output of the second inverting amplifier and configured to generate a second oscillator signal based on the second drive signal.

[0132] Example 9 may include the subject matter of Example 8, wherein the second inverting amplifier includes an input configured to receive an oscillation of a resonator; wherein the core of the second oscillator further includes a first tuning capacitor coupled to the input of the second inverting amplifier and a second tuning capacitor coupled to the output of the second inverting amplifier.

[0133] Example 10 may include the subject matter of Example 9, and may further include: a capacitor controller configured to tune the tuning capacitors of the first oscillator core and the second oscillator core based on the determination of the frequencies of the first oscillator signal and the second oscillator signal.

[0134] Example 11 may include the subject of Example 10, wherein the capacitor controller is further configured to disconnect one of the tuning capacitors of the first oscillator core or the tuning capacitor of the second oscillator core.

[0135] Example 12 may include the subject matter of any one of Examples 8 to 11, and may further include an inverter controller configured to activate the operation of the first inverting amplifier and the second inverting amplifier; wherein the inverter controller is further configured to, for example, activate one of the first inverting amplifiers or the second inverting amplifier individually, regardless of the activation state of the other of the first inverting amplifiers or the second inverting amplifiers.

[0136] Example 13 may include the subject matter of Example 12, wherein the inverter controller is further configured to deactivate the first inverting amplifier; wherein the first shaper is configured to generate a first oscillator signal based on a signal received at a second terminal when the first inverting amplifier is deactivated.

[0137] Example 14 may include the subject matter of any one of Examples 1 to 13, and may further include: a first transceiver circuit, including: a first oscillator core; at least one first communication circuit coupled to the first oscillator core and configured to receive a first oscillator signal and use the first oscillator signal to perform at least one of the following: transmitting one or more first communication signals or receiving one or more first communication signals; a second transceiver circuit, including: a second oscillator core; at least one second communication circuit coupled to the second oscillator core and configured to receive a second oscillator signal and use the second oscillator signal to perform at least one of the following: transmitting one or more second communication signals or receiving one or more second communication signals.

[0138] Example 15 may include the subject matter of Example 14 and may further include a transceiver controller configured to control at least one first communication circuit and at least one second communication circuit.

[0139] Example 16 may include the subject matter of Example 14 or Example 15, wherein the first transceiver circuitry includes at least one phase-locked loop configured to generate a phase-locked signal based on a first oscillator signal; and wherein the second transceiver circuitry includes at least another phase-locked loop configured to generate another phase-locked signal based on a second oscillator signal.

[0140] Example 17 may include the subject matter of Example 16, wherein the first transceiver circuitry includes a first radio frequency (RF) chain configured to modulate or demodulate one or more first communication signals based on a phase-locked signal; wherein the second transceiver circuitry includes a second RF chain configured to modulate or demodulate one or more second communication signals based on another phase-locked signal.

[0141] Example 18 may include the subject matter of any one of Examples 14 to 17, wherein a first transceiver circuit is configured to transmit or receive one or more first communication signals in a first frequency band; wherein a second transceiver circuit is configured to transmit or receive one or more second communication signals in a second frequency band.

[0142] Example 19 may include the subject matter of any one of Examples 14 to 17, wherein the first transceiver circuitry and the second transceiver circuitry are configured to perform multiple-input multiple-output (MIMO) communication via one or more first communication signals and one or more second communication signals.

[0143] Example 20 may include the subject matter of any one of Examples 1 to 19, and may further include an integrated circuit and a package or printed circuit board (PCB), wherein the package or PCB includes a resonator and the integrated circuit includes a first oscillator core and a second oscillator core.

[0144] Example 21 may include the subject matter of a method comprising: causing a resonator to oscillate at a resonant frequency; driving the resonator using a first oscillator core by providing a first drive signal to the resonator and generating a first oscillator signal based on the oscillation of the resonator; and driving the resonator using a second oscillator core by providing a second drive signal to the resonator and generating a second oscillator signal based on the oscillation of the resonator.

[0145] Example 22 may include the subject of Example 21, wherein the resonator is a single quartz crystal resonator.

[0146] Example 23 may include the subject of Example 21 or Example 22, and may further include enabling the first oscillator core to operate concurrently with the second oscillator core.

[0147] Example 24 may include the subject matter of any of Examples 21 to 23, and may further include: activating the first oscillator core and the second oscillator core using a core controller; and, for example, activating one of the first oscillator cores or the second oscillator core individually, regardless of the activation state of the other of the first oscillator cores or the second oscillator cores.

[0148] Example 25 may include the subject matter of any one of Examples 21 to 24, and may further include: coupling a first oscillator core to a resonator at a first terminal and a second terminal; and coupling a second oscillator core to a resonator at a first terminal and a second terminal.

[0149] Example 26 may include the subject matter of any one of Examples 21 to 25, and may further include: amplifying the oscillation of the resonator received from the first terminal by a first inverting amplifier at the core of the first oscillator to obtain a first drive signal; providing the first drive signal to the resonator by coupling the output of the first inverting amplifier to the second terminal; and generating a first oscillator signal based on the first drive signal using a first shaper coupled to the output of the first inverting amplifier.

[0150] Example 27 may include the subject matter of Example 26, and may further include: receiving the oscillation of the resonator at the input of the first inverting amplifier; and tuning the oscillation using a first tuning capacitor coupled to the input of the first inverting amplifier and a second tuning capacitor coupled to the output of the first inverting amplifier.

[0151] Example 28 may include the subject matter of Example 27 and may further include: amplifying the oscillation of the resonator received from the first terminal by a second inverting amplifier at the core of the second oscillator to obtain a second drive signal; providing the second drive signal to the resonator by coupling the output of the second inverting amplifier to the second terminal; and generating a second oscillator signal based on the second drive signal using a second shaper coupled to the output of the second inverting amplifier.

[0152] Example 29 may include the subject matter of Example 28, and may further include: receiving the oscillation of the resonator at the input of the second inverting amplifier; and tuning the oscillation using a first tuning capacitor coupled to the input of the second inverting amplifier and a second tuning capacitor coupled to the output of the second inverting amplifier.

[0153] Example 30 may include the subject matter of Example 29, and may further include: a tuning capacitor for tuning the first oscillator core and the second oscillator core based on the determination of the frequencies of the first oscillator signal and the second oscillator signal.

[0154] Example 31 may include the subject matter of Example 30 and may further include: using a capacitor controller to disconnect one of the tuning capacitors of the first oscillator core or the tuning capacitor of the second oscillator core, for example, regardless of the connection status of the other tuning capacitors.

[0155] Example 32 may include the subject matter of any of Examples 28 to 31, and may further include: activating the operation of the first inverting amplifier and the second inverting amplifier using an inverter controller; and activating one of the first inverting amplifier or the second inverting amplifier individually using an inverter controller, regardless of the other inverting amplifier.

[0156] Example 33 may include the subject matter of Example 32, and may further include: using an inverter controller to deactivate a first inverting amplifier; and when the first inverting amplifier is deactivated, generating a first oscillator signal based on a signal received at a second terminal.

[0157] Example 34 may include the subject matter of any one of Examples 21 to 33, and may further include: receiving a first oscillator signal from a first oscillator core by at least one first communication circuit of a first transceiver circuit; performing at least one of transmitting or receiving one or more first communication signals using the first oscillator signal; receiving a second oscillator signal from a second oscillator core by at least one second communication circuit of a second transceiver circuit; and performing at least one of transmitting or receiving one or more second communication signals using the second oscillator signal.

[0158] Example 35 may include the subject matter of Example 34 and may further include: using a transceiver controller to control at least one first communication circuit and at least one second communication circuit.

[0159] Example 36 may include the subject matter of Example 34 or Example 35, and may further include: generating a phase-locked signal by at least one phase-locked loop of the first transceiver circuit based on a first oscillator signal; and generating another phase-locked signal by at least one additional phase-locked loop of the second transceiver circuit based on a second oscillator signal.

[0160] Example 37 may include the subject matter of Example 36 and may further include: using a first radio frequency processing chain of a first transceiver circuit to modulate or demodulate one or more first communication signals based on a phase-locked signal; and using a second radio frequency processing chain of a second transceiver circuit to modulate or demodulate one or more second communication signals based on another phase-locked signal.

[0161] Example 38 may include the subject matter of any one of Examples 34 to 37, and may further include: using a first transceiver circuit to transmit or receive one or more first communication signals in a first frequency band; and using a second transceiver circuit to transmit or receive one or more second communication signals in a second frequency band.

[0162] Example 39 may include the subject matter of any one of Examples 34 to 37, and may further include: performing multiple-input multiple-output (MIMO) communication using a first transceiver circuit and a second transceiver circuit via one or more first communication signals and one or more second communication signals.

[0163] Example 40 may include the subject matter of any of Examples 21 to 39, and may further include: setting a resonator on a package or printed circuit board; and integrating a first oscillator core and a second oscillator core on an integrated circuit.

[0164] Example 41 may include a non-transitory computer-readable medium containing instructions that, if executed by a processor, cause a system including the processor to execute the subject matter of any one of Examples 21 to 40.

[0165] The word "exemplary" is used herein to mean "used as an embodiment, example, or illustration." Any implementation or design described herein as "exemplary" must not necessarily be considered preferred or advantageous relative to other implementations or designs.

[0166] The terms “plural” and “multiple” in this specification and claims explicitly refer to a quantity greater than one. The terms “group,” “set,” “set,” “series,” “sequence,” “grouping,” etc., in this specification and claims refer to a quantity equal to or greater than one, i.e., one or more. Any term expressed in a plural form that does not explicitly state “plural” or “multiple” also refers to a quantity equal to or greater than one.

[0167] The arbitrary vector and / or matrix notations used herein are exemplary in nature and are employed for illustrative purposes only. Accordingly, the apparatus and methods described herein with respect to vector and / or matrix notations are not limited to implementation using only vectors and / or matrices, and can perform associated processes and calculations on sets, sequences, groups, etc., of data, observations, information, signals, samples, symbols, elements, etc.

[0168] As used herein, “memory” is understood to be a non-transitory computer-readable medium in which data or information is stored for retrieval. Reference to “memory” as used herein can thus be understood to refer to volatile or non-volatile memory, including random access memory (“RAM”), read-only memory (“ROM”), flash memory, solid-state storage, magnetic tape, hard disk drive, optical drive, etc., or any combination thereof. Furthermore, registers, shift registers, processor registers, data buffers, etc., are also covered by the term memory herein. A single component referred to as “memory” or “a memory” may consist of more than one different type of memory, and thus may refer to a set of components including one or more types of memory. Any single memory component can be divided into multiple uniform and equivalent memory components, and vice versa. Furthermore, although memory can be described as separate from one or more other components (e.g., in the figures), memory can also be integrated with other components, such as on a common integrated chip or on a controller with embedded memory.

[0169] The term "software" refers to any type of executable instructions, including firmware.

[0170] In the context described herein, the term "process" may be used to mean, for example, a method. Exemplarily, any process described herein can be implemented as a method (e.g., a channel evaluation process can be understood as a channel evaluation method). Any process described herein can be implemented as a non-transitory computer-readable medium comprising instructions configured, when executed, to cause one or more processors to perform the process (e.g., execute a method).

[0171] Throughout the accompanying drawings, it should be noted that similar reference numerals are used to describe the same or similar elements, features, and structures, unless otherwise stated. It should be noted that specific components may be omitted for brevity. It should be noted that nodes (points) are provided to identify circuit line intersections in the drawings, including electronic circuit diagrams.

[0172] The phrases “at least one” and “one or more” can be understood to include a numerical quantity greater than or equal to one (e.g., one, two, three, four, [...] etc.). The phrase “at least one” for a group of elements can be used here to refer to at least one element from a group of elements. For example, the phrase “at least one” for a group of elements can be used here to refer to selecting one of the listed elements, multiple of one of the listed elements, multiple separately listed elements, or multiple of multiple separately listed elements.

[0173] The terms “plural” and “multiple” in this specification and claims explicitly refer to a quantity greater than one. Accordingly, any of the aforementioned phrases that explicitly refer to a number of elements (e.g., “plural [elements]”, “multiple [elements]”) explicitly refer to more than one of the stated elements. For example, the phrase “a plurality” can be understood to include a numerical quantity greater than or equal to two (e.g., two, three, four, five, [...] etc.).

[0174] As used herein, a signal or information that "indicates," "represents," "represents," or "indicates" a value or other information can be a digital or analog signal that encodes or otherwise communicates the value or other information in a manner that enables decoding and / or causes corresponding actions in the receiving component. The signal may be stored in or buffered in a computer-readable storage medium before being received by the receiving component, and the receiving component may retrieve the signal from the storage medium. Furthermore, a "value," i.e., "indicating" or "representing" a quantity, state, or parameter, may physically encompass a digital signal, an analog signal, or stored bits that encode or otherwise communicate the value.

[0175] As used here, signals can be transmitted or conducted through a signal chain, where they are processed to change characteristics such as phase, amplitude, and frequency. Even if these characteristics are adapted, the signals can be referred to as the same signal. Generally speaking, as long as the signals continue to encode the same information, the signals can be considered the same signal. For example, a transmitted signal can be considered as a baseband, intermediate frequency, and radio frequency transmitted signal.

[0176] For example, as used herein, the terms "processor" or "controller" can be understood as any type of technical entity that allows data processing. Data can be processed according to one or more specific functions performed by the processor. Further, as used herein, a processor or controller can be understood as any type of circuit, such as any type of analog or digital circuit. A processor or controller can thus be or include analog circuits, digital circuits, mixed-signal circuits, logic circuits, processors, microprocessors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), integrated circuits, application-specific integrated circuits (ASICs), etc., or any combination thereof. Any other type of implementation of the corresponding functions, which will be described in further detail below, can also be understood as a processor, controller, or logic circuit. It should be understood that any two (or more) of the processors, controllers, or logic circuits detailed herein can be implemented as a single entity with equivalent functions, and conversely, any single processor, controller, or logic circuit detailed herein can be implemented as two (or more) independent entities with equivalent functions.

[0177] The term "one or more processors" is intended to refer to a processor or controller. One or more processors may include one or more processors. The term is used only as an alternative to "processor" or "controller".

[0178] The term "user equipment" is intended to refer to a user device (e.g., an occupant) that can be configured to provide information related to a user. User equipment may include, exemplarily, mobile phones, smartphones, wearable devices (e.g., smartwatches, smart wristbands), computers, and the like.

[0179] As used herein, the terms “module,” “component,” “system,” “circuit,” “element,” “slice,” and “circuit” are intended to refer to a collection of one or more electronic components, computer-related entities, hardware, software (e.g., running), and / or firmware. For example, a circuit or similar term can be a processor, a process running on a processor, a controller, an object, an executable program, a storage device, and / or a computer having processing capabilities. For example, an application running on a server and a server itself can also be a circuit. One or more circuits can reside in the same circuit, and circuits can be located on one computer and / or distributed among two or more computers. A collection of elements or other collections of circuits can be described herein, wherein the term “collection” can be interpreted as “one or more.”

[0180] As used herein, the term "data" can be understood to include information in any suitable analog or digital form, such as as a file, part of a file, a set of files, a signal or stream, part of a signal or stream, a set of signals or streams, etc. Furthermore, the term "data" can also be used to refer to reference information, for example, in pointer form. However, as those skilled in the art will understand, the term "data" is not limited to the embodiments described above and can take various forms and represent arbitrary information. The term "data item" can include data or a portion of data.

[0181] It will be understood that when a component is referred to as being "connected" or "coupled" to another component, the component is physically connected or coupled to the other component such that current and / or electromagnetic radiation (e.g., signals) can flow along a conductive path formed by the component. Inherently, the component can be connected or coupled to another component. When a component is described as being coupled or connected to another component, an intervening conductive, inductive, or capacitive component may be present between the component and the other component. Furthermore, when coupled or connected to another component, a component may be able to sense the flow or propagation of voltage or current of electromagnetic waves in the other component without physical contact or intervening components. Further, when a voltage, current, or signal is referred to as being "applied" to a component, the voltage, current, or signal can be conducted to the component either through a physical connection or through capacitive, electromagnetic, or inductive coupling that does not involve a physical connection.

[0182] Unless otherwise specified, the term "instance of time" refers to the time of a specific event or situation that fits the context. An instance of time can refer to a point in time or a period of time involving a specific event or situation.

[0183] Unless explicitly stated otherwise, the term “transmit” includes both direct (point-to-point) and indirect transmission (via one or more intermediate points). Similarly, the term “receive” includes both direct and indirect reception. Further, the terms “transmit,” “receive,” “communication,” and other similar terms include both physical transmission (e.g., transmission of radio signals) and logical transmission (e.g., transmission of digital data via a logical software-level connection). For example, a processor or controller may transmit or receive data in the form of radio signals via a software-level connection to another processor or controller, wherein physical transmission and reception are handled by wireless layer components, such as RF transceivers and antennas, and logical transmission and reception via a software-level connection are performed by the processor or controller. The term “communication” includes one or both of transmission and reception, i.e., one-way or two-way communication in one or both directions of incoming and outgoing traffic. The term “computation” includes both ‘direct’ computation via mathematical expressions / formulas / relations and ‘indirect’ computation via lookup tables or hash tables and other array indexing or search operations.

[0184] Although the diagrams and connections described above can depict electronic device components as independent elements, those skilled in the art will recognize the various possibilities of combining or integrating discrete components into a single element. These possibilities may include combining two or more circuits to form a single circuit, mounting two or more circuits on a common chip or chassis to form an integrated element, running discrete software components on a common processor core, etc. Conversely, those skilled in the art will recognize the possibility of dividing a single element into two or more discrete elements, such as dividing a single circuit into two or more independent circuits, dividing a chip or chassis into discrete components initially disposed thereon, dividing software components into two or more segments, and running individual software components on independent processor cores, etc.

[0185] It should be understood that the implementation of the method detailed herein is illustrative in nature and is therefore to be understood as being implementable in a corresponding device. Similarly, it should be understood that the implementation of the device detailed herein is to be understood as being implementable as the corresponding method. Therefore, it should be understood that a device corresponding to the method detailed herein may include one or more components configured to perform various aspects of the method. All abbreviations defined in the above description also apply to all claims included herein.

Claims

1. An apparatus comprising: The resonator is configured to oscillate at its resonant frequency; as well as The first oscillator core and the second oscillator core are coupled to the resonator in a parallel configuration; The first oscillator core is configured to drive the resonator by providing a first drive signal and generate a first oscillator signal based on the oscillation of the resonator; and The second oscillator core is configured to drive the resonator by providing a second drive signal and generate a second oscillator signal based on the oscillation of the resonator.

2. The apparatus according to claim 1, wherein, The resonator is a single quartz crystal resonator.

3. The apparatus according to claim 1, wherein, The first oscillator core and the second oscillator core are configured to operate concurrently.

4. The apparatus of claim 1, further comprising a core controller configured to activate the operation of the first oscillator core and the second oscillator core; and in, The core controller is further configured to activate either the first oscillator core or the second oscillator core individually, regardless of the activation status of the other of the first oscillator core or the second oscillator core.

5. The apparatus according to claim 1, wherein, The first oscillator core is coupled to the resonator at the first and second terminals; and The second oscillator core is coupled to the resonator at the first terminal and the second terminal.

6. The apparatus according to any one of claims 1 to 5, wherein, The first oscillator core includes: A first inverting amplifier is configured to amplify the oscillation of the resonator received from the first terminal to obtain the first drive signal, wherein the output of the first inverting amplifier is coupled to the second terminal to provide the first drive signal to the resonator; and A first shaper is coupled to the output of the first inverting amplifier and configured to generate the first oscillator signal based on the first drive signal.

7. The apparatus according to claim 6, wherein, The first inverting amplifier includes an input terminal configured to receive the oscillation of the resonator; and The first oscillator core further includes a first tuning capacitor coupled to the input terminal of the first inverting amplifier and a second tuning capacitor coupled to the output terminal of the first inverting amplifier.

8. The apparatus according to claim 7, wherein, The second oscillator core includes: A second inverting amplifier is configured to amplify the oscillation of the resonator received from the first terminal to obtain the second drive signal, wherein the output of the second inverting amplifier is coupled to the second terminal to provide the second drive signal to the resonator; and A second shaper is coupled to the output of the second inverting amplifier and configured to generate the second oscillator signal based on the second drive signal.

9. The apparatus according to claim 8, wherein, The second inverting amplifier includes an input configured to receive the oscillation of the resonator; and The second oscillator core further includes a first tuning capacitor coupled to the input terminal of the second inverting amplifier and a second tuning capacitor coupled to the output terminal of the second inverting amplifier.

10. The apparatus of claim 9, further comprising: A capacitor controller is configured to tune the tuning capacitors of the first oscillator core and the second oscillator core based on the determination of the frequencies of the first oscillator signal and the second oscillator signal.

11. The apparatus of claim 8, further comprising an inverter controller configured to activate the operation of the first inverting amplifier and the second inverting amplifier, wherein, The inverter controller is further configured to activate either the first inverting amplifier or the second inverting amplifier individually, regardless of the activation state of the other of the first inverting amplifier or the second inverting amplifier.

12. The apparatus according to any one of claims 1 to 5, further comprising: The first transceiver circuit includes: The first oscillator core; and At least one first communication circuit, coupled to the first oscillator core and configured to receive the first oscillator signal and use the first oscillator signal to perform at least one of the following: transmitting one or more first communication signals or receiving one or more first communication signals; and The second transceiver circuit includes: The second oscillator core; and At least one second communication circuit is coupled to the second oscillator core and configured to receive the second oscillator signal and use the second oscillator signal to perform at least one of the following: sending one or more second communication signals or receiving one or more second communication signals.

13. The apparatus according to claim 12, wherein, The first transceiver circuit includes at least one phase-locked loop configured to generate a phase-locked signal based on the first oscillator signal; The second transceiver circuit includes at least one other phase-locked loop configured to generate another phase-locked signal based on the second oscillator signal.

14. The apparatus according to claim 12, wherein, The first transceiver circuit is configured to transmit or receive the one or more first communication signals in a first frequency band; and The second transceiver circuit is configured to transmit or receive the one or more second communication signals in a second frequency band.

15. The apparatus according to claim 12, wherein, The first transceiver circuit and the second transceiver circuit are configured to perform multiple-input multiple-output (MIMO) communication via the one or more first communication signals and the one or more second communication signals.

16. The apparatus according to any one of claims 1 to 5, further comprising an integrated circuit and a package or printed circuit board (PCB), wherein, The package or the PCB includes the resonator, and the integrated circuit includes the first oscillator core and the second oscillator core.

17. A method comprising: The resonator oscillates at its resonant frequency. The resonator is driven by a first oscillator core that provides a first drive signal to the resonator; A first oscillator signal is generated based on the oscillation of the resonator; and The resonator is driven by a second oscillator core that provides a second drive signal to the resonator, and a second oscillator signal is generated based on the oscillation of the resonator.

18. The method of claim 17, further comprising: The operation of activating the first oscillator core and the second oscillator core separately.

19. A non-transitory computer-readable medium comprising instructions that, if executed by a processor, cause a system comprising the processor to: The resonator oscillates at its resonant frequency. The resonator is driven by a first oscillator core that provides a first drive signal to the resonator; A first oscillator signal is generated based on the oscillation of the resonator; and The resonator is driven by a second oscillator core that provides a second drive signal to the resonator, and a second oscillator signal is generated based on the oscillation of the resonator.

20. The non-transitory computer-readable medium according to claim 19, wherein, The instruction further causes the system to activate the operation of the first oscillator core and the second oscillator core separately.

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