Gain adaptive readout circuit, gain controller circuit, and method of operation thereof

Abstract

The present invention relates to a gain adaptive readout circuit, a gain controller circuit and methods of operation thereof. A sample and hold circuit includes a pixel level connection coupled to a pixel cell. In a voltage domain global shutter operation, a reset voltage and a signal voltage are sequentially sampled and stored in a reset capacitor and a signal capacitor. At readout, the stored signal voltage is first read out to a comparison circuit to determine an optimal gain factor for an analog to digital converter circuit to fully utilize the conversion range of the analog to digital converter for better signal to noise ratio. Once the better gain for the analog to digital converter is determined and set by comparing the signal voltage to a predetermined threshold voltage, the same signal voltage is directly converted by the analog to digital converter to become a digital signal value. The analog to digital converter then converts the stored reset voltage to a digital reset value without changing the gain factor, thereby shortening the readout time.

Description

Technical Field

[0001] This disclosure generally relates to image sensors, and more particularly but not exclusively to sample and hold (S&H) circuit systems and the use of values ​​stored in the S&H circuit systems to assist in reading out image data from the analog-to-digital conversion (ADC) of the image sensor, and particularly to a gain adaptive readout circuit, a gain controller circuit, and a method of operating the same. Background Technology

[0002] Image sensors are ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, and in medical, automotive, and other applications. The technologies used to manufacture image sensors continue to evolve rapidly. For example, the demand for higher resolution and lower power consumption is driving further miniaturization and integration of these devices.

[0003] Traditionally, image sensors receive light across an array of pixels, which in turn generate electrical charges within those pixels. The intensity of the light can affect the amount of charge generated in each pixel; higher intensity results in a greater amount of charge. Correlated double sampling (CDS) is a technique used with complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) to reduce noise in the image readout from the image sensor by sampling the image data from the sensor and removing unwanted offsets from the reset value readings. In a global shutter CIS design, sample-and-hold switches are used for the sample-and-hold signal (SHS) reading and the sample-and-hold reset (SHR) reading from the image sensor. The SHR and SHS switches in the sample-and-hold circuitry are controlled to sample the reset and signal levels from the image sensor, respectively. Ideally, during the global sampling phase, all sample and hold switches toggle simultaneously to sample the entire frame from the image sensor into the storage capacitor. After global sampling is complete, line-by-line readout from the image sensor is performed to digitize the sampled reset and signal levels. The digitized difference between the reset and signal levels is used in CDS calculations to reconstruct the true image signal. To further reduce random noise, correlated multiple sampling (CMS) can be implemented.

[0004] Implementing CDS reduces fixed pattern noise (FPN) and other temporal noise (e.g., kT / C thermal noise) from image data. Correlated double sampling (CDS) and correlated multiple sampling (CMS) can be performed in the analog or digital domain.

[0005] Voltage domain global shutter (VDGS) pixel arrays typically use at least two storage capacitors as memory for the reset voltage value (RESET) and signal voltage value (SIGNAL) for the CDS, and three or more storage capacitors as memory for one or more RESET values ​​and one or more SIGNAL values ​​for the CMS. To meet low kT / C thermal noise requirements, the two storage capacitors need to maintain a sufficiently large layout size for typical capacitance values ​​in the tens of femtofarads (fF).

[0006] A system for digitally correlated double sampling for an image sensor with multiple pixels includes: an analog-to-digital converter (ADC) stage for converting analog data into digital image data and outputting reset data; a memory for storing both the digital image data and the reset data; and a digitally correlated double sampling (DCDS) stage for generating digitally correlated double sampled image data based on the subtraction between the digital image data and the digital reset data. Summary of the Invention

[0007] An adaptive analog-to-digital converter (ADC) gain controller circuit according to this disclosure, for use in a voltage-domain global shutter (VDGS) image sensor, includes: a pixel-level connection coupled to a pixel cell; a reset transistor coupled between a power supply voltage and the pixel-level connection; a source follower transistor having a gate coupled to the pixel-level connection; a row select transistor coupled between the source follower transistor and a bit line; a reset switch transistor coupled to the pixel-level connection; a reset storage capacitor coupled between the reset switch transistor and ground to receive a reset voltage of the pixel cell; a signal switch transistor coupled to the pixel-level connection; and a signal storage... A capacitor, coupled between the signal switching transistor and ground, to receive the signal voltage of the pixel cell; a G-cap unit, coupled to the bit line; a gain stage, including a first input coupled to the bit line, a second input coupled to the output of the G-cap unit, a third input coupled to a ramp voltage, a first output coupled to the positive input terminal of the analog-to-digital converter comparator, and a second output coupled to the negative input terminal of the analog-to-digital converter comparator, wherein the gain stage includes more than one gain factor under the control of the second input and a high gain factor is used as its initial default factor; and an analog-to-digital converter counter, coupled between the output of the analog-to-digital converter comparator and the digital output of the analog-to-digital converter.

[0008] A method for adaptively setting a gain factor to prepare for analog-to-digital converter (ADC) operation according to this disclosure includes: firstly sampling a reset voltage from a pixel cell via a reset access switch and storing the reset voltage in a reset capacitor, and secondly sampling a signal voltage from the pixel cell via a signal access switch and storing the signal voltage in a signal capacitor; then generating a voltage pulse to turn a reset transistor on and off, thereby resetting the pixel line voltage to the power supply voltage; presetting the gain factor of the gain stage of the ADC to a high value; turning on both the signal access switch and the row selection transistor to read the stored signal voltage from the signal capacitor to the bit line; and if it is determined that the signal voltage read on the bit line is lower than a threshold voltage, then setting the gain factor of the ADC to a high value. The output of the cap unit is set to a high voltage; if the output of the cap unit is a high voltage, the gain factor of the gain stage of the analog-to-digital converter is set to a low value; an auto-zero (AZ) voltage pulse is generated to turn the analog-to-digital converter comparator on and off, thereby resetting the analog-to-digital converter; the signal voltage is received from the bit line to couple to the input of the gain stage of the analog-to-digital converter; the signal voltage at the input of the gain stage is converted into a digital signal value by the analog-to-digital converter; the signal access switch is turned off; the reset access switch is turned on to read the stored reset voltage from the reset capacitor to the bit line; and the reset voltage at the input of the gain stage is converted into a digital reset value by the analog-to-digital converter.

[0009] According to the present disclosure, a gain-adaptive readout circuit for a voltage-domain global shutter (VDGS) imaging system includes: a pixel array comprising a plurality of pixel cells arranged in multiple rows and columns, wherein each of the plurality of pixel cells is coupled to generate an image charge in response to incident light and convert the image charge into an image voltage; a gain-adaptive readout circuit coupled to the pixel array, wherein the gain-adaptive readout circuit includes: a pixel-level connection coupled to one of the plurality of pixel cells; a reset transistor coupled between a power supply voltage and the pixel-level connection; a source follower transistor having a gate coupled to the pixel-level connection; a row select transistor coupled between the source follower transistor and a bit line; a reset switch transistor coupled to the pixel-level connection; and a reset storage capacitor coupled to the pixel array. A reset switch transistor is connected to ground to receive the reset voltage of the pixel cell; a signal switch transistor is coupled to the pixel level connection; a signal storage capacitor is coupled between the signal switch transistor and ground to receive the signal voltage of the pixel cell; a G-cap unit is coupled to the bit line; a gain stage includes a first input coupled to the bit line, a second input coupled to the output of the G-cap unit, a third input coupled to a ramp voltage, a first output coupled to the positive input terminal of the analog-to-digital converter comparator, and a second output coupled to the negative input terminal of the analog-to-digital converter comparator, wherein the gain stage includes more than one gain factor under the control of the second input and a high gain factor is used as its initial default factor; and an analog-to-digital converter counter is coupled between the output of the analog-to-digital converter comparator and the digital output of the analog-to-digital converter. Attached Figure Description

[0010] Non-limiting and non-exhaustive embodiments of the invention are illustrated with reference to the following figures, wherein, unless otherwise specified, the same reference numerals refer to the same parts in all the various views.

[0011] Figure 1 An example of an imaging system according to the teachings of the present invention is shown.

[0012] Figure 2 The diagram shows an example of a pixel cell in an image sensor, an example sampling and holding (SH) circuit, and an ADC with gain adaptive circuitry, according to the present invention.

[0013] Figure 3A This is a schematic diagram showing a first embodiment of an exemplary ADC readout circuit with adaptive gain according to the teachings of this disclosure.

[0014] Figure 3B This is a schematic diagram showing a second embodiment of an exemplary ADC readout circuit with adaptive gain according to the teachings of this disclosure.

[0015] Figure 3C This is a schematic diagram showing a third embodiment of an exemplary ADC readout circuit with adaptive gain according to the teachings of this disclosure.

[0016] Figure 4 An exemplary timing diagram is shown of the signal found in an exemplary SH and ADC readout combination circuit with adaptive gain during image data readout, according to the teachings of this disclosure.

[0017] Figure 5 This is based on the teaching demonstration in this public document. Figure 2 The example SH and ADC readout combination circuit with adaptive gain shown illustrates how it works with... Figure 4 The flowchart shown is a sequence diagram of the coordination operation.

[0018] In all the views of the accompanying drawings, corresponding reference characters denote corresponding components. Those skilled in the art will understand that the elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to aid in understanding the various embodiments of the invention. Furthermore, common but well-known elements that are usable or necessary in commercially feasible embodiments are often not shown so as not to obstruct the views of these various embodiments of the invention. Detailed Implementation

[0019] This document describes examples of sample and hold (S&H) circuitry and analog-to-digital conversion (ADC) circuitry used in image sensors. Numerous specific details are set forth in the following description to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without using one or more of these specific details or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0020] Throughout this specification, the terms "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment of the invention. Therefore, the phrases "in an example" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same example. Furthermore, in one or more examples, the particular feature, structure, or characteristic can be combined in any suitable manner.

[0021] Several technical terms are used throughout this specification. Unless specifically defined herein or clearly indicated in the context of their use, these terms shall have their usual meaning in the art. It should be noted that component names and symbols are used interchangeably throughout this document (e.g., Si and silicon); however, they have the same meaning.

[0022] Figure 1 An example of an imaging system 100 according to an embodiment of the present disclosure is shown. For example... Figure 1 As shown in the example, the imaging system 100 is implemented as a CMOS image sensor (CIS) using a stacked chip scheme, the CMOS image sensor including pixel dies 114 stacked with logic dies or application-specific integrated circuit (ASIC) dies 116. In this example, pixel die 114 includes a pixel array 102, and ASIC die 116 includes an array of sample-and-hold circuitry 118 coupled to pixel array 102 via pixel-level connections 106. ASIC die 116 also includes a control circuitry system 110, a readout circuitry 108, and functional circuitry 112. In one example, pixel array 102 is a two-dimensional (2D) array of photodiodes or image sensor pixel cells 104 (e.g., pixels P11, P12, P21, ...). As shown in the figure, photodiodes are arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of people, places, objects, etc., which can then be used to present two-dimensional images of people, places, objects, etc. However, photodiodes do not necessarily have to be arranged in rows and columns, and other configurations can also be used.

[0023] In one example, readout circuitry 108 may be coupled to read image data from a plurality of photodiodes 104 in pixel array 102 via sample-and-hold (S&H) circuitry 118. As will be described in more detail below, in one example, sample-and-hold circuitry 118 includes a plurality of sample-and-hold circuits coupled at the pixel level to pixel cell 104 to sample and hold reset values ​​and signal values ​​from pixel array 102 via pixel-level connection 106. Image data read out by readout circuitry 108 may then be transferred to functional circuitry 112. In various examples, readout circuitry 108 may also include amplification circuitry, analog-to-digital converter (ADC) circuitry coupled to bit line 140 of sample-and-hold circuitry 118, and ramp generator 130 working with the ADC.

[0024] In one instance, functional circuitry 112 may store only image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others). In one instance, readout circuitry 108 may read out one line of image data at a time along the readout column lines (shown), or may use various other techniques (not shown) to read out the image data (e.g., simultaneous serial readout or fully parallel readout of all pixels 104).

[0025] In one example, control circuitry 110 is coupled to pixel array 102 to control the operation of the plurality of photodiodes in pixel array 102. As will be described in more detail below, control circuitry 110 internally includes a switch driver (not shown) coupled to generate a control signal to control sample-and-hold circuitry 118 to sample and hold reset values ​​and signal voltage values ​​from the voltage domain (VD) of pixel array 102. In the illustrated example, control circuitry 110 is also coupled to generate a global shutter signal for substantially simultaneous control of image acquisition from all pixel values ​​of the pixel array; this may also be referred to as voltage domain global shutter (VDGS). In one example, the shutter signal is a global shutter signal that simultaneously enables all pixel cells 104 within pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In one example, image acquisition is synchronized with lighting effects such as flash.

[0026] The pixel array 102, pixel layer connection 106 and sampling and holding circuit 118 form a global shutter pixel array 128.

[0027] In one example, imaging system 100 may be included in a digital camera, mobile phone, laptop computer, or similar device. Additionally, imaging system 100 may be coupled to other hardware such as a processor (general purpose or otherwise), memory elements, outputs (universal serial bus (USB) port, wireless transmitter, high definition multimedia interface (HDMI) port, etc.), illumination / flash, electrical inputs (keyboard, touchscreen, touchpad, mouse, microphone, etc.), and / or a display. This other hardware may send instructions to imaging system 100, retrieve image data from imaging system 100, or manipulate image data supplied by imaging system 100.

[0028] Figure 2A schematic diagram showing an example of a pixel readout circuit 200 in an image sensor according to the present invention, the pixel readout circuit 200 including an example of a sample and hold (S&H) circuit 218. It should be noted that... Figure 2 The pixel readout circuit 200 and its included sampling and holding circuit 218 shown can be Figure 1 Examples of one of the pixel cell 104 and one of the circuits of the sample and hold circuit 118 described herein, and similarly named and numbered elements referred to below are coupled to and function similarly to those described above. As shown in the example illustrated, pixel cell 204 includes a photodiode (PD) coupled to generate image charge in response to incident light. A transfer (TX) transistor is coupled to transfer the generated image charge from the PD to the floating diffusion (FD) in response to a transfer signal TX. A reset (RST) transistor is coupled to the pixel voltage source PIXVD to reset the FD in response to a reset signal to the reset transistor. The gate of a source follower (SF) transistor is coupled to convert the charge in the FD into an image data signal in response to a select (SEL) transistor, which is coupled to be output via the select transistor through pixel-level connection 206 (e.g., hybrid bond (HB)).

[0029] In an imaging system utilizing CDS, in response to a reset signal to the reset transistor, the charge on the FD is read out via pixel-level connection 206 after a floating diffusion reset operation to obtain a reset level, and the charge on the FD is read out via pixel-level connection 206 after the image charge is transferred to the FD to obtain a signal level.

[0030] Continuing with the example shown, the sample-and-hold circuit 218 includes a reset switch transistor 222 coupled to the pixel line connection 206 to sample and hold the reset voltage Vrst from the pixel cell 204 in a reset storage capacitor Cr 224 in response to the reset switch signal SWr. Additionally, the sample-and-hold circuit 218 includes a signal switch transistor 232 coupled to the pixel layer connection 206 to sample and hold the signal voltage Vsig from the pixel cell 204 in response to the signal switch signal SWs in a signal storage capacitor Cs 234.

[0031] The reset switch signal SWr and the signal switch signal SWs are generated and controlled by the switch driver (not shown) of the control circuit 110.

[0032] A second reset (RST2) transistor 226 is coupled between the power supply voltage SVD and the pixel line connection 206. The RST2 transistor 226 responds to a second reset signal rst2. In the illustrated example, a second source follower (SF2) transistor 236 with a gate is coupled to the pixel line connection 206. A second row select (RS2) transistor 238 is coupled between the SF2 transistor 236 and the bitline (BL) 240. The second row select transistor 238 responds to a second row control signal rs2. In the illustrated example, a voltage bias (VB) transistor 227 biased by a bias voltage VB is coupled between the pixel line connection 206 and ground. The VB transistor 227 serves as a sample and hold (S&H) current source. The sample and hold current source provides a typical current of tens of nA to the SF transistor and the pixel line connection 206.

[0033] BL 240 serves as the output of the global shutter pixel 228. A current source 239 is coupled between bit line 240 and ground to supply current to the SF2 transistor. BL 240 delivers the bit line voltage V_BL to the negative (inverting) input terminal "-" of the G-hat comparator (Cmp) 241 of the G-hat unit 242. A threshold voltage V_TH 244 is coupled to the positive (non-inverting) input terminal "+" of the G-hat comparator 241. If the value of V_BL is greater than V_TH (darker pixels have higher V_BL values), the G-hat comparator 241 provides a low voltage at its output 245, and if the value of V_BL is less than V_TH (brighter pixels have lower V_BL values), the G-hat comparator 241 provides a high voltage at its output 245. The G-hat latch 243 latches the output value of the G-hat comparator 241 as needed via a G-hat latch enable signal from control circuitry 110 (not shown). G-cap latch 243 provides output 246 of G-cap unit 242. The signal lg_en at output 246 of G-cap unit 242 is used as a control signal to enable low gain for analog-to-digital converter (ADC) 260. ADC 260 includes gain stage 250, ADC comparator 280, and ADC counter 290.

[0034] The gain stage 250 of the coupled ADC 260 receives the bit line voltage V_BL from BL 240 as its input signal, the signal lg_en from the output 246 of the G-cap unit 242 as its low-gain enable signal, the ramp voltage signal Vramp 232 generated by the ramp generator 130 (not shown), and the output Vin 284, which serves as the input signal to the positive (non-inverting) terminal "+" of the ADC comparator 280. The coupled ADC comparator 280 receives the ADC auto-zero (AZ) signal 282 from the control circuit 110 (not shown) to initiate the operation of the ADC 260 (pre-setting the ADC 260 to be ready for conversion). Figure 2 As shown, the ADC 260 has an output digital value DOUT 292 coupled to the functional circuit 112 (not shown).

[0035] Figure 3A , Figure 3B and Figure 3C and Figure 2 They share some common parts. Figures 3A to 3C In this configuration, the output of the global shutter pixel 328 is a bit line (BL) 340. A current source 339 is coupled between BL 340 and ground. BL 340 delivers the bit line voltage V_BL to the negative (inverting) terminal "-" of the G-cap comparator 341 in the G-cap unit 342. A threshold voltage V_TH 344 is coupled to the positive terminal "+" of the G-cap comparator 341. If the value of V_BL is greater than V_TH, the G-cap comparator 341 provides a low voltage at its output (darker pixels have higher V_BL values), and if the value of V_BL is less than V_TH, the G-cap comparator 341 provides a high voltage at its output. The G-cap latch 343 latches the output value of the G-cap comparator 341 immediately after the Vsig comparison of V_BL and V_TH. The signal lg_en at the output 346 of the G-cap unit 342 is used as the input signal for the analog-to-digital converter (ADC) 360. The ADC 360 includes a gain stage 350, an ADC comparator (Cmp) 380, and a counter 390. The ADC comparator 380 and counter 390 are integrated throughout the entire... Figures 3A to 3C The middle remains unchanged.

[0036] Figure 3AThis is a first schematic example of a readout ADC circuit including a G-cap unit 342 and an ADC gain stage 350, as taught in this disclosure. The gain stage 350 includes a first capacitor C1 362, a second capacitor C2 364, and a bypass wire 365. The bypass wire 365 provides a connection between the negative terminal "-" of the ADC comparator 380 and ground. C1 362 is coupled between the bit line 340 (carrying the voltage value V_BL) and the positive terminal "+" of the ADC comparator 380. C2 364 is coupled between a ramp signal Vramp 332 generated by a ramp generator 130 (not shown) and the positive terminal "+" of the ADC comparator 380. C1 362 is a capacitor with a fixed capacitance. The capacitance value of C2 364 is adjustable and controlled by the signal lg_en at the output 346 of the G-cap unit 342. The capacitors C1 362 and C2 364 form the first gain factor GF1 of the gain stage 350. For Figure 3A The circuit shown in which the negative terminal "-" of the ADC comparator 380 is coupled to ground via a bypass wire 365 is determined to serve the ADC comparator 380 such that GF1 is approximately proportional to C1 / (C1+C2).

[0037] It can be seen that when the signal value of V_BL is relatively large (for darker pixels) (where V_BL > V_TH), a higher gain factor is preferred as the default value for the first gain factor GF1 = high. In principle, a higher gain factor is preferred for maintaining a higher signal-to-noise ratio (SNR) when darker pixels are associated with weaker signals. As the value of C2 364 increases, GF1 decreases from high to low, as approximately determined by the relationship C1 / (C1+C2). Here, since V_BL < V_TH, the increment of the value of C2 364 can be controlled by the signal lg_en = high at the output 346 of the G-cap unit 342. The decrease in GF1 from high to low ensures that the upper limit of the analog signal Vin 384 fed to the ADC comparator 380 does not saturate for any pixel signal generated under brighter light; instead, it reduces the input amplitude to the ADC 360 to ensure that the ADC 360 operates within its preferred input range.

[0038] Figure 3BThis is a second schematic example of a readout ADC circuit including a G-cap unit 342 and an ADC gain stage 350, as taught in this disclosure. The gain stage 350 includes a first capacitor C1 362 and a second capacitor C3 366. C1 362 is coupled between bit line 340 (at the value of V_BL) and the positive terminal "+" of ADC comparator 380. C3 366 is coupled between a ramp signal Vramp 332 generated by ramp generator 130 (not shown) and the negative terminal "-" of ADC comparator 380. C1 362 is a capacitor with a fixed capacitance. The capacitance value of C3 366 is adjustable and controlled by the signal lg_en at the output 346 of G-cap unit 342. The capacitance of C1 362 and the capacitance of C3 366 form the second gain factor GF2 of the gain stage 350. Figure 3B The circuit shown in which the negative terminal "-" of the ADC comparator 380 is coupled to the ramp signal Vramp 332 via C3 366 is determined to be such that the GF2 approximation of the ADC comparator 380 is proportional to C1 / C3.

[0039] It can be seen that when the signal value of V_BL is relatively large (for darker pixels) (where V_BL > V_TH), a higher gain factor is preferred as the default value for the second gain factor GF2 = high. In principle, a higher gain is preferred for maintaining a higher signal-to-noise ratio (SNR) when darker pixels are associated with weaker pixel signals. As the value of C3 366 increases, the gain factor GF2 decreases from high to low, as determined by the approximate C1 / C3 relationship. Here, since V_BL < V_TH, the increment of the value of C3 366 can be controlled by the signal lg_en = high at the output 346 of the G-cap unit 342. The decrease of GF2 from high to low is used to ensure that the upper limit of the analog signal Vin 384 fed into the ADC comparator 380 is not saturated for pixel signals generated under brighter light; instead, the input amplitude to the ADC 360 is reduced to ensure that the ADC 360 operates within its preferred input range.

[0040] Figure 3CThis is a third illustrative example of a readout ADC circuit including a G-cap unit 342 and an ADC gain stage 350, as taught in this invention. The gain stage 350 includes a first capacitor C1 362, a second capacitor C4 368, an operational amplifier (OpAmp) 370, a third capacitor C5 372, a low-gain enable switch SWen_lg 374, an amplifier reset switch amp_rst 376, and a capacitor Cin 378. C1 362 is coupled between bit line 340 (at the value of V_BL) and the negative terminal "-" of operational amplifier 370. C4 368 is coupled between the negative terminal "-" of operational amplifier 370 and the output terminal of operational amplifier 370. SWen_lg 374 is coupled to the negative terminal "-" of operational amplifier 370 on one terminal and to the first terminal of the third capacitor C5 372 on the other terminal. The second terminal of C5 372 is coupled to the output terminal of operational amplifier 370.

[0041] Cin 378 is coupled between the output terminal of operational amplifier 370 and the positive terminal "+" of ADC comparator 380. The ramp signal Vramp 332 generated by ramp generator 130 (not shown) is coupled to the negative terminal "-" of ADC comparator 380 through bypass wire 365 of gain stage 350.

[0042] C1 362, C4 368, and C5 372 are capacitors with fixed values. Once SWen_lg 374 is turned on, the capacitance value of C5 372 is added between the negative terminal "-" and the output terminal of operational amplifier 370 through the signal lg_en at the output 346 of G-cap unit 342. Figure 3C The capacitors C1 362, C4 368, and C5 372, together with SWen_lg 374, form the third gain factor GF3 of the gain stage 350. When the signal value of V_BL is relatively large (due to darker pixels) (where V_BL > V_TH), SWen_lg 374 remains off, and the third gain factor GF3 is approximately proportional to C1 / C4. When the signal value of V_BL is relatively small (caused by brighter pixels) (where V_BL < V_TH), SWen_lg 374 is turned on, and GF3 is approximately proportional to C1 / (C4+C5), while C1 / (C4+C5) is less than C1 / C4.

[0043] It can be seen that when V_BL > V_TH, a higher GF3 is preferred as the default value for the third gain factor GF3 = high, in proportion to C1 / C4. A higher gain factor is preferred for maintaining a higher signal-to-noise ratio (SNR) for weaker pixel signals. When capacitor C5 372 is added in parallel with capacitor C4 368 by turning on SWen_lg 374, GF3 decreases from C1 / C4 to C1 / (C4+C5) since V_BL < V_TH. The decrease in GF3 from high to low is used to ensure that the upper limit of the analog signal Vin 384 fed to ADC comparator 380 is not saturated for pixel signals generated under brighter light (related to lower signal voltage), and conversely, to reduce the input amplitude to ADC 360 to ensure that ADC 360 operates within its preferred input range.

[0044] Figure 4 Timing diagram 400 illustrates how the disclosed G-cap unit 242 controls the operation of the gain stage 250 to optimize the performance of the ADC 260, according to the teachings of this disclosure. In typical voltage domain global shutter (VDGS) operation, all reset voltages and signal voltages (for correlated double sampling) from the pixel array 102 are first simultaneously sampled and held in an array of storage capacitors, and then subsequently read out sequentially from these storage capacitors to their corresponding bit lines 240.

[0045] For each pixel cell 204, use Figure 2 In the pixel readout circuit 200 shown, the reset voltage Vrst has been sampled from pixel cell 204 and stored in reset capacitor Cr 224 via reset access switch SWr 222, and the signal voltage Vsig has been sampled from pixel cell 204 and stored in signal capacitor Cs 234 via signal access switch SWs 232. According to the teachings of this disclosure, these steps of "sampling and storing the global shutter speed Vrst to Cr and Vsig to Cs" are presented in a combined form as follows: Figure 5 Step 510 in flowchart 500 is used for the readout operation of each global shutter pixel 228. Then, as... Figure 5 As shown in step 520, the Vsig and Vrst readout sequences begin.

[0046] Initially, a pulse is applied to the second reset (RST2) transistor 226 to reset the pixel line voltage V_PIX 208 to the supply voltage SVD. This will cause V_PIX 208 at pixel line connection 206 to enter its operating conditions before time t0. Figure 4At time t0, both SWs 232 and the second row select (RS2) transistor 238 are turned on to route the pre-stored Vsig from Cs 234 to bit line (BL) 240, such that the BL voltage V_BL = Vsig. Figure 5 As shown in step 530. After the rapid stabilization period following t0, the G-cap comparator 241 compares Vsig on BL 240 with a predetermined threshold voltage value V_TH 244, as follows. Figure 5 Step 540 is shown in the diagram.

[0047] At time t1, as the first possibility, if Vsig > V_TH, the signal at output 245 of G-cap comparator 241 is determined to be low. After being latched by G-cap latch 243, output signal lg_en is generated at output 246 of G-cap unit 242 to control gain stage 250 to maintain its default high analog gain (HAG) state, such as... Figure 5 As shown in step 550. Also at t1, as a second possibility, if Vsig < V_TH, then lg_en latched at the output of G-cap unit 342 is determined to be high, which in turn controls gain stage 250 to change its gain state from a preset high analog gain (HAG) to low analog gain (LAG), as... Figure 5 As shown in step 555. By using, as Figure 3A , Figure 3B and Figure 3C One of the disclosed gain stage circuits 350 is used to implement the change to LAG. The gain stage 250 is not limited to having only two gain factors to choose from; it can take the form of multiple gains. For example, if the gain stage 250 has up to eight different gain factors to choose from, its multiplexer selection signal can contain three bits to distinguish each of the eight gain factors required by the gain stage 250.

[0048] Based on the deterministic result of the signal lg_en at output 246 at t1, the auto-zero (AZ) signal 282 emits a pulse to reset the ADC comparator 280 of the ADC 260, preparing the ADC 260 for its operation, such as... Figure 5 Step 560 is shown in the diagram.

[0049] At t2, when the dynamic ramp signal Vramp 232, coupled to the negative (inverting) terminal "-" of the ADC comparator 280, intersects with the voltage signal Vin 284 from the gain stage 250 at the positive (non-inverting) terminal "+" of the comparator 280, the digital value DOUT 292 is latched in the ADC counter 290 as DOUT_sig, representing Vsig. Since at this time, the exact same Vsig used by the G-cap comparator 241, which makes the decision and sets the gain factor of the gain stage 250, is fed into Vin 284 by the gain stage 250 using the gain factor updated by the signal lg_en at output 246, the digital value conversion of Vsig within its optimized ADC range is achieved, as... Figure 5 Step 570 is shown in the diagram.

[0050] At t3, SWs 232 is turned off, and by applying a pulse to the gate of RST2 transistor 226, V_PIX 208 at the pixel line can be reset to SVD. At t4, SWr 222 is turned on to route the pre-stored Vrst from Cr 224 to BL240, making V_BL = Vrst, as... Figure 5 As shown in step 580. At t5, the voltage signal Vin 284 is stabilized, and the new ramp signal Vramp 232 at the negative terminal "-" of the ADC comparator 280 begins to ramp up. At t6, Vramp 232 intersects Vin 284 at the positive terminal "+" of the comparator 280, and the digital value DOUT 292 is latched in the ADC counter 290. This DOUT 292 represents the digital value DOUT_rst converted by the ADC 260 from Vrst, as shown in step 580. Figure 5 Step 590 is shown in the diagram. At this point, the previously obtained DOUT_rst and DOUT_sig are converted to the gain level 250 set at time t1 by the signal lg_en at output 246, with the same gain. Both DOUT_rst and DOUT_sig can be used for further digital signal processing. By subtracting DOUT_rst from DOUT_sig, correlated double sampling (CDS) can be implemented in the digital domain as a digital CDS (DCDS), as commonly practiced for image sensors.

[0051] At t7, the entire readout cycle of each global shutter pixel 228 for a single exposure based on VDGS ends.

[0052] The above description of the examples shown is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the invention have been set forth herein for illustrative purposes, those skilled in the art will recognize that various modifications may be made within the scope of the invention.

[0053] These modifications can be made to the present invention based on the above detailed description. The terminology used in the above claims should not be construed as limiting the invention to the specific instances disclosed in this specification. Rather, the scope of the invention should be determined entirely by the above claims, and this should be understood in accordance with the established principles for the interpretation of the claims.

Claims

1. An adaptive analog-to-digital converter gain controller circuit for use in a voltage-domain global shutter image sensor, comprising: Pixel-level connections are coupled to pixel cells; A reset transistor is coupled between the power supply voltage and the pixel-level connection. A source follower transistor having a gate coupled to the pixel-level connection; A row selection transistor is coupled between the source follower transistor and the bit line; A reset switch transistor is coupled to the pixel-level connection; A reset storage capacitor is coupled between the reset switch transistor and ground to receive the reset voltage of the pixel cell; A signal switching transistor is coupled to the pixel-level connection; A signal storage capacitor is coupled between the signal switching transistor and ground to receive the signal voltage of the pixel cell; G-cap unit, coupled to the bit line; The gain stage includes a first input coupled to the bit line, a second input coupled to the output of the G-cap unit, a third input coupled to the ramp voltage, a first output coupled to the positive input terminal of the analog-to-digital converter comparator, and a second output coupled to the negative input terminal of the analog-to-digital converter comparator, wherein the gain stage includes more than one gain factor under the control of the second input and a high gain factor is used as its initial default factor; as well as An analog-to-digital converter counter is coupled between the output of the analog-to-digital converter comparator and the digital output of the analog-to-digital converter.

2. The adaptive analog-to-digital converter gain controller circuit according to claim 1 further includes: A current source is coupled between the bit line and ground; A ramp generator having an output coupled to the third input of the gain stage to supply the ramp voltage; A G-cap comparator is coupled as the input stage of the G-cap unit, wherein the G-cap comparator has a negative input terminal coupled to the bit line and a positive input terminal coupled to a threshold voltage, and wherein the output of the G-cap comparator is determined to be high if the voltage on the bit line is lower than the threshold voltage. A G-hat latch is coupled as the output stage of the G-hat unit, wherein the output of the G-hat comparator is latched into the G-hat latch under the control of a latch enable signal, and wherein the output of the G-hat latch is the output of the G-hat unit. as well as An automatic zeroing signal is coupled to the analog-to-digital converter comparator to preset the analog-to-digital converter comparator.

3. The adaptive analog-to-digital converter gain controller circuit according to claim 2, wherein the gain stage comprises: A first capacitor is coupled between the first input of the gain stage and the first output of the gain stage, wherein the first capacitor is a capacitor with a fixed capacitance. A second capacitor is coupled between the third input of the gain stage and the first output of the gain stage; as well as Ground, coupled to the second output of the gain stage.

4. The adaptive analog-to-digital converter gain controller circuit of claim 3, wherein the second capacitor changes its capacitance under the control of the second input, and wherein if the output of the G-cap unit is determined to be high, the variable capacitance of the second capacitor is changed in such a way that the gain factor of the gain stage decreases from its initially set high value to a lower value.

5. The adaptive analog-to-digital converter gain controller circuit according to claim 2, wherein the gain stage comprises: A first capacitor is coupled between the first input of the gain stage and the first output of the gain stage, wherein the first capacitor is a capacitor with a fixed capacitance. as well as A second capacitor is coupled between the third input of the gain stage and the second output of the gain stage.

6. The adaptive analog-to-digital converter gain controller circuit of claim 5, wherein the second capacitor changes its capacitance under the control of the second input, and wherein if the output of the G-cap unit is determined to be high, the variable capacitance of the second capacitor is changed in such a way that the gain factor of the gain stage decreases from its initially set high value to a lower value.

7. The adaptive analog-to-digital converter gain controller circuit according to claim 2, wherein the gain stage comprises: A first capacitor is coupled between the first input of the gain stage and the negative input terminal of the operational amplifier, wherein the first capacitor is a capacitor with a fixed capacitance. A second capacitor is coupled between the negative input terminal and the output terminal of the operational amplifier, wherein the second capacitor is a capacitor with a fixed capacitance; A third capacitor is coupled between the negative input terminal of the operational amplifier and the output terminal of the operational amplifier, wherein the third capacitor is a capacitor with a fixed capacitance; A fourth capacitor is coupled between the output terminal of the operational amplifier and the first output of the gain stage; A gain control switch is coupled between the negative input terminal of the operational amplifier and the third capacitor; as well as A gain reset switch, coupled between the negative input terminal and the output terminal of the operational amplifier, is used to reset the gain stage.

8. The adaptive analog-to-digital converter gain controller circuit of claim 7, wherein if the gain control switch is turned on by a high voltage of the second input, the third capacitor is connected in parallel to the second capacitor, and wherein if the output of the G-cap unit is determined to be high, the combined capacitance of the second capacitor and the third capacitor causes the gain factor of the gain stage to decrease from its initially set high value to a lower value.

9. A method for adaptively setting a gain factor to prepare for analog-to-digital converter operation, comprising: First, the reset voltage is sampled from the pixel cell via the reset access switch and stored in the reset capacitor. Then, the signal voltage is sampled from the pixel cell via the signal access switch and stored in the signal capacitor. A voltage pulse is generated to turn the reset transistor on and off, thereby resetting the pixel line voltage to the power supply voltage. The gain factor of the gain stage of the analog-to-digital converter is preset to a high value; Turn on both the signal access switch and the row selection transistor to read the stored signal voltage from the signal capacitor to the bit line; If it is determined that the signal voltage read on the bit line is lower than the threshold voltage, the output of the G-cap unit is set to a high voltage; If the output of the G-cap unit is a high voltage, then the gain factor of the gain stage of the analog-to-digital converter is set to a low value; An automatic zero-adjustment voltage pulse is generated to turn the analog-to-digital converter comparator on and off, thereby resetting the analog-to-digital converter; The signal voltage is received from the bit line to be coupled to the input of the gain stage of the analog-to-digital converter; The analog-to-digital converter converts the signal voltage at the input of the gain stage into a digital signal value. Turn off the signal access switch; Turn on the reset access switch to read the stored reset voltage from the reset capacitor to the bit line; as well as The analog-to-digital converter converts the reset voltage at the input of the gain stage into a digital reset value.

10. The method of adaptively setting a gain factor to prepare for analog-to-digital converter operation according to claim 9, wherein the following are controlled by a control circuit: a reset control signal for controlling the reset transistor, a reset access switch control signal for controlling the reset access switch, a signal access switch control signal for controlling the signal access switch, a row selection control signal for controlling the row selection transistor, and the automatic zeroing voltage pulse.

11. A gain-adaptive readout circuit for a voltage-domain global shutter imaging system, comprising: A pixel array, comprising multiple pixel cells arranged in multiple rows and columns, wherein Each of the plurality of pixel cells is coupled to generate an image charge in response to incident light and to convert the image charge into an image voltage; A gain-adaptive readout circuit is coupled to the pixel array, wherein the gain-adaptive readout circuit includes: Pixel-level connection, coupled to one pixel cell among the plurality of pixel cells; A reset transistor is coupled between the power supply voltage and the pixel-level connection. A source follower transistor having a gate coupled to the pixel-level connection; A row selection transistor is coupled between the source follower transistor and the bit line; A reset switch transistor is coupled to the pixel-level connection; A reset storage capacitor is coupled between the reset switch transistor and ground to receive the reset voltage of the pixel cell; A signal switching transistor is coupled to the pixel-level connection; A signal storage capacitor is coupled between the signal switching transistor and ground to receive the signal voltage of the pixel cell; G-cap unit, coupled to the bit line; A gain stage includes a first input coupled to the bit line, a second input coupled to the output of the G-cap unit, a third input coupled to the ramp voltage, a first output coupled to the positive input terminal of the analog-to-digital converter comparator, and a second output coupled to the negative input terminal of the analog-to-digital converter comparator, wherein the gain stage includes more than one gain factor under the control of the second input, and a high gain factor is used as its initial default factor; and An analog-to-digital converter counter is coupled between the output of the analog-to-digital converter comparator and the digital output of the analog-to-digital converter.

12. The gain adaptive readout circuit for a voltage-domain global shutter imaging system according to claim 11, further comprising: A current source is coupled between the bit line and ground; A ramp generator having an output coupled to the third input of the gain stage to supply the ramp voltage; A G-cap comparator is coupled as the input stage of the G-cap unit, wherein the G-cap comparator has a negative input terminal coupled to the bit line and a positive input terminal coupled to a threshold voltage, and wherein the output of the G-cap comparator is determined to be high if the voltage on the bit line is lower than the threshold voltage. A G-hat latch is coupled as the output stage of the G-hat unit, wherein the output of the G-hat comparator is latched into the G-hat latch under the control of a latch enable signal, and wherein the output of the G-hat latch is the output of the G-hat unit. An automatic zeroing signal is coupled to the analog-to-digital converter comparator to preset the analog-to-digital converter comparator. A control circuit is coupled to control the operation of the pixel array, the gain adaptive readout circuit, the current source, the ramp generator, and the G-cap unit; as well as A functional circuit coupled to the digital output of the analog-to-digital converter to store the digital value of the image charge from the pixel array.

13. The gain adaptive readout circuit for a voltage-domain global shutter imaging system according to claim 12, wherein the gain stage comprises: A first capacitor is coupled between the first input of the gain stage and the first output of the gain stage, wherein the first capacitor is a capacitor with a fixed capacitance. A second capacitor is coupled between the third input of the gain stage and the first output of the gain stage; as well as Ground, coupled to the second output of the gain stage.

14. The gain adaptive readout circuit for a voltage-domain global shutter imaging system according to claim 13, wherein the second capacitor changes its capacitance under the control of the second input, and wherein if the output of the G-cap unit is determined to be high, the variable capacitance of the second capacitor is changed in such a way that the gain factor of the gain stage decreases from its initially set high value to a lower value.

15. The gain adaptive readout circuit for a voltage-domain global shutter imaging system according to claim 12, wherein the gain stage comprises: A first capacitor is coupled between the first input of the gain stage and the first output of the gain stage, wherein the first capacitor is a capacitor with a fixed capacitance. as well as A second capacitor is coupled between the third input of the gain stage and the second output of the gain stage.

16. The gain adaptive readout circuit for a voltage-domain global shutter imaging system according to claim 15, wherein the second capacitor changes its capacitance under the control of the second input, and wherein if the output of the G-cap unit is determined to be high, the variable capacitance of the second capacitor is changed in such a way that the gain factor of the gain stage decreases from its initially set high value to a lower value.

17. The gain adaptive readout circuit for a voltage-domain global shutter imaging system according to claim 12, wherein the gain stage comprises: A first capacitor is coupled between the first input of the gain stage and the negative input terminal of the operational amplifier, wherein the first capacitor is a capacitor with a fixed capacitance. A second capacitor is coupled between the negative input terminal and the output terminal of the operational amplifier, wherein the second capacitor is a capacitor with a fixed capacitance; A third capacitor is coupled between the negative input terminal of the operational amplifier and the output terminal of the operational amplifier, wherein the third capacitor is a capacitor with a fixed capacitance; A fourth capacitor is coupled between the output terminal of the operational amplifier and the first output of the gain stage; A gain control switch is coupled between the negative input terminal of the operational amplifier and the third capacitor; as well as A gain reset switch, coupled between the negative input terminal and the output terminal of the operational amplifier, is used to reset the gain stage.

18. The gain adaptive readout circuit for a voltage-domain global shutter imaging system according to claim 17, wherein if the gain control switch is turned on by a high voltage of the second input, the third capacitor is connected in parallel to the second capacitor, and wherein if the output of the G-cap unit is determined to be high, the combined capacitance of the second capacitor and the third capacitor causes the gain factor of the gain stage to decrease from its initially set high value to a lower value.

19. The gain adaptive readout circuit for a voltage domain global shutter imaging system according to claim 12, wherein the threshold voltage, the latch enable signal, and the auto-zero signal are under the control of the control circuit.

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