Semiconductor structure and method of forming the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SMIC ORIENTAL INTEGRATED CIRCUIT MANUFACTURING CO LTD
- Filing Date
- 2024-12-19
- Publication Date
- 2026-06-26
Smart Images
Figure CN122279736A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] Bipolar-CMOS-DMOS (BCD) technology is a monolithic integration process that can fabricate bipolar transistors (Bipolar), complementary metal-oxide-semiconductor (CMOS), and dual-diffused metal-oxide-semiconductor (DMOS) devices on the same chip. Therefore, the chip can simultaneously process power signals, analog signals, and digital signals.
[0003] In the BCD process, controlling the spreading resistance profile (SRP) curve and the spreading resistance value is particularly important, as these directly affect the device performance.
[0004] However, the diffusion resistivity distribution curve is currently difficult to control and the diffusion resistance value is too low. How to make the diffusion resistivity distribution curve closer to the substrate and improve the diffusion resistance value has become an urgent problem to be solved. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which can bring the diffusion resistivity distribution curve closer to the substrate region and improve the diffusion resistance value.
[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a pre-buried layer is formed in the substrate, the pre-buried layer having doped ions; forming a diffusion barrier layer on the substrate, the step of forming the diffusion barrier layer comprising: forming a first diffusion barrier layer on the substrate at a first preset temperature; forming a second diffusion barrier layer on the first diffusion barrier layer at a second preset temperature, the second diffusion barrier layer and the first diffusion barrier layer constituting a diffusion barrier layer; wherein the first preset temperature is lower than the second preset temperature.
[0007] Optionally, the step of forming a first diffusion barrier layer on the substrate includes: performing a first oxidation treatment on the substrate at the first preset temperature to form a first diffusion barrier layer.
[0008] Optionally, the process for performing the first oxidation treatment on the substrate includes a dry oxidation process.
[0009] Optionally, the step of forming the second diffusion barrier layer on the first diffusion barrier layer includes: performing a second oxidation treatment on the substrate at a second preset temperature to form the second diffusion barrier layer.
[0010] Optionally, the process for performing the second oxidation treatment on the substrate includes a wet oxidation process.
[0011] Optionally, a first diffusion barrier layer and a second diffusion barrier layer are formed sequentially on the substrate within the same reaction chamber.
[0012] Optionally, in the same deposition process, after forming the first diffusion barrier layer on the substrate, the reaction chamber is subjected to a second heating treatment to raise the temperature of the reaction chamber from the first preset temperature to the second preset temperature.
[0013] Optionally, before forming the first diffusion barrier layer on the substrate, the method further includes: in a reaction chamber containing the substrate and used to form the diffusion barrier layer, performing a first heating process on the reaction chamber to raise the temperature of the reaction chamber to a first preset temperature.
[0014] Optionally, after the reaction chamber undergoes the first heating treatment and before the first diffusion barrier layer is formed on the substrate, the method further includes: stabilizing the process gas flow rate and process temperature for forming the first diffusion barrier layer at the first preset temperature.
[0015] Optionally, after the reaction chamber undergoes the second heating treatment, and before the second diffusion barrier layer is formed on the first diffusion barrier layer, the method further includes: stabilizing the process gas flow rate and process temperature for forming the second diffusion barrier layer at the second preset temperature.
[0016] Optionally, the second preset temperature ranges from 950 degrees Celsius to 1100 degrees Celsius.
[0017] Optionally, the difference between the second preset temperature and the first preset temperature is 10% to 20% of the second preset temperature.
[0018] Optionally, the process gas flow rate for forming the first diffusion barrier layer on the substrate is 1 to 3 times the process gas flow rate for forming the second diffusion barrier layer on the first diffusion barrier layer.
[0019] Optionally, in the step of forming the embedded layer in the substrate, the doping ions include: a first doping ion and a second doping ion, wherein the first doping ion and the second doping ion belong to the same group of elements, and the concentration of the first doping ion is higher than the concentration of the second doping ion.
[0020] This invention also provides a semiconductor structure, comprising: a substrate having a pre-buried layer therein, the pre-buried layer having doped ions; and a diffusion barrier layer located on the substrate, the diffusion barrier layer comprising: a first diffusion barrier layer covering the substrate; and a second diffusion barrier layer covering the first diffusion barrier layer, the second diffusion barrier layer and the first diffusion barrier layer constituting a diffusion barrier layer; wherein the first diffusion barrier layer is formed at a first preset temperature, the second diffusion barrier layer is formed at a second preset temperature, and the first preset temperature is lower than the second preset temperature.
[0021] Optionally, the thickness of the first diffusion barrier layer is 1 / 10 to 1 / 5 of the thickness of the diffusion barrier layer.
[0022] Optionally, the material of the first diffusion barrier layer includes silicon oxide.
[0023] Optionally, the material of the second diffusion barrier layer includes silicon oxide.
[0024] Optionally, the density of the first diffusion barrier layer is higher than that of the second diffusion barrier layer.
[0025] Optionally, the doped ions in the pre-embedded layer include a first doped ion and a second doped ion, wherein the first doped ion and the second doped ion belong to the same group of elements, and the concentration of the first doped ion is higher than the concentration of the second doped ion.
[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0027] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a pre-buried layer is formed in the substrate, the pre-buried layer having doped ions; forming a diffusion barrier layer on the substrate, the step of forming the diffusion barrier layer comprising: forming a first diffusion barrier layer on the substrate at a first preset temperature; forming a second diffusion barrier layer on the first diffusion barrier layer at a second preset temperature, the second diffusion barrier layer and the first diffusion barrier layer constituting a diffusion barrier layer; wherein the first preset temperature is lower than the second preset temperature. In this embodiment, because the first preset temperature is lower than the second preset temperature, the rate of forming the first diffusion barrier layer is lower, which in turn increases the time required to form the first diffusion barrier layer. This allows the dopant ions in the embedded layer more time to diffuse and distribute in the substrate, resulting in a more uniform concentration distribution of the dopant ions in the embedded layer in the substrate. Consequently, the concentration gradient of the dopant ions in the substrate is reduced, thereby reducing the probability of the dopant ions in the embedded layer diffusing to the substrate surface. In the subsequent epitaxial growth process, this increases the probability of neutralization between the dopant ions in the epitaxial layer and the dopant ions in the embedded layer, resulting in the diffusion resistivity distribution curve being closer to the substrate and increasing the diffusion resistance value. Furthermore, because the first preset temperature is lower, the diffusion rate of the dopant ions in the embedded layer is reduced during the formation of the first diffusion barrier layer, thereby reducing the probability of the dopant ions in the embedded layer diffusing to the chamber and thus reducing the probability of the chamber being contaminated.
[0028] This invention also provides a semiconductor structure, comprising: a substrate having a pre-buried layer therein, the pre-buried layer having doped ions; and a diffusion barrier layer located on the substrate, the diffusion barrier layer comprising: a first diffusion barrier layer covering the substrate; and a second diffusion barrier layer covering the first diffusion barrier layer; wherein the first diffusion barrier layer is formed at a first preset temperature, and the second diffusion barrier layer is formed at a second preset temperature, the first preset temperature being lower than the second preset temperature. In this embodiment, because the first preset temperature is lower than the second preset temperature, the rate of forming the first diffusion barrier layer is lower, which in turn increases the time required to form the first diffusion barrier layer. This allows the dopant ions in the embedded layer more time to diffuse and distribute in the substrate, resulting in a more uniform concentration distribution of the dopant ions in the embedded layer in the substrate. Consequently, the concentration gradient of the dopant ions in the substrate is reduced, thereby reducing the probability of the dopant ions in the embedded layer diffusing to the substrate surface. In the subsequent epitaxial growth process, this increases the probability of neutralization between the dopant ions in the epitaxial layer and the dopant ions in the embedded layer, resulting in the diffusion resistivity distribution curve being closer to the substrate and increasing the diffusion resistance value. Furthermore, because the first preset temperature is lower, the diffusion rate of the dopant ions in the embedded layer is reduced during the formation of the first diffusion barrier layer, thereby reducing the probability of the dopant ions in the embedded layer diffusing to the chamber and thus reducing the probability of the chamber being contaminated. Attached Figure Description
[0029] Figure 1 This is a schematic diagram of a semiconductor structure.
[0030] Figure 2 yes Figure 1 The diffusion resistivity distribution curve of the semiconductor structure is shown.
[0031] Figures 3 to 5 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;
[0032] Figure 6 This is a temperature curve diagram of each step in the furnace tube process in a method for forming a furnace tube according to an embodiment of the present invention;
[0033] Figure 7 This is a comparison diagram of the diffusion resistivity distribution curve of the semiconductor structure formed by the formation method of this invention and the diffusion resistivity distribution curve of the semiconductor structure formed by the prior art.
[0034] Figure 8 This is a schematic diagram of the semiconductor structure of the present invention. Detailed Implementation
[0035] Currently, diffusion resistivity distribution curves are difficult to approach the substrate region and diffusion resistance values are low. This paper analyzes the reasons why diffusion resistivity distribution curves are difficult to approach the substrate region and why diffusion resistance values are low, using a semiconductor structure formation method as an example.
[0036] Figure 1 This is a schematic diagram of a semiconductor structure. Figure 2 yes Figure 1 The diagram shows the diffusion resistivity distribution curve of the semiconductor structure.
[0037] refer to Figure 1 The semiconductor structure includes: a substrate 10 having a pre-buried layer 11 therein, and the pre-buried layer 11 having doped ions, wherein the doped ions include a first doped ion and a second doped ion, the first doped ion and the second doped ion belong to the same group of elements, and the concentration of the first doped ion is higher than the concentration of the second doped ion; and a diffusion barrier layer 12 located on the top surface (not shown) and the bottom surface (not shown) of the substrate 10.
[0038] It should be noted that the first dopant ion and the second dopant ion belong to the same group of elements. For example, if the first dopant ion is a group VA element, the second dopant ion is also a group VA element; if the first dopant ion is a group IIIA element, the second dopant ion is also a group IIIA element.
[0039] It should also be noted that in subsequent process steps, the diffusion barrier layer 12 will be removed, and then an epitaxial layer (not shown) will be formed on the substrate 10.
[0040] An epitaxial layer is grown on substrate 10 to form a substrate with a resistivity that meets process requirements, thereby controlling the resistivity required for the semiconductor structure device.
[0041] Reference Figure 2 , Figure 2 yes Figure 1 The diagram shows the diffusion resistivity distribution curve of the semiconductor structure. The horizontal axis represents the depth from the top surface of the epitaxial layer to the substrate 10, with the origin indicating the position of the top surface of the epitaxial layer. The vertical axis represents the corresponding diffusion resistivity. Because the concentration of the first doped ion in the buried layer 11 is higher than that of the second doped ion, a large number of second doped ions easily escape from the substrate 10 during the growth of the diffusion barrier layer 12, resulting in a decrease in the concentration of the second doped ion in the substrate 10. Subsequently, the diffusion barrier layer 12 on the substrate 10 is removed, and epitaxial growth is performed on the substrate 10 to form an epitaxial layer. This decrease in the concentration of the second doped ion in the substrate 10 reduces the probability of neutralization between the doped ions in the epitaxial layer and the doped ions in the buried layer 11 during the epitaxial growth process. Consequently, the diffusion resistivity distribution curve moves away from the substrate 10, and the diffusion resistance value is lower.
[0042] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a pre-buried layer is formed in the substrate, the pre-buried layer having doped ions; forming a diffusion barrier layer on the substrate, the step of forming the diffusion barrier layer comprising: forming a first diffusion barrier layer on the substrate at a first preset temperature; forming a second diffusion barrier layer on the first diffusion barrier layer at a second preset temperature, the second diffusion barrier layer and the first diffusion barrier layer constituting a diffusion barrier layer; wherein the first preset temperature is lower than the second preset temperature.
[0043] In the scheme disclosed in this embodiment of the invention, since the first preset temperature is lower than the second preset temperature, the rate of forming the first diffusion barrier layer is lower, which in turn increases the time required to form the first diffusion barrier layer. This allows the dopant ions in the embedded layer more time to diffuse and distribute in the substrate, resulting in a more uniform concentration distribution of the dopant ions in the embedded layer in the substrate. Consequently, the concentration gradient of the dopant ions in the substrate is reduced, thereby reducing the probability of the dopant ions in the embedded layer diffusing to the substrate surface. In the subsequent epitaxial growth process, this increases the probability of neutralization between the dopant ions in the epitaxial layer and the dopant ions in the embedded layer, resulting in the diffusion resistivity distribution curve being closer to the substrate and increasing the diffusion resistance value. Furthermore, since the first preset temperature is lower, the diffusion rate of the dopant ions in the embedded layer is reduced during the formation of the first diffusion barrier layer, thereby reducing the probability of the dopant ions in the embedded layer diffusing to the chamber and thus reducing the probability of the chamber being contaminated.
[0044] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0045] Figures 3 to 5 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Figure 6 This is a temperature curve diagram of each step in the furnace tube process of a method for forming a furnace tube according to an embodiment of the present invention. Figure 7 This is a comparison diagram of the diffusion resistivity distribution curve of a semiconductor structure formed by the formation method of this invention and the diffusion resistivity distribution curve of a semiconductor structure formed by the prior art.
[0046] refer to Figure 3 A substrate 100 is provided, wherein a pre-embedded layer 101 is formed in the substrate 100, and the pre-embedded layer 101 has doped ions.
[0047] Substrate 100 is used to provide a process platform for the formation of semiconductor structures.
[0048] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.
[0049] As an example, if the substrate 100 is a P-type substrate (P-Sub), then the ions doped into the substrate 100 are P-type dopant ions. Specifically, the P-type dopant ions (i.e. the doped ions) are group IIIA elements, such as boron (B).
[0050] The embedded layer 101 is located in the substrate 100 and is used to provide a substrate 100 that meets the device performance requirements for the semiconductor structure, thereby realizing basic device functions.
[0051] In this embodiment, the doped ions in the embedded layer 101 have the opposite conductivity type to the ions doped in the substrate 100. That is, when the ions doped in the substrate 100 are P-type, the ions doped in the embedded layer 101 are N-type, and when the ions doped in the substrate 100 are N-type, the ions doped in the embedded layer 101 are P-type.
[0052] Therefore, in this embodiment, the doped ions in the pre-embedded layer 101 are N-type doped ions.
[0053] In this embodiment, in the step of forming the pre-buried layer 101 in the substrate 100, the doping ions include: a first doping ion and a second doping ion, wherein the first doping ion and the second doping ion belong to the same group of elements, and the concentration of the first doping ion is higher than the concentration of the second doping ion.
[0054] It should be noted that the first dopant ion and the second dopant ion belong to the same group of elements. For example, if the first dopant ion is a group VA element, the second dopant ion is also a group VA element; if the first dopant ion is a group IIIA element, the second dopant ion is also a group IIIA element.
[0055] In this embodiment, the doping ions in the pre-embedded layer 101 can be group VA elements.
[0056] It should be noted that the first doped ion and the second doped ion in the pre-embedded layer 101 belong to the same group of elements, and the concentration of the first doped ion is higher than that of the second doped ion (i.e., the first doped ion belongs to the heavily doped ion and the second doped ion belongs to the lightly doped ion), which is beneficial to promoting the redistribution of the concentration of the first doped ion and the second doped ion in the substrate.
[0057] As an example, the first dopant ion includes sb (Sb) and the second dopant ion includes phosphorus (P).
[0058] In this embodiment, an ion implantation process is used to form a pre-buried layer 101 in the substrate 100.
[0059] Specifically, ion implantation offers advantages such as high resolution, precise control, suitability for customized modification, and the elimination of physical contact. It can be used to achieve highly controllable ion implantation, facilitating the precise formation of a buried layer 101 in the substrate 100.
[0060] Reference Figures 4 to 5 A diffusion barrier layer 102 is formed on the substrate 100. The step of forming the diffusion barrier layer 102 includes: referencing... Figure 4 At a first preset temperature, a first diffusion barrier layer 103 is formed on the substrate 100; Reference Figure 5 At a second preset temperature, a second diffusion barrier layer 104 is formed on the first diffusion barrier layer 103, and the second diffusion barrier layer 104 and the first diffusion barrier layer 103 constitute a diffusion barrier layer 102; wherein, the first preset temperature is lower than the second preset temperature.
[0061] The diffusion barrier layer 102 is used to prevent elements in the embedded layer 101 from escaping from the surface of the substrate 100.
[0062] It should be noted that, since the first preset temperature is lower than the second preset temperature, the rate of forming the first diffusion barrier layer 103 is lower, which correspondingly increases the time required to form the first diffusion barrier layer 103. This allows the dopant ions in the embedded layer 101 more time to diffuse and distribute in the substrate 100, resulting in a more uniform concentration distribution of the dopant ions in the embedded layer 101 in the substrate 100. Consequently, the concentration gradient of the dopant ions in the substrate 100 is reduced, thereby reducing the probability of the dopant ions in the embedded layer 101 diffusing to the surface of the substrate 100. In the subsequent epitaxial growth process, this increases the probability of neutralization between the dopant ions in the epitaxial layer and the dopant ions in the embedded layer 101, resulting in the diffusion resistivity distribution curve being closer to the substrate 100 and increasing the diffusion resistance value. Furthermore, since the first preset temperature is lower, the diffusion rate of the dopant ions in the embedded layer 101 is reduced during the formation of the first diffusion barrier layer 103, thereby reducing the probability of the dopant ions in the embedded layer 101 diffusing into the chamber and thus reducing the probability of the chamber being contaminated.
[0063] In this embodiment, the density of the first diffusion barrier layer 103 is higher than that of the second diffusion barrier layer 104.
[0064] The first diffusion barrier layer 103, which is closer to the substrate 100, has a higher density, which helps to reduce the probability of dopants in the buried layer 101 escaping from the substrate 100. In the subsequent epitaxial growth process, it increases the probability of dopants in the epitaxial layer neutralizing with dopants in the buried layer 101, thereby enabling the diffusion resistivity distribution curve to be closer to the substrate 100 and increasing the diffusion resistance value.
[0065] In this embodiment, the material of the first diffusion barrier layer 103 includes silicon oxide, and the material of the second diffusion barrier layer 104 includes silicon oxide.
[0066] It should be noted that silicon oxide has a good diffusion barrier effect, which can effectively prevent doped ions in the embedded layer 101 from escaping from the surface of the substrate 100. At the same time, silicon oxide is easy to grow on the substrate 100, which improves production efficiency and reduces production costs.
[0067] The following detailed description, with reference to the accompanying drawings, illustrates the formation of a diffusion barrier layer 102 on the substrate 100.
[0068] refer to Figure 4 The step of forming a first diffusion barrier layer 103 on the substrate 100 includes: performing a first oxidation treatment on the substrate 100 at the first preset temperature to form the first diffusion barrier layer 103.
[0069] The first diffusion barrier layer 103 is used to prevent elements in the embedded layer 101 from escaping from the surface of the substrate 100.
[0070] The first diffusion barrier layer 103 formed by oxidation treatment has high thickness uniformity, thus obtaining a first diffusion barrier layer 103 with good film quality; in addition, the oxidation treatment makes it easy to form the first diffusion barrier layer 103 on both the top and bottom of the substrate 100.
[0071] In this embodiment, the process for performing the first oxidation treatment on the substrate 100 includes a dry oxidation process.
[0072] It should be noted that, since the dry oxidation process is carried out in a dry environment, the growth of the first diffusion barrier layer 103 is relatively uniform, and the formed first diffusion barrier layer 103 has a high density.
[0073] In this embodiment, the proportion of the thickness of the first diffusion barrier layer 103 to the thickness of the diffusion barrier layer 102 should not be too large or too small. By appropriately increasing the proportion of the thickness of the first diffusion barrier layer 103 to the thickness of the diffusion barrier layer 102, a sufficiently thick first diffusion barrier layer 103 can be formed, which is beneficial to improving the coverage effect of the first diffusion barrier layer 103 on the substrate 100, thereby improving the uniformity of the thickness of the first diffusion barrier layer 103. By appropriately decreasing the proportion of the thickness of the first diffusion barrier layer 103 to the thickness of the diffusion barrier layer 102, the formation time of the first diffusion barrier layer 103 can be easily reduced, thereby easily increasing production capacity. Therefore, in this embodiment, the thickness of the first diffusion barrier layer 103 is 1 / 10 to 1 / 5 of the thickness of the diffusion barrier layer 102.
[0074] refer to Figure 5 The step of forming the second diffusion barrier layer 104 on the first diffusion barrier layer 103 includes: performing a second oxidation treatment on the substrate 100 at a second preset temperature to form the second diffusion barrier layer 104.
[0075] The second diffusion barrier layer 104 is also used to prevent elements in the embedded layer 101 from escaping from the surface of the substrate 100.
[0076] The second diffusion barrier layer 104 formed by oxidation treatment has high thickness uniformity, thus obtaining a second diffusion barrier layer 104 with good film quality; in addition, the oxidation treatment makes it easy to form the second diffusion barrier layer 104 on the first diffusion barrier layer 103.
[0077] It should be noted that performing the second oxidation treatment at the second preset temperature to form the second diffusion barrier layer 104 has several advantages. Firstly, the higher second preset temperature facilitates the diffusion of doped ions in the embedded layer 101 toward the bottom of the substrate 100, and also helps to activate the doped ions in the embedded layer 101. Secondly, the higher second preset temperature increases the rate at which the second diffusion barrier layer 104 is formed, which in turn increases the rate at which the diffusion barrier layer 102 is formed. This allows the thickness of the diffusion barrier layer 102 to meet the design requirements while increasing production capacity.
[0078] In this embodiment, the process for performing the second oxidation treatment on the substrate 100 includes a wet oxidation process.
[0079] The wet oxidation process has the advantage of a fast growth rate, which helps to reduce production time and thus improve production efficiency.
[0080] It should be noted that, since the first diffusion barrier layer is formed by dry oxidation process and the second diffusion barrier layer is formed by wet oxidation process, the density of the first diffusion barrier layer 103 is higher than that of the second diffusion barrier layer 104.
[0081] In this embodiment, a first diffusion barrier layer 103 and a second diffusion barrier layer 104 are sequentially formed on the substrate 100 in the same reaction chamber.
[0082] It should be noted that after the first diffusion barrier layer 103 is formed, the second diffusion barrier layer 104 can be formed directly in the same reaction chamber. This makes the first diffusion barrier layer 103 less likely to be exposed to air, which helps to reduce the probability of airborne particles adsorbing onto the first diffusion barrier layer 103. At the same time, it also reduces the steps of transporting the substrate 100 between different devices, thereby simplifying the process and improving production efficiency.
[0083] refer to Figure 6 In this embodiment, a first diffusion barrier layer 103 (e.g., ...) is formed on the substrate 100 in the same deposition process. Figure 6 After (as shown by line segment 4 in the diagram), the reaction chamber undergoes a second heating process, raising the temperature of the reaction chamber from the first preset temperature to the second preset temperature (as shown by line segment 4 in the diagram). Figure 6 As shown in line segment 5), a second diffusion barrier layer 104 is formed on the first diffusion barrier layer 103 at a second preset temperature (as shown in line segment 5). Figure 6 (As shown in line segment 7).
[0084] It should be noted that, compared to forming the first diffusion barrier layer and the second diffusion barrier layer separately through different deposition processes, this embodiment changes the temperature of the reaction chamber at different stages of the same deposition process, which helps to reduce the heating time, thereby saving production time and reducing production costs. At the same time, since it is carried out in the same deposition process, the first diffusion barrier layer 103 and the second diffusion barrier layer 104 can be formed in the same reaction chamber.
[0085] In this embodiment, the ratio of the process gas flow rate for forming the first diffusion barrier layer 103 on the substrate 100 to the process gas flow rate for forming the second diffusion barrier layer 104 on the first diffusion barrier layer 103 should not be too large or too small. If the ratio of the process gas flow rate for forming the first diffusion barrier layer 103 on the substrate 100 to the process gas flow rate for forming the second diffusion barrier layer 104 on the first diffusion barrier layer 103 is too large, it is easy to cause poor process stability in forming the first diffusion barrier layer 103 on the substrate 100, and the uniformity of the thickness of the first diffusion barrier layer 103 is difficult to control; if the ratio of the process gas flow rate for forming the first diffusion barrier layer 103 on the substrate 100 to the process gas flow rate for forming the second diffusion barrier layer 104 on the first diffusion barrier layer 103 is too small, it is easy to cause poor quality in forming the first diffusion barrier layer 103 on the substrate 100. Therefore, in this embodiment, the process gas flow rate for forming the first diffusion barrier layer 103 on the substrate 100 is 1 to 3 times the process gas flow rate for forming the second diffusion barrier layer 104 on the first diffusion barrier layer 103.
[0086] In this embodiment, the diffusion barrier layer 102 is formed by a furnace tube process.
[0087] By employing furnace tube technology, it is beneficial to control the thickness of the film and improve the quality of the film. Moreover, furnace tube technology can process multiple wafers simultaneously, thereby enabling mass production.
[0088] Therefore, continue to refer to Figure 6 Before raising the temperature of the reaction chamber used to form the diffusion barrier layer 102 to a first preset temperature, the process further includes: introducing a crystal boat containing the substrate 100 into the reaction chamber (e.g., ...). Figure 6 (as shown in line segment 1).
[0089] Specifically, after the crystal boat is loaded with the substrate 100, it enters the reaction chamber to prepare for the subsequent formation of a diffusion barrier layer on the substrate 100.
[0090] Continue to refer to Figure 6 In this embodiment, before forming the first diffusion barrier layer 103 on the substrate 100, the method further includes: in a reaction chamber containing the substrate 100 and used to form the diffusion barrier layer, performing a first heating process on the reaction chamber to raise the temperature of the reaction chamber to a first preset temperature (e.g., ...). Figure 6 (as shown in line segment 2).
[0091] Specifically, after the crystal boat containing the substrate 100 is placed into the reaction chamber, the reaction chamber is subjected to a first heating process.
[0092] The reaction chamber is subjected to a first heating treatment to raise its temperature to a first preset temperature in preparation for the subsequent formation of a first diffusion barrier layer.
[0093] Continue to refer to Figure 6 In this embodiment, after the first heating treatment is performed on the reaction chamber and before the first diffusion barrier layer 103 is formed on the substrate 100, the method further includes: stabilizing the process gas flow rate and process temperature (e.g., at the first preset temperature) for forming the first diffusion barrier layer 103. Figure 6 (As shown in line segment 3).
[0094] It should be noted that stabilizing the process gas flow rate and process temperature used to form the first diffusion barrier layer 103 prepares for the subsequent formation of the first diffusion barrier layer 103 and helps to improve the quality and thickness uniformity of the first diffusion barrier layer 103.
[0095] Continue to refer to Figure 6 In this embodiment, after the reaction chamber undergoes the second heating treatment and before the second diffusion barrier layer is formed on the first diffusion barrier layer 103, the method further includes: stabilizing the process gas flow rate and process temperature (e.g., at the second preset temperature) for forming the second diffusion barrier layer. Figure 6 (As shown in line segment 6).
[0096] It should be noted that stabilizing the process gas flow rate and process temperature used to form the second diffusion barrier layer prepares for the subsequent formation of the second diffusion barrier layer and helps to improve the quality and thickness uniformity of the second diffusion barrier layer.
[0097] In this embodiment, the second preset temperature should not be too high or too low. If the second preset temperature is too high, it may cause thermal stress inside the substrate 100, resulting in deformation of the substrate 100; if the second preset temperature is too low, it may result in poor diffusion of the first doped ions in the embedded layer 101 towards the bottom of the substrate 100. Therefore, in this embodiment, the range of the second preset temperature is 950 degrees Celsius to 1100 degrees Celsius.
[0098] In this embodiment, the difference between the second preset temperature and the first preset temperature should not be too large or too small. Appropriately reducing the difference between the second preset temperature and the first preset temperature, i.e., appropriately reducing the second preset temperature, helps to reduce damage to the formed structure caused by prolonged high-temperature treatment; appropriately increasing the difference between the second preset temperature and the first preset temperature, i.e., appropriately increasing the second preset temperature, helps to reduce the time required to form the second diffusion barrier layer, thereby increasing production capacity. Therefore, in this embodiment, the difference between the second preset temperature and the first preset temperature is 10% to 20% of the second preset temperature.
[0099] As an example, the first preset temperature is 700 to 1000 degrees Celsius.
[0100] refer to Figure 6 In this embodiment, after forming the second diffusion barrier layer 104 on the first diffusion barrier layer 103, the method further includes: performing a third heating process on the reaction chamber to raise the temperature from the second preset temperature to a third preset temperature (e.g., Figure 6 (as shown in line segment 8).
[0101] It should be noted that the reaction chamber undergoes a third heating process to raise the temperature from the second preset temperature to the third preset temperature, in preparation for the subsequent annealing process.
[0102] In this embodiment, after the third heating treatment is performed on the reaction chamber, the method further includes: annealing the embedded layer 101 at the third preset temperature (e.g., ...). Figure 6 (as shown in line segment 9).
[0103] The pre-embedded layer 101 is annealed to allow the doped ions in the pre-embedded layer 101 to diffuse toward the bottom of the substrate 100, thereby increasing the depth of the pre-embedded layer 101.
[0104] refer to Figure 6 In this embodiment, after annealing the embedded layer 101, the method further includes: cooling the reaction chamber (e.g., ...). Figure 6 (as shown by line segment 10 in the diagram); after cooling, the crystal boat containing the substrate 100 is transferred out of the reaction chamber (as shown by line segment 10 in the diagram); Figure 6 (as shown in line segment 11).
[0105] The reaction chamber is cooled to bring the substrate 100 to a temperature at which it can be transferred out of the reaction chamber; the crystal boat containing the substrate 100 is transferred out of the reaction chamber to prepare for subsequent process steps of the substrate 100.
[0106] refer to Figure 7This is a comparison diagram of the diffusion resistivity distribution curve of a semiconductor structure formed by the formation method of this invention and a semiconductor structure formed by prior art. The horizontal axis represents the depth from the top surface of the epitaxial layer to the substrate 100, the origin of the coordinate system represents the position of the top surface of the epitaxial layer, and the vertical axis represents the corresponding diffusion resistivity. Curve 1 is the diffusion resistivity distribution curve of a semiconductor structure formed by prior art, and curve 2 is the diffusion resistivity distribution curve of a semiconductor structure of this invention. Figure 7 As can be seen, compared with curve 1, curve 2 is further away from the origin, that is, curve 2 is closer to the substrate 100 region. At the same time, the peak of curve 2 is higher than the peak of curve 1, that is, the diffusion resistivity of curve 2 is higher.
[0107] Accordingly, the present invention also provides a semiconductor structure. Figure 8 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
[0108] refer to Figure 8 The semiconductor structure includes: a substrate 500 having a pre-buried layer 501 therein, and the pre-buried layer 501 having doped ions; a diffusion barrier layer 502 located on the substrate 500, the diffusion barrier layer 502 including: a first diffusion barrier layer 503 covering the substrate 500; and a second diffusion barrier layer 504 covering the first diffusion barrier layer 503; wherein the first diffusion barrier layer 503 is formed at a first preset temperature, and the second diffusion barrier layer 504 is formed at a second preset temperature, the first preset temperature being lower than the second preset temperature.
[0109] It should be noted that, since the first preset temperature is lower than the second preset temperature, the rate of forming the first diffusion barrier layer 503 is lower, which correspondingly increases the time required to form the first diffusion barrier layer 503. This allows the dopant ions in the embedded layer 501 more time to diffuse and distribute in the substrate 500, resulting in a more uniform concentration distribution of the dopant ions in the embedded layer 501 in the substrate 500. Consequently, the concentration gradient of the dopant ions in the substrate 500 is reduced, thereby reducing the probability of the dopant ions in the embedded layer 501 diffusing to the surface of the substrate 500. In the subsequent epitaxial growth process, this increases the probability of neutralization between the dopant ions in the epitaxial layer and the dopant ions in the embedded layer 501, resulting in the diffusion resistivity distribution curve being closer to the substrate 500 and increasing the diffusion resistance value. Furthermore, since the first preset temperature is lower, the diffusion rate of the dopant ions in the embedded layer 501 is reduced during the formation of the first diffusion barrier layer 503, thereby reducing the probability of the dopant ions in the embedded layer 501 diffusing into the chamber and thus reducing the probability of the chamber being contaminated.
[0110] Substrate 500 is used to provide a process platform for the formation of semiconductor structures.
[0111] In this embodiment, the substrate 500 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.
[0112] As an example, if substrate 500 is a P-type substrate, then the ions doped in substrate 500 are P-type dopant ions. Specifically, the P-type dopant ions (i.e. the doped ions) are group IIIA elements, such as boron.
[0113] The embedded layer 501 is located in the substrate 500 and is used to provide a substrate 100 that meets the device performance requirements for the semiconductor structure, thereby realizing basic device functions.
[0114] In this embodiment, the doped ions in the embedded layer 501 have the opposite conductivity type to the doped ions in the substrate 500. That is, when the ions doped in the substrate 500 are P-type, the ions doped in the embedded layer 501 are N-type, and when the ions doped in the substrate 500 are N-type, the ions doped in the embedded layer 501 are P-type.
[0115] Therefore, in this embodiment, the doped ions in the pre-embedded layer 501 are N-type doped ions.
[0116] In this embodiment, the doped ions in the pre-embedded layer 501 include: a first doped ion and a second doped ion, wherein the first doped ion and the second doped ion belong to the same group of elements, and the concentration of the first doped ion is higher than the concentration of the second doped ion.
[0117] It should be noted that the first dopant ion and the second dopant ion belong to the same group of elements. For example, if the first dopant ion is a group VA element, the second dopant ion is also a group VA element; if the first dopant ion is a group IIIA element, the second dopant ion is also a group IIIA element.
[0118] In this embodiment, the doping ions in the pre-embedded layer 501 can be group VA elements.
[0119] It should also be noted that the first doped ion and the second doped ion in the pre-embedded layer 501 belong to the same group of elements, and the concentration of the first doped ion is higher than that of the second doped ion (i.e., the first doped ion belongs to the heavily doped ion and the second doped ion belongs to the lightly doped ion), which is beneficial to promoting the redistribution of the concentration of the first doped ion and the second doped ion in the substrate.
[0120] As an example, the first dopant ion includes Sb, and the second dopant ion includes phosphorus.
[0121] The diffusion barrier layer 502 is used to prevent elements in the embedded layer 501 from escaping from the surface of the substrate 500.
[0122] In this embodiment, the density of the first diffusion barrier layer 503 is higher than that of the second diffusion barrier layer 504.
[0123] The first diffusion barrier layer 503, which is closer to the substrate 500, has a higher density, which helps to reduce the probability of dopants in the buried layer 501 escaping from the substrate 500. In the subsequent epitaxial growth process, it increases the probability of dopants in the epitaxial layer neutralizing with dopants in the buried layer 501, thereby enabling the diffusion resistivity distribution curve to be closer to the substrate 500 and increasing the diffusion resistance value.
[0124] In this embodiment, the material of the first diffusion barrier layer 503 includes silicon oxide, and the material of the second diffusion barrier layer 504 includes silicon oxide.
[0125] It should be noted that silicon oxide has a good diffusion barrier effect, which can effectively prevent doped ions in the embedded layer 501 from escaping from the surface of the substrate 500. At the same time, silicon oxide is easy to grow on the substrate 500, which improves production efficiency and reduces production costs.
[0126] The first diffusion barrier layer 503 is used to prevent elements in the embedded layer 501 from escaping from the surface of the substrate 500.
[0127] In this embodiment, the proportion of the thickness of the first diffusion barrier layer 503 to the thickness of the diffusion barrier layer 502 should not be too large or too small. By appropriately increasing the proportion of the thickness of the first diffusion barrier layer 503 to the thickness of the diffusion barrier layer 502, a sufficiently thick first diffusion barrier layer 503 can be formed, which is beneficial to improving the coverage effect of the first diffusion barrier layer 503 on the substrate 500, thereby improving the uniformity of the thickness of the first diffusion barrier layer 503. By appropriately decreasing the proportion of the thickness of the first diffusion barrier layer 503 to the thickness of the diffusion barrier layer 502, the formation time of the first diffusion barrier layer 503 can be easily reduced, thereby easily increasing production capacity. Therefore, in this embodiment, the thickness of the first diffusion barrier layer 503 is 1 / 10 to 1 / 5 of the thickness of the diffusion barrier layer 502.
[0128] The second diffusion barrier layer 504 is also used to prevent elements in the embedded layer 501 from escaping from the surface of the substrate 500.
[0129] The second diffusion barrier layer 504 is formed by oxidation treatment. On the one hand, the higher second preset temperature facilitates the diffusion of the first doped ions in the embedded layer 501 toward the bottom of the substrate 500, thereby increasing the depth of the embedded layer 501. On the other hand, the higher second preset temperature facilitates the increase in the formation rate of the second diffusion barrier layer 504, which in turn increases the formation rate of the diffusion barrier layer 502. This helps to ensure that the thickness of the diffusion barrier layer 502 meets the design requirements while increasing production capacity.
[0130] It should be noted that the semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.
[0131] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method of forming a semiconductor structure, characterized by, include: A substrate is provided in which a pre-embedded layer is formed, the pre-embedded layer having doped ions; The step of forming a diffusion barrier layer on the substrate includes: forming a first diffusion barrier layer on the substrate at a first preset temperature; and forming a second diffusion barrier layer on the first diffusion barrier layer at a second preset temperature, wherein the second diffusion barrier layer and the first diffusion barrier layer constitute a diffusion barrier layer. The first preset temperature is lower than the second preset temperature.
2. The method of forming a semiconductor structure of claim 1, wherein, The step of forming a first diffusion barrier layer on the substrate includes: performing a first oxidation treatment on the substrate at a first preset temperature to form a first diffusion barrier layer.
3. The method of forming a semiconductor structure of claim 2, wherein, The process for performing the first oxidation treatment on the substrate includes a dry oxidation process.
4. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the second diffusion barrier layer on the first diffusion barrier layer includes: performing a second oxidation treatment on the substrate at a second preset temperature to form the second diffusion barrier layer.
5. The method of forming a semiconductor structure of claim 4, wherein, The process for performing the second oxidation treatment on the substrate includes a wet oxidation process.
6. The method of forming a semiconductor structure of claim 1, wherein, In the same reaction chamber, a first diffusion barrier layer and a second diffusion barrier layer are formed sequentially on the substrate.
7. The method of forming a semiconductor structure of claim 6, wherein, In the same deposition process, after the first diffusion barrier layer is formed on the substrate, the reaction chamber is subjected to a second heating process to raise the temperature of the reaction chamber from the first preset temperature to the second preset temperature.
8. The method for forming a semiconductor structure as described in claim 7, characterized in that, Before forming the first diffusion barrier layer on the substrate, the method further includes: in a reaction chamber containing the substrate and used to form the diffusion barrier layer, performing a first heating process on the reaction chamber to raise the temperature of the reaction chamber to a first preset temperature.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, After the reaction chamber undergoes the first heating treatment, and before the first diffusion barrier layer is formed on the substrate, the method further includes: stabilizing the process gas flow rate and process temperature for forming the first diffusion barrier layer at the first preset temperature.
10. The method for forming a semiconductor structure as described in claim 7, characterized in that, After the reaction chamber is subjected to the second heating treatment, and before the second diffusion barrier layer is formed on the first diffusion barrier layer, the process further includes: stabilizing the process gas flow rate and process temperature for forming the second diffusion barrier layer at the second preset temperature.
11. The method for forming a semiconductor structure according to any one of claims 1 to 10, characterized in that, The second preset temperature ranges from 950 degrees Celsius to 1100 degrees Celsius.
12. The method for forming a semiconductor structure according to any one of claims 1 to 10, characterized in that, The difference between the second preset temperature and the first preset temperature is 10% to 20% of the second preset temperature.
13. The method for forming a semiconductor structure according to any one of claims 1 to 10, characterized in that, The process gas flow rate for forming the first diffusion barrier layer on the substrate is 1 to 3 times that for forming the second diffusion barrier layer on the first diffusion barrier layer.
14. The method for forming a semiconductor structure according to any one of claims 1 to 10, characterized in that, In the step of forming the pre-buried layer in the substrate, the doping ions include: a first doping ion and a second doping ion, wherein the first doping ion and the second doping ion belong to the same group of elements, and the concentration of the first doping ion is higher than the concentration of the second doping ion.
15. A semiconductor structure, characterized in that, include: A substrate having a pre-buried layer, wherein the pre-buried layer has doped ions; A diffusion barrier layer is located on the substrate, the diffusion barrier layer comprising: a first diffusion barrier layer covering the substrate; and a second diffusion barrier layer covering the first diffusion barrier layer, the second diffusion barrier layer and the first diffusion barrier layer constituting a diffusion barrier layer; The first diffusion barrier layer is formed at a first preset temperature, and the second diffusion barrier layer is formed at a second preset temperature, wherein the first preset temperature is lower than the second preset temperature.
16. The semiconductor structure as claimed in claim 15, characterized in that, The thickness of the first diffusion barrier layer is 1 / 10 to 1 / 5 of the thickness of the diffusion barrier layer.
17. The semiconductor structure as claimed in claim 15, characterized in that, The material of the first diffusion barrier layer includes silicon oxide.
18. The semiconductor structure as claimed in claim 15, characterized in that, The material of the second diffusion barrier layer includes silicon oxide.
19. The semiconductor structure as described in claim 15, characterized in that, The density of the first diffusion barrier layer is higher than that of the second diffusion barrier layer.
20. The semiconductor structure as claimed in claim 15, characterized in that, The doped ions in the pre-embedded layer include a first doped ion and a second doped ion, the first doped ion and the second doped ion belong to the same group of elements, and the concentration of the first doped ion is higher than the concentration of the second doped ion.