Semiconductor structure and method of forming the same
By introducing an ion barrier layer into the fin field-effect transistor, the problem of the difficulty in improving the performance of the fin field-effect transistor after the feature size is reduced is solved. By blocking ion diffusion, the working performance of the transistor is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-06-03
- Publication Date
- 2026-07-24
AI Technical Summary
In the prior art, it is difficult to further improve the performance of fin field-effect transistors when the feature size is further reduced, and ion interdiffusion is easily generated between the first and second anti-penetration ion layers, which affects the working performance of the transistor.
An ion barrier layer is introduced into the semiconductor structure, located between the first and second anti-penetration ion layers. Discrete bottom fins and device fins are formed through fin patterning, and the ion barrier layer is covered during the formation process to block ion diffusion. At the same time, a second fin material layer is formed on the second anti-penetration ion layer.
It effectively blocks ion diffusion between the first and second anti-penetration ion layers, improves the operating performance of the first and second transistors, meets their respective performance requirements, and further enhances the performance of the transistors.
Smart Images
Figure CN115440659B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as one of the basic semiconductor devices, are currently widely used. Therefore, as the density and integration of semiconductor devices increase, the gate size of planar transistors is becoming shorter and shorter. The ability of traditional planar transistors to control channel current weakens, resulting in short-channel effects, which increase leakage current and ultimately affect the electrical performance of semiconductor devices.
[0003] To better adapt to the shrinking feature size, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. However, with further reductions in feature size, it is difficult to further improve the performance of FinFETs. Summary of the Invention
[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.
[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a first device region for forming a first transistor and a second device region adjacent to the first device region and for forming a second transistor; a bottom fin protruding from the substrate of the first device region and the second device region; a first anti-penetration ion layer located on the bottom fin of the first device region; a second anti-penetration ion layer located on the bottom fin of the second device region; a first device fin located on the first anti-penetration ion layer; a second device fin located on the second anti-penetration ion layer; and an ion blocking layer located between the second anti-penetration ion layer and the bottom fin of the second device region.
[0006] Accordingly, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a first fin material layer located on the substrate, the substrate including a first device region for forming a first transistor and a second device region adjacent to the first device region for forming a second transistor, wherein a first penetration-blocking ion layer is further formed between the substrate and the first fin material layer in the first device region; removing the first fin material layer located in the second device region to expose the sidewall of the first penetration-blocking ion layer in the first device region; forming an ion barrier layer on the exposed sidewall of the first penetration-blocking ion layer in the first device region; forming a second penetration-blocking ion layer on the substrate of the second device region after forming the ion barrier layer; and forming a second fin on the second penetration-blocking ion layer. Material layers; fin patterning is performed, patterning the first fin material layer, the second fin material layer, the first anti-penetration ion layer, the second anti-penetration ion layer, the ion blocking layer, and a substrate of a certain thickness. The substrate of a certain thickness is patterned as bottom fins protruding from the remaining substrates of the first device region and the second device region, respectively. The first fin material layer is patterned as a first device fin protruding from the bottom fin of the first device region, and the second fin material layer is patterned as a second device fin protruding from the bottom fin of the second device region. After completing the fin patterning, an isolation layer is formed on the substrate. The isolation layer covers the sidewalls of the bottom fins, the sidewalls of the first and second anti-penetration ion layers, and the sidewalls of the ion blocking layer.
[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0008] The semiconductor structure provided in this embodiment of the invention includes an ion barrier layer located between the second anti-penetration ion layer and the bottom fin of the second device region. During the formation of the semiconductor structure, fin patterning is typically performed to form discrete bottom fins, a first device fin, and a second device fin. Before the fin patterning, the first anti-penetration ion layer covers the entire first device region, and the second anti-penetration ion layer covers the entire second device region. The ion barrier layer is formed between the material layers corresponding to the bottom fins of the second and second device regions, and also between the first and second anti-penetration ion layers. This ion barrier layer isolates the first and second anti-penetration ion layers, effectively preventing ion diffusion between them, thus ensuring the operating performance of the first and second transistors. Simultaneously, the first and second device fins can respectively meet the performance requirements of the first and second transistors, improving the performance of different transistors and further enhancing their operating performance.
[0009] In the formation method provided by the embodiments of the present invention, an ion blocking layer is formed on the sidewall of the first anti-penetration ion layer exposed in the first device region. After the ion blocking layer is formed, a second anti-penetration ion layer is formed on the substrate of the second device region. In the embodiments of the present invention, the formation of an ion blocking layer between the first anti-penetration ion layer and the second anti-penetration ion layer is beneficial to blocking ion diffusion between the first anti-penetration ion layer and the second anti-penetration ion layer, thereby helping to ensure the working performance of the first transistor and the second transistor. At the same time, a second fin material layer is formed on the second anti-penetration ion layer, which enables the first device fin and the second device fin to be used to meet the performance requirements of the first transistor and the second transistor respectively, so as to improve the performance of different transistors and further improve the working performance of the first transistor and the second transistor. Attached Figure Description
[0010] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0011] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
[0012] Figures 6 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0013] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.
[0014] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0015] refer to Figure 1 A substrate (not shown) is provided, including a substrate 10 and a first fin material layer 21 located on the substrate 10. The substrate includes a first device region 10N for forming a first transistor and a second device region 10P adjacent to the first device region 10N for forming a second transistor. In the first device region 10N, a first anti-penetration ion layer 13 is also formed between the substrate 10 and the first fin material layer 21. A first well region 11 is also formed in the substrate 10 of the first device region 10N, and a second well region 12 is also formed in the substrate 10 of the second device region 10P.
[0016] refer to Figure 2 In the second device region 10P, the first fin material layer 21 above the second well region 12 is subjected to anti-penetration ion implantation to form a second anti-penetration ion layer 15.
[0017] The second anti-penetration ion layer 15 is in contact with the first anti-penetration ion layer 13, which easily leads to ion interdiffusion between the first and second anti-penetration ion layers 13 and 15. This affects the concentration and distribution of anti-penetration ions in the first and second anti-penetration ion layers 13 and 15, thereby affecting the anti-penetration performance of each layer and consequently the operating performance of the first and second transistors. Furthermore, the ion doping concentration in the second and first anti-penetration ion layers 15 is typically high, thus increasing the probability of ion interdiffusion between the first and second anti-penetration ion layers 13 and 15.
[0018] In particular, when the channel conductivity types of the first transistor and the second transistor are different, the conductivity types of the anti-penetration ions in the first anti-penetration ion layer 13 and the second anti-penetration ion layer 15 are correspondingly different. In the first anti-penetration ion layer 13 and the second anti-penetration ion layer 15, N-type ions and P-type ions are more likely to diffuse into each other, which leads to a decrease in the anti-penetration performance of the first anti-penetration layer 13 and the second anti-penetration ion layer 15.
[0019] refer to Figure 3 Remove the first fin material layer 21 located in the second device region 10N; form a second fin material layer 22 on the substrate 10 in the second device region 10N.
[0020] refer to Figure 4The first fin material layer 21 and the second fin material layer 22 are patterned. The first fin material layer 21 is patterned as a first fin 41 protruding from the substrate 10 in the first device region 10P, and the second fin material layer 22 is patterned as a second fin 42 protruding from the substrate 10 in the second device region 10N.
[0021] To address the aforementioned technical problem, this invention provides a method for forming a semiconductor structure. An ion blocking layer is formed between the first and second anti-penetration ion layers, which helps to block ion diffusion between the first and second anti-penetration ion layers, thereby ensuring the operating performance of the first and second transistors. Simultaneously, a second fin material layer is formed on the second anti-penetration ion layer, enabling the first and second device fins to respectively meet the performance requirements of the first and second transistors, thereby improving the performance of different transistors and further enhancing the operating performance of the first and second transistors.
[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0023] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
[0024] The semiconductor structure includes: a substrate 101, including a first device region 101N for forming a first transistor and a second device region 101P adjacent to the first device region 101N and for forming a second transistor; a bottom fin 161 protruding from the substrate 101 of the first device region 101N and the second device region 101P; a first anti-penetration ion layer 131 located on the bottom fin 161 of the first device region 101N; a second anti-penetration ion layer 151 located on the bottom fin 161 of the second device region 101P; a first device fin 411 located on the first anti-penetration ion layer 131; a second device fin 421 located on the second anti-penetration ion layer 151; and an ion blocking layer 141 located between the second anti-penetration ion layer 151 and the bottom fin 161 of the second device region 101P.
[0025] Substrate 101 provides the basis for the process operation of forming semiconductor structures. These semiconductor structures include FinFETs and gate-all-around (GAA) transistors.
[0026] In this embodiment, the substrate 101 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 101 may be suitable for process requirements or easy to integrate.
[0027] In this embodiment, the substrate 101 includes a first device region 101N for forming a first transistor and a second device region 101P for forming a second transistor. The first transistor and the second transistor have different channel conductivity types, including N-type and P-type. As an example, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.
[0028] In this embodiment, the first transistor and the second transistor use different channel materials. By employing different channel materials, the respective performance requirements of the first and second transistors are met. In other embodiments, the first transistor and the second transistor may use the same channel material.
[0029] In this embodiment, taking a fin field-effect transistor as an example, a fin (not shown) is formed on the substrate 101, including a bottom fin 161 and a device fin (not shown). The device fin includes a first device fin 411 located in the first device region 101N and a second device fin 421 located in the second device region 101P.
[0030] In this embodiment, the bottom fin 161 and the substrate 101 are an integral structure. Therefore, the material of the bottom fin 161 is the same as the material of the substrate 101, or the material of the bottom fin 161 is the same as the material of the topmost semiconductor layer of the substrate 101. In this embodiment, the material of the substrate 101 is silicon, and the material of the bottom fin 161 is also silicon.
[0031] In this embodiment, the semiconductor structure further includes: a first well region 111 located in the substrate 101 of the bottom fin 161 of the first device region 101N, which is a portion of the thickness of the substrate 101; and a second well region 121 located in the substrate 101 of the bottom fin 161 of the second device region 101P, which is a portion of the thickness of the substrate 101.
[0032] The first well region 111 and the second well region 121 are used to provide the N-type substrate or P-type substrate required for the operation of the corresponding transistors and to achieve electrical isolation between adjacent transistors.
[0033] The first well region 111 and the second well region 121 contain well region ions, and the conductivity type of the well region ions is opposite to the channel conductivity type of the corresponding transistor. That is, the well region ions corresponding to the NMOS transistor are P-type ions, and the well region ions corresponding to the PMOS transistor are N-type ions.
[0034] In this embodiment, the first transistor and the second transistor have different channel conductivity types; therefore, the conductivity types of the well ions in the first well region 111 and the second well region 121 are different. Specifically, the well ions in the first well region 111 are P-type ions, and the well ions in the second well region 121 are N-type ions.
[0035] The first anti-penetration ion layer 131 and the second anti-penetration ion layer 151 are used to reduce the possibility of drain-source punch-through and reduce the short-channel effect.
[0036] In the first and second anti-penetration ion layers 131, the conductivity type of the ions differs from the channel conductivity type of the corresponding transistor. Specifically, the conductivity type of the ions in the first anti-penetration ion layer 131 differs from the channel conductivity type of the first transistor, and the conductivity type of the ions in the second anti-penetration ion layer 151 differs from the channel conductivity type of the second transistor. For example, for an NMOS transistor, the ions are P-type ions, including boron ions; for a PMOS transistor, the ions are N-type ions, including phosphorus ions or arsenic ions.
[0037] Therefore, in this embodiment, the material of the first anti-penetration ion layer 131 includes phosphorus-doped silicon, arsenic-doped silicon, or boron-doped silicon; the material of the second anti-penetration ion layer 151 includes phosphorus-doped silicon, arsenic-doped silicon, or boron-doped silicon. The materials of the first anti-penetration ion layer 131 and the second anti-penetration ion layer 151 are specifically determined according to the channel conductivity type of the corresponding transistor.
[0038] In this embodiment, the channel conductivity types of the first transistor and the second transistor are different. Therefore, the ion types in the materials of the first anti-penetration ion layer 131 and the second anti-penetration ion layer 151 are different. Specifically, the material of the first anti-penetration ion layer 131 is boron-doped silicon, and the material of the second anti-penetration ion layer 151 includes phosphorus-doped silicon or arsenic-doped silicon.
[0039] The first device fin 411 and the second device fin 421 are used to provide the channel of the fin field-effect transistor.
[0040] In this embodiment, the material of the first device fin 411 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials; the material of the second device fin 421 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.
[0041] In this embodiment, the channel materials of the first transistor and the second transistor are different. Specifically, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor. Therefore, in this embodiment, the material of the first device fin 411 is silicon, and the material of the second device fin 421 is silicon germanide. By using silicon germanide for the device fins of the PMOS transistor, the channel mobility of the PMOS transistor is improved. Simultaneously, this helps to mitigate the negative bias temperature instability (NBTI) problem of the PMOS transistor, thereby improving the performance of the PMOS transistor.
[0042] The ion blocking layer 141 is used to block ion diffusion between the first anti-penetration ion layer 131 and the second anti-penetration ion layer 151.
[0043] During the formation of the semiconductor structure, fin patterning is typically performed to form discrete bottom fins 161, first device fins 411, and second device fins 421. Before the fin patterning, a first anti-penetration ion layer 131 covers the entire first device region 101N, and a second anti-penetration ion layer 151 covers the entire second device region 101P. An ion blocking layer 141 is formed between the material layers corresponding to the bottom fins 161 of the second anti-penetration ion layer 151 and the second device region 101P, and is also formed between the first anti-penetration ion layer 131 and... Between the second anti-penetration ion layers 151, the ion blocking layer 141 isolates the first anti-penetration ion layer 131 and the second anti-penetration ion layer 151, which helps to block ion diffusion between the first anti-penetration ion layer 131 and the second anti-penetration ion layer 151, thereby helping to ensure the working performance of the first transistor and the second transistor. At the same time, the first device fin 411 and the second device fin 421 can be used to meet the performance requirements of the first transistor and the second transistor respectively, so as to improve the performance of different transistors and further improve the working performance of the first transistor and the second transistor.
[0044] It should be noted that the thickness of the ion blocking layer 141 cannot be too large or too small. During the formation of the semiconductor structure, before the fin patterning process, the ion barrier layer 141 is obtained by ion implantation of the material layer corresponding to the bottom fin 161 or by epitaxial growth on top of the material layer corresponding to the bottom fin 161. If the thickness of the ion barrier layer 141 is too large, when using the ion implantation process, the ion barrier layer 141 will easily occupy too much space in the second well region 121 in the bottom fin 161, affecting the formation quality of the second well region 121. When using the epitaxial growth process, if the thickness of the ion barrier layer 141 is too large, and the distance from the top of the second device fin 421 to the top of the substrate 101 is certain, the height of the second device fin 421 will be too small, which will easily cause the channel surface area or volume to be too small, thereby affecting the performance of the transistor (e.g., device speed). If the thickness of the ion barrier layer 141 is too small, the blocking effect of the ion barrier layer 141 will be weakened, and it will be difficult to block ion diffusion between the first anti-penetration ion layer 131 and the second anti-penetration ion layer 151. Therefore, in this embodiment, the thickness of the ion blocking layer 141 is 3 nm to 40 nm.
[0045] In this embodiment, the material of the ion blocking layer 141 includes one or more of silicon carbide, silicon nitride, and silicon carbonitride.
[0046] Since silicon atoms are octahedral and have relatively large interatomic gaps, while in silicon carbide, silicon nitride, and silicon carbonitride, carbon or nitrogen atoms are embedded in the interatomic gaps of silicon atoms, the silicon carbide, silicon nitride, and silicon carbonitride have high density and small interatomic gaps, which can play a better role in blocking ion diffusion between the first anti-penetration ion layer 131 and the second anti-penetration ion layer 151.
[0047] In this embodiment, the semiconductor structure further includes an isolation layer 171, which is located on the substrate 101 and covers the sidewalls of the bottom fin 161, the sidewalls of the first anti-penetration ion layer 131 and the second anti-penetration ion layer 151, and the sidewalls of the ion blocking layer 151.
[0048] The isolation layer 171 serves as a shallow trench isolation (STI) structure to isolate adjacent transistors. In this embodiment, the isolation layer 171 covers the sidewalls of the bottom fin 161, the sidewalls of the first anti-penetration ion layer 131 and the second anti-penetration ion layer 151, and the sidewalls of the ion blocking layer 151, thereby enabling the transistor to use only the first device fin 411 and the second device fin 421 as channels.
[0049] It should be noted that even if the surface roughness of the bottom fin 161 is high, the impact of the bottom fin 161 on the transistor performance is reduced because the isolation layer 171 covers the sidewall of the bottom fin 161.
[0050] In this embodiment, the top surface of the isolation layer 171 is higher than the top surface of the first anti-penetration ion layer 131 and the second anti-penetration ion layer 151. That is, the isolation layer 171 also covers part of the sidewalls of the first device fin 411 and the second device fin 421. The possibility of the first and second anti-penetration ion layers 131 and 151 diffusing into the first device fin 411 and the second device fin 421 is reduced. Therefore, by making the top surface of the isolation layer 171 higher than the top surfaces of the first and second anti-penetration ion layers 131 and 151, the portion of the first device fin 411 near the first anti-penetration ion layer 131 and the portion of the second device fin 421 near the second anti-penetration ion layer 151 will not be used as a channel. This reduces or avoids the impact on the transistor channel caused by the upward diffusion of the first and second anti-penetration ion layers 131 and 151, thereby reducing or avoiding the impact of the first anti-penetration ion layer 131, the second anti-penetration ion layer 151, and the ion blocking layer 141 on the transistor performance.
[0051] In this embodiment, the portion of the device fin exposed above the isolation layer 171 is designated as an effective fin, meaning that the portion of the device fin exposed above the isolation layer 171 is covered by the device gate structure. Therefore, depending on actual needs, the top of the isolation layer 171 is higher than or flush with the bottom of the first device fin 411 and the second device fin 421. In other words, the isolation layer 171 exposes the entire or part of the sidewalls of the first device fin 411 and the second device fin 421. As an example, Figure 5 The top of the isolation layer 171 is shown above the bottom of the first device fin 411 and the second device fin 421 to reduce the possibility that the first ion-blocking layer 131, the second ion-blocking layer 151, or the ion-blocking layer 141 will be exposed by the isolation layer 171.
[0052] In this embodiment, the material of the insulating layer 171 is silicon oxide. In other embodiments, the material of the insulating layer may also be other insulating materials such as silicon nitride or silicon oxynitride.
[0053] Figures 6 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0054] refer to Figure 6A substrate (not shown) is provided, including a substrate 100 and a first fin material layer 210 located on the substrate 100. The substrate includes a first device region 100N for forming a first transistor and a second device region 100P adjacent to the first device region 100N for forming a second transistor. In the first device region 100N, a first anti-penetration ion layer 130 is also formed between the substrate 100 and the first fin material layer 210.
[0055] The substrate provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes a finned field-effect transistor or a fully enclosed gate transistor.
[0056] In this embodiment, the substrate includes a first device region 100N for forming a first transistor and a second device region 100P for forming a second transistor. The first transistor and the second transistor have different channel conductivity types, including N-type and P-type. As an example, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.
[0057] In this embodiment, the first transistor and the second transistor use different channel materials. By employing different channel materials, the respective performance requirements of the first and second transistors are met. In other embodiments, the first transistor and the second transistor may use the same channel material.
[0058] In this embodiment, taking a fin field-effect transistor as an example, the substrate includes a substrate 100 and a first fin material layer 210 located on the substrate 100. The first fin material layer 210 is used to subsequently form the first device fin.
[0059] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate 100 may be a material suitable for process requirements or easy to integrate.
[0060] In this embodiment, the material of the first fin material layer 210 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.
[0061] In this embodiment, the first transistor is an NMOS transistor, therefore, the material of the first fin material layer 210 is silicon.
[0062] Specifically, the first fin material layer 210 and the substrate 100 are integrally formed. In other embodiments, the first fin material layer may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the first fin material layer.
[0063] In other embodiments, the material of the first fin material layer may also be different from the material of the substrate.
[0064] The first anti-penetration ion layer 130 is used to reduce the possibility of drain-source punch-through in the first transistor and reduce the short-channel effect.
[0065] The first anti-penetration ion layer 130 is obtained by ion implantation into the substrate 100. The conductivity type of the ions in the first anti-penetration ion layer 130 is different from the channel conductivity type of the first transistor. When the first transistor is an NMOS transistor, the ions are P-type ions, including boron ions. When the first transistor is a PMOS transistor, the ions are N-type ions, including phosphorus ions or arsenic ions.
[0066] Therefore, in this embodiment, the material of the first anti-penetration ion layer 130 includes phosphorus-doped silicon, arsenic-doped silicon, or boron-doped silicon. Specifically, the first transistor is an NMOS transistor, and the material of the first anti-penetration ion layer 130 is boron-doped silicon.
[0067] In this embodiment, a first well region 110 is also formed in the substrate of the first device region 100N, and a second well region 120 is also formed in the substrate of the second device region 100P.
[0068] The first well region 110 and the second well region 120 are used to provide the N-type substrate or P-type substrate required for the operation of the corresponding transistors and to achieve electrical isolation between adjacent transistors.
[0069] The first well region 110 and the second well region 120 contain well region ions, and the conductivity type of the well region ions is opposite to the channel conductivity type of the corresponding transistor. That is, the well region ions corresponding to the NMOS transistor are P-type ions, and the well region ions corresponding to the PMOS transistor are N-type ions.
[0070] In this embodiment, the first transistor and the second transistor have different channel conductivity types. Therefore, the conductivity types of the well ions in the first well region 110 and the second well region 120 are different. Specifically, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor. Therefore, the well ions in the first well region 110 are P-type ions, and the well ions in the second well region 120 are N-type ions.
[0071] It should be noted that in this embodiment, the formation method is used to form a fin field-effect transistor (FinFET), meaning that fins protruding from the substrate 100 will be formed subsequently. As the critical dimensions of the device continue to decrease, the linewidth of the fins becomes increasingly smaller. If well region ion implantation is performed on the fins after their formation to form well regions, it can easily damage the fins. Therefore, in this embodiment, the well regions are formed before the fins are formed, thereby avoiding damage to the fins caused by the formation processes of the first well region 110 and the second well region 120.
[0072] In this embodiment, a protective layer 300 is formed on the top of the first fin material layer 210.
[0073] The protective layer 300 is used to protect the top of the first fin material layer 210 when the ion barrier layer is subsequently formed.
[0074] The protective layer 300 is a dielectric material to improve process compatibility with subsequent manufacturing processes. In this embodiment, the material of the protective layer 300 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the protective layer 300 is silicon nitride.
[0075] refer to Figure 7 Remove the first fin material layer 210 located in the second device region 100P to expose the sidewall of the first anti-penetration ion layer 130 in the first device region 100N.
[0076] Remove the first fin material layer 210 located in the second device region 100P to expose the sidewall of the first anti-penetration ion layer 130 in the first device region 100N, providing space for the subsequent formation of the ion blocking layer, the second anti-penetration ion layer and the second fin material layer.
[0077] In this embodiment, a dry etching process is used to remove the first fin material layer 210 located in the second device region 100P.
[0078] The dry etching process is an anisotropic etching process, which helps to reduce damage to the first fin material layer 210 and the first anti-penetration ion layer 130. At the same time, the dry etching process can better control the process parameters, so that the thickness of the first fin material layer 210 for removing the second device region 100P can be controlled more precisely.
[0079] Correspondingly, the protective layer 300 located in the second device region 100P is also removed.
[0080] refer to Figure 8An ion blocking layer 140 is formed on the sidewall of the first anti-penetration ion layer 130 exposed in the first device region 100N.
[0081] A second anti-penetration ion layer will be formed subsequently. In this embodiment, an ion blocking layer 140 is formed between the first anti-penetration ion layer 130 and the second anti-penetration ion layer, which helps to block ion diffusion between the first anti-penetration ion layer 130 and the second anti-penetration ion layer, thereby helping to ensure the working performance of the first transistor and the second transistor. At the same time, a second fin material layer is formed on the second anti-penetration ion layer, which allows the subsequently formed first device fin and second device fin to be used to meet the performance requirements of the first transistor and the second transistor, respectively, so as to improve the performance of different transistors and further improve the working performance of the first transistor and the second transistor.
[0082] In this embodiment, during the process of forming an ion blocking layer 140 on the sidewall of the first anti-penetration ion layer 130 exposed in the first device region 100N, the ion blocking layer 140 also extends to cover the top surface of the substrate 100 in the second device region 100P and the sidewall of the first fin material layer 210 in the first device region 100N.
[0083] The ion blocking layer 140 further extends to cover the top surface of the substrate 100 in the second device region 100P and the sidewall of the first fin material layer 210 in the first device region 100N, further ensuring that the ion blocking layer 140 completely blocks the sidewall of the first anti-penetration ion layer 130, thus ensuring the ion diffusion blocking effect of the ion blocking layer 140. Moreover, forming an ion blocking layer that extends to cover the top surface of the substrate 100 in the second device region 100P and the sidewall of the first fin material layer 210 in the first device region 100N allows for a simpler process and higher process efficiency.
[0084] In this embodiment, an epitaxial growth process is used to form an epitaxial layer on the sidewall of the first anti-penetration ion layer 130 exposed in the first device region 100N. During the epitaxial growth process, in-situ self-doping of blocking ions is performed, and the epitaxial layer doped with the blocking ions serves as the ion blocking layer 140.
[0085] The epitaxial growth process allows for better control of process parameters, resulting in high process controllability and making it easy to obtain a precise thickness of the ion barrier layer 140. Furthermore, the epitaxial growth process facilitates the formation of a film layer with fewer impurities, leading to a higher quality of the ion barrier layer 140.
[0086] In this embodiment, the ion blocking layer 140 is formed by an epitaxial growth process.
[0087] Since other films will be epitaxially grown on the ion barrier layer 140 in the future, using an epitaxial growth process to form the ion barrier layer 140 is beneficial for growing the ion barrier layer 140 together with other films, which simplifies the process flow, improves process efficiency, and enhances process integration and compatibility.
[0088] In this embodiment, the material of the epitaxial layer includes silicon.
[0089] The substrate 100, the first anti-penetration ion layer 130 and the first fin material layer 210 are all made of silicon, which is beneficial for growing an epitaxial layer containing silicon.
[0090] In this embodiment, the blocking ions include one or both of carbon ions and nitrogen ions.
[0091] Since silicon atoms are octahedral with relatively large interatomic gaps, and when carbon and nitrogen elements are incorporated, carbon or nitrogen atoms will be embedded in the interatomic gaps of silicon atoms. Therefore, the ion barrier layer 140 formed by incorporating nitrogen atoms has a high density and small interatomic gaps, which can play a good role in blocking ion diffusion between the first anti-penetration ion layer 130 and the second anti-penetration ion layer.
[0092] Therefore, in this embodiment, the material of the ion blocking layer 140 includes one or more of silicon carbide, silicon nitride, and silicon carbonitride.
[0093] It should be noted that, since a protective layer 300 is formed on top of the first fin material layer 210, the probability of epitaxial growth occurring on the first fin material layer 210 during the epitaxial growth process is low, thereby reducing the subsequent impact on the fin of the first device. Moreover, the protective layer 300 is a dielectric material, which is compatible with the epitaxial process.
[0094] It should also be noted that in other embodiments, an ion implantation process can be used to implant blocking ions into the sidewall of the first penetration-blocking ion layer exposed in the first device region, and the first penetration-blocking ion layer doped with the blocking ions serves as the ion blocking layer.
[0095] Ion implantation technology features uniform and large-area ion implantation, more accurate control of ion doping depth, and high repeatability, making it easy to obtain ion barrier layers with relatively precise thickness and good surface uniformity.
[0096] It should be noted that the thickness of the ion barrier layer 140 cannot be too large or too small. If the thickness of the ion barrier layer 140 is too large, during ion implantation, it may occupy too much space in the second well region 120 of the substrate 100, affecting the formation quality of the second well region 120. During epitaxial growth, if the thickness of the ion barrier layer 140 is too large, and the distance from the top of the subsequently formed second device fin to the top of the substrate 100 is constant, the height of the subsequently formed second device fin will be too small, easily causing the channel surface area or volume to be too small, thus affecting the transistor performance (e.g., device speed). If the thickness of the ion barrier layer 140 is too small, its blocking effect is weakened, making it difficult to prevent ion diffusion between the first anti-penetration ion layer 130 and the subsequently formed second anti-penetration ion layer. Therefore, in this embodiment, the thickness of the ion barrier layer 140 is 3 nm to 40 nm.
[0097] refer to Figure 9 After the ion blocking layer 140 is formed, a second anti-penetration ion layer 150 is formed on the substrate 100 of the second device region 100P.
[0098] The second anti-penetration ion layer 150 is used to reduce the possibility of drain-source punch-through in the second transistor and reduce the short-channel effect.
[0099] In this embodiment, during the formation of the second anti-penetration ion layer 150, the second anti-penetration ion layer 150 also extends to cover the sidewall of the ion blocking layer 140 located on the sidewall of the first fin material layer 210, making the process of forming the second anti-penetration ion layer 150 simple and easy to operate, without the need for additional masking.
[0100] In this embodiment, the second anti-penetration ion layer 150 is formed by epitaxial growth process.
[0101] The epitaxial growth process can better control the process parameters, has high process controllability, and can easily obtain a more accurate thickness of the second anti-penetration ion layer 150, improve the uniformity of the concentration of anti-penetration ions in the second anti-penetration ion layer 150, and the epitaxial growth process can easily form a film layer with fewer impurities, resulting in a higher quality of the second anti-penetration ion layer 150.
[0102] Specifically, an epitaxial layer is formed on the ion barrier layer 140 using an epitaxial growth process, and during the epitaxial growth process, in-situ self-doping with anti-penetration ions is performed, and the epitaxial layer doped with the anti-penetration ions serves as the second anti-penetration ion layer 150.
[0103] In this embodiment, silicon is used as the epitaxial material during the epitaxial growth process of forming the second anti-penetration ion layer 150.
[0104] When forming the second anti-penetration ion layer 150 and the ion blocking layer 140, the same epitaxial layer material is used, which makes it easy to form the ion blocking layer 140 and the second anti-penetration ion layer 150 in the same process, and only the in-situ self-doped ions need to be changed, which simplifies the process.
[0105] The conductivity type of the ions in the second anti-penetration ion layer 150 is different from the channel conductivity type of the second transistor. When the second transistor is an NMOS transistor, the ions are P-type ions, which include boron ions. When the second transistor is a PMOS transistor, the ions are phosphorus ions or arsenic ions. Therefore, in this embodiment, the material of the epitaxial layer includes silicon, and the anti-penetration ions are N-type ions, which include boron ions, phosphorus ions, or arsenic ions.
[0106] Therefore, in this embodiment, the material of the second anti-penetration ion layer 150 includes phosphorus-doped silicon, arsenic-doped silicon, or boron-doped silicon.
[0107] In this embodiment, the first transistor and the second transistor have different channel conductivity types. Therefore, the ion types in the materials of the first anti-penetration ion layer 130 and the second anti-penetration ion layer 150 are different. Specifically, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor. Therefore, the material of the second anti-penetration ion layer 150 includes phosphorus-doped silicon or arsenic-doped silicon.
[0108] refer to Figure 10 A second fin material layer 220 is formed on the second anti-penetration ion layer 150.
[0109] The second fin material layer 220 is used to subsequently form the second device fin.
[0110] In this embodiment, the second fin material layer 220 also covers the sidewall of the second anti-penetration ion layer 150 located on the sidewall of the ion blocking layer 140, forming a second device fin material layer 220 of sufficient height, and making the top of the second device fin material layer 220 close to the top of the first device fin material layer 210, forming a top surface with high flatness. Moreover, it also makes the process of forming the second device fin material layer 220 simple and easy to operate.
[0111] In this embodiment, the second fin material layer 220 is formed by epitaxial growth process.
[0112] The epitaxial growth process can better control the process parameters, has high process controllability, and is easy to obtain a more accurate thickness of the second fin material layer 220. Moreover, the epitaxial growth process is easy to form a film layer with fewer impurities, resulting in a higher quality of the second fin material layer 220.
[0113] In this embodiment, the ion blocking layer 140, the second anti-penetration ion layer 150, and the second fin material layer 220 are formed sequentially in the same process.
[0114] The formation of the ion barrier layer 140, the second anti-penetration ion layer 150, and the second fin material layer 220 are all achieved through epitaxial growth processes. These layers can be formed sequentially in the same process, simplifying the process flow, improving process efficiency, and enhancing process integration and compatibility. "Same process" means that the formation of the ion barrier layer 140, the second anti-penetration ion layer 150, and the second fin material layer 220 is completed sequentially on the same machine in the same process, without requiring additional steps.
[0115] The material of the second device fin material layer 220 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.
[0116] In this embodiment, the channel materials of the first transistor and the second transistor are different. Specifically, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor. Therefore, in this embodiment, the material of the first device fin layer 210 is silicon, and the material of the second device fin layer 220 is silicon germanide. By using silicon germanide for the second device fin of the PMOS transistor, the channel mobility of the PMOS transistor is improved. Simultaneously, this helps to mitigate the negative bias temperature instability (NBTI) problem of the PMOS transistor, thereby improving the performance of the PMOS transistor.
[0117] refer to Figure 11 After the second fin material layer 220 is formed, the protective layer 300 is removed.
[0118] Remove the protective layer 300 to prepare for the subsequent formation of the first device fin and the second device fin.
[0119] refer to Figure 12 After the second fin material layer 220 is formed, before the first fin material layer 210 and the second fin material layer 220 are patterned, the method further includes forming a hard mask layer 310 on the first fin material layer 210 and the second fin material layer 220.
[0120] The hard mask layer 310 provides a platform with good flatness for the subsequent formation of the core layer and sidewalls. The hard mask layer 310 is also used as an etching mask for the subsequent patterning of the first fin material layer 210 and the second fin material layer 220.
[0121] In this embodiment, the material of the hard mask layer 310 includes one or more of silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the hard mask layer 310 is silicon nitride.
[0122] Reference Figures 13 to 16 The fins are patterned by performing fin patterning processing, which pattern the first fin material layer 210, the second fin material layer 220, the first anti-penetration ion layer 130, the second anti-penetration ion layer 150, the ion blocking layer 140, and a substrate 100 of a certain thickness. The substrate 100 of a certain thickness is patterned into bottom fins 160 that protrude from the remaining substrates 100 of the first device region 100N and the second device region 100P, respectively. The first fin material layer 210 is patterned into a first device fin 410 that protrudes from the substrate 100 of the first device region 100N, and the second fin material layer 220 is patterned into a second device fin 420 that protrudes from the substrate 100 of the second device region 100P.
[0123] The first device fin 410 and the second device fin 420 are respectively used to provide the channels for the first transistor and the second transistor.
[0124] In this embodiment, a dry etching process is used for fin patterning.
[0125] The dry etching process is an anisotropic etching process with directional etching, which is beneficial for forming a first device fin 410 and a second device fin 420 with better sidewall quality. At the same time, the dry etching process can better control the process parameters, so that the parameters of the fin patterning process can be controlled more precisely.
[0126] Accordingly, the material of the first device fin 410 is silicon, and the material of the second device fin 420 is silicon germanide.
[0127] In this embodiment, the step of patterning a portion of the substrate 100 during the fin patterning process includes: patterning a portion of the substrate 100 corresponding to the first well region 110 and a portion of the substrate 100 corresponding to the second well region 120, as the bottom fin 160.
[0128] It should be noted that even if the ions in the trap region affect the etching rate of the substrate 100, resulting in a higher surface roughness of the bottom fin 160, the impact of the bottom fin 160 on the transistor performance is reduced or avoided because the subsequently formed isolation layer covers the sidewalls of the bottom fin 160.
[0129] Figures 13 to 16 The specific steps of the graphic processing of the fin are illustrated.
[0130] Specifically, refer to Figure 13 A core layer 320 is formed on the first fin material layer 210 and the second fin material layer 220.
[0131] Specifically, the core layer 320 is formed on the hard mask layer 310.
[0132] The core layer 320 provides support for the subsequent formation of sidewalls on the side walls of the core layer 320.
[0133] The core layer 320 will be removed subsequently. Therefore, the material of the core layer 320 is one that is easy to remove, thereby reducing the difficulty of removing the core layer 320 and minimizing damage to other films located below the core layer 320. Therefore, the material of the core layer 320 includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning film (APF) materials, spin-on carbon (SOC), and silicon carbide. In this embodiment, the core layer 320 is an advanced patterning film material.
[0134] refer to Figure 14 A sidewall 330 is formed on the sidewall of the core layer 320.
[0135] During the fin patterning process, the sidewall 330 is used as an etching mask for the patterned hard mask layer 310.
[0136] The sidewall 330 is made of a material that has etching selectivity with the core layer 320 and the hard mask layer 310. In this embodiment, the material of the sidewall 330 includes Si3N4, SiBCN or SiCN.
[0137] Specifically, the step of forming the sidewall 330 includes: forming a sidewall material layer (not shown) that conformally covers the top and sidewall of the core layer 320 and the top of the hard mask layer 320; removing the sidewall material layer located on the top of the core layer 320 and the top of the hard mask layer 320, and retaining the sidewall material layer located on the sidewall of the core layer 320 as the sidewall 330.
[0138] refer to Figure 15After the sidewall 330 is formed, the core layer 320 is removed.
[0139] Remove the core layer 320 to prepare for the patterned hard mask layer 310, which uses the sidewalls 330 as a mask.
[0140] In this embodiment, the core layer 320 is removed using a wet etching process.
[0141] The wet etching process has the characteristics of isotropic etching, which is beneficial to completely remove the core layer 320. At the same time, the wet etching process can provide good etching selectivity, which is beneficial to remove the core layer 320 while reducing damage to the sidewalls 330 and the hard mask layer 310.
[0142] refer to Figure 16 The hard mask layer 310 is graphically visualized to form a fin mask layer (not shown).
[0143] The fin mask layer is used as an etching mask for fin patterning.
[0144] In this embodiment, during the step of patterning the fin, the first fin material layer 210 and the second fin material layer 220 are etched using the fin mask layer as a mask.
[0145] Patterning the first fin material layer 210 and the second fin material layer 220 with the fin mask layer helps to improve the accuracy of pattern transfer and form the first fin 410 and the second fin 420 with higher dimensional accuracy.
[0146] Specifically, after removing the core layer 320, the hard mask layer 310 is etched using the sidewall 330 as a mask, and the remaining hard mask layer 310 after etching serves as the fin mask layer.
[0147] refer to Figure 17 After completing the fin patterning process, an isolation layer 170 is formed on the substrate 100. The isolation layer 170 covers the sidewalls of the bottom fin 160, the sidewalls of the first anti-penetration ion layer 130 and the second anti-penetration ion layer 150, and the sidewalls of the ion blocking layer 140.
[0148] The isolation layer 170 serves as a shallow trench isolation (STI) structure to isolate adjacent transistors. In this embodiment, the isolation layer 170 covers the sidewalls of the bottom fin 160, the sidewalls of the first anti-penetration ion layer 130 and the second anti-penetration ion layer 150, and the sidewalls of the ion blocking layer 150, thereby enabling the transistor to use only the first device fin 410 and the second device fin 420 as channels.
[0149] It should be noted that even if the surface roughness of the bottom fin 160 is high, the impact of the bottom fin 160 on the transistor performance is reduced because the isolation layer 170 covers the sidewall of the bottom fin 160.
[0150] In this embodiment, the top surface of the isolation layer 170 is higher than the top surfaces of the first anti-penetration ion layer 130 and the second anti-penetration ion layer 150. That is, the isolation layer 170 also covers part of the sidewalls of the first device fin 410 and the second device fin 420. The possibility of the first and second anti-penetration ion layers 130 and 150 diffusing into the first device fin 410 and the second device fin 420 is reduced. Therefore, by making the top surface of the isolation layer 170 higher than the top surfaces of the first and second anti-penetration ion layers 130 and 150, the portion of the first device fin 410 near the first anti-penetration ion layer 130 and the portion of the second device fin 420 near the second anti-penetration ion layer 150 will not be used as a channel. This reduces or avoids the impact on the transistor channel caused by the upward diffusion of the first and second anti-penetration ion layers 130 and 150, thereby reducing or avoiding the impact of the first anti-penetration ion layer 130, the second anti-penetration ion layer 150 and the ion barrier layer 140 on the transistor performance.
[0151] In this embodiment, the portion of the device fin exposed above the isolation layer 170 is designated as an effective fin, meaning that the portion of the device fin exposed above the isolation layer 170 is covered by the device gate structure. Therefore, depending on actual needs, the top of the isolation layer 170 is higher than or flush with the bottom of the first device fin 410 and the second device fin 420. In other words, the isolation layer 170 exposes the entire or part of the sidewalls of the first device fin 410 and the second device fin 420. As an example, Figure 17 The top of the isolation layer 170 is shown above the bottom of the first device fin 410 and the second device fin 420 to reduce the possibility that the first ion-blocking layer 130, the second ion-blocking layer 150, or the ion-blocking layer 140 will be exposed by the isolation layer 170.
[0152] In this embodiment, the material of the insulating layer 170 is silicon oxide. In other embodiments, the material of the insulating layer may also be other insulating materials such as silicon nitride or silicon oxynitride.
[0153] Specifically, the steps for forming the isolation layer 170 include: forming an isolation material layer (not shown) on the substrate 100 covering the sidewalls of the bottom fin 160, the sidewalls of the first and second penetration-through ion layers 130 and 150, the sidewalls of the ion blocking layer 140, and the first and second device fins 410 and 420; planarizing the isolation material layer (e.g., chemical mechanical polishing) with the top of the fin mask layer (i.e., the remaining hard mask layer 310) as the stop position; after planarization, etching back a portion of the isolation material layer, retaining the isolation material layer covering the sidewalls of the bottom fin 160, the sidewalls of the first and second penetration-through ion layers 130 and 150, and the sidewalls of the ion blocking layer 140 as the isolation layer 170. By sequentially performing planarization and etching back, it is beneficial to control the height of the formed isolation layer 170.
[0154] It should be noted that, after planarization and before etching back a portion of the isolation material layer, the remaining hard mask layer 310 can be removed; or, the remaining hard mask layer 310 can be removed after the isolation layer 170 is formed.
[0155] It should also be noted that a gate structure spanning the first fin 410 and the second fin 420 will be formed subsequently, which will not be discussed in detail here.
[0156] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that, include: The substrate includes a first device region for forming a first transistor and a second device region adjacent to the first device region for forming a second transistor; The bottom fin protrudes from the substrate of the first device region and the second device region; The first anti-penetration ion layer is located on the bottom fin of the first device region; The second anti-penetration ion layer is located on the bottom fin of the second device region; The first device fin is located on the first anti-penetration ion layer; The second device fin is located on the second anti-penetration ion layer; An ion blocking layer is located between the second anti-penetration ion layer and the bottom fin of the second device region. The ion blocking layer is also used to isolate the first anti-penetration ion layer and the second anti-penetration ion layer.
2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a first well region located in the substrate, which is a portion of the thickness of the bottom fin of the first device region; The second well region is located in the substrate of a portion of the bottom fin of the second device region.
3. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: an isolation layer located on the substrate and covering the sidewalls of the bottom fin, the sidewalls of the first and second anti-penetration ion layers, and the sidewalls of the ion blocking layer.
4. The semiconductor structure as described in claim 1, characterized in that, The thickness of the ion blocking layer is 3 nm to 40 nm.
5. The semiconductor structure as described in claim 1, characterized in that, The material of the ion blocking layer includes one or more of silicon carbide, silicon nitride, and silicon carbonitride.
6. The semiconductor structure as described in claim 1, characterized in that, The material of the first ion-penetrating barrier layer includes phosphorus-doped silicon, arsenic-doped silicon, or boron-doped silicon; the material of the second ion-penetrating barrier layer includes phosphorus-doped silicon, arsenic-doped silicon, or boron-doped silicon.
7. The semiconductor structure as described in claim 1, characterized in that, The material of the first device fin includes silicon, germanium, silicon germanide, or group III-V semiconductor materials; the material of the second device fin includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.
8. The semiconductor structure as described in claim 1, characterized in that, The first transistor and the second transistor have different channel conductivity types; The conductivity type of the ions in the first anti-penetration ion layer is different from the conductivity type of the channel of the first transistor. The conductivity type of the ions in the second anti-penetration ion layer is different from the conductivity type of the channel of the second transistor.
9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a first fin material layer located on the substrate. The substrate includes a first device region for forming a first transistor and a second device region adjacent to the first device region for forming a second transistor. In the first device region, a first anti-penetration ion layer is further formed between the substrate and the first fin material layer. Remove the first fin material layer located in the second device region to expose the sidewall of the first penetration-resistant ion layer in the first device region; An ion blocking layer is formed on the sidewall of the first anti-penetration ion layer in the exposed first device region; After the ion blocking layer is formed, a second ion-blocking layer is formed on the substrate of the second device region; A second fin material layer is formed on the second anti-penetration ion layer; The fins are patterned by patterning the first fin material layer, the second fin material layer, the first anti-penetration ion layer, the second anti-penetration ion layer, the ion blocking layer, and a substrate of a certain thickness. The substrate of a certain thickness is patterned as bottom fins protruding from the remaining substrates of the first device region and the second device region, respectively. The first fin material layer is patterned as a first device fin protruding from the bottom fin of the first device region, and the second fin material layer is patterned as a second device fin protruding from the bottom fin of the second device region. After the fin patterning process is completed, an isolation layer is formed on the substrate. The isolation layer covers the sidewalls of the bottom fin, the sidewalls of the first and second anti-penetration ion layers, and the sidewalls of the ion blocking layer.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, During the process of forming an ion barrier layer on the sidewall of the first ion-blocking layer that exposes the first device region, the ion barrier layer also extends to cover the top surface of the substrate in the second device region and the sidewall of the first fin material layer in the first device region. During the formation of the second anti-penetration ion layer, the second anti-penetration ion layer also extends to cover the sidewall of the ion blocking layer located on the sidewall of the first fin material layer. During the formation of the second fin material layer, the second fin material layer also covers the sidewall of the second anti-penetration ion layer located on the sidewall of the ion barrier layer.
11. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming the second fin material layer and before patterning the first fin material layer and the second fin material layer, the method further includes: forming a hard mask layer on the first fin material layer and the second fin material layer; The hard mask layer is patterned to form a fin mask layer; In the step of performing the fin patterning process, the first fin material layer and the second fin material layer are etched using the fin mask layer as a mask.
12. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing the substrate, a first well region is further formed in the substrate of the first device region, and a second well region is further formed in the substrate of the second device region; During the fin patterning process, the step of patterning a substrate of partial thickness includes patterning a substrate corresponding to the first well region of partial thickness and a substrate corresponding to the second well region of partial thickness.
13. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing the substrate, a protective layer is formed on top of the first fin material layer; After the second fin material layer is formed, the protective layer is removed.
14. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the ion barrier layer, an epitaxial growth process is used to form an epitaxial layer on the sidewall of the first anti-penetration ion layer exposed in the first device region. During the epitaxial growth process, in-situ self-doping of barrier ions is performed, and the epitaxial layer doped with the barrier ions serves as the ion barrier layer. Alternatively, an ion implantation process can be used to implant barrier ions into the sidewall of the first penetration-blocking ion layer in the exposed first device region, with the first penetration-blocking ion layer doped with the barrier ions serving as the ion barrier layer.
15. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the second anti-penetration ion layer, the second anti-penetration ion layer is formed by epitaxial growth process, and anti-penetration ions are self-doped in situ during the epitaxial growth process.
16. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the second fin material layer, the second fin material layer is formed by an epitaxial growth process.
17. The method for forming a semiconductor structure according to any one of claims 14 to 16, characterized in that, The ion barrier layer is formed using an epitaxial growth process, and in the same process, the ion barrier layer, the second anti-penetration ion layer, and the second fin material layer are formed sequentially.
18. The method for forming a semiconductor structure as described in claim 14, characterized in that, The material of the epitaxial layer includes silicon.
19. The method for forming a semiconductor structure as described in claim 14, characterized in that, The blocking ions include one or both of carbon ions and nitrogen ions.