F-P standard cavity length inclination adjustment method and device based on FPGA

Abstract

This invention discloses an FPGA-based F-P etalon length tilt adjustment method and device. It performs layered adjustment of "X and Y direction parallelism adjustment" and "Z direction cavity fixing," relying on an FPGA to construct a two-level priority scheduling mechanism with fixed underlying hardware. Utilizing the parallel processing advantages and nanosecond-level clock determinism of FPGA hardware logic, the X and Y direction parallelism determination is fixed as the highest hardware priority. In each control iteration, the FPGA performs threshold comparison with low latency. If the parallelism does not meet the standard, the system intercepts the Z-direction cavity fixing command within a deterministic control cycle and prioritizes the leveling branch. This "software algorithm hardwareization" strategy effectively suppresses multidimensional cross-coupling oscillations. The adjusted etalon achieves the theoretical peak transmittance and spectral resolution, and the area array detector exhibits a sharp interference ring with good contrast.

Description

Technical Field

[0001] This invention belongs to the field of optical resonator technology, specifically relating to a method and device for adjusting the cavity length tilt of an FPGA-based FP etalon. Background Technology

[0002] The Fabry-Perot etalon (FP etalon) is a high-resolution optical resonant cavity based on the principle of multi-beam interference. Its core structure consists of two parallel optical plates, each with a highly reflective dielectric film coated on its inner surface. When incident light enters the "resonant cavity" between these two plates, the light wave undergoes multiple reflections and transmissions within the cavity. Only light waves that meet specific phase resonance conditions can undergo constructive interference and pass through smoothly; light waves that do not meet the conditions are reflected. This physical characteristic allows the FP etalon to macroscopically behave as a narrow-band optical filter, capable of precisely extracting extremely subtle specific wavelength components from complex broadband spectra.

[0003] FP etalons can be designed as dynamically tunable structures, and the core parameters for adjustment and control are "cavity length" and "parallelism." Based on the principle of interference... It is known that by precisely controlling the expansion and contraction of the cavity length, continuous scanning or precise locking of a specific wavelength spectrum can be achieved. However, achieving this high-resolution characteristic has an extremely stringent prerequisite: the parallelism of the two optical plates must be very high, reaching the nanometer (nm) level. If a tilting error occurs between the two plates during the process of changing the cavity length, it will cause slight differences in the local cavity length at different positions within the aperture. This microscopic non-parallelism will directly cause severe broadening of the transmission peak, a sharp reduction in peak transmittance, and a deterioration in the system's fineness, ultimately causing the entire optical system to lose its high-resolution measurement and filtering capabilities.

[0004] However, traditional control schemes typically employ closed-loop logic with multi-channel parallel adjustment, where servo loops in each dimension operate independently at the same time. The lack of strict priority determination and global backtracking logic can cause the system to fall into multi-dimensional oscillations.

[0005] In traditional control methods, although existing technologies have proposed basic coordinate transformation matrices for coordinate decoupling between orthogonal triaxial capacitive sensing and three-point piezoelectric ceramic actuation, conventional schemes generally employ parallel adjustment or lack a fixed control timing with global planning. Due to the lack of strict priority determination and global backtracking logic for multi-degree-of-freedom adjustment, when the system adjusts the cavity length over a wide range, minute differences in the physical responses of individual piezoelectric ceramics can easily disrupt the locked parallelism; conversely, local leveling can also cause fluctuations in the overall cavity length. This deficiency in control logic often leads to complex oscillations when the system approaches the target value, resulting in large errors in the X-axis tilt angle, Y-axis tilt angle, and Z-axis cavity length, making leveling difficult.

[0006] Therefore, how to overcome the limitations of traditional control architecture and design a set of FP standard utero cavity length tilt adjustment logic with strict priority judgment, so as to maintain good optical parallelism in broadband scanning, is a technical bottleneck that urgently needs to be overcome in this field. Summary of the Invention

[0007] The purpose of this invention is to solve the multidimensional cross-coupling and oscillation problems existing in the prior art. Under the scheduling of FPGA, it breaks the traditional parallel adjustment mode and constructs a rigorous FP etalon cavity length tilt adjustment process that integrates "absolute leveling priority" judgment and global backtracking mechanism, thereby realizing efficient adjustment of FP etalon. Thus, it provides an FPGA-based FP etalon cavity length tilt adjustment method and device.

[0008] To achieve the above objectives, the technical solution provided by this invention is as follows:

[0009] A method for adjusting the cavity length tilt of an FPGA-based etalon includes the following steps:

[0010] Step 1, State Initialization:

[0011] The FPGA control logic starts, receives the target cavity length L set by the user, and configures strict X-axis and Y-axis parallelism error thresholds in the register. , and Z-axis cavity length error threshold ;

[0012] Step 2: Obtain the current state:

[0013] Leveraging the multi-channel parallel acquisition capabilities of the FPGA, the system simultaneously measures the capacitance values ​​of six channels. The current X-axis and Y-axis parallelism error is calculated using high-speed computation within the FPGA. ;

[0014] Step 3, Prioritize leveling the cycle (Level 1):

[0015] The system executes the parallelism threshold determination logic: [determines / determines] and Do they both hold true?

[0016] If the result is "no" (i.e., parallelism does not meet the standard), the system intercepts the cavity length adjustment command and prioritizes the leveling branch: the algorithm uses the coordinate matrix to determine the current X-axis and Y-axis parallelism errors. Calculate the control values ​​used to correct the X and Y tilt. Subsequently, the system directly outputs the actuation voltage to the piezoelectric actuator and executes the timing delay logic of "waiting for the system to stabilize" to wait for the piezoelectric ceramic to complete the mechanical and physical response. After the "waiting for the system to stabilize" is completed, the system jumps back to step 2 to obtain a new round of the current state until the parallelism converges within the set threshold.

[0017] Step 4, Condition-triggered cavity length control and global backtracking (Level 2):

[0018] If step 3 determines "yes" (i.e., the parallelism in the X and Y directions has met the standard), the system enters the adjustment cavity length (Z direction) branch:

[0019] The system measures the current cavity length and the error calculation unit calculates the Z-axis cavity length error. ,judge Is it valid?

[0020] If the result is "no", the algorithm calculates the required cavity control amount (Z-direction) for adjusting the cavity length using a coordinate matrix. The system outputs an actuation voltage to the piezoelectric actuator and enters a "wait for system stabilization" state.

[0021] Global backtracking mechanism: After completing the single cavity length voltage output and waiting for the system to stabilize, the control flow does not enter a local dead loop in the fixed cavity branch, but jumps back to the global starting point (i.e., step 2), remeasures the multi-channel capacitance value, and checks the parallelism again with priority. This backtracking mechanism ensures that if the non-ideal physical response of the piezoelectric ceramic accidentally destroys the parallelism when correcting the cavity length, the system can instantly interrupt the fixed cavity task and switch back to the first-level leveling loop with priority.

[0022] Step 5, Status Output and Locking:

[0023] If and only if the system passes the first level of parallelism determination in sequence ( and ) and the determination of the second-stage cavity length ( When the system determines that the actual physical posture has matched the set target state, the system outputs the final cavity length position and the parallelism error of the X and Y axes, completing the closed-loop control of the cavity length, and the entire FP etalon cavity length tilt adjustment process ends.

[0024] An adjustment device for adjusting the cavity length tilt of an FPGA-based etalon standard relies on an FPGA-based underlying hardware digital closed-loop architecture. At the physical level, it includes: multi-channel micro-capacitive sensing probes evenly distributed on the FPGA standard, and multi-channel piezoelectric actuators, i.e., piezoelectric ceramics. The system includes a high-precision ADC and DAC that connect the multi-channel micro-capacitive sensing probe to the multi-channel piezoelectric actuator drive. The control center of the system is a field-programmable gate array (FPGA), which is configured with a parallel communication interface for multi-channel feedback data. The priority-based FPGA cavity length tilt adjustment logic proposed in this invention can be implemented in hardware in the FPGA using a finite state machine (FSM).

[0025] Compared with the prior art, the present invention has the following beneficial technical effects:

[0026] 1. This invention proposes a method and device for adjusting the cavity length tilt of an FPGA-based etalon, which effectively suppresses multidimensional cross-coupling oscillations.

[0027] 2. Conventional methods for adjusting multi-degree-of-freedom FP etalons often employ parallel adjustment modes. This not only tends to become entangled in complex vibrations when approaching the target but also results in slow convergence, leading to significant errors in the X-axis tilt angle, Y-axis tilt angle, and Z-axis cavity length, making leveling difficult. This invention breaks with convention by relying on pure hardware logic within the FPGA to implement a two-level algorithm execution sequence of "absolute leveling priority" and "global backtracking mechanism" through a finite state machine (FSM) inside the FPGA.

[0028] 3. By introducing a strict hardware-level threshold determination mechanism, this invention achieves time-series isolation between X / Y parallelism adjustment and Z-axis cavity translation within an extremely short clock cycle. This not only ensures the monotonous and rapid convergence of the adjustment process, but also guarantees that the system can maintain the user-set parallelism and cavity length state when performing large-range cavity length steps or continuous scanning. The adjusted etalon achieves the theoretical peak transmittance and spectral resolution, and the array detector presents a sharp interference ring with good contrast. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of orthogonal triaxial capacitive sensing and three-point piezoelectric ceramic actuation of the FP standard according to an embodiment of the present invention.

[0030] Figure 2 This is a flowchart of a priority-based method for adjusting the cavity length tilt of an FP etalon according to an embodiment of the present invention.

[0031] Figure 3 The image shows the detector interference ring pattern in the unadjusted method flow of this invention.

[0032] Figure 4 The interference ring pattern of the detector is shown in the process flow of the adjustment method in this embodiment of the invention. Detailed Implementation

[0033] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Those skilled in the art should understand that these embodiments are merely used to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0034] like Figure 1 , Figure 2 As shown, this embodiment provides a method for adjusting the cavity length tilt of an FPGA-based etalon, including the following steps:

[0035] Step 1, State Initialization:

[0036] The FPGA control logic starts, receives the target cavity length L set by the user, and configures strict X-axis and Y-axis parallelism error thresholds in the register. , and Z-axis cavity length error threshold ;

[0037] Step 2: Obtain the current state:

[0038] Leveraging the multi-channel parallel acquisition capabilities of the FPGA, the system simultaneously measures the capacitance values ​​of six channels. The current X-axis and Y-axis parallelism error is calculated at high speed through the internal computing of the FPGA. ;

[0039] Step 3, Level 1: Priority leveling loop:

[0040] The system executes the parallelism threshold determination logic: [determines / determines] and Do they both hold true?

[0041] If the result is "no" (i.e., parallelism does not meet the standard), the system intercepts the cavity length adjustment command and prioritizes the leveling branch: the algorithm uses the coordinate matrix to determine the current X-axis and Y-axis parallelism errors. Calculate the control values ​​used to correct the X and Y tilt. Subsequently, the system directly outputs an actuation voltage to the piezoelectric actuator, i.e., the piezoelectric ceramic. And execute the "wait for system stabilization" timing delay logic to wait for the piezoelectric ceramic to complete its mechanical and physical response, such as... Figure 1 As shown; after the system stabilizes, the system jumps back to step 2 to obtain the current state for a new round, until the parallelism converges within the set threshold.

[0042] Step 4, Level 2: Condition-triggered cavity length control and global backtracking:

[0043] If step 3 determines "yes" (i.e., the parallelism in the X and Y directions has met the standard), the system enters the adjustment cavity length (Z direction) branch:

[0044] The system measures the current cavity length and the error calculation unit calculates the Z-axis cavity length error. ;judge Is it valid?

[0045] If the result is "no", the algorithm calculates the required cavity control amount (Z-direction) for adjusting the cavity length using a coordinate matrix. The system outputs an actuation voltage to the piezoelectric actuator. The system then enters a "waiting for system stabilization" state. Global backtracking mechanism: After completing the single-cavity long voltage output and waiting for system stabilization, the control flow does not enter a local dead loop within the fixed-cavity branch, but instead jumps back to the global starting point (step 2) to remeasure the multi-channel capacitance value. And then prioritize checking the parallelism again; this backtracking mechanism ensures that if the non-ideal physical response of the piezoelectric ceramic accidentally destroys the parallelism when correcting the cavity length, the system can instantly interrupt the cavity setting task and prioritize switching back to the first-level leveling loop.

[0046] Step 5, Status Output and Locking:

[0047] If and only if the system passes the first level of parallelism determination in sequence ( and ) and the determination of the second-stage cavity length ( When the system determines that the actual physical posture has matched the target state set by the user, the system outputs the final cavity length position and the parallelism error of the X and Y axes, completing the closed-loop control of the cavity length, and the entire FP etalon cavity length tilt adjustment process ends.

[0048] like Figure 3 As shown, without adjustment methods, the interference of the detector is limited by the minute physical response differences between individual piezoelectric ceramics and the spatial cross-coupling effect of the X-axis tilt angle, Y-axis tilt angle, and Z-axis cavity length. The plate exhibits a slight tilt, and the interference rings on the area array detector often show deterioration phenomena such as contour distortion, blurred edges, and low contrast, leading to a decrease in instrument finesse and spectral resolution. The "absolute leveling priority" and "global backtracking" logic implemented in this invention effectively suppresses multidimensional cross-coupling oscillations by changing the scanning period of the cavity length (Z-axis). Figure 4 As shown, by adding the adjustment method to the detector interference, the adjusted etalon achieves the theoretical peak transmittance and spectral resolution, and the area array detector presents a sharp interference ring with good contrast.

[0049] To implement the cavity length tilt adjustment method proposed in this invention, this embodiment relies on a low-level hardware digital closed-loop architecture based on FPGA, which physically includes: a multi-channel micro-capacitive sensing probe evenly distributed on the FPGA standard, and a multi-channel piezoelectric actuator, i.e., piezoelectric ceramic. The system also includes high-precision ADCs and DACs that connect the sensing and driving ends; the control center of the system is a field-programmable gate array (FPGA), which is configured with a parallel communication interface for multi-channel feedback data; the priority-based FPGA cavity length tilt adjustment logic proposed in this invention can be hardware-implemented in the FPGA through a finite state machine (FSM).

[0050] The embodiments of the present invention use a field-programmable gate array (FPGA) as the control center and rely on a finite state machine (FSM) to perform nanosecond-level scheduling. However, the scope of protection of the present invention is not limited to this hardware platform. Without departing from the core control logic of the present invention, the digital signal processing and control core can also use a high-performance digital signal processor (DSP) with a hard real-time operating system (RTOS) or an advanced microcontroller with a high-frequency clock (such as the ARM Cortex-M / R series) to achieve equivalent logic scheduling and signal decoupling functions.

[0051] Not limited to multi-degree-of-freedom FP etalons, the pose adjustment control architecture with priority determination and global backtracking mechanism proposed in this invention can also be extended horizontally to other high-end precision instruments and semiconductor manufacturing equipment with multi-degree-of-freedom decoupling and nanometer-level stability.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A method for adjusting the cavity length tilt of an FPGA-based etalon, characterized in that, Includes the following steps: Step 1, State Initialization: The FPGA control logic starts, receives the set target cavity length L, and configures strict X-axis and Y-axis parallelism error thresholds in the register. , and Z-axis cavity length error threshold ; Step 2: Obtain the current state: Utilizing the multi-channel parallel acquisition capabilities of an FPGA, the system simultaneously measures the capacitance values ​​of six channels and calculates the current X-axis and Y-axis parallelism error through high-speed computation within the FPGA. ; Step 3, Level 1, i.e., priority leveling cycle: The system executes the parallelism threshold determination logic: [determines / determines] and Do they both hold true? Step 4, Level 2, namely condition-triggered cavity length control and global backtracking: If step 3 determines "yes", meaning the parallelism in the X and Y directions has met the standard, the system enters the adjustment cavity length stage, i.e., the Z-direction branch: The system measures the current cavity length and the error calculation unit calculates the Z-axis cavity length error. ,judge Is it valid? If step 3 determines "no", the algorithm calculates the adjustment cavity length using the coordinate matrix, i.e., the required fixed cavity control amount in the Z direction. The system outputs an actuation voltage to the piezoelectric actuator and enters a "wait for system stabilization" state. Global backtracking mechanism: After completing the single-cavity long voltage output and "waiting for the system to stabilize", the control flow does not enter a local dead loop in the fixed cavity branch, but jumps back to the global starting point, i.e., step 2, to remeasure the multi-channel capacitance value and check the parallelism again. Step 5, Status Output and Locking: If and only if the system passes the first level of parallelism determination in sequence, that is and The determination of the second-stage cavity length, i.e. At this point, the system determines that the actual physical posture has matched the set target state; at this time, the system outputs the final cavity length position and the parallelism error of the X and Y axes, completing the closed-loop control of the cavity length, and the entire FP etalon cavity length tilt adjustment process ends.

2. The method for adjusting the cavity length tilt of an FPGA-based etalon according to claim 1, characterized in that: In step 3, if the result is "no," meaning the parallelism does not meet the standard, the system intercepts the cavity length adjustment command and prioritizes entering the leveling branch: the algorithm uses the coordinate matrix to determine the current X-axis and Y-axis parallelism errors. Calculate the control values ​​used to correct the X and Y tilt. Subsequently, the system directly outputs the actuation voltage to the piezoelectric actuator and executes the timing delay logic of "waiting for the system to stabilize" to wait for the piezoelectric ceramic to complete the mechanical physical response. After the "waiting for the system to stabilize" is completed, the system jumps back to step 2 to obtain a new round of the current state until the parallelism converges within the set threshold.

3. The method for adjusting the cavity length tilt of an FPGA-based etalon according to claim 1, characterized in that: In step 4, the backtracking mechanism ensures that if the non-ideal physical response of the piezoelectric ceramic unexpectedly disrupts the parallelism when correcting the cavity length, the system will instantly interrupt the cavity setting task and prioritize switching back to the first-level leveling loop.

4. An adjustment device for implementing the FPGA-based FP etalon length tilt adjustment method according to any one of claims 1 to 3, characterized in that: Based on an FPGA-based underlying hardware digital closed-loop architecture, the system includes: multi-channel micro-capacitive sensing probes and multi-channel piezoelectric actuators evenly distributed on the FPGA standard; high-precision ADCs and DACs connecting the multi-channel micro-capacitive sensing probes and the multi-channel piezoelectric actuator drivers; the system's control center is a field-programmable gate array (FPGA), internally configured with a parallel communication interface for multi-channel feedback data.

5. The adjustment device for the FPGA-based etalon cavity length tilt adjustment method according to claim 4, characterized in that: The multi-channel piezoelectric actuator is a piezoelectric ceramic. .

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