Method and system for inter-module local frequency-division clock phase consistency in large-scale chips
By introducing clock synchronization pulse indication signals and frequency divider counters for cyclic counting between modules in a large-scale chip, the problem of inconsistent clock phases between modules is solved, achieving timing consistency and efficient data transmission for data interaction between modules.
Patent Information
- Application Number
- CN202411917141.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2026-06-26
AI Technical Summary
In large-scale chips, the inconsistency of local frequency division clock phases between modules leads to data interaction timing problems, affecting the real-time performance of data transmission. Existing technologies cannot effectively solve this problem through buffer buffers or SRAM isolation.
By dividing the local system clock within module A, a clock synchronization pulse indication signal Bus_en is generated. This signal is then detected in module B to trigger the local frequency division enable Div_en, ensuring that the frequency division clocks between modules are in phase. A frequency division counter and an anchor point synchronization mechanism are used to achieve clock synchronization between modules.
It achieves phase consistency of frequency division clocks between modules, simplifies timing convergence, reduces data processing latency, meets the requirements of clocks with the same or different frequencies, and improves data transmission efficiency.
Smart Images
Figure CN122284764A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of clock synchronization technology, specifically relating to a method and system for achieving phase consistency of local frequency division clocks between modules in a large-scale chip. Background Technology
[0002] In chip design, when the scale is small, the clock network structure is often simpler, the number of global clocks is also smaller, and timing convergence is easier. Clock design often uses a master clock divided to drive various modules and perform global control of the chip.
[0003] When the scale is large, in order to facilitate timing convergence issues in the backend, a "split-as-needed" approach is often adopted, that is, frequency division is performed locally where it is needed. If the frequency division circuits between modules are not related, the consistency of the frequency division clock phase between modules cannot be guaranteed. Therefore, for situations where different modules have data interaction, buffering or SRAM isolation is often used for control.
[0004] For systems that require two high-speed clock modules to be synchronized, if the phase consistency of the frequency divider clocks between modules cannot be guaranteed, continuing to use buffer or SRAM mechanisms when data is exchanged between modules will greatly affect the latency of data transmission, which is not conducive to the requirement of real-time data transmission. Summary of the Invention
[0005] Based on the above analysis, the present invention aims to disclose a method and system for achieving phase consistency of local frequency division clocks between modules in a large-scale chip, thereby solving the problem of phase consistency of local frequency division clocks between different modules.
[0006] This invention discloses a method for achieving local frequency division clock phase consistency between modules in a large-scale chip, comprising:
[0007] Modules A and B are Harden IPs in large-scale chips. The local system clocks clk1 and clk2 of modules A and B are clocks of the same source and frequency. The local frequency divider clocks of the two modules have data interaction.
[0008] Within module A, the local system clock clk1 is divided to obtain the local divided clock clk1_div of module A; and a clock synchronization pulse indicator signal Bus_en, which is synchronized with the clock period of the local divided clock clk1_div, is generated and output to module B.
[0009] The clock synchronization pulse indication signal Bus_en is an indication pulse sequence; the trailing edge of each indication pulse is aligned with the leading edge of the frequency division clock clk1_div;
[0010] The module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en, generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division, and outputs a local frequency division clock clk2_div that is in phase with the local frequency division clock clk1_div.
[0011] The enable front edge of the local frequency divider enable Div_en is aligned with the trailing edge of the first indicator pulse of the detected Bus_en.
[0012] Furthermore, including:
[0013] In module A, the clock synchronization pulse indication signal Bus_en and the local frequency division clock clk1_div are independent of each other;
[0014] When the local frequency divider clock clk1_div of module A is controlled to be turned off or powered off, the clock synchronization pulse indication signal Bus_en is still output to module B under the drive of the local system clock clk1;
[0015] In module B, the local frequency divider clock clk2_div of module B, triggered by the local frequency divider enable Div_en, is independent of the local frequency divider clock clk1_div of module A.
[0016] Furthermore, including:
[0017] In module A, the local frequency divider clock clk1_div is generated by the frequency divider counter counting cyclically. An indicator pulse is generated at the anchor point of the frequency divider counter counting cyclically, so that the trailing edge of the indicator pulse is aligned with the leading edge of the next frequency divider clock cycle of the local frequency divider clock clk1_div; the pulse width of the indicator pulse is one clock cycle of the local system clock clk1.
[0018] Furthermore, including:
[0019] After the local frequency divider clock enable signal of module B is valid, the received clock synchronization pulse indication signal Bus_en is detected. After the first indication pulse of the clock synchronization pulse indication signal Bus_en is detected within one clock cycle of the local system clock clk2, the local frequency divider enable Div_en is set and its level is maintained in the next clock cycle. At the same time, the frequency divider counter of module B starts counting when the div_en signal is valid. Based on the result of the frequency divider counter, the local frequency divider clock clk2_div is generated.
[0020] When controlling the clock shutdown of the local frequency divider clock clk2_div, after receiving the clock shutdown command, module B does not immediately stop the frequency divider clock clk2_div, but instead determines the Bus_en indicator pulse period in which the clock shutdown command is received; at the trailing edge of the pulse in the Bus_en indicator pulse period, the local frequency divider enable Div_en level is toggled, thus shutting down the frequency divider clock clk2_div.
[0021] Furthermore, including:
[0022] At the system level, module A is connected to module B. Data output by module A's local divided clock clk1_div is transmitted to module B, where it is received by module B's local divided clock clk2_div, forming a complete clock cycle path. The data is directly sampled and processed without the need for additional buffers or FIFOs.
[0023] The present invention also discloses a system for implementing the method for local frequency division clock phase consistency between modules in a large-scale chip as described above, comprising:
[0024] Module A and Module B;
[0025] The local system clocks of modules A and B are clocks of the same origin and frequency; the local frequency-divided clocks of the two modules have data exchange capabilities.
[0026] Module A outputs a clock synchronization pulse indication signal Bus_en to module B to make the local frequency division clocks of the two modules synchronized.
[0027] Within module A, the local system clock clk1 is divided to obtain the local divided clock clk1_div of module A; and a clock synchronization pulse indication signal Bus_en, which is synchronized with the clock period of the local divided clock clk1_div, is generated and output to module B; the clock synchronization pulse indication signal Bus_en is an indication pulse sequence; the trailing edge of each indication pulse is aligned with the leading edge of the divided clock clk1_div;
[0028] Module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en, generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division, and outputs a local frequency division clock clk2_div with the same phase as the local frequency division clock clk1_div; the leading edge of the local frequency division enable Div_en is aligned with the trailing edge of the first indication pulse of the detected Bus_en.
[0029] This invention also discloses another method for achieving local frequency division clock phase consistency between modules in a large-scale chip, including:
[0030] Modules A and B are Harden IPs in large-scale chips. The local system clocks clk1 and clk2 of modules A and B are set to clocks of the same source but different frequencies. The local frequency divider clocks of the two modules have data interaction.
[0031] Within module A, the local system clock clk1 is divided to obtain the local divided clock clk1_div of module A; and a clock synchronization pulse indicator signal Bus_en, which is synchronized with the clock period of the local divided clock clk1_div, is generated and output to module B.
[0032] The clock synchronization pulse indication signal Bus_en is an indication pulse sequence; the trailing edge of each indication pulse is aligned with the leading edge of the frequency division clock clk1_div; the pulse width of each indication pulse is at least one clock cycle of the lower frequency clock among the two local system clocks of module A and module B.
[0033] The module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en. After detecting the last valid level within the pulse width range of the indication pulse, it generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division and outputs a local frequency division clock clk2_div that is in phase with the local frequency division clock clk1_div.
[0034] The enable front edge of the local frequency divider enable Div_en is aligned with the trailing edge of the first indicator pulse of the detected Bus_en.
[0035] Furthermore, including:
[0036] In module A, the local frequency divider clock clk1_div is generated by the frequency divider counter counting cyclically. An indicator pulse is generated at the anchor point of the frequency divider counter counting cyclically, so that the trailing edge of the indicator pulse is aligned with the leading edge of the next frequency divider clock cycle of the local frequency divider clock clk1_div. The pulse width of the indicator pulse ensures that module B can detect the clock synchronization pulse indicator signal Bus_en on its own local system clock.
[0037] Furthermore, including:
[0038] When the frequencies of the local system clocks of module A and module B are integer multiples of N, and module B is a low-speed clock, the pulse width of the clock synchronization pulse indicator signal Bus_en is N local system clock cycles of module A; after module B detects the effective level of the indicator pulse through one local system clock cycle, it generates the local frequency division enable Div_en.
[0039] When the frequencies of the local system clocks of module A and module B are integer multiples of N, and module B is a high-speed clock, the pulse width of the clock synchronization pulse indicator signal Bus_en is one local system clock cycle of module A; after module B detects the valid level of the indicator pulse N times in N consecutive local system clock cycles, it generates the local frequency division enable Div_en.
[0040] The present invention also discloses a system for implementing the method of local frequency division clock phase consistency between modules in a large-scale chip as described above, comprising: module A and module B;
[0041] The local system clocks of modules A and B are clocks of the same origin but different frequencies; the local frequency-divided clocks of the two modules have data exchange capabilities.
[0042] Module A outputs a clock synchronization pulse indication signal Bus_en to module B to make the local frequency division clocks of the two modules synchronized.
[0043] Within module A, the local system clock clk1 is divided to obtain a local frequency-divided clock clk1_div; and a clock synchronization pulse indication signal Bus_en, synchronized with the clock cycle of the local frequency-divided clock clk1_div, is generated and output to module B; the clock synchronization pulse indication signal Bus_en is an indication pulse sequence; the trailing edge of each indication pulse is aligned with the leading edge of the frequency-divided clock clk1_div; the pulse width of each indication pulse is at least one clock cycle of the lower frequency clock of the two local system clocks of module A and module B;
[0044] Module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en. After detecting the last valid level within the pulse width range of the indication pulse, it generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division, and outputs a local frequency division clock clk2_div with the same phase as the local frequency division clock clk1_div. The leading edge of the local frequency division enable Div_en is aligned with the trailing edge of the first indication pulse of the detected Bus_en.
[0045] This invention can achieve one of the following beneficial effects:
[0046] The present invention discloses a method and system for achieving phase consistency of local frequency-division clocks between modules in a large-scale chip, which solves the timing problem when frequency-division clocks between various Harden IP modules interact during data transmission. During data transmission, data can be directly sampled and processed according to the principle of synchronous clocks. It can meet the requirements of dividing a source clock of the same frequency into a clock of the same or different frequencies, and it can also meet the requirements of dividing a source clock of different frequencies into a clock of the same or different frequencies.
[0047] This invention facilitates timing convergence, has a simple design structure, and reduces data processing latency. Attached Figure Description
[0048] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0049] Figure 1 This is a flowchart of a method for achieving local frequency division clock phase consistency between modules in a large-scale chip according to an embodiment of the present invention;
[0050] Figure 2 This is a schematic diagram of the local frequency division clock data interaction between the two modules in an embodiment of the present invention;
[0051] Figure 3 This is the timing sequence of the inter-module local frequency division clock phase consistency method in this embodiment of the invention;
[0052] Figure 4 This is a flowchart of another method for achieving local frequency division clock phase consistency between modules in a large-scale chip according to an embodiment of the present invention;
[0053] Figure 5 This is a waveform diagram illustrating an example of clk2 being twice the frequency of clk1 in an embodiment of the present invention.
[0054] Figure 6 This is a waveform diagram of an example of clk1 being twice the frequency of clk2 in an embodiment of the present invention. Detailed Implementation
[0055] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and, together with the embodiments of the present invention, serve to illustrate the principles of the present invention.
[0056] Example 1
[0057] One embodiment of the present invention discloses a method for achieving phase consistency of local frequency division clocks between modules in a large-scale chip.
[0058] In large-scale chips, to address timing issues during data exchange between Harden IP modules using frequency-divided clocks, it's necessary to constrain and shape the clock divider circuits between modules to ensure phase consistency. This allows for direct sampling and processing of data during transmission, following the principle of synchronous clocks. If the phase consistency of the frequency dividers cannot be guaranteed, the timing path during data exchange between Harden IPs will not be a complete clock cycle, making timing convergence difficult and increasing the workload for designers.
[0059] To ensure that the timing path between modules is a complete clock cycle, the method in this embodiment is as follows: Figure 1 As shown, it includes:
[0060] Step S1: Modules A and B are Harden IPs in a large-scale chip. The local system clocks clk1 and clk2 of modules A and B are clocks of the same origin and frequency. The local frequency-divided clocks of the two modules have data exchange capabilities. Figure 2 As shown;
[0061] Step S2: Divide the local system clock clk1 inside module A to obtain the local divided clock clk1_div of module A; and generate a clock synchronization pulse indicator signal Bus_en that is synchronized with the clock period of the local divided clock clk1_div and output it to module B.
[0062] The clock synchronization pulse indication signal Bus_en is an indication pulse sequence; the trailing edge of each indication pulse is aligned with the leading edge of the frequency division clock clk1_div;
[0063] Step S3: Module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en, generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division, and outputs a local frequency division clock clk2_div that is in phase with the local frequency division clock clk1_div;
[0064] The enable front edge of the local frequency divider enable Div_en is aligned with the trailing edge of the first indicator pulse of the detected Bus_en.
[0065] Specifically, in module A, the clock synchronization pulse indication signal Bus_en and the local frequency division clock clk1_div are independent of each other;
[0066] When the local frequency divider clock clk1_div of module A is controlled to be turned off or powered off, the clock synchronization pulse indication signal Bus_en is still output to module B under the drive of the local system clock clk1;
[0067] In module B, the local frequency divider clock clk2_div of module B, triggered by the local frequency divider enable Div_en, is independent of the local frequency divider clock clk1_div of module A.
[0068] In a preferred embodiment of this invention, in module A, the local frequency divider clock clk1_div is generated by the frequency divider counter counting cyclically. An indicator pulse is generated at the anchor point of the frequency divider counter counting cyclically, so that the trailing edge of the indicator pulse is aligned with the leading edge of the next frequency divider clock cycle of the local frequency divider clock clk1_div. The pulse width of the indicator pulse is one clock cycle of the local system clock clk1, which facilitates detection in module B.
[0069] In module A, a gate circuit is set between the local frequency divider clock clk1_div and the functional submodule module. When the gate circuit is turned on, the local frequency divider clock clk1_div can drive the functional submodule module to work. When the gate circuit is turned off, the local frequency divider clock clk1_div is disconnected from driving the functional submodule module, and the functional submodule does not work. The opening or closing of the gate circuit does not affect the generation and transmission of the synchronization pulse indication signal Bus_en.
[0070] In another preferred embodiment, in module A, the local frequency division clock clk1_div is generated by the frequency division counter counting cyclically, and the clock synchronization pulse indication signal Bus_en is generated by the indication counter counting cyclically; the two counters are independent; the indication counter generates the indication pulse at the anchor point of the frequency division counter counting cyclically;
[0071] Specifically, the counting clock of the indicator counter is the local system clock clk1 of module A, and the counting period is the division period of the local frequency divider clock clk1_div. The indicator counter starts counting at the leading edge of one division clock cycle of the local frequency divider clock clk1_div, and outputs an indicator pulse after each counting cycle. The trailing edge of the indicator pulse is aligned with the leading edge of the next division clock cycle of the local frequency divider clock clk1_div. The pulse width of the indicator pulse is one clock cycle of the local system clock clk1, which facilitates detection in module B.
[0072] Specifically, after the local frequency division clock enable signal of module B is valid, the received clock synchronization pulse indication signal Bus_en is detected; after the first indication pulse of the clock synchronization pulse indication signal Bus_en is detected within one clock cycle of the local system clock clk2, the local frequency division enable Div_en is set and its level is maintained in the next clock cycle; at the same time, the frequency division counter of module B starts counting when the div_en signal is valid.
[0073] Since the clock synchronization pulse indicator signal Bus_en indicates the anchor point of the frequency divider counter of module A, the anchor point of the frequency divider counter of module B triggered by Bus_en is kept consistent with the anchor point of the frequency divider counter of module A, thus establishing a completely synchronized phase relationship; based on the result of the frequency divider counter, a local frequency divider clock clk2_div is generated.
[0074] The frequency of the local frequency divider clock clk2_div can be the same as or different from the frequency of the local frequency divider clock clk1_div. The corresponding frequency division coefficient is used for frequency division according to the requirements.
[0075] When controlling the clock shutdown of the local frequency divider clock clk2_div, module B, upon receiving the clock shutdown command, does not immediately stop the frequency divider clock clk2_div. Instead, it determines the Bus_en indicator pulse period in which the clock shutdown command is received; at the trailing edge of the pulse in the Bus_en indicator pulse period, it toggles the level of the local frequency divider enable Div_en, thus shutting down the frequency divider clock clk2_div. This ensures the integrity of the frequency divider clock.
[0076] At the system level, module A is connected to module B. Data output by module A's local divided clock clk1_div is transmitted to module B, where it is received by module B's local divided clock clk2_div, forming a complete clock cycle path. The data is directly sampled and processed without the need for additional buffers or FIFOs.
[0077] Due to the large chip size and long physical distance, modules A and B in this embodiment adopt a "split-as-you-go" approach, with each module's local frequency divider clock being its internal clock. To achieve phase consistency of the frequency divider clocks between modules, a clock synchronization pulse indicator signal Bus_en is transmitted between modules A and B. The anchor point of the frequency divider counter's cyclic counting is consistent with the anchor point of the counter within module A, establishing a fully synchronized phase relationship. This ensures phase consistency of the local frequency divider clocks between different modules, and the clock synchronization pulse indicator signal Bus_en and the local frequency divider clock clk1_div in module A are independent of each other. That is, the independence of the local frequency divider clocks of modules A and B is achieved. When the local frequency divider clock clk1_div of module A is controlled to be turned off or powered off, it does not affect the generation of the local frequency divider clock of module B. There is no need to continuously maintain the generation of the local frequency divider clock clk1_div of module A in order to generate the local frequency divider clock of module B, thereby enhancing the chip's energy-saving design requirements.
[0078] like Figure 3The diagram shows a timing example of a local frequency division clock phase consistency method between modules. In the diagram, the local system clocks clk1 and clk2 of module A and module B are clocks of the same source and frequency. The clock synchronization pulse indicator signal Bus_en is active high. The local frequency division enable Div_en is active high. The falling edge of the Bus_en indicator pulse is aligned with the rising edge of the clock clk1_div pulse and the rising edge of the local frequency division enable Div_en. With the local frequency division enable Div_en enabled, the rising edge of the clock clk2_div pulse is aligned with the falling edge of the Bus_en indicator pulse and the rising edge of the clock clk1_div pulse, thus achieving a completely synchronized phase relationship between clock clk2_div and clk1_div.
[0079] This embodiment also provides a system for implementing local frequency division clock phase consistency between modules in a large-scale chip; the system includes: module A and module B;
[0080] The local system clocks of modules A and B are clocks of the same origin and frequency; the local frequency-divided clocks of the two modules have data exchange capabilities.
[0081] Module A outputs a clock synchronization pulse indication signal Bus_en to module B to make the local frequency division clocks of the two modules synchronized.
[0082] Within module A, the local system clock clk1 is divided to obtain the local divided clock clk1_div of module A; and a clock synchronization pulse indication signal Bus_en, which is synchronized with the clock period of the local divided clock clk1_div, is generated and output to module B; the clock synchronization pulse indication signal Bus_en is an indication pulse sequence; the trailing edge of each indication pulse is aligned with the leading edge of the divided clock clk1_div;
[0083] Module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en, generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division, and outputs a local frequency division clock clk2_div with the same phase as the local frequency division clock clk1_div; the leading edge of the local frequency division enable Div_en is aligned with the trailing edge of the first indication pulse of the detected Bus_en.
[0084] In summary, the method and system for local frequency division clock phase consistency between modules in a large-scale chip in this embodiment solves the timing problem when frequency division clocks between various Harden IP modules interact for data in a large-scale chip. During data transmission, the data can be directly sampled and processed according to the principle of synchronous clock.
[0085] Furthermore, it facilitates timing convergence, has a simple design structure, and reduces data processing latency.
[0086] Example 2
[0087] One embodiment of the present invention discloses a method for achieving local frequency division clock phase consistency between modules in a large-scale chip, such as... Figure 4 As shown, it includes:
[0088] Step S1: Module A and Module B are Harden IPs in a large-scale chip. The local system clocks clk1 and clk2 of Module A and Module B are set to clocks of the same source but different frequencies. The local frequency division clocks of the two modules have data interaction.
[0089] Step S2: Divide the local system clock clk1 inside module A to obtain the local divided clock clk1_div of module A; and generate a clock synchronization pulse indicator signal Bus_en that is synchronized with the clock period of the local divided clock clk1_div and output it to module B.
[0090] The clock synchronization pulse indication signal Bus_en is an indication pulse sequence; the trailing edge of each indication pulse is aligned with the leading edge of the frequency division clock clk1_div; the pulse width of each indication pulse is at least one clock cycle of the lower frequency clock among the two local system clocks of module A and module B.
[0091] Step S3: The module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en. After detecting the last valid level within the pulse width range of the indication pulse, it generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division and outputs a local frequency division clock clk2_div that is in phase with the local frequency division clock clk1_div.
[0092] The enable front edge of the local frequency divider enable Div_en is aligned with the trailing edge of the first indicator pulse of the detected Bus_en.
[0093] In a preferred embodiment of this invention, in module A, the local frequency divider clock clk1_div is generated by the cyclic counting of the frequency divider counter. An indicator pulse is generated at the anchor point of the cyclic counting of the frequency divider counter, so that the trailing edge of the indicator pulse is aligned with the leading edge of the next frequency divider clock cycle of the local frequency divider clock clk1_div. The pulse width of the indicator pulse ensures that module B can detect the clock synchronization pulse indicator signal Bus_en in its own local system clock.
[0094] In another preferred embodiment, in module A, the local frequency division clock clk1_div is generated by the frequency division counter counting cyclically, and the clock synchronization pulse indication signal Bus_en is generated by the indication counter counting cyclically; the two counters are independent; the indication counter generates the indication pulse at the anchor point of the frequency division counter counting cyclically;
[0095] The counting clock of the indicator counter is the local system clock clk1 of module A, and the counting period is the division period of the local frequency divider clock clk1_div. The indicator counter starts counting at the leading edge of one division clock cycle of the local frequency divider clock clk1_div, and outputs an indicator pulse after each counting cycle. The trailing edge of the indicator pulse is aligned with the leading edge of the next division clock cycle of the local frequency divider clock clk1_div. The pulse width of the indicator pulse ensures that module B can detect the clock synchronization pulse indicator signal Bus_en on its own local system clock.
[0096] Module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en, generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division, and outputs a local frequency division clock clk2_div with the same phase as the local frequency division clock clk1_div; the leading edge of the local frequency division enable Div_en is aligned with the trailing edge of the first indication pulse of the detected Bus_en.
[0097] Specifically, when the frequencies of the local system clocks of module A and module B are integer multiples of N, and module B is a low-speed clock, the pulse width of the clock synchronization pulse indicator signal Bus_en is N local system clock cycles of module A; after module B detects the effective level of the indicator pulse through one local system clock cycle, it generates the local frequency division enable Div_en.
[0098] When the frequencies of the local system clocks of module A and module B are integer multiples of N, and module B is a high-speed clock, the pulse width of the clock synchronization pulse indicator signal Bus_en is one local system clock cycle of module A; after module B detects the valid level of the indicator pulse N times in N consecutive local system clock cycles, it generates the local frequency division enable Div_en.
[0099] like Figure 5 The diagram shows the waveform when clk2 is twice the frequency of clk1. In the diagram, clk1 normally outputs a clock clk1_div with a 4-fold frequency division. Since the frequency of clk2 is twice that of clk1, the frequency divider will detect that bus_en is valid for 2 beats and then pull div_en high to achieve synchronization.
[0100] For other frequency multiplication cases, synchronization can be achieved simply by continuously detecting consecutive high levels of the multiplication factor in the high-frequency clock domain using the bus_en generated by the low-frequency clock.
[0101] like Figure 6 The diagram shows the waveform when clk1 is twice the frequency of clk2. In the diagram, clk1 normally outputs a clock clk1_div with an 8-fold frequency division. If the output bus_en signal is still one cycle, clk2 will not be able to detect it. Therefore, when dividing the clk1 clock, the bus_en signal is widened to two cycles of clk1 (which is one cycle of clk2). When the frequency divider of clk2 detects one cycle of the bus_en signal, it pulls div_en high, and the frequency division can proceed normally.
[0102] For other frequency multiplication cases, synchronization can be achieved simply by extending the bus_en generated during high-frequency clock division to one cycle of the low-frequency clock.
[0103] This embodiment also provides a system for implementing local frequency division clock phase consistency between modules in a large-scale chip; the system includes: module A and module B;
[0104] The local system clocks of modules A and B are clocks of the same origin but different frequencies; the local frequency-divided clocks of the two modules have data exchange capabilities.
[0105] Module A outputs a clock synchronization pulse indication signal Bus_en to module B to make the local frequency division clocks of the two modules synchronized.
[0106] Within module A, the local system clock clk1 is divided to obtain a local frequency-divided clock clk1_div; and a clock synchronization pulse indication signal Bus_en, synchronized with the clock cycle of the local frequency-divided clock clk1_div, is generated and output to module B; the clock synchronization pulse indication signal Bus_en is an indication pulse sequence; the trailing edge of each indication pulse is aligned with the leading edge of the frequency-divided clock clk1_div; the pulse width of each indication pulse is at least one clock cycle of the lower frequency clock of the two local system clocks of module A and module B;
[0107] Module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en. After detecting the last valid level within the pulse width range of the indication pulse, it generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division, and outputs a local frequency division clock clk2_div with the same phase as the local frequency division clock clk1_div. The leading edge of the local frequency division enable Div_en is aligned with the trailing edge of the first indication pulse of the detected Bus_en.
[0108] In summary, the local frequency division clock phase consistency method and system for large-scale chips in this embodiment solves the timing problem when frequency division clocks of various Harden IP modules interact during data transmission. During data transmission, data can be directly sampled and processed according to the principle of synchronous clocks. It can meet the requirements of dividing a source clock of the same frequency into a clock of the same or different frequency, and it can also meet the requirements of dividing a source clock of different frequency into a clock of the same or different frequency.
[0109] Furthermore, it facilitates timing convergence, has a simple design structure, and reduces data processing latency.
[0110] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for achieving phase consistency of local frequency-division clocks between modules in a large-scale chip, characterized in that, include: Modules A and B are Harden IPs in large-scale chips. The local system clocks clk1 and clk2 of modules A and B are clocks of the same source and frequency. The local frequency divider clocks of the two modules have data interaction. Within module A, the local system clock clk1 is divided to obtain the local divided clock clk1_div of module A; and a clock synchronization pulse indicator signal Bus_en, which is synchronized with the clock period of the local divided clock clk1_div, is generated and output to module B. The clock synchronization pulse indicator signal Bus_en is an indicator pulse sequence; The trailing edge of each indicator pulse is aligned with the leading edge of the frequency divider clock clk1_div; The module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en, generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division, and outputs a local frequency division clock clk2_div that is in phase with the local frequency division clock clk1_div. The enable front edge of the local frequency divider enable Div_en is aligned with the trailing edge of the first indicator pulse of the detected Bus_en.
2. The method for achieving local frequency division clock phase consistency among modules in a large-scale chip according to claim 1, characterized in that, include: In module A, the clock synchronization pulse indication signal Bus_en and the local frequency division clock clk1_div are independent of each other; When the local frequency divider clock clk1_div of module A is controlled to be turned off or powered off, the clock synchronization pulse indication signal Bus_en is still output to module B under the drive of the local system clock clk1; In module B, the local frequency divider clock clk2_div of module B, triggered by the local frequency divider enable Div_en, is independent of the local frequency divider clock clk1_div of module A.
3. The method for achieving local frequency division clock phase consistency among modules in a large-scale chip according to claim 2, characterized in that, include: In module A, the local frequency divider clock clk1_div is generated by the frequency divider counter counting cyclically. An indicator pulse is generated at the anchor point of the frequency divider counter counting cyclically, so that the trailing edge of the indicator pulse is aligned with the leading edge of the next frequency divider clock cycle of the local frequency divider clock clk1_div; the pulse width of the indicator pulse is one clock cycle of the local system clock clk1.
4. The method for achieving local frequency division clock phase consistency among modules in a large-scale chip according to claim 3, characterized in that, include: After the local frequency division clock enable signal of module B is valid, the received clock synchronization pulse indication signal Bus_en is detected. After detecting the first indication pulse of the clock synchronization pulse indication signal Bus_en within one clock cycle of the local system clock clk2, the local frequency divider enable Div_en is set and its level is held in the next clock cycle; at the same time, the frequency divider counter of module B starts counting when the div_en signal is valid; based on the result of the frequency divider counter, the local frequency divider clock clk2_div is generated. When controlling the clock shutdown of the local frequency divider clock clk2_div, after receiving the clock shutdown command, module B does not immediately stop the frequency divider clock clk2_div, but instead determines the Bus_en indicator pulse period in which the clock shutdown command is received; at the trailing edge of the pulse in the Bus_en indicator pulse period, the local frequency divider enable Div_en level is toggled, thus shutting down the frequency divider clock clk2_div.
5. The method for achieving local frequency division clock phase consistency among modules in a large-scale chip according to claim 4, characterized in that, include: At the system level, module A is connected to module B. Data output by module A's local divided clock clk1_div is transmitted to module B, where it is received by module B's local divided clock clk2_div, forming a complete clock cycle path. The data is directly sampled and processed without the need for additional buffers or FIFOs.
6. A system for implementing the method for local frequency division clock phase consistency among modules in a large-scale chip according to any one of claims 1-5, characterized in that, include: Module A and Module B; The local system clocks of modules A and B are clocks of the same origin and frequency; The local frequency divider clocks of the two modules have data exchange capabilities; Module A outputs a clock synchronization pulse indication signal Bus_en to module B to make the local frequency division clocks of the two modules synchronized. Within module A, the local system clock clk1 is divided to obtain the local divided clock clk1_div of module A; and a clock synchronization pulse indication signal Bus_en, which is synchronized with the clock period of the local divided clock clk1_div, is generated and output to module B; the clock synchronization pulse indication signal Bus_en is an indication pulse sequence. The trailing edge of each indicator pulse is aligned with the leading edge of the frequency divider clock clk1_div; Module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en, generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division, and outputs a local frequency division clock clk2_div with the same phase as the local frequency division clock clk1_div; the leading edge of the local frequency division enable Div_en is aligned with the trailing edge of the first indication pulse of the detected Bus_en.
7. A method for achieving phase consistency of local frequency-division clocks between modules in a large-scale chip, characterized in that, include: Modules A and B are Harden IPs in large-scale chips. The local system clocks clk1 and clk2 of modules A and B are set to clocks of the same source but different frequencies. The local frequency divider clocks of the two modules have data interaction. Within module A, the local system clock clk1 is divided to obtain the local divided clock clk1_div of module A; and a clock synchronization pulse indicator signal Bus_en, which is synchronized with the clock period of the local divided clock clk1_div, is generated and output to module B. The clock synchronization pulse indicator signal Bus_en is an indicator pulse sequence; The trailing edge of each indicator pulse is aligned with the leading edge of the frequency divider clock clk1_div; The pulse width of each indicator pulse is at least one clock cycle of the lower frequency clock among the two local system clocks of module A and module B. The module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en. After detecting the last valid level within the pulse width range of the indication pulse, it generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division and outputs a local frequency division clock clk2_div that is in phase with the local frequency division clock clk1_div. The enable front edge of the local frequency divider enable Div_en is aligned with the trailing edge of the first indicator pulse of the detected Bus_en.
8. The method for achieving local frequency division clock phase consistency among modules in a large-scale chip according to claim 7, characterized in that, include: In module A, the local frequency divider clock clk1_div is generated by the frequency divider counter counting cyclically. An indicator pulse is generated at the anchor point of the frequency divider counter counting cyclically, so that the trailing edge of the indicator pulse is aligned with the leading edge of the next frequency divider clock cycle of the local frequency divider clock clk1_div. The pulse width of the indicator pulse ensures that module B can detect the clock synchronization pulse indicator signal Bus_en on its own local system clock.
9. The method for achieving local frequency division clock phase consistency among modules in a large-scale chip according to claim 8, characterized in that, include: When the frequencies of the local system clocks of module A and module B are integer multiples of N, and module B is a low-speed clock, the pulse width of the clock synchronization pulse indicator signal Bus_en is N local system clock cycles of module A; after module B detects the effective level of the indicator pulse through one local system clock cycle, it generates the local frequency division enable Div_en. When the frequencies of the local system clocks of module A and module B are integer multiples of N, and module B is a high-speed clock, the pulse width of the clock synchronization pulse indicator signal Bus_en is one local system clock cycle of module A; after module B detects the valid level of the indicator pulse N times in N consecutive local system clock cycles, it generates the local frequency division enable Div_en.
10. A system for implementing the method for local frequency division clock phase consistency among modules in a large-scale chip according to any one of claims 7-9, characterized in that, include: Module A and Module B; The local system clocks of modules A and B are clocks of the same origin but different frequencies; the local frequency-divided clocks of the two modules have data exchange capabilities. Module A outputs a clock synchronization pulse indication signal Bus_en to module B to make the local frequency division clocks of the two modules synchronized. Within module A, the local system clock clk1 is divided to obtain the local divided clock clk1_div of module A; and a clock synchronization pulse indication signal Bus_en, which is synchronized with the clock period of the local divided clock clk1_div, is generated and output to module B; the clock synchronization pulse indication signal Bus_en is an indication pulse sequence. The trailing edge of each indicator pulse is aligned with the leading edge of the frequency divider clock clk1_div; The pulse width of each indicator pulse is at least one clock cycle of the lower frequency clock among the two local system clocks of module A and module B. Module B uses the local system clock clk2 to detect the clock synchronization pulse indication signal Bus_en. After detecting the last valid level within the pulse width range of the indication pulse, it generates a local frequency division enable Div_en to trigger the local system clock clk2 to perform frequency division, and outputs a local frequency division clock clk2_div with the same phase as the local frequency division clock clk1_div. The leading edge of the local frequency division enable Div_en is aligned with the trailing edge of the first indication pulse of the detected Bus_en.