A method and system for globally invalidating an address translation cache based on a generation flag

Abstract

The present application relates to address translation cache invalidation technology field, particularly to a kind of address translation cache global invalidation method and system based on generation mark.This application maintains current generation mark for each function mark, and records entry generation mark for each address mapping entry.When receiving global invalidation request, only flip the current generation mark of target function mark, without traversing any address mapping entry.Inquiry, compare entry generation mark with function mark current generation mark: if not equal, mark the entry as invalid and trigger re-request.Therefore, global invalidation is reduced from traversing N entries to flipping only one flag bit, time complexity is reduced from O (N) to O (1), eliminating performance jitter;Storage overhead is only a few KB, and hardware implementation is simple;Comparison operation can be parallel with query step, without increasing delay.

Description

Technical Field

[0001] This invention relates to the field of address translation cache invalidation technology, and in particular to a method and system for globally invalidating address translation caches based on generational flags. Background Technology

[0002] In PCIe (Peripheral Component Interconnect Express) devices (Endpoint devices, EPs) that support Address Translation Services (ATS), an Address Translation Cache (ATC) is typically integrated on the device side. This cache stores virtual-to-physical address mapping entries obtained from the Input / Output Memory Management Unit (IOMMU) of the Root Complex (RC). ATC reduces address translation latency when the device accesses host memory or performs peer-to-peer (P2P) communication, thus lowering the lookup load on the Root Complex.

[0003] The PCIe ATS protocol requires endpoint devices to respond to invalidation requests from the root complex, including partial address range invalidation and global address space invalidation. The global address space invalidation request requires clearing all ATC entries under a specified function ID. In traditional implementations, the hardware needs to traverse all ATC entries associated with that function ID, marking or deleting them one by one. When the ATC capacity is large (e.g., 16K entries or more), the traversal operation requires thousands of clock cycles. During this time, the device cannot properly process new address translation requests, resulting in severe performance jitter and a degraded quality of service.

[0004] In existing technologies, some solutions accelerate invalidation by adding a timestamp or version number to each ATC entry, but this usually requires additional comparison logic and storage overhead, and cannot complete all invalidation operations within a single cycle. Therefore, how to achieve O(1) time completion of global ATC invalidation without increasing hardware complexity is a pressing technical problem that needs to be solved. Summary of the Invention

[0005] To address one of the aforementioned technical problems, the present invention adopts the following technical solution: According to one aspect of the present invention, a method for globally invalidating an address translation cache based on generational flags is provided, applied in an endpoint device, comprising: Maintain a current generation flag for each functional identifier; a functional identifier is associated with at least one address mapping entry. Record an entry generation flag for each address mapping entry stored in the address translation cache; when the address mapping entry is created, the entry generation flag is set to the current generation flag of the function identifier associated with the address mapping entry; When a global invalidation request for a target function identifier is received, only the current generation flag of the target function identifier is flipped to a different value, without traversing any address mapping entries in the address translation cache. When querying address translation, if an address mapping entry matching the input virtual address is found in the address translation cache, the entry generation flag of the address mapping entry is compared with the current generation flag of the function identifier to which the input virtual address belongs. When the generational flag of an address mapping entry is not equal to the current generational flag of the function identifier to which the input virtual address belongs, the address mapping entry is marked as invalid or ignored, and a new address translation request is triggered to the root complex.

[0006] According to a second aspect of the present invention, a generational flag-based address translation cache global invalidation system is provided, applied in an endpoint device, comprising: The generational identifier maintenance module is used to maintain a current generational identifier for each functional identifier; each functional identifier is associated with at least one address mapping entry. The generational flag recording module is used to record an entry generational flag for each address mapping entry stored in the address translation cache; when the address mapping entry is created, the entry generational flag is set to the current generational flag of the function identifier associated with the address mapping entry; The generation flag flipping module is used to flip the current generation flag of the target function identifier to a different value only when a global invalidation request for the target function identifier is received, without traversing any address mapping entries in the address translation cache. The generational flag comparison module is used to compare the generational flag of the address mapping entry with the current generational flag of the function identifier to which the input virtual address belongs when querying address translation. The address mapping invalidation module is used to mark an address mapping entry as invalid or ignore the address mapping entry when the entry generation flag of the address mapping entry is not equal to the current generation flag of the function identifier to which the input virtual address belongs, and to trigger a new request for address translation to the root complex.

[0007] This invention has at least one of the following beneficial effects: The time complexity of global invalidation is reduced from O(N) to O(1), completely eliminating performance jitter. This invention specifies that "a current generation flag is maintained for each function identifier" and "an entry generation flag is recorded for each address mapping entry, which is set to the current generation flag of the function identifier when the entry is created." Based on this, when a global invalidation request is received, this invention "only flips the current generation flag of the target function identifier to a different value, without traversing any address mapping entries in the address translation cache." Therefore, the global invalidation operation only involves flipping a single-bit register, and its execution time is independent of the number of address mapping entries stored in the ATC (does not increase with N), thus the time complexity is O(1). In contrast, existing technologies require traversing all associated entries and deleting them one by one, with a time complexity of O(N). When the ATC capacity is large (e.g., 16K entries), the traversal can take thousands of cycles. This invention eliminates the performance jitter problem caused by the traversal operation, which prevents the device from responding to new requests for extended periods.

[0008] This invention achieves global invalidation with extremely low hardware overhead. The "current generation flag" maintained in this invention is a flag for each function identifier, typically designed as a single bit; the "entry generation flag" adds a flag bit to each address mapping entry. Taking support for 8K function identifiers and 16K ATC entries as an example, the total storage for the current generation flag is 8K bits (approximately 1KB), and the total storage for the entry generation flag is 16K bits (approximately 2KB), totaling approximately 3KB. In this invention, the global invalidation operation only flips the current generation flag, requiring no additional traversal logic, queues, or complex state machines. Therefore, this invention achieves a fast invalidation effect that requires significant hardware resources in existing technologies with extremely low memory and logic gate overhead.

[0009] While ensuring cache consistency, this invention does not increase the critical path latency of the query path. The invention specifies that "when querying address translation, if an address mapping entry matching the input virtual address is found in the address translation cache, the entry generation flag of that address mapping entry is compared with the current generation flag of the function identifier to which the input virtual address belongs; if they are not equal, the address mapping entry is marked as invalid or ignored, and a re-request for address translation from the root complex is triggered." This comparison operation is only a one-bit comparison, which can be executed in parallel or piped with existing query steps such as hash lookup and address matching, without extending the critical path latency of the query path. Simultaneously, when the generation flags are equal, the entry is considered valid, ensuring consistency; when they are not equal, the entry is automatically considered invalid and a re-request is triggered, ensuring that invalidated mappings are not returned. Therefore, this invention achieves fast global invalidation while completely maintaining cache consistency, and has almost no impact on normal query performance. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of a method for globally invalidating an address translation cache based on generational flags, provided as an embodiment of the present invention.

[0012] Figure 2 This is a flowchart illustrating the address translation cache storage and query method for multiple fixed granularity tables provided in an embodiment of the present invention.

[0013] Figure 3 This is a structural block diagram of a partial address invalidation system for an address translation cache provided in an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] As one possible embodiment of the present invention, such as Figure 1 As shown, a method for globally invalidating address translation caches based on generational flags is provided, applied in endpoint devices, including: S100: Maintain a current generation flag for each function identifier, and associate a function identifier with at least one address mapping entry.

[0016] This step provides the foundational data structure support for the entire generational flag mechanism. A function identifier is an identifier in the PCIe protocol used to uniquely identify a device's function. One function identifier can be associated with multiple address mapping entries. For example, multiple DMA requests under the same function identifier may access different virtual address ranges, and the address mapping entries corresponding to these address ranges all belong to that function identifier. This one-to-many association allows subsequent global invalidation operations to invalidate all address mapping entries under that function identifier at once, thereby significantly improving invalidation efficiency.

[0017] Specifically, the hardware (i.e., the PCIe endpoint device) configures a single-bit register `current_gen[func_id]` for each function identifier to store the current generation flag. This single-bit register is initially set to 0. When a global invalidation request is received, the toggle operation involves inverting this single bit, either changing 0 to 1 or 1 to 0. Using a single-bit register offers advantages such as low storage overhead (only 1 bit is needed per function identifier) ​​and simple toggle operation (completed within one clock cycle).

[0018] S200: Record an entry generation flag for each address mapping entry stored in the address translation cache. When the address mapping entry is created, the entry generation flag is set to the current generation flag of the function identifier associated with that address mapping entry.

[0019] This step establishes a generational association between address mapping entries and their respective function identifiers. When an entry is created, it records the generational value of the function identifier at the time of creation. This association allows subsequent queries to quickly determine whether an entry was created after the most recent global invalidation operation by comparing the entry's generational flag with the generational flag of the current function identifier, thus determining whether the entry is still valid.

[0020] Specifically, each address mapping entry adds a bit field `entry_gen` to record the current generation flag value of the function identifier to which the entry belongs when it is created. When creating a new address mapping entry, the `current_gen[func_id]` of the function identifier associated with the new address mapping entry is read, and the current generation flag is written to the `entry_gen` field of the new address mapping entry. For example, if `current_gen[1] = 0`, then the `entry_gen` of the newly created address mapping entry is also set to 0.

[0021] S300: When a global invalidation request for a target function identifier is received, the current generation flag of the target function identifier is flipped to a different value only, without traversing any address mapping entries in the address translation cache.

[0022] This step is the core of the generational flag mechanism. Traditional global invalidation requires traversing all address mapping entries associated with the function identifier and marking them as invalid one by one. When the address translation cache capacity is large (such as 16K entries), the traversal operation requires thousands of clock cycles, which seriously affects performance. This step achieves true O(1) time complexity global invalidation by only flipping the generational flag of the function identifier.

[0023] Specifically, when a full address space Invalidate message is received for a target function identifier, the hardware only needs to perform a single-cycle operation: inverting the current_gen[func_id] corresponding to the target function identifier. This operation does not require accessing or modifying any address mapping entries in the address translation cache, so the execution time is independent of the number of address mapping entries. For example, the current_gen[1] = 0 at present becomes current_gen[1] = 1 after inversion.

[0024] S400: When querying address translation, if an address mapping entry matching the input virtual address is found in the address translation cache, the entry generation flag of the address mapping entry is compared with the current generation flag of the function identifier to which the input virtual address belongs.

[0025] This step integrates generational flag checking into the address translation query process. By adding a generational flag comparison operation after a query hit, expired address mapping entries can be automatically identified and filtered without significant hardware overhead. This comparison operation can be executed in parallel or piped with existing hash lookup and address matching steps, without increasing critical latency in the query path.

[0026] Specifically, when a DMA request arrives carrying a virtual address (VA), a lookup is performed in the address translation cache. If an address mapping entry is matched, the following comparison operation is performed: the entry_gen field of that address mapping entry is compared with the current_gen[func_id] of the function identifier to which the DMA request belongs. This comparison operation involves only a one-bit XOR operation; for example, if entry_gen = 0 and current_gen[func_id] = 1, the comparison result will be unequal.

[0027] S500: When the generational flag of an address mapping entry is not equal to the current generational flag of the function identifier to which the input virtual address belongs, mark the address mapping entry as invalid or ignore the address mapping entry, and trigger a new request for address translation to the root complex.

[0028] Specifically, when the comparison results are not equal, it indicates that the address mapping entry has expired and is considered a cache miss. The hardware no longer uses the entry and instead sends an ATS Request to the root complex to re-acquire the address mapping relationship.

[0029] This step defines the handling logic for generational flag mismatches. When the comparison results are unequal, it indicates that the generation of the address mapping entry has expired, possibly due to an older entry created before the most recent global invalidation. By marking such entries as invalid or ignoring them and triggering a re-request, the correctness and consistency of address translation results can be ensured, avoiding the use of expired address mapping relationships.

[0030] After comparing the entry generation flag of the address mapping entry with the current generation flag of the function identifier to which the input virtual address belongs, the method further includes: S510: When the generational flag of the address mapping entry is equal to the current generational flag of the function identifier to which the input virtual address belongs, the address mapping entry is determined to be hit.

[0031] Specifically, when the comparison results are equal, it means that the address mapping entry is a valid entry and its stored address mapping relationship has not been invalidated. For example, if entry_gen = 1 and current_gen[func_id] = 1, then the comparison results are equal, and the entry is determined to be a match.

[0032] This step defines the normal processing flow for intergenerational flag matching. When the comparison results are equal, it indicates that the address mapping entry is a valid entry, and its stored address mapping relationship has not been invalidated. At this time, the entry can continue to be used for address translation without triggering a re-request, thus maintaining the high hit rate and low latency characteristics of the address translation cache.

[0033] S520: The final physical address is obtained by concatenating the physical address base address stored in the address mapping entry with the low-order offset of the input virtual address.

[0034] This step completes the final step of address translation: physical address generation. The physical address stored in the address translation cache is the base address, while the input virtual address contains low-order offsets; the two are concatenated to obtain the complete physical address. This design allows the address translation cache to store only the high-order address information, without needing to store the complete address mapping, thus saving storage space and improving lookup efficiency.

[0035] Specifically, the physical address stored in the address mapping entry is the physical address base address (PA_base), and its number of bits is determined by the address mapping entry size (SIZE). The final physical address PA is calculated as follows: PA = PA_base + (VA&(SIZE - 1)), which is the physical address base address plus the low-order offset of the input virtual address. Here, & is the bitwise AND operator, which performs a bitwise AND operation on the binary bits of two numbers, resulting in 1 only when both bits are 1. The number of bits in the low-order offset is determined by the address mapping entry size.

[0036] For example, when the SIZE is 4KB, the offset is 12 bits (2). 12 = 4096), when SIZE is 2MB, the offset is 21 bits (2 21 =2097152). Taking a 2MB entry as an example, assuming PA_base = 0x10000000000 (high 43 bits) and VA = 0x18000000000 (including 6KB offset 0x1800), then the final PA = 0x10000001800.

[0037] This embodiment reduces the time complexity of global invalidation from O(N) to O(1) through a generational flag mechanism, completely eliminating performance jitter. The global invalidation operation involves only flipping a single-bit register, and its execution time is independent of the number of address mapping entries stored in the address translation cache. Furthermore, this embodiment achieves global invalidation with extremely low hardware overhead; each function flag requires only 1 bit of storage, and each address mapping entry requires only an additional 1 bit of storage. In addition, this mechanism has almost no impact on normal query performance because the generational flag comparison operation involves only a one-bit comparison and can be executed in parallel with the original query steps.

[0038] The generational flag mechanism provided in the first embodiment above perfectly solves the global invalidation problem of the entire function address space in the PCIe ATS protocol with O(1) time and extremely low hardware overhead. However, in actual PCIe devices, the Address Translation Cache (ATC) faces another fundamental challenge: in the PCIe ATS protocol, the address translation response returned by the root complex to the endpoint device includes the virtual address, physical address, and address mapping entry size (SIZE). This SIZE represents the size of the address space covered by the address mapping entry, which can be a variable value such as 4KB, 2MB, or 1GB. If the address translation cache uses only a single hash table to store these address mapping entries, the hardware will not be able to determine which bits of the virtual address to use to calculate the hash key because different entries have different SIZEs: if the SIZE is 4KB, the lower 12 bits of the virtual address need to be used; if the SIZE is 2MB, the lower 21 bits of the virtual address need to be used. Furthermore, during a query, the hardware also cannot determine which bits of the virtual address to use for matching. Therefore, a storage and retrieval mechanism that can adapt to address mapping entries of different sizes is needed.

[0039] As another possible embodiment of the present invention, such as Figure 2 As shown, a method for storing and retrieving address translation caches using multiple fixed-granularity tables is provided to solve the above problems. Specifically, the address translation cache consists of multiple address translation tables, each configured to store address mapping entries of a fixed size, with the size of address mapping entries differing between different address translation tables.

[0040] This step introduces a structure design using multiple fixed-granularity tables. Each table specifically stores an address mapping entry of a fixed size, allowing the system to determine which bits of the virtual address to use as the hash key based on the size during writes and to determine which bits of the virtual address to compare during queries. This design fundamentally solves the hash calculation problem caused by variable sizes.

[0041] Specifically, the multiple address translation tables include four tables: a 4KB address translation table, a 64KB address translation table, a 2MB address translation table, and a 1GB address translation table. Among them: 4KB Address Translation Table: Used to store address mapping entries of size 4KB, with the hash key being the lower 12 bits of the input virtual address. 64KB Address Translation Table: Used to store address mapping entries of size 64KB, with the hash key being the lower 16 bits of the input virtual address. 2MB Address Translation Table: Used to store address mapping entries of size 2MB, with the hash key being the lower 21 bits of the input virtual address. 1GB Address Translation Table: Used to store address mapping entries of size 1GB, with the hash key being the lower 30 bits of the input virtual address. The default address mapping entry size is configurable to adapt to the address mapping granularity requirements of different server architectures (Intel, AMD, ARM, etc.).

[0042] S600: When an address translation response is received from the root complex, the virtual address, physical address, and address mapping entry size are resolved.

[0043] This step marks the entry point for writing address mapping entries to the address translation cache. By parsing the address translation response, the three core elements of the address mapping entry are obtained: Virtual Address (VA), Physical Address (PA), and Address Mapping Entry Size (SIZE). These three elements collectively determine which table the entry should be stored in, how the hash key is calculated during storage, and how matching and verification are performed during queries.

[0044] Specifically, the virtual address (VA) and physical address (PA) contained in the Address Translation Response (ATS Response) are both starting addresses (base addresses). For example, when SIZE = 2MB, the starting address of VA is a 2MB aligned address, that is, the lower 21 bits of VA are 0; the starting address of PA is also a 2MB aligned address.

[0045] Taking the address translation response VA = 0x18000000000, PA = 0x200000000000, SIZE = 2MB as an example, the lower 21 bits of VA are 0 (2MB aligned), and the lower 21 bits of PA are also 0.

[0046] S610: If the size of the address mapping entry is equal to the size of the preset address mapping entry in an address translation table, then the address mapping entry is directly stored in the address translation table.

[0047] This step handles cases where the SIZE perfectly matches the preset granularity. When the size of an address mapping entry is equal to the preset SIZE of a table, the entry can be directly stored in the corresponding table without any truncation or splitting operations. This direct storage method simplifies the processing flow and reduces storage overhead.

[0048] Specifically, taking SIZE = 2MB as an example, when an address mapping entry is stored in a 2MB address translation table, the stored virtual address hash key is the portion above the lower 21 bits of VA, and the stored physical address base address is the portion above the lower 21 bits of PA. For example, for VA = 0x18000000000 and PA = 0x20000000000, when stored in the 2MB table, the stored VA hash key is 0xC0000 (the higher 43 bits of VA, i.e., 0x18000000000>>21), and the stored PA base address is 0x100000 (the higher 43 bits of PA, i.e., 0x200000000000>>21). >> is the right shift operator, which shifts the binary representation of the virtual address VA 21 bits to the right, effectively removing the lower 21 bits.

[0049] S620: If the size S of the parsed address mapping entry is not equal to the preset address mapping entry size of any address translation table, then select the maximum value T of all preset address mapping entry sizes that is less than or equal to S, and split the original address mapping entry corresponding to S into multiple sub-address mapping entries of size T.

[0050] This step handles cases where the SIZE does not match the preset granularity. The SIZE of address mapping entries in the PCIe protocol can be any value (e.g., 4MB, 8MB), while the preset granularity of the address translation cache is finite. To ensure correct storage and retrieval, larger address mapping entries need to be split into multiple sub-entries conforming to the preset granularity. This backward-compatible splitting strategy ensures that all SIZE address mapping entries can be correctly stored and retrieved.

[0051] Specifically, taking SIZE = 4MB as an example. Preset address mapping entry sizes include 4KB, 64KB, 2MB, and 1GB. Iterating through the preset values, the largest value less than or equal to 4MB is found to be 2MB, therefore T = 2MB is chosen. Since 4MB = 2 × 2MB, the original 4MB address mapping entry is split into two sub-address mapping entries of size 2MB.

[0052] S630: Based on the input virtual address corresponding to the currently received address translation response, determine which sub-address mapping entry the input virtual address falls within, and store the sub-address mapping entry into an address translation table with a preset address mapping entry size of T.

[0053] This step determines which sub-address mapping entry the input virtual address should correspond to. Since the original address mapping entry is split into multiple sub-entries, each covering a different address range, it's necessary to determine which sub-entry's range the input virtual address falls into. Only sub-entries matching the input virtual address need to be stored in the address translation cache so that subsequent queries can find them.

[0054] Specifically, continuing with the 4MB entry example above. Assume the original VA = 0x10000000000, the original PA = 0x20000000000, and SIZE = 4MB. This 4MB range covers [0x10000000000, 0x10000400000]. Since each entry in the 2MB granularity address translation table covers 2MB of address space, it is necessary to determine which 2MB sub-entry the input virtual address falls into.

[0055] The calculation method is as follows: Sub-entry index = floor((VA - original VA starting address) / T), where floor() rounds down. For example, if VA = 0x10000200000 (located in the second 2MB interval of the original 4MB range), then the sub-entry index = floor((0x10000200000 - 0x10000000000) / 0x00200000) = floor(0x200000 / 0x200000) = 1.

[0056] S640: The virtual address base address of this sub-address mapping entry is equal to the original virtual address base address plus an offset, which is an integer multiple of T, down-aligned to the low-order part of the input virtual address. The physical address base address of this sub-address mapping entry is equal to the original physical address base address plus the same offset.

[0057] This step is the core operation of truncation storage. By calculating the VA base address and PA base address of the sub-entry, entries that originally covered a large address range are converted into sub-entries covering an address range of size T. The downward alignment offset ensures that the starting address of the sub-entry conforms to the alignment requirement of T, thus enabling it to be correctly stored in the address translation table of the corresponding granularity.

[0058] Specifically, let's take SIZE = 4MB and VA = 0x10000200000 as an example.

[0059] Offset calculation: Offset = (VA & (T - 1)) = 0x10000200000 & 0x001FFFFF = 0x00200000 (down-aligned to the 2MB boundary).

[0060] Sub-entry VA base address = Original VA base address + Offset = 0x10000000000 + 0x00200000 = 0x10000200000.

[0061] When storing the VA base address of a sub-entry into a 2MB table, its high 43 bits are stored as a hash key: 0x10000200000>>21= 0x80010.

[0062] Similarly, the sub-entry PA base address is calculated as follows: Sub-entry PA base address = Original PA base address + Offset = 0x20000000000 + 0x00200000 = 0x20000200000.

[0063] The high 43 bits are used for storage: 0x20000200000>>21 = 0x100001. The effective bits of the stored sub-address mapping entry are 2MB, and the entry can be marked as "truncated from a larger SIZE" to facilitate overlap judgment during subsequent queries.

[0064] This embodiment achieves efficient storage and retrieval of address mapping entries of different sizes through a structure design of multiple fixed-granularity tables. Each table uses a fixed-length hash key, simplifying hardware design. Meanwhile, the backward-compatible truncated storage strategy ensures that address mapping entries of any size can be processed correctly. Furthermore, the configurable preset address mapping entry size allows this solution to flexibly adapt to the address mapping granularity requirements of different server architectures.

[0065] The methods disclosed in the foregoing embodiments solve the storage problem of address mapping entries of different sizes, while the method disclosed in this embodiment solves the query problem of these entries. Since multiple tables of different granularities exist simultaneously in the address translation cache, and the same virtual address may have matching entries in tables of different granularities, a mechanism is needed that can correctly and efficiently search for matching address mapping entries from multiple tables.

[0066] S700: When querying address translation, parallel hash lookups are performed in multiple address translation tables simultaneously based on the input virtual address to find a matching address mapping entry.

[0067] This step introduces the core idea of ​​parallel hash lookup. Since the address translation cache contains multiple tables of different granularities, and the virtual address carried by the query request may match an entry in any of these tables, a lookup needs to be performed simultaneously in all tables. Parallel lookup fully utilizes hardware parallelism, completing multi-table queries without increasing critical path latency.

[0068] Specifically, when a DMA request arrives carrying the virtual address VA, the hardware simultaneously performs lookups in the 4KB, 64KB, 2MB, and 1GB address translation tables. Parallel lookups can fully utilize hardware parallelism, requiring only the addition of comparator arrays and hash calculation units, without increasing the critical path latency of the lookup path.

[0069] S701: For each address translation table, determine the high-order bits used for hash calculation in the input virtual address based on the preset address mapping entry size of the address translation table.

[0070] This step defines the hash key extraction rules for each table during lookups. Each table has a different preset granularity, therefore different numbers of bits in the virtual address are needed as the hash key. This rule is consistent with the rules during storage, ensuring that entries stored in a specific table are retrieved during queries.

[0071] Specifically, during a hash lookup, the input virtual address VA is divided into a high-order part and a low-order offset part: 4KB table: Uses VA's [63:52] (high 12 bits) as the hash key.

[0072] 64KB table: Uses [63:48] (high 16 bits) of VA as the hash key. Here, [63:48] is a bit field slice, representing the 63rd to 48th bits of the virtual address VA (a total of 16 bits).

[0073] 2MB table: Uses VA[63:43] (high 21 bits) as hash key.

[0074] 1GB table: Uses VA's [63:34] (high 30 bits) as the hash key.

[0075] For example, for VA = 0x18000000000: The hash key used by the 4KB table is VA>>52 = 0x18 The hash key used by the 64KB table is VA>>48 = 0x180. The hash key used by the 2MB table is VA>>43 = 0xC00 The hash key used by the 1GB table is VA>>34 = 0x1800. S702: Input the high-order bits into the hash function to obtain the index in the table, and read the address mapping entry at that index position.

[0076] This step converts the hash key into its actual storage location in the address translation table. A hash function is used to operate on the hash key, generating an index within the table, which allows the corresponding address mapping entry to be retrieved. The choice of hash function should ensure even distribution to reduce hash collisions.

[0077] Specifically, the hash function operates on the input hash key to generate an index within the table. For example, for a 2MB table, the hash function performs a modulo operation on VA[63:43] to obtain an index value in the range of 0 to (table capacity - 1). The corresponding address mapping entry stored in the address translation table is then read based on this index. For example, if the 2MB table capacity is 1024 entries and the hash key is 0xC00, then the index = 0xC00 mod 1024 = 768.

[0078] S703: Compare whether the base address of the virtual address stored in the address mapping entry is equal to the high-order part of the input virtual address.

[0079] This step is the core verification process for address mapping entry matching. By comparing the corresponding bit portions of the stored virtual address base address with the queried virtual address, it can be determined whether the entry matches the query request. This comparison process eliminates false hits caused by hash collisions, ensuring that only entries that actually store the target address mapping relationship are considered a match.

[0080] Specifically, after retrieving an address mapping entry from an address translation table, it is necessary to verify whether the entry matches the query request: Step 1: Compare the virtual address base address. Compare the stored virtual address base address (the bit portion corresponding to the table) with the corresponding bit portion of the VA being queried. For example, when querying a 2MB table, the stored VA base address is 0xC00, and the VA[63:43] being queried is equal to 0xC00. If they are equal, the verification passes.

[0081] Step 2: Compare the physical address base address. The stored physical address base address is matched and verified against the higher bits of the expected PA in the ATS Response.

[0082] Step 3: Verify the valid bit range. Check if the query VA is within the valid address range of the stored entry (i.e., VA_offset). <SIZE)。

[0083] If all the above comparisons pass, the address mapping entry is a match; if any comparison fails, the entry is a mismatch, and the process continues to check other tables.

[0084] Parallel table lookup ensures that address mapping entries of any size can be found correctly: If the original size of the address mapping entry is 4KB, then only the 4KB table will be hit. If the original size of the address mapping entry is 2MB, then only the 2MB table will be hit. If the original size of the address mapping entry is 4MB (truncated and stored in a 2MB table), then when the VA of a query falls within the corresponding 2MB sub-range, the 2MB table will be hit. This embodiment achieves efficient querying of multiple fixed-granularity tables through a parallel hash lookup mechanism. Parallel lookup fully utilizes hardware parallelism, allowing queries on multiple tables to be performed simultaneously without increasing query latency. Furthermore, the hash key extraction rules are consistent with the storage rules, ensuring search accuracy. Truncated entries can also be correctly matched during queries, guaranteeing complete coordination between the storage and query mechanisms.

[0085] The following examples, with specific numerical examples, illustrate the complete collaborative workflow of the generational marker mechanism and the multi-fixed granularity table structure disclosed in the above embodiments: Initial state: current_gen[1] = 0 for function identifier 1, and all address translation tables are initially empty.

[0086] Received address translation response for SIZE = 4KB Address translation response: VA = 0x1000, PA = 0x2000, SIZE = 4KB SIZE equals the default value of 4KB, stored in a 4KB table. Storage: VA_key = 0x0 (VA>>12), PA_base = 0x0 (PA>>12), entry_gen = current_gen[1] = 0 Received address translation response for SIZE = 4MB (truncated storage) Address translation response: VA = 0x10000000000, PA = 0x20000000000, SIZE = 4MB 4MB does not match any preset value. Select T = 2MB (the maximum preset value is less than 4MB). The 4MB entry was truncated into two 2MB sub-entries and stored in a 2MB table. Sub-entry 1: VA_base = 0x10000000000 (stored as 0x8000000, i.e., 0x10000000000>>21), PA_base = 0x10000000000 (stored as 0x8000000, i.e., 0x200000000000>>21) Sub-entry 2: VA_base = 0x10000200000 (stored as 0x8001000), PA_base = 0x20000200000 Received global invalidation for function identifier 1 Flip current_gen[1]: 0 → 1 No need to access any address mapping entries Query the above 4KB entries VA = 0x1000, search in the 4KB table, hit. Comparing entry_gen(0) with current_gen1, they are not equal. If the hit is considered a failure, an ATS Request will be sent. Query the above 4MB entries (range of sub-entry 1) VA = 0x1000010000, parallel search in a 2MB table Hit at sub-item 1 Comparing entry_gen(0) with current_gen1, they are not equal. If the hit is considered a failure, an ATS Request will be sent. Received new address translation response, create entry Read current_gen[1] = 1 The new entry `entry_gen = 1` (consistent with the current generation). Subsequent queries for this entry returned a normal match.

[0087] As another possible embodiment of the present invention, such as Figure 3 As shown, a generational flag-based address translation cache global invalidation system is also provided, applied in endpoint devices, including: The generational flag maintenance module is used to maintain a current generational flag for each functional identifier. Each functional identifier is associated with at least one address mapping entry.

[0088] The generational flag recording module is used to record an entry generational flag for each address mapping entry stored in the address translation cache. When the address mapping entry is created, the entry generational flag is set to the current generational flag of the function identifier associated with that address mapping entry.

[0089] The generation flag flipping module is used to flip the current generation flag of the target function identifier to a different value only when a global invalidation request for the target function identifier is received, without traversing any address mapping entries in the address translation cache.

[0090] The generational flag comparison module is used to compare the generational flag of the address mapping entry with the current generational flag of the function identifier to which the input virtual address belongs when querying address translation. If an address mapping entry matching the input virtual address is found in the address translation cache, the generational flag of the address mapping entry is compared with the current generational flag of the function identifier to which the input virtual address belongs.

[0091] The address mapping invalidation module is used to mark an address mapping entry as invalid or ignore the address mapping entry when the entry generation flag of the address mapping entry is not equal to the current generation flag of the function identifier to which the input virtual address belongs, and to trigger a new request for address translation to the root complex.

[0092] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0093] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0094] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0095] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely in hardware, entirely in software (including firmware, microcode, etc.), or in a combination of hardware and software, collectively referred to herein as “circuit,” “module,” or “system.”

[0096] An electronic device according to this embodiment of the invention. The electronic device is merely an example and should not be construed as limiting the functionality or scope of the embodiments of the invention.

[0097] Electronic devices are manifested in the form of general-purpose computing devices. Components of an electronic device may include, but are not limited to: at least one processor, at least one memory, and buses connecting different system components (including memory and processor).

[0098] The memory stores program code that can be executed by a processor, causing the processor to perform the steps described in the "Exemplary Methods" section above, according to various exemplary embodiments of the present invention.

[0099] The storage may include readable media in the form of volatile storage, such as random access memory (RAM) and / or cache memory, and may further include read-only memory (ROM).

[0100] The storage may also include programs / utilities having a set (at least one) of program modules, including but not limited to: an operating system, one or more applications, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0101] A bus can represent one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus that uses any of the various bus architectures.

[0102] The electronic device can also communicate with one or more external devices (e.g., keyboards, pointing devices, Bluetooth devices, etc.), one or more devices that enable a user to interact with the electronic device, and / or any device that enables the electronic device to communicate with one or more other computing devices (e.g., routers, modems, etc.). This communication can be performed via input / output (I / O) interfaces. Furthermore, the electronic device can communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter. The network adapter communicates with other modules of the electronic device via a bus. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with the electronic device, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0103] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the present invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the present invention described in the "Exemplary Methods" section above.

[0104] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0105] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0106] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0107] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0108] Furthermore, the accompanying drawings are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention and are not intended to be limiting. It is readily understood that the processes shown in the above drawings do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0109] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0110] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for globally invalidating address translation caches based on generational flags, applied in endpoint devices, characterized in that, include: Maintain a current generational flag for each functional identifier; A function identifier is associated with at least one address mapping entry; Record an entry generation flag for each address mapping entry stored in the address translation cache; The entry generation flag is set to the current generation flag of the function identifier associated with the address mapping entry when the address mapping entry is created; When a global invalidation request for a target function identifier is received, only the current generation flag of the target function identifier is flipped to a different value, without traversing any address mapping entries in the address translation cache. When querying address translation, if an address mapping entry matching the input virtual address is found in the address translation cache, the entry generation flag of the address mapping entry is compared with the current generation flag of the function identifier to which the input virtual address belongs. When the generational flag of the address mapping entry is not equal to the current generational flag of the function identifier to which the input virtual address belongs, the address mapping entry is marked as invalid or ignored, and a new address translation request is triggered to the root complex.

2. The method according to claim 1, characterized in that, After comparing the entry generation flag of the address mapping entry with the current generation flag of the function identifier to which the input virtual address belongs, the method further includes: When the generational flag of the address mapping entry is equal to the current generational flag of the function identifier to which the input virtual address belongs, the address mapping entry is determined to be a hit. The final physical address is obtained by concatenating the physical address base address stored in the address mapping entry with the low-order offset of the input virtual address; wherein the number of bits of the low-order offset is determined by the size of the address mapping entry.

3. The method according to claim 1, characterized in that, The current generation flag is a single-bit flag, and the operation of flipping it to a different value is to invert that single bit.

4. The method according to claim 1, characterized in that, Also includes: When creating a new address mapping entry, the current generation flag of the function identifier associated with the new address mapping entry is read, and the current generation flag is written to the entry generation flag field of the new address mapping entry.

5. The method according to claim 1, characterized in that, The address translation cache consists of multiple address translation tables. Each address translation table is configured to store address mapping entries of a fixed size. The address mapping entry sizes of different address translation tables are different. When querying address translation, a parallel hash lookup is performed simultaneously in the multiple address translation tables based on the input virtual address to find a matching address mapping entry.

6. The method according to claim 5, characterized in that, Also includes: When an address translation response is received from the root complex, the virtual address, physical address, and address mapping entry size are resolved. If the size of the address mapping entry is equal to the preset address mapping entry size of an address translation table, then the address mapping entry is directly stored in that address translation table.

7. The method according to claim 6, characterized in that, After resolving the virtual address, physical address, and address mapping entry size, the process also includes: If the size S of the parsed address mapping entry is not equal to the preset address mapping entry size of any address translation table, then select the maximum value T less than or equal to S from all preset address mapping entry sizes, and split the original address mapping entry corresponding to S into multiple sub-address mapping entries of size T. Based on the input virtual address corresponding to the currently received address translation response, determine which sub-address mapping entry the input virtual address falls within, and store the sub-address mapping entry into an address translation table with a preset address mapping entry size of T; The virtual address base address of the sub-address mapping entry is equal to the original virtual address base address plus an offset, which is an integer multiple of T that is down-aligned to the low-order part of the input virtual address; the physical address base address of the sub-address mapping entry is equal to the original physical address base address plus the same offset.

8. The method according to claim 5, characterized in that, The parallel hash lookup includes: For each address translation table, the number of high-order bits used for hash calculation in the input virtual address is determined according to the preset address mapping entry size of the address translation table; The high-order bits are input into a hash function to obtain the index in the table, and the address mapping entry at that index position is read. Compare the base address of the virtual address stored in the address mapping entry with the high-order part of the input virtual address to see if they are equal.

9. The method according to claim 5, characterized in that, The preset address mapping entry size of the multiple address translation tables includes at least two of the following: 4KB, 64KB, 2MB, and 1GB. The preset address mapping entry size is configurable.

10. A generational flag-based address translation cache global invalidation system, applied in endpoint devices, characterized in that, include: The generational identifier maintenance module is used to maintain a current generational identifier for each functional identifier. A function identifier is associated with at least one address mapping entry; The generational flag recording module is used to record an entry generational flag for each address mapping entry stored in the address translation cache; The entry generation flag is set to the current generation flag of the function identifier associated with the address mapping entry when the address mapping entry is created; The generation flag flipping module is used to flip the current generation flag of the target function identifier to a different value only when a global invalidation request for the target function identifier is received, without traversing any address mapping entries in the address translation cache. The generational flag comparison module is used to compare the generational flag of the address mapping entry with the current generational flag of the function identifier to which the input virtual address belongs when querying address translation. The address mapping invalidation module is used to mark the address mapping entry as invalid or ignore the address mapping entry when the entry generation flag of the address mapping entry is not equal to the current generation flag of the function identifier to which the input virtual address belongs, and to trigger a new request for address translation to the root complex.

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