A multi-core package and optical interconnection cluster cross-level optimization method, system, device and medium for large language model training
By constructing a design space and a hybrid search framework to optimize the chip hardware architecture and optical interconnect network, the problem of low efficiency of traditional network clusters in large language model training is solved, achieving high training throughput and low-cost cluster design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2026-04-01
- Publication Date
- 2026-06-26
AI Technical Summary
In large language model training, traditional data center network clusters cannot efficiently utilize chip technology and optical interconnect technology, resulting in training efficiency and cost bottlenecks, and there is a lack of optimization methods for LLM training tasks.
A multi-core encapsulation and optical interconnect cluster cross-level optimization method for training large language models is proposed. By constructing a design space, defining optimization objectives, and adopting a hybrid search framework (outer black box + inner white box) to collaboratively optimize the core hardware architecture, optical interconnect network, and training parallel strategy, Pareto optimal design points are selected.
It achieves cross-layer collaborative optimization between software and hardware, reduces optimization complexity, improves the communication efficiency and resource utilization of the training cluster, optimizes training throughput, and reduces cluster costs.
Smart Images
Figure CN122287353A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of artificial intelligence hardware architecture design, and in particular relates to a method, system, device and medium for cross-level optimization of multi-core packaging and optical interconnect clusters for training large language models. Background Technology
[0002] Artificial intelligence is playing an irreplaceable role in an increasing number of scenarios, especially Large Language Models (LLMs), which have demonstrated powerful intelligence and broad application prospects. In pursuit of stronger reasoning capabilities and richer knowledge reserves, the number of LLM model parameters and the length of supported contexts have been continuously increasing. However, this has directly led to an explosive increase in model training complexity and computational load, forcing the training process to rely on large-scale device clusters composed of numerous devices. This results in enormous hardware purchase costs and training time costs. Because LLM training differs from traditional computing load characteristics, traditional data center network clusters cannot achieve efficient training throughput. In particular, communication between devices restricts overall training efficiency. To overcome the bottlenecks in training efficiency and cost, new hardware technologies and training cluster designs are needed.
[0003] Chiplet technology and optical interconnects are emerging technologies considered to enable efficiency breakthroughs in next-generation training clusters. Chiplet technology integrates multiple chips into a single package using advanced processes, forming a multi-chiplet module (MCM) and achieving high-bandwidth, low-latency interconnects between chips. Chiplet technology allows for the efficient construction of large-scale MCMs using multiple small-area chips, offering the following advantages: First, the area of a single chip can be reduced, improving yield and lowering manufacturing costs. Second, the package size can be increased, and the communication efficiency of interconnects within the package is far higher than traditional interconnect technologies. This allows for the integration of more hardware resources within a more efficient and wider bandwidth domain.
[0004] Optical interconnect technology provides high-bandwidth, long-distance interconnect solutions through optical links (OI) and optical switches (OCS). In particular, the recently emerging co-packaged optics allows optical I / O chips to be directly integrated with computing chips within a package, achieving higher bandwidth density. Based on chip-embedded technology, more efficient scale-up networks can be built within MCMs; based on optical interconnect technology, more efficient scale-out networks can be built between a wide range of MCMs.
[0005] However, there is still a lack of conclusions and optimization methods for building efficient training clusters based on core-particle and optical interconnect technologies. Traditional data center networks often use CLOS or Fat-tree structures, which are not optimized for LLM training tasks. The application of core-particle and optical interconnect technologies changes the underlying communication parameters and introduces a new design space. Therefore, optimization methods are needed to search this vast design space, optimizing aspects such as joint architecture, network structure, and parallel strategies to find the most ideal design. Summary of the Invention
[0006] The purpose of this invention is to propose a cross-level joint optimization method for chip architecture, interconnect network structure, and training parallelism strategy for LLM training clusters based on chip-embedded and optical interconnect technologies. The input to this scheme is the relevant model and hardware configuration, and the output is a series of design points that offer advantages in training throughput or cluster cost. This method can guide the design of relevant training clusters, thereby fully leveraging the advantages and potential of chip-embedded and optical interconnect technologies in LLM training.
[0007] To achieve the above objectives, the present invention provides a multi-core packaging and optical interconnect cluster cross-level optimization method for training large language models, comprising:
[0008] S1: Construct the design space, which includes a chip hardware architecture layer, an optical interconnect network layer, and a training parallel strategy layer;
[0009] S2: Define the optimization objective, which is the cluster training performance and the cluster cost;
[0010] S3: Search for the architecture parameters of the multi-core module in the core hardware architecture layer and generate outer search sampling points;
[0011] S4: Perform inner-layer search for outer-layer search sampling points, collaboratively optimize the optical interconnect network topology and training parallel strategy in the optical interconnect network layer and training parallel strategy layer, and obtain the cluster training performance and cluster cost under the current design point; wherein, each design point includes a multi-core module architecture, optical interconnect network topology and training parallel strategy;
[0012] S5: Iterate through steps S3 to S4 based on a preset number of iterations to obtain multiple design points and the cluster training performance and cluster cost corresponding to each design point; perform non-dominated sorting on the obtained design points based on the optimization objective, and select the Pareto optimal design point based on the non-dominated sorting results.
[0013] Optionally, the design space of the chip hardware architecture layer in step S1 includes the total number of multi-chip modules in the cluster, the number of rows and columns of the logical chip array in each multi-chip module, the number of storage chips coupled to each logical chip, and the number of optical links provided by each optical I / O chip.
[0014] Optionally, in step S1, the design space of the optical interconnect network layer is quantitatively described using an orbital model, wherein the orbital model includes multiple intertwined orbital dimensions D. i ;
[0015] Each orbital dimension D i Specifically:
[0016] D i =(N i ,R i ,S i )
[0017] In the formula, N i R represents the number of interconnected multi-core module nodes in the i-th orbital dimension; i S represents the number of optical links allocated to the i-th orbital dimension for each multi-core module node. i This represents the number of optical circuit switches contained in the i-th orbital dimension;
[0018] Each orbital dimension D i The constraints are:
[0019] S i =R i / k i
[0020] k i ×N i <P
[0021]
[0022] In the formula, S i k represents the number of optical circuit switches contained in the i-th orbital dimension. i The number of links connecting each multi-core module node to the same optical switch; N i For the first i The number of interconnected multi-core module nodes in each track dimension; P is the total number of ports of a single optical switch; L is the total number of external links for each multi-core module node; x and y are the number of rows and columns of the logical core array in each multi-core module, respectively; o is the number of optical links provided for each optical I / O core.
[0023] Optionally, the design space for training the parallel strategy layer in step S1 includes the parallelism of tensor parallelism, the parallelism of data parallelism, the parallelism of pipeline parallelism, the parallelism of expert parallelism, and the parallelism of context parallelism, wherein the product of each parallelism is equal to the total number of core modules in the cluster.
[0024] Optionally, step S3 employs a white-box optimization method, specifically including:
[0025] The sampling planner reads the performance and cost results of historical sampling points and the simulation log of the current sampling point; the simulation log includes hardware resource usage and bottleneck information during the training process.
[0026] Based on the simulation logs, identify resource bottlenecks during the training process and adjust the architecture parameters of the multi-core module.
[0027] Optionally, step S4 specifically includes:
[0028] S41: Sample the parallel strategy using a black-box optimization algorithm;
[0029] S42: Predict the communication traffic distribution during the training process based on the parallel strategy obtained from sampling;
[0030] S43: Construct an ideal logical topology based on the communication traffic distribution, and allocate optical link resources of multi-core modules according to the traffic ratio;
[0031] S44: Based on the track model, select the physical topology that supports the ideal logical topology and has the fewest optical switches as the actual interconnection network.
[0032] Optionally, step S43 further includes:
[0033] By reconfiguring the optical switch configuration at runtime, time-division multiplexing of optical links is achieved between different communication groups to respond to communication changes at different stages of training.
[0034] Secondly, to achieve the above objectives, this invention provides a multi-core packaging and optical interconnect cluster cross-level optimization system for large language model training, comprising:
[0035] The design space definition module is used to construct the design space, which includes a chip hardware architecture layer, an optical interconnect network layer, and a training parallel strategy layer; it also defines optimization objectives, namely, cluster training performance and cluster cost.
[0036] The outer search module is used to search for the architecture parameters of the multi-core module in the core hardware architecture layer and generate outer search sampling points.
[0037] The inner search module is used to perform an inner search on the outer search sampling points, and to collaboratively optimize the optical interconnect network topology and training parallel strategy in the optical interconnect network layer and the training parallel strategy layer, and obtain the cluster training performance and cluster cost under the current design point; wherein, each design point includes a multi-core module architecture, an optical interconnect network topology and a training parallel strategy;
[0038] The output module is used to iteratively execute steps S3 to S4 according to a preset number of iterations to obtain multiple design points and the cluster training performance and cluster cost corresponding to each design point; the obtained design points are non-dominated and sorted based on the optimization objective, and Pareto optimal design points are selected based on the non-dominated sorting results.
[0039] Thirdly, to achieve the above objectives, the present invention provides an electronic device, including a memory and a processor, wherein the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to perform the multi-core packaging and optical interconnect cluster cross-level optimization method for training large language models as described in the first aspect.
[0040] Fourthly, to achieve the above objectives, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the multi-core packaging and optical interconnect cluster cross-level optimization method for training large language models as described in the first aspect.
[0041] The technical effects of this invention are as follows:
[0042] Achieving cross-layer collaborative optimization between hardware and software: This invention breaks through the limitations of traditional optimization methods by establishing a unified optimization framework that integrates the internal configuration of the multi-core module (MCM), the physical structure of the optical interconnect network, and the distributed parallel training strategy into the same design space. Through multi-level collaborative optimization, it avoids problems such as local optimization and inter-layer mismatch, thereby improving optimization performance.
[0043] A targeted quantitative modeling method reduces optimization complexity: For the complex optimization object of the "core + optical interconnect" training cluster, this invention proposes a simplified and efficient quantitative design template to efficiently define optimization variables. In particular, it quantifies and abstracts various complex topological connections in the optical interconnect network. This invention can accurately capture the key design variables for designing the aforementioned training cluster and define the design space. This ensures the searchability of the design space and the efficient execution of the optimization method.
[0044] A hybrid two-level search framework: This invention employs a two-level search architecture of "outer black-box + inner white-box". The outer search utilizes black-box algorithms such as Probabilistic Random Forest (PRF) to efficiently find the optimal solution within a broad hardware space; the inner search combines white-box heuristic algorithms for LLM communication traffic. This hybrid-driven approach can quickly narrow down the search scope using known patterns (white-box) while simultaneously exploring non-intuitive optimal design points using random search (black-box), greatly improving the search efficiency in complex design spaces.
[0045] Deeply aligned with the spatiotemporal characteristics of large model training traffic: By predicting communication traffic in different parallel modes, precise on-demand allocation of optical link resources in space is achieved. Simultaneously, considering the dynamic link reuse mechanism, the reconfigurable characteristics of optical circuit switches are utilized to enable physical links to be reused at different time stages, further improving the utilization efficiency of communication resources. Attached Figure Description
[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0047] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0048] Figure 1 This is an architectural diagram of the multi-core module (MCM) in an embodiment of the present invention;
[0049] Figure 2 This is a schematic diagram of an optical interconnect network with two orbital dimensions in an embodiment of the present invention;
[0050] Figure 3 This is an overview diagram of the optimization method in the embodiments of the present invention;
[0051] Figure 4 This is a flowchart of the inner search process in an embodiment of the present invention;
[0052] Figure 5 This is a flowchart of the outer search process in an embodiment of the present invention;
[0053] Figure 6 This is a flowchart illustrating the implementation of this invention. Detailed Implementation
[0054] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as a limitation of the present invention, but rather as a more detailed description of certain aspects, features, and embodiments of the present invention.
[0055] It should be understood that the terminology used in this invention is merely for describing particular embodiments and is not intended to limit the invention. Furthermore, with respect to numerical ranges in this invention, it should be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed. Every smaller range between any stated value or intermediate value within a stated range, and any other stated value or intermediate value within said range, is also included in this invention. The upper and lower limits of these smaller ranges may be independently included or excluded from the range.
[0056] Various modifications and variations can be made to the specific embodiments described in this specification without departing from the scope or spirit of the invention, as will be apparent to those skilled in the art. Other embodiments derived from this specification will also be obvious to those skilled in the art. This application specification and embodiments are merely exemplary.
[0057] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.
[0058] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0059] Example 1
[0060] like Figure 1 - Figure 6 As shown in the figure, this embodiment provides a multi-core encapsulation and optical interconnect cluster cross-layer optimization method for training large language models, including: constructing a design space, which includes a core hardware architecture layer, an optical interconnect network layer, and a training parallel strategy layer; defining optimization objectives, which are cluster training performance and cluster cost; searching for the architecture parameters of multi-core modules in the core hardware architecture layer and generating outer search sampling points; performing inner search for the outer search sampling points, co-optimizing the optical interconnect network topology and training parallel strategy in the optical interconnect network layer and the training parallel strategy layer, and obtaining the cluster training performance and cluster cost under the current design point; wherein, each design point includes a multi-core module architecture, an optical interconnect network topology, and a training parallel strategy; iteratively performing outer search and inner search based on a preset number of iterations to obtain multiple design points and the cluster training performance and cluster cost corresponding to each design point; performing non-dominated sorting on the obtained design points based on the optimization objectives, and selecting Pareto optimal design points based on the non-dominated sorting results.
[0061] This embodiment proposes a cross-level joint optimization method for LLM training clusters based on chip-embedded and optical interconnect technologies, focusing on chip architecture, interconnect network structure, and training parallelism strategies. The input to this scheme is the relevant model and hardware configuration, and the output is a series of design points that offer advantages in training throughput or cluster cost. This method can guide the design of relevant training clusters, thereby fully leveraging the advantages and potential of chip-embedded and optical interconnect technologies in LLM training.
[0062] The specific implementation scheme of this embodiment includes two parts: design space definition and search optimization method.
[0063] The design space definition includes the design parameters that this optimization method can adjust, as well as design templates for quantifying and abstracting complex designs across multiple levels. Specifically, it includes three levels: chip hardware architecture, optical interconnect network, and training parallel strategy.
[0064] At the core hardware architecture layer, the architecture of each MCM is as follows: Figure 1 As shown. Each MCM contains Each logic chip is associated with a logic core. Individual memory chip couplings. Optical I / O chips utilize co-packaged optics technology, integrated next to the logic chip at the package edge to provide external interconnect links. Each optical I / O chip provides... There are 10 optical links. Therefore, a single MCM has a total of 10 optical links. One optical link is used for external interconnection. In this design template, it is assumed that the internal interconnection network adopts a mesh topology, and its inter-chip interconnection interface bandwidth is... This bandwidth is proportional to the length used for interconnection between adjacent logical chips, which is equal to the side length of the logical chip minus the length occupied by the interconnection with the storage chip. This embodiment assumes that the entire training cluster contains N of the above-mentioned MCMs, and its overall computing power is C.
[0065] In summary, the optimization variables that can be independently adjusted at the chip hardware architecture layer during the optimization process include the total number of MCMs N in the cluster, the number of rows x and columns y of the logical chip array in an MCM, the number of storage chips m coupled to a logical chip, and the number of optical links o provided by each optical I / O chip.
[0066] In the optical interconnection network layer, to quantitatively describe the physical topology of the complex and diverse optical interconnection networks in a large-scale distributed training cluster, this embodiment adopts a multi-dimensional rail (Multi-Rail) abstraction model. This model abstracts the entire optical interconnection network into multiple intertwined rail dimensions, and the i-th rail dimension is denoted as Di. Each rail dimension describes multiple switches and the connection relationships between these switches and multiple MCMs. Each optical switch belongs to only one rail dimension, while each MCM can be connected by multiple rail dimensions. A rail dimension Di is quantitatively described by a triple (N i , R i , S i ), and the meanings of these variables are as follows:
[0067] Node scale (N i ): It represents the number of MCM nodes interconnected in the i-th rail dimension.
[0068] Link allocation (R i ): It represents the number of optical links allocated to the i-th rail dimension for each MCM node.
[0069] Switch resource (S i [[ID=2:1]]): It represents the number of optical circuit switches included in the i-th rail dimension.
[0070] Figure 2 Fig. i shows a schematic diagram of an optical interconnection network with two rail dimensions (D j ). Inside each rail dimension, the network connections follow the following physical constraints and calculation criteria:
[0071] Switch quantity constraint: Each MCM node is allocated k i links to connect to the same optical switch. Thus, the calculation formula for the number of optical switches included in this rail dimension is: S i = R i / k i .
[0072] Switch port constraint: To ensure physical feasibility, the number of links accessed by each optical switch must be less than its port number, that is, the constraint condition k i × N i < P, where P represents the total number of ports of a single optical switch.
[0073] MCM link quantity constraint: During the interweaving process of the multi-dimensional network, the total number of links allocated by all rail dimensions must be equal to the total external links L of each MCM node, that is, it satisfies:
[0074]
[0075] In summary, the optimization variables that can be independently adjusted at the optical interconnect network layer include the number of orbital dimensions. The number of optical links allocated to each MCM node in the i-th orbital dimension The number of optical circuit switches contained in the i-th orbital dimension and the number of interconnected MCM nodes in the i-th orbital dimension ;
[0076] Feasible, two different orbital dimensions (N) i ,R i ,S i They are not necessarily equal.
[0077] In the training parallel strategy layer, this embodiment supports five currently used parallel strategies, as well as their hybrid strategies. These include: Tensor Parallelism (TP), Data Parallelism (DP), Pipeline Parallelism (PP), Expert Parallelism (EP), and Context Parallelism (CP). The degree of parallelism for each parallel strategy constitutes an independently tuned optimization variable: the degree of parallelism for tensor parallelism, data parallelism, pipeline parallelism, expert parallelism, and context parallelism.
[0078] Under the hybrid parallel strategy, the constraint of the number of MCMs must be satisfied: the product of all parallelisms is equal to the total number of MCMs in the cluster.
[0079] In the design space definition section, this embodiment adopts a multi-track abstract model to quantitatively describe the diverse and complex topologies of interconnected networks. This model can cover a large number of topological cases and describe the topological connections with as few variables as possible, which is beneficial for subsequent optimization.
[0080] Based on the above design space definition, this embodiment constructs a cross-level multi-objective optimization method. For example... Figure 3As shown, the entire optimization process is divided into two parts: outer-search and inner-search. The outer-search optimizes the design parameters of the chip hardware architecture layer, while for each outer-search sampling point, the inner-search optimizes the parallel strategy and optical interconnect network topology based on this hardware architecture, i.e., it performs parallelism-topology collaborative exploration. The input parameters of the entire optimization method include the configuration parameters of the target LLM and the design constant. The optimization variables are the variables listed in the design space definition. The optimization objectives are the training performance of the cluster (quantified by training throughput) and the cluster cost (quantified by total equipment cost). The output results include the Pareto optimal design point on the training performance-cluster cost plane. Each design point includes the final values of the three optimization variables: multi-chip module architecture (MCM arch), optical interconnect network structure (physic topo), and parallel strategy, as well as the corresponding training performance and cluster cost results (perf / cost) obtained by the simulator.
[0081] In the inner-layer search of parallel strategies and network topology, this embodiment adopts a search process centered on parallelism. The entire process is divided into the following steps: (1) Set the parallel strategy as the optimization variable and sample it through a black-box optimization algorithm (such as PRF). Then, the network topology is determined through the following process: (2) Predict the training traffic distribution according to the parallel strategy. Large model training has relatively static characteristics, and the communication traffic is mainly determined by the parallel strategy, so the traffic prediction is relatively accurate. (3) Construct an ideal logical topology based on the predicted communication traffic distribution. For each parallelism across MCMs, the link resources of the MCMs are allocated proportionally to the proportion of its communication traffic in the total traffic for interconnection. The MCMs between each parallel group form a ring according to the allocated link resources, and finally form an ideal logical topology. All links under this topology are fully utilized and aligned with the distribution characteristics of the traffic. In the process of classifying and configuring link resources, this embodiment also covers the optimization possibility of dynamic reuse of links. That is, by reconstructing the optical switch configuration at runtime, changing the connection relationship of the links, time-division multiplexing a part of the physical links between different communication groups, responding to the communication changes at different stages of training. (4) Select a physical topology that supports the ideal logical topology to generate the actual interconnection network. Based on the multi-dimensional track model, all feasible physical topologies can be selected by enumerating all parallelism-track mapping relationships. The scheme with the fewest optical switches is selected because it has the lowest overall network cost.
[0082] In the outer-layer search of the chip hardware architecture, given the total computing power constraint C, a white-box search method is used to find the optimal hardware design point. The so-called white-box optimization method is a concept relative to the black-box optimization method. Traditional black-box optimization methods only refer to the input optimization variables and the final result at the sampling point, without paying attention to the process and mechanism that produces the result (in this embodiment, the cluster is simulated). White-box optimization methods, on the other hand, not only refer to the results of historical sampling points but also to the process information during the simulation of the current sampling point. For example... Figure 5 As shown, the sample planner determines the MCM design parameters for each search step. The sample planner not only reads the final performance / cost results of historical sampling points but also the simulation log file from the previous sampling point. Based on the simulation log, bottlenecks in the training process can be directly identified, and corresponding resource adjustments can be made. The sample planner is written based on prior knowledge. Since each sampling in the outer search triggers a complete inner search process, the cost of a single sampling in the outer search is high. In this case, traditional black-box optimization methods perform poorly due to the lack of historical sampling data. The white-box search method used in this embodiment not only uses the results of historical sampling points as input information but also uses the simulation process information of the current sampling as input. Through the simulation process information, the sample planner can directly check the usage of various hardware resources, analyze bottlenecks and redundancies, and guide the adjustment of the design parameters of the multi-core module in the next sampling step. This process incorporates the designer's prior knowledge and more simulation information into the optimization process, making it more efficient than black-box optimization methods in outer searches with fewer sampling times.
[0083] After multiple rounds of outer-inner layer searches, a large number of design points will be sampled and evaluated.
[0084] In the search optimization method section, this embodiment employs a multi-layered black-box and white-box optimization scheme. By decoupling the multi-core module architecture, interconnection network, and parallel strategy, it divides the search into inner and outer layers, improving the logicality and efficiency of the search. In the outer layer search for the multi-core modules, this embodiment uses a white-box optimization scheme based on simulation reports, utilizing simulation process information to guide sampling. In the inner layer search for the interconnection network and parallel strategy, this embodiment leverages the predictability of training traffic, employing a process centered on the parallel strategy and generating the optimal network topology based on the parallel strategy. Compared to the intuitive process of first determining the network structure and then formulating the parallel strategy, the process adopted in this embodiment avoids getting trapped in local optima due to network structure limitations, and reduces the number of network structure parameters as variables in the search, significantly reducing the search space and improving search efficiency.
[0085] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for cross-level optimization of multi-core packaging and optical interconnect clusters for training large language models, characterized in that, include: S1: Construct the design space, which includes a chip hardware architecture layer, an optical interconnect network layer, and a training parallel strategy layer; S2: Define the optimization objective, which is the cluster training performance and the cluster cost; S3: Search for the architecture parameters of the multi-core module in the core hardware architecture layer and generate outer search sampling points; S4: Perform inner-layer search for outer-layer search sampling points, collaboratively optimize the optical interconnect network topology and training parallel strategy in the optical interconnect network layer and training parallel strategy layer, and obtain the cluster training performance and cluster cost under the current design point; wherein, each design point includes a multi-core module architecture, optical interconnect network topology and training parallel strategy; S5: Iterate through steps S3 to S4 based on a preset number of iterations to obtain multiple design points and the cluster training performance and cluster cost corresponding to each design point; perform non-dominated sorting on the obtained design points based on the optimization objective, and select the Pareto optimal design point based on the non-dominated sorting results.
2. The method for cross-level optimization of multi-core packaging and optical interconnect clusters for training large language models according to claim 1, characterized in that, The design space of the chip hardware architecture layer in step S1 includes the total number of multi-chip modules in the cluster, the number of rows and columns of the logical chip array in each multi-chip module, the number of storage chips coupled to each logical chip, and the number of optical links provided by each optical I / O chip.
3. The method for cross-level optimization of multi-core packaging and optical interconnect clusters for training large language models according to claim 1, characterized in that, In step S1, the design space of the optical interconnect network layer is quantitatively described using an orbital model, wherein the orbital model includes multiple intertwined orbital dimensions D. i ; Each orbital dimension D i Specifically: D i =(N i ,R i ,S i ) In the formula, N i R represents the number of interconnected multi-core module nodes in the i-th orbital dimension; i S represents the number of optical links allocated to the i-th orbital dimension for each multi-core module node. i This represents the number of optical circuit switches contained in the i-th orbital dimension; Each orbital dimension D i The constraints are: S i =R i / k i k i ×N i <P In the formula, S i k represents the number of optical circuit switches contained in the i-th orbital dimension. i The number of links connecting each multi-core module node to the same optical switch; N i For the first i The number of interconnected multi-core module nodes in each track dimension; P is the total number of ports of a single optical switch; L is the total number of external links for each multi-core module node; x and y are the number of rows and columns of the logical core array in each multi-core module, respectively; o is the number of optical links provided for each optical I / O core.
4. The method for cross-level optimization of multi-core packaging and optical interconnect clusters for large language model training according to claim 1, characterized in that, The design space for training the parallel strategy layer in step S1 includes the parallelism of tensor parallelism, the parallelism of data parallelism, the parallelism of pipeline parallelism, the parallelism of expert parallelism, and the parallelism of context parallelism, wherein the product of each parallelism is equal to the total number of core modules in the cluster.
5. The method for cross-level optimization of multi-core packaging and optical interconnect clusters for training large language models according to claim 1, characterized in that, Step S3 employs a white-box optimization method, specifically including: The sampling planner reads the performance and cost results of historical sampling points and the simulation log of the current sampling point; the simulation log includes hardware resource usage and bottleneck information during the training process. Based on the simulation logs, identify resource bottlenecks during the training process and adjust the architecture parameters of the multi-core module.
6. The method for cross-level optimization of multi-core packaging and optical interconnect clusters for large language model training according to claim 3, characterized in that, Step S4 specifically includes: S41: Sample the parallel strategy using a black-box optimization algorithm; S42: Predict the communication traffic distribution during the training process based on the parallel strategy obtained from sampling; S43: Construct an ideal logical topology based on the communication traffic distribution, and allocate optical link resources of multi-core modules according to the traffic ratio; S44: Based on the track model, select the physical topology that supports the ideal logical topology and has the fewest optical switches as the actual interconnection network.
7. The method for cross-level optimization of multi-core packaging and optical interconnect clusters for large language model training according to claim 6, characterized in that, Step S43 further includes: By reconfiguring the optical switch configuration at runtime, time-division multiplexing of optical links is achieved between different communication groups to respond to communication changes at different stages of training.
8. A multi-core packaging and optical interconnect cluster cross-level optimization system for training large language models, characterized in that, include: The design space definition module is used to construct the design space, which includes a chip hardware architecture layer, an optical interconnect network layer, and a training parallel strategy layer. Define the optimization objectives as cluster training performance and cluster cost; The outer search module is used to search for the architecture parameters of the multi-core module in the core hardware architecture layer and generate outer search sampling points. The inner search module is used to perform an inner search on the outer search sampling points, and to collaboratively optimize the optical interconnect network topology and training parallel strategy in the optical interconnect network layer and the training parallel strategy layer, and obtain the cluster training performance and cluster cost under the current design point; wherein, each design point includes a multi-core module architecture, an optical interconnect network topology and a training parallel strategy; The output module is used to iteratively execute steps S3 to S4 according to a preset number of iterations to obtain multiple design points and the cluster training performance and cluster cost corresponding to each design point; the obtained design points are non-dominated and sorted based on the optimization objective, and Pareto optimal design points are selected based on the non-dominated sorting results.
9. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program and the processor runs the computer program to enable the electronic device to perform a multi-core packaging and optical interconnect cluster cross-level optimization method for training large language models according to any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements a multi-core packaging and optical interconnect cluster cross-level optimization method for training large language models as described in any one of claims 1-7.