Component analysis method and system for printed circuit board, electronic device and storage medium

Abstract

This application relates to a method, system, electronic device, and storage medium for component analysis of printed circuit boards. The method may include: acquiring a digital surface image of the printed circuit board under test; inputting the digital surface image into a component recognition and segmentation model for recognition and segmentation processing to obtain physical attribute information corresponding to multiple electronic components; selecting a target electronic component from the multiple electronic components; determining the spatial layout relationship between the target electronic component and at least one associated electronic component within a preset neighborhood based on the spatial coordinate information of the target electronic component; and matching the functional semantic label of the target electronic component from a preset circuit function knowledge base based on the type information of the target electronic component and the corresponding spatial layout relationship. According to the technical solution provided in this application, high-precision, pixel-level perception of all components on the PCB surface is achieved, avoiding the missed detections or misjudgments caused by traditional AOI relying solely on template matching.

Description

Technical Field

[0001] This application relates to the field of optical inspection technology for printed circuit boards, and in particular to a component analysis method, system, electronic device, and storage medium for printed circuit boards. Background Technology

[0002] In the automated manufacturing process of printed circuit boards (PCBs), surface mount technology (SMT) is widely used to densely mount electronic components such as resistors, capacitors, and integrated circuits onto the board surface. To ensure assembly quality, automated optical inspection (AOI) systems are commonly deployed in the later stages of the production line to screen for defects in the mounted PCBs.

[0003] Traditional AOI systems primarily rely on geometric template matching or rule-based image comparison techniques. Their typical workflow includes: acquiring high-resolution images of the PCB; and identifying the presence, offset, or polarity reversal of components through edge detection or template matching. For example, technologies like Cognex PatMax determine whether a component falls within a preset tolerance range by precisely locating its center coordinates and rotation angle.

[0004] However, the above methods have significant limitations: Focusing solely on physical presence while ignoring the intended function of the circuit. Even if components are correctly mounted, if their type or location does not meet the functional requirements of the circuit design (such as mistakenly mounting a 0Ω resistor as a pull-up resistor, or placing a decoupling capacitor far from the IC power supply pin), traditional AOI will still classify them as "qualified," leading to functional defects flowing into subsequent testing or end products, causing communication anomalies, power supply noise, or signal integrity issues; It heavily relies on netlists or CAD data. Some advanced AOI systems require importing circuit design files to obtain component functional information, but functional-level testing cannot be performed in scenarios without netlists (such as repair boards, reverse engineering, or supply chain disruptions). Lack of context awareness. Existing technologies typically analyze individual components in isolation, failing to infer their role in the local circuit based on the spatial layout relationships between components. Summary of the Invention

[0005] This application provides a component analysis method, system, electronic device, and storage medium for printed circuit boards, aiming to at least solve the problems in related technologies such as how to automatically infer the circuit functional role of components based on visual images and detect whether there are functional non-compliance defects caused by incorrect type, positional deviation, or improper connection, thereby improving the ability of AOI systems to detect latent manufacturing defects. The technical solution of this application is as follows: According to a first aspect of the embodiments of this application, a method for component analysis of a printed circuit board is provided, comprising: Acquire a digital surface image of the printed circuit board under test; the digital surface image includes visual information of multiple electronic components mounted on the printed circuit board under test; The digital surface image is input into the component recognition and segmentation model for recognition and segmentation processing to obtain the physical attribute information corresponding to each of the multiple electronic components; the physical attribute information includes the type information of each electronic component, the edge contour information of each electronic component, and the spatial coordinate information of each electronic component; Select a target electronic component from the plurality of said electronic components; Based on the spatial coordinate information of the target electronic component, determine the spatial layout relationship between the target electronic component and at least one associated electronic component within a preset neighborhood range; Based on the type information of the target electronic component and the spatial layout relationship corresponding to the target electronic component, the functional semantic tag of the target electronic component is matched from the preset circuit function knowledge base; the functional semantic tag is used to characterize the circuit function of the target electronic component in the printed circuit board under test.

[0006] According to a second aspect of the embodiments of this application, a component analysis system for a printed circuit board is provided, comprising: An image acquisition module is used to acquire a digital surface image of a printed circuit board under test; the digital surface image includes visual information of multiple electronic components mounted on the printed circuit board under test; The identification and segmentation module is used to input the digital surface image into the component identification and segmentation model for identification and segmentation processing to obtain the physical attribute information corresponding to each of the multiple electronic components; the physical attribute information includes the type information of each electronic component, the edge contour information of each electronic component, and the spatial coordinate information of each electronic component; A target electronic component selection module is used to select a target electronic component from a plurality of said electronic components; The layout relationship determination module is used to determine the spatial layout relationship between the target electronic component and at least one associated electronic component within a preset neighborhood range based on the spatial coordinate information of the target electronic component. The functional semantic tag matching module is used to match the functional semantic tags of the target electronic component from a preset circuit function knowledge base based on the type information of the target electronic component and the spatial layout relationship corresponding to the target electronic component; the functional semantic tags are used to characterize the circuit function of the target electronic component in the printed circuit board under test.

[0007] According to a third aspect of the embodiments of this application, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the method as described in any one of the first aspects above.

[0008] According to a fourth aspect of the present application, a computer-readable storage medium is provided, wherein when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform any of the methods described in the first aspect of the present application.

[0009] According to a fifth aspect of the embodiments of this application, a computer program product is provided, including computer instructions that, when executed by a processor, cause a computer to perform the method described in any one of the first aspects of the embodiments of this application.

[0010] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application.

[0011] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects: By acquiring digital surface images of the printed circuit board under test and using a component recognition and segmentation model for recognition and segmentation, the type information, edge contour information and spatial coordinate information of each electronic component are obtained. This achieves high-precision, pixel-level perception of all components on the PCB surface, providing a complete and reliable physical attribute basis for subsequent functional analysis and avoiding missed detections or misjudgments caused by traditional AOI relying solely on template matching. The system selects a target electronic component from multiple electronic components and determines its spatial layout relationship with at least one associated electronic component within a preset neighborhood based on its spatial coordinate information. This introduces local circuit context awareness, enabling the system to simulate the logic of "judging by looking at the surroundings" in manual visual inspection, thus overcoming the limitations of existing technologies that analyze individual components in isolation. By jointly matching the type information of the target electronic component with its spatial layout relationship to a preset circuit function knowledge base and assigning it a functional semantic label, the automatic inference of the circuit function role of the component is realized without the need for netlist or CAD data, filling the technical gap of pure visual inspection in functional understanding.

[0012] Other features and aspects of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0013] To more clearly illustrate the technical solutions and advantages in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a flowchart illustrating a component analysis method for a printed circuit board according to an exemplary embodiment.

[0015] Figure 2 This is a flowchart illustrating a segmentation model prediction method according to an exemplary embodiment.

[0016] Figure 3 This is a flowchart illustrating a recognition and segmentation model training method according to an exemplary embodiment.

[0017] Figure 4 This is a flowchart illustrating a functional semantic tag matching method according to an exemplary embodiment.

[0018] Figure 5 This is a system block diagram illustrating a component analysis system for a printed circuit board according to an exemplary embodiment.

[0019] Figure 6 This is a block diagram of an electronic device for component analysis of a printed circuit board, according to an exemplary embodiment. Figure 1 .

[0020] Figure 7 This is a block diagram of an electronic device for component analysis of a printed circuit board, according to an exemplary embodiment. Figure 2 . Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments in the specification, and not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0023] Various exemplary embodiments, features, and aspects of the present invention will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0024] The term "exemplary" as used herein means "serving as an example, embodiment, or illustration." Any embodiment illustrated herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments. The term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships may exist, for example, A and / or B, which can represent: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more of a plurality, for example, including at least one of A, B, and C, which can represent including any one or more elements selected from the set consisting of A, B, and C.

[0025] Unless otherwise specified, the directions in this article should be understood as follows: the direction closer to the user is forward, and the direction farther from the user is backward.

[0026] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without certain specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order to highlight the spirit of the invention.

[0027] It should be noted that the following diagram shows one possible sequence of steps, and it is not strictly necessary to follow this order. Some steps can be executed in parallel without interdependence.

[0028] Before introducing the method embodiments provided by the present invention, a brief introduction will be given on the application scenarios, related terms or nouns that may be involved in the method embodiments of the present invention, so as to facilitate the understanding of those skilled in the art.

[0029] Existing printed circuit board component analysis methods mainly rely on template matching, rule engines, or deep learning for geometric recognition. However, they generally suffer from the inability to infer the functional role of components from visual information without a netlist, making it difficult to detect hidden defects that are "physically present but functionally incorrect".

[0030] To address the aforementioned technical issues, this application provides a component analysis method, system, electronic device, and storage medium for printed circuit boards. This method, without relying on circuit netlists or CAD design files, can automatically infer the circuit functional semantics of target electronic components based solely on digital images of the PCB surface. By integrating component types and neighborhood spatial layout relationships, it provides a reliable basis for subsequent functional defect determination, thereby effectively identifying hidden manufacturing defects that are "physically present but functionally incorrect," and improving the intelligence level and detection coverage of AOI systems.

[0031] Figure 1 This is a flowchart illustrating a component analysis method for a printed circuit board according to an exemplary embodiment. For example... Figure 1 As shown, the steps may include the following.

[0032] In step S101, a digital surface image of the printed circuit board to be tested is acquired.

[0033] In the embodiments of this specification, a digital surface image can refer to a high-resolution digital image acquired by an industrial camera, scanner, or other optical imaging device, characterizing the appearance of the top or bottom surface of a printed circuit board (PCB) under test. The image contains visual information of electronic components mounted on the board surface, such as shape, color, silkscreen printing, solder joint reflections, etc., but does not contain electrical connection relationships (such as netlists) or three-dimensional structural information. For example, a digital surface image may include visual information of multiple electronic components mounted on the PCB under test.

[0034] For example, an industrial vision imaging device, such as a high-resolution area scan camera, a line scan camera, or a 3D AOI system, is used to optically acquire images of the surface of a printed circuit board (PCB) under test, generating one or more digital images. The digital surface images are stored in the form of a pixel matrix and contain visual information about the appearance of all mounted electronic components on the top or bottom layer of the PCB, such as the shape, color, silkscreen markings, reflective features of the pads, and their relative positions.

[0035] Preferably, the imaging process is performed under controlled lighting conditions, such as ring LED light sources, coaxial light, or structured light illumination, to reduce interference from reflections, shadows, or noise on subsequent identification. The image resolution is typically no less than 5 micrometers per pixel to ensure that details of tiny components such as 01005 packages can be effectively distinguished.

[0036] It should be noted that the digital surface image is generated solely based on optical visual information and does not rely on PCB circuit design files such as Gerber, CAD, or netlists, nor does it contain electrical connection relationships or three-dimensional stacking structure data. This image serves as the input source for the component analysis method of this application and is used in the entire process of subsequent component identification, functional inference, and defect determination.

[0037] In step S103, the digital surface image is input into the component recognition and segmentation model for recognition and segmentation processing to obtain the physical attribute information corresponding to each of the multiple electronic components; the physical attribute information includes the type information of each electronic component, the edge contour information of each electronic component, and the spatial coordinate information of each electronic component. In the embodiments of this specification, the component recognition and segmentation model can refer to a computer vision model based on artificial intelligence (such as deep learning), used to perform pixel-level processing on the input digital surface image to achieve simultaneous detection, classification, and instance segmentation of multiple electronic components. Typical models include, but are not limited to, Mask R-CNN, U-Net, YOLOv8-Seg, etc. This model outputs the semantic category and precise boundary region of each component, such as instance masks.

[0038] Physical property information can refer to quantifiable features extracted from digital surface images that describe the physical state of electronic components, and includes at least the following three categories: Type information: The category identifier of the component, such as "0603 resistor", "SOT-23 transistor", "QFP chip", etc.; Edge contour information: The outer boundary shape of an element on the image plane, usually represented as an ordered sequence of coordinate points or a polygon; Spatial coordinate information: The position of an element in the image coordinate system, usually represented by its geometric center (centroid) or the center of its smallest bounding rectangle.

[0039] Figure 2 This is a flowchart illustrating a segmentation model prediction method according to an exemplary embodiment. Figure 2 As shown, it includes the following steps.

[0040] Step S201: Based on the component recognition and segmentation model, perform pixel-level semantic parsing processing on the digital surface image to generate an instance mask for each electronic component; Step S203: Extract the edge contour information of each electronic component based on the instance mask; Step S205: Determine the spatial coordinate information of each electronic component based on the positional distribution of the instance mask in the image coordinate system; Step S207: Obtain the category probability distribution associated with each instance mask, and determine the category prediction result with the highest priority in the category probability distribution as the type information.

[0041] In the embodiments of this specification, an instance mask can refer to a binary or labeled mask image with the same size as the input image, in which the pixels covered by each target electronic component are assigned a unique identifier, such as a specific grayscale value or color, while the remaining areas, i.e., the background or other components, are marked with 0 or a different identifier. Instance masks can accurately represent the shape and position of individual components and are the basic data structure for realizing subsequent contour extraction, coordinate calculation, and category association.

[0042] Edge contour information can refer to geometric data describing the shape of the outer boundary of an electronic component, typically represented as an ordered sequence of two-dimensional coordinate points or a set of polygon vertices. In this application, this edge contour information is obtained by extracting the outer boundary of its non-zero regions from an instance mask, for example, using the findContours algorithm in OpenCV, to characterize the actual physical shape of the component. The image coordinate system can refer to a two-dimensional Cartesian coordinate system established with the top-left corner of the digital surface image as the origin (0, 0), the horizontal axis to the right as the X-axis, and the vertical axis downwards as the Y-axis. All spatial locations, such as the component center and contour points, are represented in this coordinate system, with the unit being pixels.

[0043] The category probability distribution refers to the confidence output of the component recognition and segmentation model for the component corresponding to a certain instance mask belonging to each preset category. It is usually a normalized probability vector. For example, for a component to be identified, the model may output: [resistor: 0.92, capacitor: 0.05, chip: 0.03], indicating that there is a 92% probability that it is a resistor.

[0044] The highest priority category prediction result can refer to using the category with the highest probability output by the model as the final type determination result.

[0045] For example, the acquired digital surface image of the printed circuit board under test is input into a pre-trained component recognition and segmentation model. This model, based on a deep learning architecture such as Mask R-CNN, U-Net, or variants thereof, performs pixel-level semantic parsing of the image, determining whether each pixel belongs to a specific electronic component and distinguishing different component instances. The processing result is a set of instance masks, where each mask corresponds to an independent electronic component, accurately marking the component's coverage area in the image in binary image form.

[0046] Subsequently, based on each instance mask, the edge contour information of the electronic component is extracted using an image contour extraction algorithm, such as the findContours function in the OpenCV library. This edge contour information is typically represented as an ordered sequence of two-dimensional coordinate points, accurately reflecting the actual external boundary of the component and can be used for subsequent size verification or shape matching.

[0047] Next, based on the pixel distribution of the instance mask in the image coordinate system, for example with the top-left corner of the image as the origin, the horizontal direction to the right as the X-axis, and the vertical direction downward as the Y-axis, the spatial coordinate information of the element is calculated. In a preferred embodiment, the geometric center (centroid) of all foreground pixels within the mask is taken as the spatial coordinates of the element. , where M represents the set of foreground pixels of the instance mask, and N is the total number of pixels.

[0048] Simultaneously, the component identification and segmentation model, while generating an instance mask, also outputs a category probability distribution associated with that mask, i.e., the confidence level of the component belonging to each preset category, such as "0603 resistor: 95%", "0805 capacitor: 3%", and "SOT-23 transistor: 2%". The system selects the category with the highest probability in this probability distribution as the type information of the component. For example, if "0603 resistor" has the highest probability, then its type information is determined to be "0603 resistor".

[0049] Through the above processing, the system synchronously obtains three core physical attribute information for each electronic component on the PCB: type information, edge contour information, and spatial coordinate information, providing a high-precision, structured data foundation for subsequent functional semantic analysis and verification.

[0050] Figure 3 This is a flowchart illustrating a method for training a recognition and segmentation model according to an exemplary embodiment. For example... Figure 3 As shown, the training process of the component recognition and segmentation model includes: Step S301: Obtain the sample digital surface image, the target electronic component on the sample digital surface image, and the actual physical property information corresponding to each actual electronic component; Step S303: Perform image preprocessing on the digital surface image of the sample to obtain the digital surface image of the sample to be identified; Step S305: Input the sample digital image into the initial component recognition and segmentation model for recognition and segmentation processing to obtain the sample physical attribute information corresponding to multiple sample electronic components; Step S307: Determine the component identification loss information based on the actual physical attribute information corresponding to each actual electronic component and the sample physical attribute information corresponding to multiple sample electronic components. Step S309: Optimize the model parameters of the initial component recognition and segmentation model based on the component recognition loss information until the preset training iteration conditions are met, and determine the initial component recognition and segmentation model that meets the preset training iteration conditions as the component recognition and segmentation model.

[0051] In the embodiments of this specification, the sample digital surface image can refer to the input image in the labeled dataset used to train the component recognition and segmentation model. The acquisition method is the same as that of the digital surface image of the PCB under test. It contains multiple known types of mounted electronic components, and each image is manually or semi-automatically labeled to provide corresponding "actual physical attribute information".

[0052] Actual electronic components refer to the real electronic components that exist in the sample image. Actual physical attribute information can refer to the real attribute data obtained by manually and accurately annotating each electronic component in the sample digital surface image.

[0053] The initial component recognition and segmentation model can refer to a neural network model architecture built before training begins, with unoptimized parameters, such as U-Net or Mask R-CNN. Its structure is fixed, but the weights are randomly initialized or pre-trained weights are loaded, serving as the starting point for training. The sample physical attribute information can refer to the prediction results output by the initial component recognition and segmentation model after performing forward inference on the sample digital surface image. This includes the generated instance mask, the predicted class probability distribution, and the calculated spatial coordinates, used for comparison with the actual physical attribute information.

[0054] Component recognition loss information refers to a numerical metric that quantifies the difference between the model's prediction and the ground truth labeling. It is typically composed of a combination of multi-task loss functions, such as: segmentation loss (e.g., Dice Loss, Binary Cross-Entropy) measures instance mask accuracy; classification loss (e.g., Cross-Entropy Loss) measures type prediction accuracy; and regression loss (e.g., Smooth L1 Loss) can optionally be used for coordinate fine-tuning. The total loss is the weighted sum of all sub-losses. Preset training iteration conditions refer to the criteria for terminating training, which may include: reaching the maximum number of training epochs; the validation set loss no longer decreasing for several consecutive epochs; and the model's mAP (mean accuracy) on the validation set reaching a preset threshold (e.g., ≥95%). Training stops and the current model is saved when any of these conditions are met.

[0055] For example, sample digital surface images and their corresponding annotation data are acquired. These images are captured using the same imaging equipment (such as a high-resolution industrial camera) as the printed circuit board under test (PCB) and contain various typical electronic components mounted on the PCB. For each sample image, a professional or semi-automatic annotation tool precisely annotates each actual electronic component, generating its actual physical attribute information as a supervisory label (Ground Truth). This actual physical attribute information includes: an instance mask for each component, such as a pixel-level boundary region; a component type label, such as a 0603 resistor or an SOT-23 transistor; and the component's spatial coordinates, typically calculated from the mask centroid.

[0056] Subsequently, the sample digital surface images undergo image preprocessing to improve the robustness and convergence speed of model training. Preprocessing operations may include: illumination normalization, noise reduction filtering, contrast enhancement, uniform image scaling to the model input requirements, such as 1024×1024 pixels, and color space conversion, such as RGB to grayscale or preserving color channels. The processed image is referred to as the sample digital surface image to be identified.

[0057] Next, the digital surface image of the sample to be identified is input into the initial component recognition and segmentation model. This initial model is a pre-built deep neural network architecture, such as Mask R-CNN, U-Net, or an improved version thereof, whose parameters have not yet been task-specific optimized. The model performs forward inference on the image and outputs the physical attribute information of each detected sample electronic component, including the predicted instance mask, class probability distribution, and spatial coordinates.

[0058] Then, the physical attribute information of the samples output by the model is compared with the actual physical attribute information labeled by humans to calculate the element recognition loss. This loss information is composed of a combination of multi-task loss functions, which may include: segmentation loss, such as Dice Loss or Binary Cross-Entropy Loss, used to measure the overlap between the predicted mask and the real mask; classification loss, such as Softmax Cross-Entropy Loss, used to measure the difference between the predicted class and the real class; and optionally, localization loss, such as Smooth L1 Loss, used to fine-tune the accuracy of spatial coordinates. The total loss is the weighted sum of the sub-losses and reflects the overall prediction error of the model.

[0059] Finally, based on the component recognition loss information, an optimization algorithm, such as Adam or SGD, is used to optimize the model parameters of the initial component recognition and segmentation model through backpropagation. This training process is iterative on the training set until preset training iteration conditions are met. These preset conditions may include: reaching the maximum number of training epochs, the validation set loss no longer decreasing for several consecutive epochs, or the model's average accuracy (mAP) on the validation set exceeding a preset threshold, such as 95%. When the conditions are met, the current model parameters are saved, and the optimized model is determined as the final component recognition and segmentation model for subsequent analysis and processing of the PCB image under test.

[0060] In step S105, a target electronic component is selected from the plurality of said electronic components.

[0061] In the embodiments described in this specification, the target electronic component can refer to any electronic component selected for functional semantic inference in the current analysis flow. The system can traverse all components and analyze them sequentially as target electronic components.

[0062] For example, after completing the recognition and segmentation of the digital surface image and obtaining the physical attribute information of all electronic components, the system selects one of the multiple electronic components as the current analysis object, or the user or engineer can manually specify an electronic component to be analyzed as the target electronic component through the human-computer interaction interface.

[0063] Specifically, the selection operation can be implemented in any of the following ways: Iterative selection: The system sequentially sets each electronic component as the target electronic component in turn, performs functional analysis one by one, and ensures that all components on the entire board are covered; Condition-triggered selection: Based on preset rules, such as the component type belonging to a critical function category, located in a high-risk area, or preliminary detection of anomalies, select some components as targets; User interactive selection: In the human-computer interaction interface, the operator manually clicks or selects a specific component as the target. This is applicable to maintenance, re-inspection, or key sampling inspection scenarios. This application does not limit this.

[0064] Regardless of the selection method used, the target electronic component is a specific instance of an electronic component on the printed circuit board under test that has been identified and possesses complete physical attribute information, including type, outline, and coordinates. After selection, the system constructs a neighborhood range centered on its spatial coordinates, analyzes its spatial layout relationship with surrounding related electronic components, and then, combined with its type information, matches the corresponding functional semantic tags from a preset circuit function knowledge base.

[0065] In step S107, the spatial layout relationship between the target electronic component and at least one associated electronic component within a preset neighborhood is determined based on the spatial coordinate information of the target electronic component. In the embodiments of this specification, the preset neighborhood range can refer to a local spatial region centered on the target electronic component, such as a circular region with a radius of 3mm or a square region of 5mm×5mm, used to screen related components that may constitute a specific circuit function with it. This range can be dynamically set according to the component type or functional role. For example, the neighborhood of a decoupling capacitor is usually small, while the neighborhood of a power supply module is large.

[0066] Spatial layout relationship can refer to the relative spatial configuration between a target electronic component and one or more related electronic components in the vicinity, including but not limited to: relative distance, azimuth angle, arrangement direction, whether collinear, whether enclosing, and other geometric and topological features.

[0067] Using the spatial coordinates of the target electronic component, such as its centroid coordinates (x0, y0), as a reference center, a preset neighborhood range is defined. This neighborhood range can be a circular area, such as a radius r = 3 mm, a square area, such as a side length of 5 mm × 5 mm, or dynamically set according to the type of the target electronic component. For example, for decoupling capacitors, the neighborhood radius is set to 2-3 mm; for power management ICs, the neighborhood is expanded to 10 mm. The neighborhood size can be pre-configured based on typical circuit design specifications or statistical analysis of historical good boards.

[0068] Subsequently, within that neighborhood, the system retrieves the spatial coordinates of all other identified electronic components and identifies these components as candidate associated electronic components.

[0069] Furthermore, based on the relative positional relationship between the target electronic component and each candidate associated electronic component, geometric features describing their spatial configuration are calculated and extracted, including but not limited to: Euclidean distance between two points; relative azimuth angle; whether they are collinear or symmetrically distributed; and whether they constitute a specific topological structure.

[0070] Finally, according to preset association rules, for example, if there is a component whose X-coordinate difference is less than 1 mm and whose Y-coordinate is the same, it is considered to be connected in parallel in the same row. At least one functionally related electronic component is selected from the candidate related electronic components, and this related electronic component is combined with the aforementioned geometric features between it and the target electronic component to form a structured spatial layout relationship. This spatial layout relationship serves as a contextual key feature, which is used for subsequent matching with a preset circuit function knowledge base to infer the functional role of the target electronic component in the local circuit, such as determining whether a resistor forms a pull-up network with IC pins and power supply.

[0071] In step S109, based on the type information of the target electronic component and the spatial layout relationship corresponding to the target electronic component, the functional semantic tag of the target electronic component is matched from the preset circuit function knowledge base.

[0072] In the embodiments of this specification, the preset circuit function knowledge base may refer to a pre-built database that stores structured descriptions of typical circuit function modules. Each function module, for example, "I..." 2 The definitions for "C-type pull-up network," "power supply decoupling circuit," and "high-speed signal termination matching" all specify the required component type combinations and their allowed spatial layout constraints. This knowledge base can be built using expert experience or historical good-quality board data, and supports rule matching or vector similarity retrieval.

[0073] Functional semantic tags can refer to high-level functional description tags assigned to target electronic components to characterize their role or function in local circuits, such as "decoupling capacitor", "pull-up resistor", "termination matching resistor", "feedback network voltage divider resistor", etc.

[0074] Figure 4 This is a flowchart illustrating a functional semantic tag matching method according to an exemplary embodiment. For example... Figure 4 As shown, it includes the following steps.

[0075] Step S401: Perform feature encoding fusion processing on the type information of the target electronic component and the spatial layout relationship corresponding to the target electronic component to generate a joint feature vector; Step S403: Perform similarity condition matching processing on the joint feature vector and the features of multiple functional modules pre-stored in the preset circuit function knowledge base to obtain the functional semantic matching result; Step S405: Based on the functional semantic matching results, determine the preset functional semantic label associated with the functional module feature with the highest similarity as the functional semantic label corresponding to the target electronic component.

[0076] In the embodiments described in this specification, the joint feature vector can refer to a high-dimensional numerical vector, such as 128-dimensional or 256-dimensional, generated after feature encoding fusion processing to characterize the target electronic component and its local context. This vector serves as the query key for functional matching and is input to the matching module.

[0077] Functional semantic matching results can refer to the ranking or scoring results output by similarity condition matching processing, indicating the degree of matching between the target electronic component and each preset functional module. For example: ["Pull-up resistor": 0.92, "Terminal matching": 0.35, "Current limiting resistor": 0.18]. Preset functional semantic tags can refer to high-level functional description tags bound to the features of each functional module, used to characterize the role or function of the component in the circuit. Unlike physical types, such as 0603 resistors, functional semantic tags reflect the circuit intent, such as "pull-up resistor," "decoupling capacitor," and "feedback voltage divider resistor."

[0078] For example, the type information of the target electronic component, such as the 0603 resistor and its spatial layout relationship, such as its distance from the IC power pin being 2.1 mm and its location between VCC and GND, is subjected to feature encoding and fusion processing. Specifically, the type information is mapped to a fixed-dimensional vector, such as 64-dimensional, through category embedding. The spatial layout relationship is quantified into structured numerical features, such as relative distance, azimuth angle, and number of neighboring components. After normalization, these features are concatenated with the type embedding vector or fused through a multilayer perceptron (MLP) to finally generate a unified joint feature vector, such as 128-dimensional, used to characterize the comprehensive contextual semantics of the component in the local circuit.

[0079] Subsequently, the joint feature vector is matched with the features of multiple functional modules pre-stored in the preset circuit function knowledge base using similarity conditions. The preset circuit function knowledge base is a structured database that stores several typical circuit function modules, such as I... 2 Standardized feature representations are used for C-type pull-up networks, power supply decoupling circuits, high-speed signal termination matching, etc. Each functional module feature is a reference vector with the same dimension as the joint feature vector, constructed in the same way as the aforementioned encoding and fusion process, ensuring fairness and consistency in matching. Similarity calculation can employ known methods such as cosine similarity, Euclidean distance, or dot product, outputting a functional semantic matching result that includes the matching scores of each functional module.

[0080] Finally, based on the functional semantic matching results, the functional module with the highest similarity is selected, and its associated preset functional semantic tags, such as pull-up resistors, decoupling capacitors, and termination matching resistors, are determined as the functional semantic tags corresponding to the target electronic components.

[0081] In one possible implementation, the expected functional information of the target electronic component is determined based on the functional semantic tag corresponding to the target electronic component; the expected functional information is compared with the preset physical state constraints to determine the functional comparison result; if the functional comparison result indicates that the expected functional information does not meet the state constraints, it is determined that the target electronic component has functional non-compliance, and a functional alarm instruction is generated.

[0082] In the embodiments of this specification, the expected functional information can refer to the set of functional requirements that the target electronic component should meet under normal operating conditions, derived from the functional semantic tags. The expected functional information may include component parameter ranges, such as resistance, capacitance, and accuracy; electrical connection logic, such as one end connected to VCC and the other end connected to a signal line; and spatial layout constraints, such as being located within 3mm of the IC power supply pins. The expected functional information can be automatically generated by mapping from a preset rule base, circuit design specifications, or knowledge base.

[0083] Preset physical state constraints refer to converting the expected functional information into quantifiable and measurable physical acceptance criteria for comparison with the actual physical properties of the component. Preset physical state constraints may include type / parameter constraints, such as capacitance ≥ 0.1μF; positional constraints, such as distance from the target IC pin ≤ 2.5 mm; and layout existence constraints, such as the requirement for a VCC pad to exist in the vicinity. These constraints are pre-configured in the system and serve as the basis for functional verification.

[0084] Functional comparison results refer to the judgment output obtained after verifying the actual physical attribute information of the target electronic component against the preset physical state constraints item by item. Functional comparison results can be expressed as Boolean values ​​(compliant / non-compliant); multi-dimensional scores, such as position compliance 85%, parameter compliance 0%; structured difference reports, such as actual capacitance: 100pF, requirement ≥0.1μF. Functional non-compliance can refer to a situation where the target electronic component physically exists and its mounting position is not significantly offset, but its actual state does not meet the physical state constraints corresponding to its functional role, which is a kind of implicit manufacturing defect. For example, mistakenly mounting a 0Ω jumper as an IΩ jumper. 2 Pull-up resistors on the C bus; use 100pF capacitors instead of 0.1μF decoupling capacitors; keep the termination matching resistors away from the high-speed signal receiver. These defects cannot be detected by conventional AOI, but can lead to signal integrity issues, power supply noise, or communication failures.

[0085] A functional alarm instruction is a structured alarm signal automatically generated by the system when a functional non-conformity is detected, used to trigger subsequent handling procedures. A functional alarm instruction can at least include the defect type, target component identifier, violated constraints, and a comparison between actual and expected conditions. This instruction can be displayed on a human-machine interface or transmitted to a manufacturing execution system (MES) to initiate process intervention.

[0086] For example, the expected functional information of the target electronic component is determined based on its corresponding functional semantic tag. For instance, if the functional semantic tag is a decoupling capacitor, the system retrieves the expected functional information associated with that tag from a preset rule base, including: capacitance should be no less than 0.1μF, it should be mounted within 3 mm of the target IC power supply pin, one end should be connected to the VCC network, and the other end should be grounded; if the tag is I... 2 For pull-up resistor C, the expected functional information includes: the resistance value should be between 4.7 kΩ and 10 kΩ, one end should be connected to the SDA / SCL signal line, and the other end should be connected to VCC, etc. The expected functional information is predefined by circuit design common sense or industry standards (such as IPC specifications) and stored in a structured manner in the system knowledge base.

[0087] Subsequently, the expected functional information is converted into quantifiable preset physical state constraints and compared with the actual physical attribute information of the target electronic component. The comparison process includes: checking whether the component parameters are within the allowable range, such as inferring nominal values ​​through type information; calculating whether the actual distance between the component and related components, such as IC pins and power pads, meets the positional constraints; and verifying whether there are necessary coexisting components in the neighborhood, such as whether there is a VCC mark near the pull-up resistor. The comparison result is the functional comparison result, which can be expressed as a compliance / non-compliance judgment or a structured report containing specific deviation values.

[0088] Finally, if the functional comparison results indicate that the expected functional information does not meet the preset physical state constraints, the system determines that the target electronic component has a functional non-compliance. Specific scenarios include misusing a 0Ω jumper as a pull-up resistor, using a 100pF capacitor instead of a 0.1μF decoupling capacitor, and placing the terminating matching resistor far from the high-speed signal receiver. Although such defects may appear geometrically "correctly mounted," they can lead to abnormal circuit function and are considered high-risk latent defects.

[0089] Once a functional non-compliance is confirmed, the system immediately generates a functional alarm instruction. This instruction includes the defect type, target component coordinates, functional semantic label, violated constraints, and suggested remedial measures for subsequent visual prompts or automated intervention. Through this mechanism, this application achieves a leap from "physical presence detection" to "circuit functional verification," significantly improving the quality assurance capabilities for high-value PCBs.

[0090] In another possible implementation, the functional alarm instruction and the physical attribute information and functional semantic tag of the target electronic component with the functional non-compliance are packaged together to generate a component structured defect report; the component structured defect report is pushed to the human-machine interface for visualization and / or transmitted to the manufacturing execution system to trigger the process intervention process. In the embodiments of this specification, a component structured defect report can refer to a standardized defect description file generated after packaging, whose content structurally includes: defect type, component location, actual physical attributes, expected functional role, violated constraints, and alarm level and timestamp. The human-machine interface can refer to a graphical user interface for operators to interact with the inspection system, typically deployed on the local terminal of the AOI equipment or a remote monitoring platform. The manufacturing execution system can refer to a factory-level production management software system used to monitor, schedule, and control the manufacturing process. In this invention, upon receiving a component structured defect report, a process intervention process can be automatically triggered, such as pausing the current production line; generating a maintenance work order; and feeding back to the pick-and-place machine to adjust the feeding parameters. The process intervention process can refer to a quality response mechanism that is automatically or semi-automatically initiated based on the defect report, aiming to prevent defective boards from flowing into the next process and improve yield and reliability.

[0091] For example, after determining that the target electronic component has a functional non-compliance and generating a functional alarm instruction, the system further performs structured encapsulation and distribution of defect information to support manual review or automated intervention.

[0092] Specifically, the system packages the functional alarm instructions, including the defect type, risk level and triggering basis, physical attribute information of the target electronic component with functional non-compliance (including type information, edge contour information, and spatial coordinate information), and its corresponding functional semantic tags, such as pull-up resistors and decoupling capacitors. This packaging process integrates multi-source information into a clearly structured and complete data object according to a preset data format, such as JSON or XML, generating a structured component defect report. The structured component defect report includes at least the following: a unique defect identifier and timestamp; the precise location (spatial coordinates) of the target component on the PCB; the actual identified component type and contour; the inferred functional semantic tags; the violated physical state constraints (e.g., "Expected resistance: 10 kΩ, Actual type: 0 Ω jumper"); and the alarm level (e.g., high / medium / low risk).

[0093] Subsequently, the system distributes the structural defect report of the component: on the one hand, it pushes it to the human-machine interface (HMI) to present it to the operator in a visual way. For example, the problematic component is marked with a red highlight box on the PCB digital image, and an information window pops up displaying "Function mismatch: Should be I". 2 "C is a pull-up resistor, which is actually a 0Ω jumper", and provides interactive options such as "confirm", "re-inspect" or "release"; On the other hand, and / or transmitted to the Manufacturing Execution System (MES), the defect report is automatically uploaded via standard industrial communication protocols (such as SECS / GEM, OPC UA, or REST API). Upon receiving the report, the MES can trigger preset process intervention procedures, such as: automatically pausing the current SMT production line; generating a repair work order and assigning it to the rework station; recording quality anomaly events to the SPC (Statistical Process Control) database; and feeding back to the pick-and-place machine feeding system to verify whether the material station configuration is incorrect.

[0094] Through the above mechanism, the present invention achieves intelligent identification of latent functional defects, significantly improving the efficiency and intelligence level of quality control in the electronic manufacturing process.

[0095] Figure 5 This is a system block diagram illustrating a component analysis system for a printed circuit board according to an exemplary embodiment. (Refer to...) Figure 5 The system may include: Image acquisition module 501 is used to acquire digital surface images of the printed circuit board under test; the digital surface images include visual information of multiple electronic components mounted on the printed circuit board under test; The identification and segmentation module 503 is used to input the digital surface image into the component identification and segmentation model for identification and segmentation processing to obtain the physical attribute information corresponding to each of the plurality of electronic components; the physical attribute information includes the type information of each electronic component, the edge contour information of each electronic component, and the spatial coordinate information of each electronic component. In one possible implementation, the segmentation identification module 503 includes: An instance mask generation unit is used to perform pixel-level semantic parsing processing on the digital surface image based on the component recognition and segmentation model to generate an instance mask for each electronic component. An edge contour information extraction unit is used to extract the edge contour information of each electronic component based on the instance mask. A spatial coordinate information determination unit is used to determine the spatial coordinate information of each electronic component based on the positional distribution of the instance mask in the image coordinate system. The type information determination unit is used to obtain the category probability distribution associated with each instance mask, and determine the highest priority category prediction result in the category probability distribution as the type information.

[0096] In one possible implementation, the segmentation identification module 503 includes: The actual physical property information acquisition unit is used to acquire the actual physical property information of the actual electronic components on the sample digital surface image and the real-time sample digital surface image. The digital surface image determination unit for the sample to be identified is used to perform image preprocessing on the digital surface image of the sample to obtain the digital surface image of the sample to be identified. The sample physical attribute information determination unit is used to input the sample digital image into the initial component recognition and segmentation model for recognition and segmentation processing to obtain sample physical attribute information corresponding to multiple sample electronic components; The component identification loss information determination unit is used to determine component identification loss information based on the actual physical attribute information corresponding to each of the actual electronic components and the sample physical attribute information corresponding to multiple sample electronic components. The training iteration unit is used to optimize the model parameters of the initial component recognition and segmentation model based on the component recognition loss information until a preset training iteration condition is met, and the initial component recognition and segmentation model that meets the preset training iteration condition is determined as the component recognition and segmentation model.

[0097] The target electronic component selection module 505 is used to select a target electronic component from the plurality of said electronic components; The layout relationship determination module 507 is used to determine the spatial layout relationship between the target electronic component and at least one associated electronic component within a preset neighborhood range based on the spatial coordinate information of the target electronic component. In one possible implementation, the layout relationship determination module 507 includes: A preset neighborhood range determination unit is used to determine the preset neighborhood range based on the type information of the target electronic component and the spatial coordinate information of the target electronic component; The candidate associated electronic component determination unit is used to determine other electronic components within the preset neighborhood range as candidate associated electronic components, centered on the spatial coordinate information of the target electronic component. The associated electronic component screening unit is used to screen out at least one associated electronic component from the candidate associated electronic components based on the positional relationship between the candidate associated electronic components and the target electronic component.

[0098] The functional semantic tag matching module 509 is used to match the functional semantic tag of the target electronic component from a preset circuit function knowledge base based on the type information of the target electronic component and the spatial layout relationship corresponding to the target electronic component; the functional semantic tag is used to characterize the circuit function of the target electronic component in the printed circuit board under test.

[0099] In one possible implementation, the functional semantic tag matching module 509 includes: A joint feature vector generation unit is used to perform feature encoding and fusion processing on the type information of the target electronic component and the spatial layout relationship corresponding to the target electronic component to generate a joint feature vector. The functional semantic matching result determination unit is used to perform similarity condition matching processing on the joint feature vector and multiple functional module features pre-stored in the preset circuit function knowledge base to obtain the functional semantic matching result; The functional semantic label determination unit is used to determine the preset functional semantic label associated with the functional module feature with the highest similarity as the functional semantic label corresponding to the target electronic component based on the functional semantic matching result.

[0100] In one possible implementation, the functional semantic tag matching module 509 includes: The expected function information determination unit is used to determine the expected function information corresponding to the target electronic component based on the functional semantic tag corresponding to the target electronic component; The function comparison result determination unit is used to compare the expected function information with preset physical state constraints and determine the function comparison result; A functional alarm instruction generation unit is used to determine that the target electronic component has a functional non-compliance when the functional comparison result indicates that the expected functional information does not meet the state constraint conditions, and to generate a functional alarm instruction.

[0101] In one possible implementation, the functional semantic tag matching module 509 includes: The component structured defect report generation unit is used to package the functional alarm instruction and the physical attribute information and functional semantic tags of the target electronic component that has the functional non-compliance to generate a component structured defect report. The process intervention triggering unit is used to push the structural defect report of the component to the human-machine interface for visualization and / or transmit it to the manufacturing execution system to trigger the process intervention process. Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0102] Figure 6 This is a block diagram illustrating an electronic device for component analysis of a printed circuit board according to an exemplary embodiment. The electronic device may be a terminal, and its internal structure diagram may be as follows: Figure 6As shown, the electronic device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a component analysis method for a printed circuit board. The display screen can be a liquid crystal display (LCD) or an e-ink display. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the device's casing, or an external keyboard, touchpad, or mouse.

[0103] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0104] Figure 7 This is a block diagram illustrating an electronic device for component analysis of a printed circuit board according to an exemplary embodiment. The electronic device may be a server, and its internal structure diagram may be as follows: Figure 7 As shown, the electronic device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a component analysis method for a printed circuit board.

[0105] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0106] In an exemplary embodiment, an electronic device is also provided, including: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement a component analysis method for a printed circuit board as described in the embodiments of this application.

[0107] In an exemplary embodiment, a computer-readable storage medium is also provided, which, when executed by a processor of an electronic device, enables the electronic device to perform the component analysis method for a printed circuit board according to the embodiments of this application. The computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, or optical data storage device, etc.

[0108] In an exemplary embodiment, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute the component analysis method for printed circuit boards in the embodiments of this application.

[0109] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0110] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0111] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for component analysis of a printed circuit board, characterized in that, include: Acquire a digital surface image of the printed circuit board under test; The digital surface image includes visual information of multiple electronic components mounted on the printed circuit board under test; The digital surface image is input into the component recognition and segmentation model for recognition and segmentation processing to obtain the physical attribute information corresponding to each of the multiple electronic components; the physical attribute information includes the type information of each electronic component, the edge contour information of each electronic component, and the spatial coordinate information of each electronic component; Select a target electronic component from the plurality of said electronic components; Based on the spatial coordinate information of the target electronic component, determine the spatial layout relationship between the target electronic component and at least one associated electronic component within a preset neighborhood range; Based on the type information of the target electronic component and the spatial layout relationship corresponding to the target electronic component, the functional semantic tag of the target electronic component is matched from the preset circuit function knowledge base; the functional semantic tag is used to characterize the circuit function of the target electronic component in the printed circuit board under test.

2. The component analysis method for printed circuit boards according to claim 1, characterized in that, The step of inputting the digital surface image into the component recognition and segmentation model for recognition and segmentation processing to obtain the physical attribute information corresponding to each of the multiple electronic components includes: Based on the component identification and segmentation model, pixel-level semantic parsing processing is performed on the digital surface image to generate an instance mask for each electronic component; Based on the instance mask, the edge contour information of each electronic component is extracted; Based on the positional distribution of the instance mask in the image coordinate system, the spatial coordinate information of each electronic component is determined; Obtain the category probability distribution associated with each instance mask, and determine the category prediction result with the highest priority in the category probability distribution as the type information.

3. The component analysis method for printed circuit boards according to claim 1, characterized in that, The training process of the component recognition and segmentation model includes: Acquire the actual physical property information of the actual electronic components on the sample digital surface image and the real-time sample digital surface image; The digital surface image of the sample is preprocessed to obtain the digital surface image of the sample to be identified; The sample digital surface image is input into the initial component recognition and segmentation model for recognition and segmentation processing to obtain sample physical attribute information corresponding to multiple sample electronic components; Based on the actual physical attribute information corresponding to each actual electronic component and the sample physical attribute information corresponding to multiple sample electronic components, component identification loss information is determined. The model parameters of the initial component recognition and segmentation model are optimized based on the component recognition loss information until a preset training iteration condition is met. The initial component recognition and segmentation model that meets the preset training iteration condition is then determined as the component recognition and segmentation model.

4. The component analysis method for printed circuit boards according to claim 1, characterized in that, Determining the spatial layout relationship between the target electronic component and at least one associated electronic component within a preset neighborhood range based on the spatial coordinate information of the target electronic component includes: The preset neighborhood range is determined based on the type information of the target electronic component and the spatial coordinate information of the target electronic component; Using the spatial coordinates of the target electronic component as the center, other electronic components within the preset neighborhood range are identified as candidate associated electronic components; Based on the positional relationship between the candidate associated electronic components and the target electronic component, at least one associated electronic component is selected from the candidate associated electronic components.

5. The component analysis method for printed circuit boards according to claim 1, characterized in that, The step of matching the functional semantic tags of the target electronic component from a preset circuit function knowledge base based on the type information of the target electronic component and the spatial layout relationship corresponding to the target electronic component includes: The type information of the target electronic component and the spatial layout relationship corresponding to the target electronic component are subjected to feature encoding and fusion processing to generate a joint feature vector; The joint feature vector and the features of multiple functional modules pre-stored in the preset circuit function knowledge base are subjected to similarity condition matching to obtain the functional semantic matching result. Based on the functional semantic matching results, the preset functional semantic label associated with the functional module feature with the highest similarity is determined as the functional semantic label corresponding to the target electronic component.

6. The component analysis method for printed circuit boards according to claim 1, characterized in that, The method further includes: Based on the functional semantic tags corresponding to the target electronic component, determine the expected functional information corresponding to the target electronic component; The expected functional information is compared with the preset physical state constraints to determine the functional comparison result; If the functional comparison result indicates that the expected functional information does not meet the state constraint conditions, it is determined that the target electronic component has a functional non-compliance, and a functional alarm command is generated.

7. The component analysis method for printed circuit boards according to claim 6, characterized in that, The method further includes: The functional alarm command, the physical attribute information of the target electronic component with the functional non-compliance, and the functional semantic tag are packaged together to generate a component structured defect report. The structural defect report of the component is pushed to the human-machine interface for visualization and / or transmitted to the manufacturing execution system to trigger process intervention.

8. A component analysis system for printed circuit boards, characterized in that, include: An image acquisition module is used to acquire a digital surface image of a printed circuit board under test; the digital surface image includes visual information of multiple electronic components mounted on the printed circuit board under test; The identification and segmentation module is used to input the digital surface image into the component identification and segmentation model for identification and segmentation processing to obtain the physical attribute information corresponding to each of the multiple electronic components; the physical attribute information includes the type information of each electronic component, the edge contour information of each electronic component, and the spatial coordinate information of each electronic component; A target electronic component selection module is used to select a target electronic component from a plurality of said electronic components; The layout relationship determination module is used to determine the spatial layout relationship between the target electronic component and at least one associated electronic component within a preset neighborhood range based on the spatial coordinate information of the target electronic component. The functional semantic tag matching module is used to match the functional semantic tags of the target electronic component from a preset circuit function knowledge base based on the type information of the target electronic component and the spatial layout relationship corresponding to the target electronic component; the functional semantic tags are used to characterize the circuit function of the target electronic component in the printed circuit board under test.

9. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the component analysis method for a printed circuit board as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is able to perform the component analysis method for a printed circuit board as described in any one of claims 1 to 7.

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