Adaptive electronic filter

Abstract

An adaptive electronic filter (200) includes a memristor-based filter circuit (201) for filtering an electrical input signal to obtain a filtered electrical signal. The adaptive electronic filter (200) further includes: a memristor-based subtractor circuit (202) for obtaining an error signal based on the filtered electrical signal and a reference signal; and an error minimization circuit (203) configured to provide adapted filter coefficients of the memristor-based filter circuit based on the error signal to minimize the error signal.

Description

Technical Field

[0001] The embodiments described herein relate to adaptive electronic filters and methods for filtering electrical signals. Corresponding computer programs and computer program carriers are also disclosed. Background Technology

[0002] Traditional electronic filters with fixed filter coefficients are typically designed for specific purposes, such as attenuation of all frequencies above a specific "cutoff" frequency within the input signal. In contrast, adaptive electronic filters have filter coefficients that are allowed to vary over time. Therefore, adaptive filters possess self-adjusting properties, allowing the filter to automatically adjust its coefficients via an adaptive algorithm to adapt to variations in its input signal. Adaptive filters are commonly used to adapt to environments with changing signals. Adaptive filters are typically used in the following environments:

[0003] • When there is spectral overlap between the signal and noise,

[0004] • In scenarios where filter characteristics need to be variable and adaptable to changing conditions, and

[0005] • If the frequency band occupied by noise is unknown or changes over time.

[0006] For example, when the interference noise level is very high and the noise spectrum overlaps with the spectrum of the desired signal, using a conventional filter with fixed filter coefficients to eliminate the interference will not preserve the spectrum of the desired signal.

[0007] Applications of adaptive filters include the following:

[0008] System identification

[0009] Adaptive filters can be used to solve general problems of system identification. For unknown systems, the quantities within the system cannot be observed externally. To identify the impulse response / function of an unknown system, a known signal x(n) is sent to the unknown system and an adaptive filter. The difference between the unknown signal and the output signal of the adaptive filter is then obtained by a subtractor, which is called the error signal. The error signal is fed back to the adaptive filter to adjust the filter coefficients. This process is repeated iteratively to reduce the error signal until a certain error signal level is reached. Finally, the frequency response of the filter converges to the frequency response of the unknown system, meaning that the unknown system can be identified.

[0010] Wireless channel estimation

[0011] The non-ideal nature of wireless channels distorts the transmitted signal. Where the effects of distortion can be modeled as a linear filter, adaptive filters can be used to simulate the effects of the channel. The underlying principle of this idea is similar to the previous use case, namely, "system identification."

[0012] • Echo cancellation for long-distance transmission

[0013] In voice communication across telephone networks, adaptive filters can be used to eliminate echoes caused by junction boxes known as hybrid junction boxes located near either end of the network link.

[0014] Acoustic echo cancellation

[0015] One issue related to echo cancellation in telephone transmission systems is acoustic echo cancellation used in conference speaker systems. After considering the speaker, callers want to increase the amplifier gain of both the microphone and the audio speaker to transmit and hear voice signals more clearly and with higher quality.

[0016] Adaptive noise cancellation

[0017] ○ Adaptive filters are used for adaptive noise cancellation in several applications, including electroencephalography (EEG) systems.

[0018] Adaptive Equilibrium

[0019] A common problem in wireless communication is signal distortion caused by the communication channel. Adaptive filters can create an inverse response to the distortion, thus removing the distortion from the received signal.

[0020] Interference suppression

[0021] Adaptive filtering is a powerful tool for suppressing narrowband interference in direct sequence spread spectrum receivers.

[0022] Linear predictor

[0023] ○ A linear predictor estimates the value of the signal at future times. This scheme is widely used in speech processing applications, such as speech coding, speech enhancement, and speech recognition in cellular phones.

[0024] Adaptive speech enhancement

[0025] Adaptive feedback cancellation in hearing aids

[0026] The challenge with adaptive filters lies in the fact that the level of parallelism can be limited due to feedback paths within their structure. For example, to parallelize and increase the processing speed of digital circuits, registers are often inserted into long computational paths. This increases the pipeline level in the circuit and improves throughput. However, this technique fails to function properly if the digital circuit includes feedback paths in its structure due to timing mismatch.

[0027] Moreover, as previously described, adaptive filtering is an iterative process, which reduces the throughput and latency of the adaptive filter. On the other hand, achieving a high-performance adaptive filter requires a large number of iterations. Therefore, balancing the throughput and performance of adaptive filters becomes a very challenging task.

[0028] Furthermore, high-performance adaptive filters require high-performance FIR / IIR filters, which are typically implemented with a large number of filter taps. This significantly increases the hardware complexity of such filters.

[0029] Furthermore, as the filter order increases, the critical path of the circuit—the path with the maximum delay between the input and output—also increases. Therefore, the filter's delay and throughput become constrained, leading to challenges in high-throughput and low-latency applications. Thus, the design of high-throughput and low-power digital filters is a bottleneck, especially for a large number of filter taps.

[0030] Furthermore, another challenge in adaptive filter design is the selection of error minimization algorithms used to tune the adaptive filter. Some of these algorithms are good in terms of performance / accuracy, but are very complex and expensive from a hardware implementation perspective. Simpler algorithms often suffer from low performance. Therefore, in the case of adaptive filter design, the trade-off between the complexity and performance of these algorithms is an issue. Summary of the Invention

[0031] The embodiments described herein disclose an adaptive electronic filter and a method for filtering electrical signals.

[0032] Specifically, embodiments herein disclose a memristor-based adaptive electronic filter and a method for filtering electrical signals using the memristor-based adaptive electronic filter. The disclosed memristor-based adaptive electronic filter uses in-memory computing (PIM) technology. All functional blocks within the memristor-based adaptive electronic filter can be implemented using an analog crossbar array. However, in some embodiments, a hybrid of analog crossbar arrays and circuits without memristors (such as digital circuits) can be used to implement different functions of the memristor-based adaptive electronic filter, such as error minimization.

[0033] Analog cross switch arrays (such as two-dimensional arrays) consist of M×N memristor devices, each of which can be programmed to represent an M-bit binary value.

[0034] According to the first aspect, the objective is achieved by an adaptive electronic filter, which includes a memristor-based filter circuit for filtering an electrical input signal to obtain a filtered electrical signal. The adaptive electronic filter further includes: a memristor-based subtractor circuit for obtaining an error signal based on the filtered electrical signal and a reference signal; and an error minimization circuit configured to provide adapted filter coefficients for the memristor-based filter circuit based on the error signal to minimize the error signal.

[0035] According to the second aspect, the objective is achieved by a method for filtering an electrical signal using an adaptive electronic filter, the adaptive electronic filter comprising a memristor-based filter circuit, a memristor-based subtractor circuit, and an error minimization circuit configured to provide filter coefficients of the memristor-based filter circuit based on an error signal to minimize the error signal.

[0036] The method includes: using a memristor-based filter circuit to filter the electrical input signal to obtain a filtered electrical signal.

[0037] The method also includes obtaining an error signal using a memristor-based subtractor circuit based on a filtered electrical signal and a reference signal.

[0038] The method also includes: adjusting the filter coefficients of the memristor-based filter circuit based on the error signal.

[0039] According to a further aspect, the purpose is achieved by a computer program comprising instructions that, when executed by a processor, cause the processor to perform the actions according to any of the foregoing aspects.

[0040] According to a further aspect, the purpose is achieved by a carrier of a computer program that includes the above aspects, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electrical signal, a radio signal, a microwave signal, or a computer-readable storage medium.

[0041] Memristor-based adaptive electronic filters are fully parallel architectures that achieve ultra-high throughput without requiring additional intermediate registers or buffers to increase speed. Because the adaptive electronic filter comprises a memristor-based filter circuit including an analog cross-switch array of memristor devices, it can process electronic signals in complete parallel. The cross-switch array according to embodiments herein enables the parallel execution of large-scale multiply-accumulate (MAC) operations. More specifically, the cross-switch array can compute matrix-vector multiplication (MVM) by calculating the dot product of the input vector applied to the cross-switch rows (i.e., word lines) and each column of the cross-switch (i.e., bit lines). This reduces latency and increases throughput.

[0042] Since the adaptive electronic filter includes a memristor-based filter circuit, different filter coefficients can be effectively updated by reprogramming the memristor devices of the memristor-based filter circuit based on the error signal from the memristor-based subtractor circuit.

[0043] Since the adaptive electronic filter includes a memristor-based filter circuit and a memristor-based subtractor circuit, no analog-to-digital or digital-to-analog conversion is required between the filter circuit and the subtractor circuit.

[0044] Since adaptive electronic filters comprise both memristor-based filter circuits and memristor-based subtractor circuits, and because memristor devices consume significantly less power compared to conventional multiply-accumulate (MAC) modules (such as digital MAC modules), the proposed PIM-based filter has the potential for low power / energy consumption, a critical requirement in many use cases, such as IoT devices. Lower power consumption can, in turn, lead to increased battery life in battery-powered devices, such as mobile phones.

[0045] The delay of a memristor-based adaptive electronic filter is limited only by the read cycle of the cross-switch array of the memristor-based filter circuit, and it is not limited by the filter order, type, etc.

[0046] Memristor-based adaptive electronic filters are computationally efficient because the computational complexity of the filter circuitry and other required components is reduced from O(N) to O(1), where N is the number of filter taps. This results in a significant reduction in the hardware complexity of the adaptive filter.

[0047] Memristor-based adaptive electronic filters offer complete flexibility in terms of filter order and filter coefficients.

[0048] Memristor-based adaptive electronic filters support the processing of complex-valued input samples and complex-valued filter coefficients without any reduction in the filter's throughput or performance.

[0049] Memristor-based adaptive electronic filters enable the realization of large adaptive filter banks, which include multiple filters with different filter orders and filtering characteristics.

[0050] Memristor-based adaptive electronic filters enable the realization of arbitrary frequency responses. Therefore, all the advantages mentioned above can be achieved regardless of the filter's impulse response.

[0051] Memristor-based adaptive electronic filters enable the effective implementation of various algorithmic functions listed above, such as wireless channel estimation, system identification, and noise cancellation. Attached Figure Description

[0052] In the figure, features appearing in some embodiments are indicated by dashed lines.

[0053] The various aspects of the embodiments disclosed herein (including their particular features and advantages) will be readily understood from the following detailed description and accompanying drawings, wherein:

[0054] Figure 1 This is a schematic block diagram illustrating a cross-switch array of memristors.

[0055] Figure 2 This is a schematic block diagram illustrating a memristor-based adaptive filter according to an embodiment of this document.

[0056] Figure 3 (a) is a block diagram schematically illustrating a portion of a memristor-based error minimization circuit according to an embodiment of this document.

[0057] Figure 3 (b) is a block diagram schematically illustrating a portion of a memristor-based error minimization circuit according to an embodiment of this document.

[0058] Figure 3 (c) is a block diagram schematically illustrating a portion of a memristor-based error minimization circuit according to an embodiment of this document.

[0059] Figure 3 (d) is a block diagram schematically illustrating a memristor-based error minimization circuit according to an embodiment of this document.

[0060] Figure 4 This is a flowchart illustrating an embodiment of a method for filtering electrical signals using a memristor-based adaptive filter.

[0061] Figure 5a This is a further flowchart illustrating an embodiment of a method for filtering electrical signals using a memristor-based adaptive filter.

[0062] Figure 5b This is a further flowchart illustrating an embodiment of a method for adjusting the filter coefficients of a memristor-based adaptive filter.

[0063] Figure 6 This is a schematic diagram illustrating further block diagrams of a memristor-based adaptive filter according to embodiments of this document.

[0064] Figure 7 This is a block diagram schematically illustrating the system settings used for system identification.

[0065] Figure 8 This is a block diagram schematically illustrating a memristor-based filter circuit according to an embodiment of this document.

[0066] Figure 9 This is a schematic diagram illustrating further block diagrams of a memristor-based adaptive filter according to embodiments of this document.

[0067] Figure 10 This is a schematic illustration of a further block diagram of a memristor-based filter circuit according to an embodiment of this document.

[0068] Figure 11 This is a schematic diagram illustrating further block diagrams of a memristor-based adaptive filter according to embodiments of this document.

[0069] Figure 12 This is a schematic illustration of a further block diagram of a memristor-based adaptive filter according to embodiments herein.

[0070] Figure 13 This is a block diagram schematically illustrating a baseband processor that can implement the embodiments described herein.

[0071] Figure 14 It is a schematic diagram showing the network nodes.

[0072] Figure 15 This is a block diagram schematically illustrating a wireless communication device, and

[0073] Figure 16 This is a block diagram schematically illustrating a wireless communication system. Detailed Implementation

[0074] The embodiments described herein relate to adaptive electronic filters. Adaptive filters may, for example, include finite impulse response (FIR) or infinite impulse response (IIR) filters, a subtractor circuit for obtaining an error signal, and circuitry for minimizing the error signal. In this way, the filter coefficients are tuned, and a desired filter response with target characteristics is achieved.

[0075] An FIR filter can be mathematically represented as:

[0076]

[0077] Furthermore, an IIR filter can be represented as

[0078]

[0079] in, It is the input sequence. It is the output of the filter. , , These are the coefficients of the corresponding filter, and N and M are the filter lengths, i.e., the number of filter taps.

[0080] In many use cases, the characteristics of a filter need to be modified and adapted under different system or environmental conditions. Adaptive filters are widely used in many applications, as listed above. In such applications, the filter coefficients can be determined during training sequences with known data patterns being transmitted.

[0081] Unlike many analog filters, the characteristics of digital filters can be easily altered by changing the filter coefficients. This makes digital filters attractive in adaptive filtering applications. A crucial part of digital filter design is the appropriate selection of filter coefficients and specifying the number of taps to achieve the desired frequency response (i.e., transfer function).

[0082] However, digital adaptive filters may be computationally inefficient due to the high computational complexity of the filter circuitry. Furthermore, delay and power consumption may be high.

[0083] More specifically, the embodiments described herein relate to memristor-based adaptive electronic filters, specifically adaptive electronic filters implemented using a cross-switch array of memristors. Memristors can also be referred to as memristor devices. Analog memristor devices have emerged as a novel technique for storing and processing information in the analog domain. These devices enable computation to be performed where data is stored. This concept, known as in-memory computing (or in-memory processing), eliminates the need to move data from memory to the processing unit. Different types of memristor devices exist, differing in the materials used, switching principles, device durability, retention, and other aspects. The main types of memristor devices include phase-change memory (PCM), resistive random access memory (ReRAM), spin-transfer torque magnetic RAM (STT-MRAM), and ferroelectric memristor devices (FeRAM). Memristor devices can support limited bit precision due to the limited number of conductance levels that can be reliably programmed within the device. For example, a PCM device can support approximately 50 conductance levels, meaning it can represent approximately 6 bits.

[0084] Multiple memristor devices can be organized to form an analog cross switch array. Figure 1 An electronic device 301, such as a baseband signal processor, is shown. It includes a memristor cross-switch array 310 that calculates the MVM by computing the dot product of the input vector applied to each row (i.e., word line) of the cross-switch and each column (i.e., bit line) of the cross-switch. The memristor cross-switch array 310 is a two-dimensional array comprising an M×N array of memristors 311, 312, 321, and 322, each of which can be programmed to represent an M-bit binary value. The memristors are tunable and programmable. A dielectric layer sandwiched between two electrodes may be included in the memristors. A unique feature of memristors is that their conductance depends on historical electrical signals, enabling them to function as non-volatile memory. Furthermore, memristors can store multi-bit information with continuously tunable conductance, equipping them with a higher bit density in contrast to the binary states "0" and "1" in conventional digital storage systems. Therefore, the m-bit binary value of a memristor can be set or programmed by applying current to the memristor. The binary value can depend on the amplitude of the current. Therefore, the binary word... Matrix G can be composed of... The memristor cross-switch array 310 represents a memristor. The input to the memristor cross-switch array 310 is an electronic input signal with multiple samples, such as a vector of M analog voltages corresponding to M binary values, for example, V.

[0085] The analog crossbar switch array includes parallel conductors, such as metal lines, referred to as word lines and bit lines, respectively, as electrodes of the memristors. The word lines and bit lines may be perpendicular to each other. Memristors are formed at the intersections of the word lines and bit lines. In the embodiments herein, the input conductors 331 of the analog crossbar switch array 310 correspond to the word lines, and the output conductors 332 of the analog crossbar switch array 310 correspond to the bit lines.

[0086] The analog crossbar array 310 computes the MVM by calculating the dot product of the input vector applied to the crossbar row (i.e., word line) and each column (i.e. bit line) of the crossbar, all of which is performed in the analog domain using Ohm's law for multiplication and Kirchhoff's law for accumulation.

[0087] exist Figure 1 In this process, entries of matrix G (an M×M matrix) are programmed into memristor devices 311, 312, 321, and 322 of the M×M crossbar switch array 310, while input vector V (an M×1 vector) is applied to the crossbar switch rows. Note that vector V corresponds to the actual input vector (input 1, ..., input M), which can be used... Figure 1One or more DAC modules 304 shown are used to convert the voltage to analog voltage. Therefore, the following MVM can be implemented using the cross switch array 310 shown.

[0088]

[0089]

[0090] Here, the output vector I is the output current of the cross-connected switch column, which is equal to the result of matrix-vector multiplication, i.e., I = G‧V. The output vector I can be used as follows: Figure 1 One or more ADC modules 305 shown are used to convert the data into corresponding binary words. This conversion can be performed individually for each crossbar switch column (i.e., one ADC for each binary word), or it can be performed in a time-multiplexed manner, thus reducing ADC overhead (i.e., multiple bit lines can share one ADC 305).

[0091] In this disclosure, vectors and matrices are represented using uppercase bold letters, while their entries are shown using normal letters.

[0092] Therefore, when the electronic input signal is a digital signal, the electronic device 301 further includes one or more DACs 304, which are adapted to convert the input signal with multiple samples into corresponding analog voltages V1, V2, ... V N .

[0093] In other words, when the input signal with multiple samples is a digital signal, the electronic device 301 may also include a DAC 304 configured to convert the digital input signal with multiple samples into an analog voltage.

[0094] Each input sample can have one DAC 304. In some other embodiments, since a DAC 304 can be shared among several input samples through multiplexing, each input sample can have fewer than one DAC 304. For example, two input samples can share the same DAC 304.

[0095] The output signal will be drawn from the bit line of the cross switch array 310 ( Figure 1 The output of the crossbar switch array 310 can be extracted from the columns in the array. If a digital output value is required, the output of the crossbar switch array 310 can be converted into a digital value. Therefore, the electronic device 301 may also include one or more ADCs 305 adapted to convert output samples including analog output currents into corresponding digital output values. In other words, the electronic device 301 may also include an ADC 305 configured to convert the output from the corresponding output wire into a digital signal.

[0096] If an analog signal is needed in the next block in the processing chain, then the ADC305 may not be necessary in the electronic device 301.

[0097] Furthermore, if the analog outputs are sent to another cross switch array, they can be converted into voltage signals, which can be done using resistors.

[0098] An embodiment of the PIM-based adaptive filter 200 will be about Figure 2 The embodiment of the adaptive filter 200 will be illustrated using an adaptive FIR filter. However, other types of filters, such as IIR filters, can also be implemented in a similar manner, as will be explained further below.

[0099] The goal of the adaptive filter 200 is to filter the input signal X[n] so that the filtered signal Y[n] matches the desired / target signal Z[n].

[0100] The adaptive electronic filter 200 includes a memristor-based filter circuit 201 for filtering an electrical input signal to obtain a filtered electrical signal. Specifically, the memristor-based filter circuit 201 may include one or more cross-switch arrays 210 of memristors 211, 212. Each memristor 211, 212 in the one or more cross-switch arrays 210 is configured to represent a corresponding filter coefficient of the filter function implemented as a filter matrix.

[0101] The adaptive electronic filter 200 also includes a memristor-based subtractor circuit 202 for obtaining an error signal based on the filtered electrical signal and a reference signal. The subtraction is based on a memristor. The memristor-based subtractor circuit 202 can also be referred to as an error calculation circuit 202.

[0102] The adaptive electronic filter 200 also includes an error minimization circuit 203, which is configured to provide adapted filter coefficients of the memristor-based filter circuit (201) based on the error signal to minimize the error signal. The error minimization circuit 203 can be memristor-based, i.e., error minimization can be performed using a memristor.

[0103] Therefore, the adaptive electronic filter 200 may also include a memristor-based error minimization circuit 203 to minimize the error signal. The error minimization circuit 203 may be adapted to generate an updated set of filter coefficients for the filter function.

[0104] exist Figure 3 (a) to Figure 3 (d) shows the details of the memristor-based error minimization circuit 203. Figure 3 (d) shows the complete error minimization circuit 203.

[0105] The error minimization circuit 203 can be adapted to minimize the error signal by calculating updated filter coefficients based on previous filter coefficients. The error minimization circuit 203 may include at least one memristor-based multiplier 203a, 203b, such as... Figure 3 (a) and Figure 3 As shown in (b), the error signal is multiplied by the input signal and the convergence factor. Therefore, the error minimization circuit 203 can provide the adjusted filter coefficients of the memristor-based filter circuit 201 based on the error signal and further based on the input signal.

[0106] At least one memristor-based multiplier 203a, 203b may include multiplicative memristors 203a, 2036b. The memristor-based multipliers 203a, 203b are suitable, for example, for the least mean square (LMS) error minimization algorithm.

[0107] The error minimization circuit 203 may also include an analog adder circuit 203c, such as... Figure 3 As shown in (c), the updated filter coefficients are calculated by adding the multiplied error signal to the previous filter coefficients, and at least one current-to-voltage converter 203d, 203e is operatively arranged between at least one memristor-based multiplier 203a, 203b and adder circuit 203c, such that the multiplied error information is converted into a voltage signal by the current-to-voltage converter 203d, 203e.

[0108] In some embodiments described herein, the adder circuit 203c is based on a memristor. That is, the addition function can be performed using a memristor.

[0109] In some embodiments herein, the adaptive electronic filter 200 further includes a first current-to-voltage converter 204 operatively arranged between the memristor-based filter circuit 201 and the memristor-based subtractor circuit 202, such that a filtered current signal is converted into a filtered voltage signal by the first current-to-voltage converter 204. The filtered voltage signal is then input to the memristor-based subtractor circuit 202.

[0110] The adaptive electronic filter 200 may further include a second current-to-voltage converter 205 operably arranged between the memristor-based subtractor circuit 202 and the memristor-based error minimization circuit 203, such that the current error signal is converted into a voltage error signal by the second current-to-voltage converter 205. The error voltage signal is then input to the memristor-based error minimization circuit 203.

[0111] All the current-to-voltage converters mentioned above can be implemented as resistors.

[0112] If a digital version of the filtered signal is needed as the output from the adaptive filter 200, an analog-to-digital converter (ADC) 208 can be used, such as... Figure 2 The dotted line in the middle depicts it.

[0113] Figure 4 A flowchart of a method for filtering an electrical signal according to an embodiment of this document is shown. The following method actions can be performed in any suitable order.

[0114] Action 400

[0115] The quantized filter coefficients corresponding to the target frequency response can be extracted. The frequency response of the target filter can be extracted, for example, by using Fast Fourier Transform (FFT), Z-transform, etc., to calculate the corresponding quantized filter coefficients.

[0116] You can specify the structure of the crossbar switch array required to implement the filter. For example, you can specify the number of filter coefficients.

[0117] Action 401

[0118] The method may also include configuring the memristor device of the adaptive electronic filter 200. The memristor device of the memristor-based filter circuit 201 can be configured according to matrix coefficients, i.e., according to the filter coefficients. Therefore, the vector / matrix of the filter coefficients will be programmed into the memristor of the filter circuit 201.

[0119] Action 402

[0120] The input samples can then be sent to the delay element 206 and the digital-to-analog converter (DAC) 207 of the adaptive electronic filter 200. The delay element 206 and DAC 207 can be part of a memristor-based filter circuit 201. The output voltage of DAC 207 will be applied to the crossbar switch. Note that in Figure 2 In this configuration, there is no delay element for the first filter coefficients. The delay element 206 can be implemented as a register. When the input is digital, the delay element 206 can be a digital delay element, such as a digital register.

[0121] The adaptive electronic filter 200 uses a memristor-based filter circuit 201 to filter the electrical input signal to obtain a filtered electrical signal.

[0122] The input signal X[n] will be filtered using a PIM-based filter circuit 201, and the filtered signal Y[n] will be generated as follows:

[0123] (3)

[0124] Here, N defines the filter length / order. As mentioned earlier, other filter types with different frequency responses can be used in a corresponding manner. For example, as described above, an IIR filter can be represented as:

[0125]

[0126] Action 403

[0127] The analog filtered signal generated at the cross switch column will be sent to the error calculation circuit 202.

[0128] Action 404

[0129] The error signal is calculated by comparing the filtered signal and the desired signal. Specifically, the desired signal Z[n] is subtracted from the filtered signal Y[n] to generate the error signal. This error signal is used as a reference to update the filter coefficients and generate a new set of coefficients. For this purpose, if the desired signal is a digital signal, it will be converted to a corresponding analog signal using a DAC module 509, which can be part of a memristor-based subtractor circuit 202 (error calculation circuit 202). The subtraction is then performed in the analog domain using the memristor-based subtractor circuit 202.

[0130] Action 405

[0131] The filter coefficients will be updated based on the calculated error. The error signal represents the difference between the filtered signal and the desired signal. The error signal can be minimized using several methods, such as the Least Mean Square (LMS) algorithm and the Recursive Least Squares (RLS) algorithm. Therefore, new filter coefficients will be generated, which will be programmed into the PIM-based filter circuit 201, as follows: Figure 2 As shown by the double arrows in the image.

[0132] This process will be repeated until the error signal falls below a certain threshold specified by the application.

[0133] Action 406

[0134] Once the error has been minimized, samples of the filtered signal can be converted to binary values ​​using an analog-to-digital converter (ADC) 208. Conversion to the digital domain is optional, such as... Figure 2 The dashed rectangle in the diagram is shown, and it depends on the application, i.e., whether an analog or digital filtered signal is required.

[0135] The process can be repeated for the next input sample sequence. If the size and type of the filter remain unchanged, there is no need to reprogram the cross-switch array of filter circuit 201. However, if the filter coefficients are changed for any reason, such as changing the filtering scheme, the cross-switch of filter circuit 201 can be programmed with a new coefficient vector / matrix.

[0136] Figure 5a A flowchart of a method for filtering an electrical signal using an adaptive electronic filter 200, according to an embodiment of this document, is shown. The adaptive electronic filter 200 includes a memristor-based filter circuit 201, a memristor-based subtractor circuit 202, and an error minimization circuit 203. This method can be performed by the adaptive electronic filter 200 or by an electronic device including the adaptive electronic filter 200. The following method actions can be performed in any suitable order.

[0137] Action 501

[0138] This method may include configuring the memristor device of the adaptive electronic filter 200. The memristor device of the memristor-based filter circuit 201 can be configured according to the matrix coefficients, i.e., according to the filter coefficients.

[0139] Action 502

[0140] The adaptive electronic filter 200 uses a memristor-based filter circuit 201 to filter the electrical input signal to obtain a filtered electrical signal.

[0141] Action 503

[0142] In some embodiments of this document, the filtered electrical signal is a current signal, and the method may further include converting the filtered current signal into a filtered voltage signal via a first current-to-voltage converter 204, the first current-to-voltage converter 204 being operatively arranged between a memristor-based filter circuit 201 and a memristor-based subtractor circuit 202. The filtered voltage signal is input to the memristor-based subtractor circuit 202.

[0143] Action 504

[0144] An error signal is obtained using a memristor-based subtractor circuit 202 based on the filtered electrical signal and the reference signal.

[0145] Action 505

[0146] In some embodiments of this document, the error signal is a current signal. The method may further include converting the current error signal into a voltage error signal via a second current-to-voltage converter 205, operatively arranged between a memristor-based subtractor circuit 202 and a memristor-based error minimization circuit 203. The error voltage signal is input to the memristor-based error minimization circuit 203.

[0147] Action 506

[0148] Based on the error signal, the filter coefficients of the memristor-based filter circuit 201 are adjusted. The filter coefficients of the memristor-based filter circuit 201 are adjusted to minimize the error signal. In some embodiments herein, the filter coefficients of the memristor-based filter circuit 201 are adjusted and the error signal is minimized using a memristor-based error minimization circuit 203.

[0149] Figure 5b This is a flowchart showing the details of action 506.

[0150] Action 506a

[0151] When the filter coefficients of the memristor-based filter circuit 201 are adjusted using the memristor-based error minimization circuit 203, the minimized error signal may include multiplying the error signal with the input signal and the convergence factor by at least one memristor-based multiplier 203a, 203b.

[0152] Action 506b

[0153] Then, adjusting the filter coefficients of the memristor-based filter circuit 201 may further include converting the multiplied error signal into a voltage signal by current-to-voltage converters 203d and 203e operably arranged between at least one memristor-based multiplier 203a, 203b and analog adder circuit 203c.

[0154] Action 506c

[0155] Adjusting the filter coefficients of the memristor-based filter circuit 201 may further include calculating updated filter coefficients by adding the multiplied error signal to the previous filter coefficients using adder circuit 203c.

[0156] The above steps can be repeated until the error signal falls below a certain threshold, which can be predefined based on the target application. When the error is acceptable, the filter is tuned, and the coefficients have converged to the solution. At this state, the filter output Y[n] is considered to be very close to the desired signal Z[n]. If the characteristics of the input data, environmental conditions, etc., change, the filter will adapt to the new conditions by generating a new set of coefficients.

[0157] Error minimization

[0158] In the context of adaptive filters, the tuning of filter coefficients can be based on minimizing the mean square error (MSE) between the filtered signal and the desired / target signal. The error signal can be mathematically represented as...

[0159] (5)

[0160] in, It is the desired / target signal, and It is a filtered signal.

[0161] Several algorithms have been proposed in the literature to perform error minimization. The most common adaptation algorithms are Recursive Least Squares (RLS) and Least Mean Squares (LMS). Compared with LMS, RLS can achieve a faster convergence speed, but it has high computational complexity. On the other hand, LMS has the advantages of low complexity and relatively good performance. Due to its lower computational complexity, LMS is most often used in the design and hardware implementation of adaptive filters.

[0162] The LMS algorithm works based on gradient search. The update process for the filter coefficients is performed via the following equation.

[0163] (6)

[0164] in, It is a coefficient The updated version, and It is the convergence factor, which has a value much less than 1 (it is proportional to the convergence rate and is set offline).

[0165] In the embodiments described herein, error minimization can be performed in the analog domain using a memristor-based error minimization circuit 203. However, digital adders and multipliers can also be used to implement the hardware for equation (6). Therefore, the calculation in (6) can be rewritten as follows:

[0166]

[0167] in, ,and Therefore, equation (7) can be calculated using two memristor-based multipliers 203a and 203b respectively. and And a memristor-based adder 203c is used to compute the updated coefficients. This is achieved by connecting all these small modules together via current-to-voltage converters 203d and 203e to realize the presented error minimization block 203.

[0168] Analog input signal

[0169] In some applications, the input signal to the adaptive filter 200, and therefore the desired / target signal, is an analog domain signal. In this case, a simple solution is to use an additional ADC to convert the input signal to the digital domain and then send it to... Figure 2 The filter shown is used to perform the filtering as previously described. Furthermore, if the desired signal (Z) is in the analog domain, the DAC module in the error calculation block will be removed.

[0170] In the case of analog domain input signals, some other embodiments of the adaptive filter 200 will now be discussed. Figure 6 As shown in the image. Used for Figure 6 The processing flow of the architecture in it is very similar to that used for Figure 2 The processing flow of the architecture is different. The difference lies in the architecture shown in Figure 5, where "time-shifting of samples" is performed using analog domain delay element 215 instead of digital delay. Therefore, since the input signal and the desired / target signal are already in the analog domain, all DAC modules can be removed from the adaptive filter 200, as shown in... Figure 6 middle.

[0171] Different implementations of analog domain delay have been proposed. In some embodiments herein, the analog domain delay element 215 includes a single-cycle time delay (OPTD), which can be created using simple analog circuitry. The OPTD block takes an input sample X[n] and produces X[n-1] (i.e., X[n] delayed by one cycle). Therefore, by connecting a series of such modules and applying X[n] to the input of the first module, all desired delayed versions of X[n] will be generated.

[0172] Figure 6 The output signal of the architecture is generated in the analog domain. However, if a filtered digital domain output signal is needed for any reason, an ADC can be used for that purpose, such as... Figure 6 As shown by the dashed line in the image.

[0173] It is worth mentioning that even if the input signal and the desired / target signal of the adaptive filter are in the digital domain, it can still be used. Figure 6 The architecture proposed in [the document], rather than Figure 2 The architecture in question. The only thing to consider is whether to use two DAC modules to convert the input signal and the desired / target signal from the digital domain to the analog domain.

[0174] therefore, Figure 6 The architecture supports the implementation of adaptive filters for all possible scenarios: digital input signals, analog input signals, digital output signals, and analog output signals.

[0175] System identification: wireless channel estimation, adaptive equalization, etc.

[0176] Adaptive filters are used in many applications, as mentioned above. One of the most important use cases for adaptive filters is "system identification".

[0177] System identification is a method for functional modeling of unknown systems. For this purpose, methods such as... Figure 7 The system setup shown is as follows. In this setup, an adaptive filter 701 is used in parallel with an unknown system 702, both of which receive the same signal X(n) as their input. The output signal of the unknown system to be identified is Z(n), and the output signal of the adaptive filter is Y(n). The goal is to find (i.e., estimate) the frequency response of the unknown system (i.e., the function of the unknown system). To this end, the coefficients of the adaptive filter should be adjusted such that the error between the two signals E(n) = Z(n) – Y(n) is below a certain threshold. This threshold is defined depending on the application.

[0178] Considering Figure 7 The settings in the diagram, where the amplitude of the error signal is minimized (e.g., when the mean square error (MSE) is minimized), mean that the filter represents the function of the unknown system and the filter's frequency response matches the frequency response of the unknown system.

[0179] Figure 7 The setup presented in the document enables the performance of several complex tasks, such as wireless channel estimation and adaptive equalization, which are key components in wireless communication systems.

[0180] PIM-based filter bank

[0181] There are several use cases where employing multiple filters with different frequency responses can be beneficial. This is because different filtering characteristics are required depending on the environment and system conditions. Furthermore, there are other use cases where multiple data / information streams are received in parallel and processed simultaneously. Therefore, in such cases, multiple filters with the same or different coefficients can be implemented in parallel.

[0182] Some embodiments in this paper are intended for filter banks using in-memory computation methods, such as multidimensional filter banks. Consider A filter bank consists of M filters, where N is the length of the largest filter in the filter bank. To implement such a filter bank using in-memory computation, a coefficient matrix can first be created. For this purpose, the quantized coefficients corresponding to each filter are considered as a separate column of this matrix. Therefore, we will obtain... The coefficient matrix, where the m-th column ( ) represents the coefficient of the m-th filter in the filter bank.

[0183] Note that the proposed scheme enables the implementation of filters with different lengths / orders. For example, if the m-th filter has L( If the length of the filter is given, then the first L entries in the m-th column of the matrix will represent L filter coefficients, and the remaining entries in the m-th column will be considered zero. Therefore, the filtering operation will be performed in parallel for M separate streams, where the length, order, and coefficients of these M filters can be the same or different.

[0184] Finally, the coefficient matrix will be programmed to a size of In the memristor of the crossbar switch array. The remaining process is related to... Figure 4 The process is similar to that described in the flowchart. The output of each filter is generated in parallel via the corresponding crossbar switch column.

[0185] The proposed filter bank is characterized by having fixed throughput and delay. This means that the output samples of all filters in the filter bank will be generated in parallel, and the throughput and delay of each filter are independent of the order and length of the other filters.

[0186] exist Figure 8 An example of this concept is shown in the figure. Figure 8 A filter bank implementing four different FIR filters is shown. The output sample of the j-th filter in the filter bank can be mathematically represented as...

[0187]

[0188] in, .

[0189] In some embodiments herein, filter circuitry 201 is adapted to operate as a filter bank, and then one or more cross-switch arrays 510 of memristors include a first memristor column 201-1 and a second memristor column 201-2. The memristor columns may be on the same cross-switch array or on different cross-switch arrays.

[0190] Each memristor in the first memristor column 201-1 is configured to represent a corresponding filter coefficient of a first filter function implemented as a filter matrix, and each memristor in the second memristor column 201-2 is configured to represent a corresponding filter coefficient of a second filter function implemented as a filter matrix. The second filter function may differ from the first filter function.

[0191] In some embodiments of this document, the number of second filter coefficients for the second filter function differs from the number of first filter coefficients for the first filter function, such that the number of second filter coefficients is greater than the number of first filter coefficients. However, the first memristors 211, 212 columns 201-1 may still include a first number of memristors equal to the second number of memristors in the second column 201-2. Then, at least one memristor in the first memristors 211, 212 columns 201-1 may be configured with a value equal to zero.

[0192] This is possible if the first column 201-1 and the second column 201-2 are two columns within a crossbar switch array, which means that the first column 201-1 and the second column 201-2 are connected together.

[0193] However, if the first column 201-1 and the second column 201-2 are implemented using two separate cross switches, then the first column 201-1 and the second column 201-2 can have different sizes (i.e., the number of memristors).

[0194] Another feature of the filter bank according to the embodiments herein is that it requires only one set of delay elements and one set of DACs. This means that the hardware cost incurred by the delay lines and DACs is the same in a single filter and in a filter bank with multiple filters.

[0195] Hardware sharing in filter banks

[0196] To further reduce the hardware cost of filter banks Figure 8 The ADC in the system can be shared across multiple columns. For example, in a filter bank with M filters, it can be used... An ADC to come in Generate all output samples of the filter bank within each read cycle.

[0197] Figure 9 An adaptive filter 200 including an adaptive filter bank 901 is shown according to an embodiment of this document. The proposed adaptive filter bank 901 includes a size of A filter bank, where each crossbar switch column is programmed with multiple coefficients. For example... Figure 9As shown, depending on the desired characteristics of the target adaptive filter, a multiplexer 216 is used to select the appropriate output signal. This multiplexer can be implemented using an analog switch, as described below.

[0198] A key advantage of using a filter bank 901 instead of a single filter within the adaptive filter is the more accurate initialization process, as described below. In the first iteration of the adaptive filtering process, multiple versions of the filtered signal are generated. These signals are subtracted from the desired / target signal, generating corresponding error signals. This allows it to be seen which set of filter coefficients (corresponding to the cross-switch column) results in lower error. Therefore, for the remainder of the filtering process, the selected cross-switch column is used, and its coefficients are updated as previously explained.

[0199] Therefore, the filtering process begins with a more accurate set of filter coefficients. This reduces the number of iterations and convergence time required to match the filtered signal to the desired / target signal. The remainder of the process is similar to the above, for example, regarding... Figure 2 The described process is similar.

[0200] Note that everything described above regarding the use of digital / analog delay elements, the required number of DACs / ADCs, and the types of input / output signals remains valid and can also be applied in the context of adaptive filter banks.

[0201] Therefore, in some embodiments herein, the adaptive electronic filter 200 further includes a multiplexer 216 operatively arranged between the filter circuit 201 and the subtractor circuit 202. The multiplexer 216 is adapted to multiplex filtered electrical signals from the filter circuit 201, which is adapted to operate as a filter bank, so that a single filtered electrical signal is obtained from the filter circuit 201.

[0202] PIM-based filters with real or complex input samples and real or complex coefficients.

[0203] The embodiments described below enable fully parallel implementation of PIM-based filters for real and complex input samples and for real and complex coefficients. Figure 10 An embodiment of a memristor-based filter circuit 201 adapted for real and complex input samples, and real and complex coefficients, is shown. This is the most general case. The memristor-based filter circuit 201 may include those with complex coefficients. An N-tap FIR filter. Figure 10 In the embodiment, the input sample It is a complex value. To implement this filter using PIM, a value of size can be used. A cross-switch array. Therefore, a memristor cross-switch array can comprise four columns. Note that these four columns can be within four separate cross-switch arrays or within two cross-switch arrays, such as... Figure 10 As shown. Two of the four columns are programmed using the real parts of the coefficients, while the other two columns are programmed using the imaginary parts of the coefficients. Figure 10 The first cross switch 221 of the two memristor columns, which are programmed with the real and imaginary parts of the coefficients respectively, receives the real part of the input, and the second cross switch 222 of the two memristor columns, which are programmed with the real and imaginary parts of the coefficients respectively, receives the imaginary part of the input.

[0204] exist Figure 10 In the code, the first and third columns are programmed using the real parts of the coefficients; they will receive and process the real and imaginary parts of the input samples, respectively. For example... Figure 10 As shown, columns two and four are programmed using the imaginary parts of the coefficients, and these two columns will process the real and imaginary parts of the input samples, respectively. Therefore, in Figure 10 In this embodiment, the first memristor column 201-RR is programmed with the real part of the coefficients and receives and processes the real part of the input sample. The second memristor column 201-RI is programmed with the imaginary part of the coefficients and receives and processes the real part of the input sample. The third memristor column 201-IR is programmed with the real part of the coefficients and receives and processes the imaginary part of the input sample. The fourth memristor column 201-II is programmed with the imaginary part of the coefficients and receives and processes the imaginary part of the input sample. If the input sample is only a real or complex number and the coefficient is complex, only two columns are needed, either the first and second columns or the third and fourth columns. If the coefficient is only a real or imaginary number and the input sample is complex, only two columns are needed, either the first and third columns or the second and fourth columns. Figure 10 The embodiments are able to handle all situations.

[0205] Filtering operations can be performed according to Figure 4 , Figure 5a and Figure 5b To execute any flowchart. Therefore, in Figure 10 In the most general case shown, four current signals will be generated, which can then be converted into voltage signals (e.g., using resistors).

[0206] like Figure 10 As shown, two memristor-based circuits (adder circuits) are designed to combine the output signals of a cross switch and generate the output of filter circuit 201. A current-to-voltage converter can then convert the output from the memristor-based adder circuits.

[0207] like Figure 10 As further shown, the adaptive filter 200 may include two multiplexers (e.g., analog switches) to select the appropriate output signal.

[0208] Therefore, in some embodiments herein, filter circuit 201 is adapted to filter complex electrical signals, or the filter coefficients are complex numbers, or both are complex numbers. Filter circuit 201 then includes at least two memristor columns 201-RR, 201-RI, 201-IR, 201-II, and may also include two multiplexers 231, 232 for selecting electrical signals from at least two memristor columns 201-RR, 201-RI, 201-IR, 201-II as filtered electrical signals.

[0209] The first multiplexer 231 can select electrical signals using a first selector Sel 1 based on the outputs from the second column 201-RI and the third column 201-IR, while the second multiplexer 232 can select electrical signals using a second selector Sel 2 based on the outputs from the first column 201-RR and the fourth column 201-II. The first multiplexer 231 can have three inputs: signals from the second column 201-RI and the third column 201-IR respectively, and a combination of signals from the second column 201-RI and the third column 201-IR. The second multiplexer 232 can have two inputs: a signal from the first column 201-RR, and a combination of signals from the first column 201-RR and the fourth column 201-II. Table 1 below shows all four possible configurations of the multiplexers. The choice of which configuration to use depends on whether the coefficients and / or the input samples are real or complex numbers.

[0210] Table 1. Different configurations of multiplexers that support real and complex inputs as well as real and complex coefficients.

[0211]

[0212] To combine outputs from different columns, the adaptive electronic filter 200 may also include two memristor-based adder circuits 241, 242, which are operatively arranged between at least two memristor columns 201-RR, 201-RI, 201-IR, 201-II and two multiplexers 231, 232.

[0213] In some embodiments herein, the adaptive electronic filter 200 further includes: a plurality of current-to-voltage converters 251, 252, 253, 254 operably arranged between at least two memristor columns 201-RR, 201-RI, 201-IR, 201-II and two memristor-based adder circuits 241, 242; and corresponding current-to-voltage converters 261, 262 operably arranged between corresponding adder circuits 241, 242 in the two memristor-based adder circuits 241, 242 and two multiplexers 231, 232.

[0214] The advantage of the above embodiments is that the outputs of the cross switch are combined in the analog domain, rather than being converted to digital values ​​and then addition / subtraction is performed. This reduces hardware costs and the number of ADCs required from four in the case of combining the cross switch outputs in the digital domain to two ADCs in the embodiments disclosed above. Furthermore, if an analog output signal is requested at the filter output for any reason, these two ADCs can be removed.

[0215] PIM-based filters with long length

[0216] While the actual size of a cross switch is large enough to implement many filtering schemes, sometimes the filter length is so large that it cannot be implemented using a single cross switch array. In such cases, the coefficient matrix can be divided into multiple smaller matrices, which can be programmed into multiple cross switch arrays.

[0217] For an FIR filter with a length of 64, in Figure 11 An example of this concept is shown, where the generator matrix is ​​divided into two parts, each of size 32, and then they are programmed into two smaller cross-switch arrays. Figure 11 In this embodiment, the integrator block is used to sum multiple current signals generated in different cross switches. However, other hardware can be used to sum the current signals. The output signal of the integrator block can be sent to the ADC module to generate binary value samples of the filtered signal.

[0218] PIM-based filter with bit serial input

[0219] The input samples of the adaptive filter 200 can be represented by multiple bits, which means that a high-resolution ADC and DAC may be required. The bit resolution of the supported ADC determines the quantization error; the higher the supported bit resolution, the lower the quantization error, and therefore the better the performance. Therefore, if the ADC 208 does not support the required resolution, or to improve performance, each input sample (which is a binary word) can be sent to the DAC 207 in a bit-serial manner. Thus, at each time point corresponding to the readout cycle of the crossbar switch array, one bit of all the input binary words is applied to the corresponding DAC 207.

[0220] exist Figure 12 An example embodiment of the FIR filter circuit 201 is shown. Figure 12 In this design, the flip-flop (FF) 271 is used as a delay element. Furthermore, since the input is bit-serial, a 1-bit DAC is used, which reduces hardware costs.

[0221] The computation is complete after W read cycles, where W is the number of bits in each input binary word (input sample). To compute the final result in the bit-serial scheme, the adaptive filter 200 may include a shift-adder circuit 281 operably arranged after the ADC 208.

[0222] PIM-based filters with coefficient slices

[0223] To improve the performance of filter circuit 201 and / or reduce hardware costs by using simpler and cheaper memristor devices, more than one memristor can be assigned to each coefficient of filter circuit 201. In other words, each filter coefficient can be divided into multiple parts, which can be programmed into multiple memristor devices in the crossbar of filter circuit 201. Therefore, each part of the filter coefficient can be programmed into a corresponding memristor.

[0224] For example, consider that each filter coefficient is represented by 8 bits, i.e., As explained above, the coefficient It is programmed into a memristor. However, in the coefficient slice scenario, the coefficients... It is programmed into more than one memristor. Assuming two memristors for each coefficient, then... It was programmed into the first memristor, and It can be programmed to a second memristor. Similar to the bit-serial input scenario, a shift-adder circuit is used to calculate the output samples of filter circuit 201 by combining the outputs of the corresponding crossbar switch columns.

[0225] As mentioned above, adaptive filters can be used in many applications. In particular, the adaptive filter 200 according to the embodiments herein can be used in various electronic devices. Figure 13 A baseband processor 1300 for example, used for wireless communication signals, is shown, which includes an adaptive filter 200. The adaptive filter 200 can, for example, filter the wireless communication signals. The baseband signal processor 1300 may include further baseband signal processing circuitry 1302, and the adaptive filter 200 may be adapted to be operatively coupled to the further signal processing circuitry 1302 of the baseband signal processor 1300. Therefore, an electronic device may include the adaptive electronic filter 200.

[0226] Figure 14 A network node 601 of a wireless communication network 170 is shown. The network node 601 includes an electronic device that includes an adaptive filter 200.

[0227] Figure 15 A wireless communication device 602 is shown, which includes electronic devices including an adaptive filter 200.

[0228] Network node 601 and wireless device 602 can be configured to perform the above. Figure 4 , Figure 5a and Figure 5b The method or action.

[0229] The embodiments described herein can be implemented using a processor or one or more processors, such as in Figure 15 and Figure 16 The processors 1504 and 1604 of the processing circuitry in the network node 601 and wireless device 602, respectively, are depicted together with computer program code for performing the functions and actions of the embodiments herein. The program code mentioned above can also be provided as a computer program product, for example, in the form of a data carrier carrying computer program code for executing the embodiments herein when loaded into the network node 601 and wireless device 602, respectively. One such carrier can be a CD-ROM. However, pages are feasible for other data carriers, such as memory sticks. Furthermore, the computer program code can be provided as plain program code on a server and downloaded to the network node 601 and wireless device 602, respectively.

[0230] Network node 601 and wireless device 602 may also include memories 1502 and 1602, respectively, which include one or more memory units. The memories include instructions executable by processors in network node 601 and wireless device 602, respectively.

[0231] The corresponding memories 1502 and 1602 are arranged to store, for example, information, data, configuration and applications, to execute the methods herein when executed in network node 601 and wireless device 602, respectively.

[0232] In some embodiments, computer programs 1503, 1603 include instructions that, when executed by at least one processor, cause at least one processor of network node 601 and wireless device 602 to perform the aforementioned actions, respectively.

[0233] In some embodiments, the carriers 1505 and 1605 include a computer program, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electrical signal, a radio signal, a microwave signal, or a computer-readable storage medium.

[0234] Network node 601 and wireless device 602 may also include input / output interface I / O 1506 and 1606, respectively, configured to communicate with other devices. Input / output interfaces 1506 and 1606 may include a receiver (such as a wireless receiver) (not shown) and a transmitter (such as a wireless transmitter) (not shown).

[0235] Those skilled in the art will also understand that the units described above can refer to a combination of analog and digital circuitry, and / or one or more processors configured with software and / or firmware, for example, stored in network node 601 and wireless device 602 respectively, when executed by the respective one or more processors (such as the processors described above). One or more of these processors, along with other digital hardware, may be included in a single application-specific integrated circuit (ASIC), or several processors and various digital hardware may be distributed among several separate components, either individually packaged or assembled into a system-on-a-chip (SoC).

[0236] Figure 16 A wireless communication network 170 that can implement the embodiments described herein is shown.

[0237] Wireless communication network 170 can use a variety of different technologies, such as Wi-Fi, LTE, LTE-Advanced, 5G, New Radio (NR), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications / Enhanced Data Rate GSM Evolution (GSM / EDGE), Global Microwave Access Interoperability (WiMax), or Ultra Mobile Broadband (UMB), to name just a few possible implementations. The embodiments in this document relate to recent technology trends of particular interest in the 5G context. However, the embodiments are also applicable to the further development of other existing wireless communication systems, such as WCDMA and LTE, and future wireless communication systems, such as 6G systems.

[0238] Network nodes operate in wireless communication network 170, such as network node 601. Network node 601 provides radio coverage for a geographic area, referred to as the service area of ​​cell 15, or a beam or beam group of a first radio access technology (RAT), such as 5G, LTE, Wi-Fi, etc. More than one cell may exist. For example, a second cell 16 may also exist. Network node 601 may be an NR-RAN node, a transmission and reception point (e.g., a base station), a radio access node (such as a wireless local area network (WLAN) access point or access point station (AP STA)), an access controller, a base station (e.g., a radio base station, such as NodeB, evolved Node B (eNB, eNode B), gNB), a base transceiver station, a radio remote unit, an access point base station, a base station router, a transmission arrangement of a radio base station, a stand-alone access point, or any other network element capable of communicating with wireless devices within the service area, depending on, for example, the radio access technology and terminology used. The corresponding network node 601 can be referred to as the serving radio access node, and communicates with the UE using the UE's downlink (DL) transmissions and uplink (UL) transmissions from the UE.

[0239] Multiple wireless communication devices operate in the wireless communication network 170, such as wireless communication device 602.

[0240] Wireless communication device 602 may be a mobile station, a non-access point (non-AP) STA, STA, user equipment, and / or wireless terminal that communicates via one or more access networks (ANs) (e.g., RANs), such as via network node 601, with one or more core networks (CNs) (e.g., including CN node 13, which may include access management functions (AMF)). Those skilled in the art will understand that "UE" is a non-limiting term that refers to any terminal, wireless communication terminal, user equipment, machine-type communication (MTC) device, device-to-device (D2D) terminal, or node, such as a smartphone, laptop, mobile phone, sensor, relay, mobile tablet, or even a small base station communicating within a cell.

[0241] When the words “include” or “contain” are used, they should be interpreted as non-restrictive, meaning “at least including”.

[0242] The embodiments described herein are not limited to the preferred embodiments described above. Various alternatives, modifications, and equivalents may be used.

Claims

1. An adaptive electronic filter (200), comprising: A memristor-based filter circuit (201) is used to filter an electrical input signal to obtain a filtered electrical signal. A memristor-based subtractor circuit (202) is used to obtain an error signal based on the filtered electrical signal and the reference signal; as well as An error minimization circuit (203) is configured to provide adapted filter coefficients of the memristor-based filter circuit (201) based on the error signal to minimize the error signal.

2. The adaptive electronic filter (200) of claim 1, wherein, The error minimization circuit (203) is based on memristors.

3. The adaptive electronic filter (200) of claim 2, wherein, The error minimization circuit (203) is adapted to minimize the error signal by calculating updated filter coefficients based on previous filter coefficients, and wherein the error minimization circuit (203) includes: At least one memristor-based multiplier (203a, 203b) is used to multiply the error signal with the input signal and the convergence factor; An analog adder circuit (203c) is used to calculate updated filter coefficients by adding the multiplied error signal to the previous filter coefficients; and At least one current-to-voltage converter (203d, 203e) is operatively arranged between the at least one memristor-based multiplier (203a, 203b) and the adder circuit (203c) such that the multiplied error signal is converted into a voltage signal by the current-to-voltage converter (203d, 203e).

4. The adaptive electronic filter (200) of claim 3, wherein, The adder circuit (203c) is based on memristors.

5. The adaptive electronic filter (200) according to any one of claims 1 to 4, further comprising: A first current-to-voltage converter (204) is operatively arranged between the memristor-based filter circuit (201) and the memristor-based subtractor circuit (202) such that a filtered current signal is converted by the first current-to-voltage converter (204) into a filtered voltage signal, which is then input to the memristor-based subtractor circuit (202).

6. The adaptive electronic filter (200) according to any one of claims 2 to 5, further comprising: A second current-to-voltage converter (205) is operatively arranged between the memristor-based subtractor circuit (202) and the memristor-based error minimization circuit (203) such that a current error signal is converted by the second current-to-voltage converter (205) into a voltage error signal, the error voltage signal being input to the memristor-based error minimization circuit (203).

7. The adaptive electronic filter (200) according to any one of claims 1 to 6, wherein, The memristor-based filter circuit (201) includes one or more cross-switch arrays (210) of memristors (211, 212), wherein each memristor (211, 212) in the one or more cross-switch arrays (210) is configured to represent a corresponding filter coefficient of the filter function implemented as a filter matrix.

8. The adaptive electronic filter (200) of claim 7, wherein, The filter circuit (201) is adapted to operate as a filter bank, and wherein the one or more crossbar arrays (210) of memristors comprises a first column (201-1) of memristors and a second column (201-2) of memristors, wherein each memristor in the first column (201-1) of memristors is configured to represent a respective filter coefficient of a first filter function implemented as a filter matrix, and wherein each memristor in the second column (201-2) of memristors is configured to represent a respective filter coefficient of a second filter function implemented as a filter matrix, wherein the second filter function is different from the first filter function.

9. The adaptive electronic filter (200) of claim 8, wherein, A second number of filter coefficients of the second filter function is different from a first number of filter coefficients of the first filter function, such that the second number of filter coefficients is greater than the first number of filter coefficients, and wherein the first column (201-1) of memristors (211, 212) comprises a first number of memristors equal to a second number of memristors of the second column (201-2).

10. The adaptive electronic filter (200) of claim 9, wherein, At least one memristor in the first column (201-1) of memristors (211, 212) is configured with a value equal to zero.

11. The adaptive electronic filter (200) according to any one of claims 7 to 10, further comprising: A multiplexer (216) is operatively arranged between the filter circuit (201) and the subtractor circuit (202), wherein the multiplexer (216) is adapted to multiplex the filtered electrical signal from the filter circuit (201) adapted to operate as a filter bank, such that a single filtered electrical signal is obtained from the filter circuit (201).

12. The adaptive electronic filter (200) according to any one of claims 1 to 11, wherein, The filter circuit (201) is adapted to filter a complex electrical signal, or wherein the filter coefficients are complex numbers, or both, and wherein the filter circuit (201) comprises at least two columns of memristors (201-RR, 201-RI, 201-IR, 201-II), and further comprises two multiplexers (231, 232) for selecting an electrical signal from the at least two columns of memristors (201-RR, 201-RI, 201-IR, 201-II) as the filtered electrical signal.

13. The adaptive electronic filter (200) according to claim 12, further comprising: two memristive adder circuits (241, 242) operatively arranged between the at least two columns of memristors (201-RR, 201-RI, 201-IR, 201-II) and the two multiplexers (231, 232).

14. The adaptive electronic filter (200) according to claim 13, further comprising: a plurality of current-to-voltage converters (251, 252, 253, 254) operatively arranged between the at least two columns of memristors (201-RR, 201-RI, 201-IR, 201-II) and the two memristive adder circuits (241, 242); and a plurality of current-to-voltage converters (251, 252, 253, 254) operatively arranged between the at least two columns of memristors (201-RR, 201-RI, 201-IR, 201-II) and the two memristive adder circuits (241, 242); and a respective current-voltage converter (261, 262) operably arranged between a respective one of the two memristor-based adder circuits (241, 242) and the two multiplexers (231, 232).

15. The adaptive electronic filter (200) according to any one of claims 2 to 14, wherein, The error minimization circuit (203) is adapted to generate an updated set of filter coefficients of the filter function.

16. An electronic device (400) comprising the adaptive electronic filter (200) according to any one of claims 1 to 15.

17. A network node (601) of a wireless communication network (170), the network node (601) comprising the electronic device according to claim 16.

18. A wireless communication device (602) comprising the electronic device according to claim 16.

19. A method (200) for filtering an electrical signal with an adaptive electronic filter (200) comprising a memristor-based filter circuit (201), a memristor-based subtractor circuit (202) and an error minimization circuit (203) configured to provide adapted filter coefficients of the memristor-based filter circuit (201) based on an error signal to minimize the error signal, the method comprising: filtering (502) an electrical input signal with the memristor-based filter circuit (201) to obtain a filtered electrical signal; obtaining (504) an error signal with the memristor-based subtractor circuit (202) based on the filtered electrical signal and a reference signal; and adapting (506) filter coefficients of the memristor-based filter circuit (201) based on the error signal.

20. The method of claim 19, wherein, Adapting (506) filter coefficients of the memristor-based filter circuit (201) is performed with a memristor-based error minimization circuit (203).

21. The method of claim 19 or 20, wherein, Minimizing (805) the error signal comprises: multiplying (805a) the error signal with the input signal and a convergence factor by at least one memristor-based multiplier (203a, 203b); converting (805b) the multiplied error signal into a voltage signal by a current-voltage converter (203d, 203e) operably arranged between the at least one memristor-based multiplier (203a, 203b) and an analog adder circuit (203c); and calculating (805c) an updated filter coefficient by adding the multiplied error signal with a previous filter coefficient by the adder circuit (203c).

22. The method of any of claims 19-21, further comprising: converting (802) the filtered electrical current signal into a filtered electrical voltage signal by a first current-voltage converter (204) operably arranged between the memristor-based filter circuit (201) and the memristor-based subtractor circuit (202), the filtered electrical voltage signal being input to the memristor-based subtractor circuit (202).

23. The method of any of claims 19-22, further comprising: A second current-to-voltage converter (205) operably arranged between the memristor-based subtractor circuit (202) and the memristor-based error minimization circuit (203) converts the current error signal (804) into a voltage error signal, which is then input to the memristor-based error minimization circuit (203).

24. A computer program (1503, 1603) comprising computer-readable code units that, when executed on a computer, cause the computer to perform the method according to any one of claims 19 to 23.

25. A carrier (1505, 1605) comprising the computer program according to the preceding claim, wherein The carrier (1505, 1605) is one of electronic signals, optical signals, radio signals, and computer-readable media.

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