An addressable test circuit and method of testing with multiple addressing modes

Abstract

This invention discloses an addressable test circuit and test method with multiple addressing modes, wherein: the addressing circuit connects to and controls the switching circuit, and the switching circuit connects to each unit under test in the DUT array; the addressing circuit includes an address input terminal, a decoding output terminal, and an enable control terminal, and the enable control terminal receives a prefix enable signal; the addressing circuit is configured to switch between the following two modes according to the state of the prefix enable signal: Prefix gating mode: when the prefix enable signal is at a first logic level, the decoding output terminal simultaneously generates gating signals for multiple units under test to select all units under test whose addresses are less than or equal to the input address; Precise addressing mode: when the prefix enable signal is at a second logic level, the decoding output terminal outputs only a single gating signal corresponding to the input address to select the corresponding unit under test.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor testing, specifically relating to an addressable test circuit and test method with multiple addressing modes. Background Technology

[0002] As CMOS technology nodes continue to shrink, the impact of random process variations on device performance becomes increasingly significant. Factors such as line edge roughness, random doping variations, and metal gate grain size can lead to significant performance differences in identical transistors, even causing circuit malfunctions and unstable power consumption. A large amount of data is needed for statistical modeling of random variations to ensure sufficient margins in circuit design. To accurately characterize these variations and assess their impact on performance, the traditional method of testing a transistor using four pads is too time- and area-intensive, necessitating a circuit capable of large-scale, rapid transistor testing. Currently, many works have designed test arrays to efficiently characterize transistor performance and reliability. By using address decoding circuits to control switching circuits, thousands of cells under test can be connected together with a limited number of pads, enabling simultaneous measurement and effectively improving testing efficiency.

[0003] Existing addressable test circuits typically use row and column decoders for addressing. After inputting a binary address, a corresponding strobe signal is generated, allowing only the single Device Under Test (DUT) corresponding to that address to be selected at any given time for applying stimulus or reading the response. However, in applications such as reliability testing, lifetime assessment, and stress screening, it is often necessary to apply sustained voltage, current, or temperature stress to a large number of DUTs within an array, and to statistically analyze performance drift and failure distribution during or before the voltage stress process. These tests are characterized by "long duration and batch processing." If stress is still applied serially, selecting only one DUT at a time, each DUT must be selected sequentially and the stress time must be waited for. The overall test duration will increase approximately linearly with the number of DUTs. When the array size is large and the single stress duration is long, the total test cycle can easily become excessively long, significantly reducing test throughput and affecting the feasibility of large-scale reliability assessments.

[0004] Therefore, existing technologies have significant limitations in scenarios requiring high efficiency and large-scale stress application. Even with external controllers to accelerate address scanning or optimize the test process, the parallelism of testing remains limited, as the decoding output is still a single gating, making it difficult to apply the same stress to multiple DUTs simultaneously to shorten the overall time. Therefore, an addressable circuit structure is needed that retains precise addressing capabilities while supporting parallel gating of multiple DUTs during the stress application phase. This would allow the test system to switch between single-point precision testing and multi-point parallel stress testing depending on the testing phase, thereby improving the efficiency and flexibility of large-scale reliability testing. Summary of the Invention

[0005] This invention provides an addressable test circuit and method with multiple addressing modes. While maintaining the ability to accurately select a single DUT by address, the circuit introduces enable control, allowing the same address to select either only the corresponding DUT or multiple DUTs covered by that address simultaneously. This enables parallel selection in tests requiring long-term stress application, shortens large-scale test time, and supports flexible DUT selection by row, column, and region.

[0006] The technical solution of the present invention includes:

[0007] A multi-addressable mode addressable test circuit, characterized in that it includes a multi-addressable mode addressing circuit, a switching circuit, and a DUT array; wherein:

[0008] An addressing circuit connects to and controls the switching circuit, which in turn connects to each unit under test (DUT) in the DUT array. The addressing circuit includes an address input, a decoding output, and an enable control terminal, the latter receiving a prefix enable signal. The addressing circuit is configured to switch between two modes based on the state of the prefix enable signal:

[0009] Prefix gating mode: When the prefix enable signal is at the first logic level, the decoder output terminal simultaneously generates gating signals for multiple test units to select all test units whose addresses are less than or equal to the input address;

[0010] Precise addressing mode: When the prefix enable signal is at the second logic level, the decoder output terminal outputs only a single strobe signal corresponding to the input address to select the corresponding unit under test.

[0011] A further improvement of the present invention is that the decoder in the addressing circuit includes equality determination logic and size comparison logic; the equality determination logic is used to generate an address equality determination signal; the size comparison logic is used to generate an address greater than determination signal; the decoder generates an address greater than or equal to determination signal by the equality determination logic and the size comparison logic; in the prefix gating mode, the decoder forms a decoding output based on the address greater than or equal to determination signal; in the precise addressing mode, the decoder forms a decoding output based on the address equality determination signal.

[0012] A further improvement of the present invention is that the size comparison logic adopts a bit-by-bit hierarchical comparison structure; the bit-by-bit hierarchical comparison structure is configured to use the high-bit priority principle, directly output the comparison result when the most significant bits are not equal, and recursively push to the low bits for comparison when the high bits are equal; the size comparison logic introduces an enable gate at the final stage to logically synthesize the comparison function with the prefix enable signal.

[0013] A further improvement of the present invention is that the addressing circuit further includes a mode switching unit, which is composed of a transmission gate or a complementary control multiplexing structure; the mode switching unit is configured to selectively transmit the decoding result of the prefix gating mode or the decoding result of the precise addressing mode to the decoding output terminal according to the logic state of the prefix enable signal.

[0014] A further improvement of the present invention is that the mode switching unit further includes an isolation unit; the isolation unit is configured to provide a predetermined safety level clamp to the decoded output node in the non-gated state to suppress output dangling, crosstalk coupling or leakage.

[0015] A further improvement of the present invention is that the addressing circuit of the multi-addressing mode includes a row decoder and a column decoder; the enable control terminal is introduced in the row decoder and / or the column decoder; the circuit supports configuring the row decoder and column decoder to achieve at least one of the following gating methods: row gating: selecting all test cells within the range from the starting row to the target row; column gating: selecting all test cells within the range from the starting column to the target column; region gating: selecting the set of test cells within the region defined by the starting row to the target row and the starting column to the target column.

[0016] This invention also provides a testing method based on the above circuit. During the parameter reading phase, the prefix enable signal is set to precise addressing mode, and point-by-point measurements are performed on the DUT under test. During the stress application phase, the prefix enable signal is switched to prefix gating mode, and the target address is used as the upper limit address for parallel gating, thereby simultaneously applying stress to multiple DUTs whose addresses are not greater than the target address. After the stress is applied, the system switches back to precise addressing mode, and point-by-point readings and failure analysis are performed on each DUT.

[0017] Compared with the prior art, the present invention has at least the following beneficial effects:

[0018] Firstly, without changing the original address encoding rules, only an enable control is added to switch between single-point selection and multi-point parallel selection, which is compatible with traditional addressable test circuits, requiring minimal modification and easy integration.

[0019] Secondly, during the stress application phase, multiple DUTs covered from the starting address to the target address can be selected simultaneously for parallel pressurization / stressing, changing the total test time from sequential accumulation to parallel coverage, thus significantly improving test efficiency.

[0020] Third, it supports three types of extended gating modes: by row, by column, and by region. It allows for flexible selection of the first few rows × first few columns or the first few rows × first few columns of DUT set according to testing needs, which facilitates rapid coverage and partition screening. Fourth, in precise mode, it still maintains the gating relationship of one address to one DUT, which can be used for single-point fine measurement and positioning analysis, avoiding the impact of parallel gating on the needs of precise testing. Attached Figure Description

[0021] Figure 1 This is a framework diagram of the addressable test circuit for multiple addressing modes of the present invention.

[0022] Figure 2 This is a schematic diagram of the multi-addressing mode switching principle of the present invention.

[0023] Figure 3 This is a schematic diagram illustrating the gating process of the present invention in precise addressing mode and prefix gating mode. Detailed Implementation

[0024] The present invention will now be described in detail with reference to embodiments and accompanying drawings. However, it should be understood that the embodiments and drawings are for illustrative purposes only and do not constitute any limitation on the scope of protection of the present invention. All reasonable modifications and combinations included within the inventive spirit of the present invention fall within the scope of protection of the present invention.

[0025] like Figure 1 , Figure 2 As shown, an embodiment of the present invention provides an addressable test circuit with multiple addressing modes, comprising: an addressing circuit, a switching circuit, and a DUT array. The addressing circuit with multiple addressing modes includes an address input terminal, a decoding output terminal, and an enable control terminal. The enable control terminal includes a prefix enable signal. When the prefix enable signal is high, the decoder operates in prefix gating mode, causing the decoding output terminal to simultaneously gating multiple DUTs, and the address range of the selected DUTs satisfies that its address is not greater than the input address. When the prefix enable signal is low, the decoder operates in precise addressing mode, causing the decoding output terminal to gating only a single DUT corresponding to the input address.

[0026] The decoder includes equality determination logic for generating an address equality determination signal and size comparison logic for generating an address greater than determination signal. The equality determination logic and the size comparison logic jointly generate an address greater than or equal to determination signal. The prefix gating mode forms a decoded output based on the address greater than or equal to determination signal, and the precise addressing mode forms a decoded output based on the address equality determination signal.

[0027] The decoder's size comparison logic is a bit-by-bit hierarchical comparison structure. It uses the high-bit priority principle to directly obtain the comparison result when the most significant bits are not equal, and recursively obtains the comparison result to the low bits when the high bits are equal. An enable gate is introduced in the final stage to realize the logic and synthesis of the comparison function and the external enable condition (prefix enable signal).

[0028] The decoder also includes a mode switching unit composed of a transmission gate or a complementary control multiplexing structure. This mode switching unit selectively transmits the decoding result of the prefix-gated path or the precise addressing path to the decoder output terminal under different logic states of the prefix enable signal. Based on the above logical description of the decoder, obtaining its RTL implementation is prior art in this field.

[0029] The mode switching unit includes an isolation unit that provides a predetermined safety level clamp to the decoded output node in the non-gated state to suppress false gating caused by output floating, crosstalk coupling or leakage.

[0030] like Figure 3 As shown, when the array size is N, the stress holding time of a single DUT is Ts, the single-point measurement time is Tm, and the address switching time is Tw, the total time of traditional serial stress testing is approximately N×(Ts+Tm+Tw), while the total time of parallel stress testing and point-by-point measurement using the present invention is approximately Ts+N×(Tm+Tw). Therefore, when Ts is significantly greater than Tm and Tw, the present invention can significantly shorten the total test cycle and improve test throughput. Taking a test array consisting of 1000 DUTs as an example, when Ts is 10 seconds, Tm is 20 milliseconds, and Tw is 1 millisecond, the total time of traditional serial stress testing is approximately 10021 seconds; using the method of applying stress in parallel first and then measuring point by point according to the present invention, the total time is approximately 31 seconds. The total test time can be shortened from approximately 2.78 hours to approximately 31 seconds, and the throughput is increased by approximately 323 times.

[0031] The above embodiments are merely preferred embodiments of the present invention, and the scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. An addressable test circuit with multiple addressing modes, characterized in that, This includes addressing circuits with multiple addressing modes, switching circuits, and a DUT array; among which: An addressing circuit connects to and controls the switching circuit, which in turn connects to each unit under test (DUT) in the DUT array. The addressing circuit includes an address input, a decoding output, and an enable control terminal, the latter receiving a prefix enable signal. The addressing circuit is configured to switch between two modes based on the state of the prefix enable signal: Prefix gating mode: When the prefix enable signal is at the first logic level, the decoder output terminal simultaneously generates gating signals for multiple test units to select all test units whose addresses are less than or equal to the input address; Precise addressing mode: When the prefix enable signal is at the second logic level, the decoder output terminal outputs only a single strobe signal corresponding to the input address to select the corresponding unit under test.

2. The addressable test circuit with multiple addressing modes according to claim 1, characterized in that, The decoder in the addressing circuit includes equality determination logic and size comparison logic; the equality determination logic is used to generate an address equality determination signal; the size comparison logic is used to generate an address greater than determination signal; the decoder generates an address greater than or equal to determination signal by the equality determination logic and the size comparison logic together; In the prefix selection mode, the decoder generates a decoding output based on the address being greater than or equal to the determination signal; In the precise addressing mode, the decoder generates a decoding output based on the address equality determination signal.

3. The addressable test circuit with multiple addressing modes according to claim 2, characterized in that, The size comparison logic adopts a bit-by-bit hierarchical comparison structure. The bit-by-bit hierarchical comparison structure is configured to use the high-bit priority principle, directly outputting the comparison result when the most significant bits are not equal, and recursively comparing the low bits when the high bits are equal. The size comparison logic introduces an enable gating at the final stage to logically synthesize the comparison function with the prefix enable signal.

4. The addressable test circuit with multiple addressing modes according to claim 1, characterized in that, The addressing circuit further includes a mode switching unit, which is composed of a transmission gate or a complementary control multiplexing structure; the mode switching unit is configured to selectively transmit the decoding result of the prefix gating mode or the decoding result of the precise addressing mode to the decoding output terminal according to the logic state of the prefix enable signal.

5. The addressable test circuit with multiple addressing modes according to claim 4, characterized in that, The mode switching unit further includes an isolation unit; the isolation unit is configured to provide a predetermined safety level clamp to the decoded output node in the non-gated state to suppress output dangling, crosstalk coupling or leakage.

6. An addressable test circuit for multiple addressing modes according to any one of claims 1 to 5, characterized in that, The addressing circuit includes a row decoder and a column decoder; the row decoder and / or the column decoder incorporates the enable control terminal; the circuit supports configuring the row decoder and column decoder to achieve at least one of the following gating modes: row gating: selecting all test cells within the range from the starting row to the target row; column gating: selecting all test cells within the range from the starting column to the target column; region gating: selecting the set of test cells within the region defined by the starting row to the target row and the starting column to the target column.

7. A method for stress testing a DUT array using an addressable test circuit with multiple addressing modes as described in any one of claims 1 to 6, characterized in that, The steps include: in precise addressing mode, initial parameter measurement is performed on the target unit under test; switch to prefix gating mode and input the corresponding target address into the addressing circuit to simultaneously gating multiple units under test within the range from the starting address to the target address, and apply stress to the multiple units under test in parallel; After the stress has been sustained for a predetermined duration, the system switches back to precise addressing mode to read parameters or determine failure for each of the multiple units under test.

8. The method according to claim 7, characterized in that, The stress includes gate voltage stress, current stress, temperature stress, or a combination thereof; the parameter readings include at least one of threshold voltage, leakage current, drive current, subthreshold swing, on-resistance, delay, or failure state.

9. The method according to claim 7 or 8, characterized in that, In prefix gating mode, stress is applied in parallel to the test cells in the entire row, column, or target area by configuring the working modes of the row decoder and column decoder.

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