A data access method, a memory controller, an electronic device, and a medium

Abstract

This disclosure provides a data access method, a memory controller, an electronic device, and a medium, relating to the field of chip technology. It includes: determining a first storage region in a memory cell of a dynamic random access memory (DRAM), the first storage region being used to store error detection and correction (ECC) data; responding to write command information corresponding to an access request, determining first ECC data corresponding to the write command information, the first ECC data being used to verify the write data corresponding to the write command information; storing the write data corresponding to the write command information and the first ECC data in the same first memory cell, the first ECC data being stored in the first storage region within the first memory cell. The method proposed in this disclosure, while ensuring data integrity, significantly reduces space overhead, row activation latency, and bandwidth usage, improving the effective bandwidth and access efficiency of DRAM.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a data access method, memory controller, electronic device, and medium. Background Technology

[0002] Dynamic Random Access Memory Error Correcting Code (DRAM ECC) is a technology that uses redundancy check codes to detect and correct errors in memory data. It is mainly used to improve system reliability, especially in critical areas such as servers, data centers, and automotive applications. Summary of the Invention

[0003] This disclosure provides a data access method, a memory controller, an electronic device, and a medium, and provides an Inline ECC (Inline Error Correction Code) bandwidth optimization scheme based on same storage row (ROW) binding and configurable storage.

[0004] A first aspect of this disclosure provides a data access method, comprising: determining a first storage region in a storage cell of a dynamic random access memory (DRAM), the first storage region being used to store error detection and correction (ECC) data; responding to write command information corresponding to an access request, determining first ECC data corresponding to the write command information, the first ECC data being used to verify write data corresponding to the write command information; storing the write data corresponding to the write command information and the first ECC data in the same first storage cell, the first ECC data being stored in the first storage region of the first storage cell.

[0005] In some embodiments of this disclosure, determining a first storage region in a storage cell of a dynamic random access memory (DRAM) includes: determining the maximum value of a bus command corresponding to an access request; determining a first space based on the maximum value of the bus command; determining a region of the first space in the storage cell as the first storage region, and determining a region outside the first space in the storage cell as a second storage region, wherein the second storage region is used to store write data.

[0006] In some embodiments of this disclosure, in response to the write command information corresponding to the access request, determining the first ECC data corresponding to the write command information includes: determining a user data write command and an ECC write command based on the write request in the write command information; determining the first ECC data based on the write data corresponding to the write request, wherein the ECC write command and the first ECC data are associated.

[0007] In some embodiments of this disclosure, storing the write data corresponding to the write command information and the first ECC data in the same first storage unit includes: determining the first storage unit corresponding to the write request based on the logical address corresponding to the write request in the write command information; determining the preset configuration corresponding to the write command information, wherein the preset configuration indicates the scheduling ratio of the write data and the first ECC data; storing the write data in the second storage area of ​​the first storage unit based on the scheduling ratio; and storing the first ECC data in the first storage area of ​​the first storage unit.

[0008] In some embodiments of this disclosure, the scheduling ratio of the preset configuration indication is greater than 8:1.

[0009] In some embodiments of this disclosure, the method further includes: responding to read command information corresponding to an access request, determining a second storage unit corresponding to the read command information; based on the read command information, reading user data corresponding to the read command information and second ECC data corresponding to the user data from the second storage unit; and based on the second ECC data, verifying and correcting the user data to determine the target user data.

[0010] In some embodiments of this disclosure, reading user data corresponding to the read command information and second ECC data corresponding to the user data from the second storage unit based on read command information includes: determining user data read command and ECC read command based on the read request in the read command information; reading second ECC data corresponding to the ECC read command from the first storage area in the second storage unit based on a preset configuration, and sequentially reading user data corresponding to at least one user data read command from the second storage area in the second storage unit.

[0011] In some embodiments of this disclosure, user data is verified and corrected based on the second ECC data to determine target user data, including: determining at least one user data corresponding to the second ECC data, wherein the second ECC data and the at least one user data conform to a preset configured scheduling ratio; and verifying and correcting each user data in the at least one user data based on the second ECC data to determine the target user data.

[0012] In the above embodiments, "co-unit data-ECC bound storage" achieves the following: at the storage level, space waste is reduced through dynamically configurable ECC regions; at the access level, additional row activation overhead is eliminated through co-unit layout; and at the transmission level, the proportion of ECC bandwidth is reduced through optimized scheduling. These three factors work synergistically to significantly improve the effective bandwidth and access efficiency of DRAM while ensuring data integrity and error correction capabilities, making it particularly suitable for high-end computing scenarios with stringent performance and reliability requirements.

[0013] A second aspect of this disclosure provides a memory controller, comprising: an address processing module, a command processing module, and a scheduling module. The address processing module is configured to determine a first storage region in a storage cell of a dynamic random access memory (DRAM), the first storage region being used to store error detection and correction (ECC) data. The command processing module is configured to, in response to a write command message corresponding to an access request, determine first ECC data corresponding to the write command message, the first ECC data being used to verify the write data corresponding to the write command message. The scheduling module is configured to store the write data corresponding to the write command message and the first ECC data in the same first storage cell, the first ECC data being stored in the first storage region within the first storage cell.

[0014] In some embodiments of this disclosure, the address processing module is used to: determine the maximum value of the bus command corresponding to the access request; determine a first space based on the maximum value of the bus command; determine a region of the first space in the storage unit as a first storage region, and determine a region outside the first space in the storage unit as a second storage region, wherein the second storage region is used to store write data.

[0015] In some embodiments of this disclosure, the command processing module is used to: determine a user data write command and an ECC write command based on the write request in the write command information; determine first ECC data based on the write data corresponding to the write request, wherein the ECC write command and the first ECC data are associated.

[0016] In some embodiments of this disclosure, the scheduling module is configured to: determine the first storage unit corresponding to the write request based on the logical address corresponding to the write request in the write command information; determine the preset configuration corresponding to the write command information, wherein the preset configuration indicates the scheduling ratio of write data and first ECC data; and, based on the scheduling ratio, store the write data in the second storage area of ​​the first storage unit and store the first ECC data in the first storage area of ​​the first storage unit.

[0017] In some embodiments of this disclosure, the scheduling ratio of the preset configuration indication is greater than 8:1.

[0018] In some embodiments of this disclosure, the memory controller further includes a verification module, an address processing module for determining the second storage unit corresponding to the read command information in response to the read command information corresponding to the access request, a scheduling module for reading the user data corresponding to the read command information and the second ECC data corresponding to the user data from the second storage unit based on the read command information, and a verification module for verifying and correcting the user data based on the second ECC data to determine the target user data.

[0019] In some embodiments of this disclosure, the scheduling module is used to determine user data read commands and ECC read commands based on read requests in read command information; based on a preset configuration, it reads second ECC data corresponding to the ECC read command from the first storage area in the second storage unit, and sequentially reads user data corresponding to at least one user data read command from the second storage area in the second storage unit.

[0020] In some embodiments of this disclosure, the verification module is used to determine at least one user data corresponding to the second ECC data, wherein the second ECC data and the at least one user data conform to the preset scheduling ratio; based on the second ECC data, each user data in the at least one user data is verified and corrected to determine the target user data.

[0021] In the above embodiments, the memory controller enables intelligent address mapping, efficient command scheduling, and parallel data processing. The controller adapts to different system requirements through built-in configurable registers, achieves collaborative processing of user data and ECC data through optimized pipeline design, and hides ECC check latency through prefetching and caching mechanisms. This hardware implementation makes ECC protection virtually transparent to upper-layer applications, providing robust data integrity while minimizing performance overhead, achieving a balance between reliability and high-performance access.

[0022] A third aspect of this disclosure provides a system-on-a-chip that integrates a memory controller as described in any one of the first aspects of this disclosure. The memory controller is used to access data in a dynamic random access memory (DRAM) based on an access request, the data access including data writing and data reading.

[0023] A fourth aspect of this disclosure provides an electronic device including: a processor and a memory for storing a computer program capable of running on the processor, wherein the processor, when running the computer program, performs the method described in any embodiment of the first aspect of this disclosure.

[0024] A fifth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the methods described in any of the embodiments of the first aspect of this disclosure.

[0025] A sixth aspect of this disclosure provides a program product including computer instructions for causing a computer to perform the methods described in any of the embodiments of the first aspect of this disclosure.

[0026] A seventh aspect of this disclosure provides a chip including at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method described in any one of the first aspects of this disclosure through logic circuits or executing code instructions.

[0027] In summary, the data access method, memory controller, electronic device, and media proposed in this disclosure systematically solve the performance bottleneck problem introduced by inline ECC technology in related technologies through a co-cell data-ECC bound storage architecture, combined with configurable region partitioning and an optimized command scheduling mechanism. The following improvements are achieved: at the storage level, space waste is reduced through dynamically configurable ECC regions; at the access level, additional row activation overhead is eliminated through co-cell layout; and at the transmission level, the proportion of ECC bandwidth is reduced through optimized scheduling. These three aspects work synergistically to significantly improve the effective bandwidth and access efficiency of DRAM while ensuring data integrity and error correction capabilities, further enhancing data access performance and reliability.

[0028] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0030] Figure 1 This is a schematic diagram of the ECC technical solution;

[0031] Figure 2 A schematic diagram of ECC command addresses and ECC data processing logic; Figure 3 This is a diagram illustrating the application scenarios of the publicly available data access method; Figure 4 This is a flowchart illustrating a data access method proposed in an embodiment of this disclosure; Figure 5 This is a flowchart illustrating another data access method proposed in an embodiment of this disclosure; Figure 6 This is a flowchart illustrating another data access method proposed in an embodiment of this disclosure; Figure 7A This is a schematic diagram of an Inline ECC bandwidth scheme; Figure 7B A schematic diagram of the address processing logic; Figure 8This is a schematic diagram of the structure of a memory controller according to an embodiment of the present disclosure; Figure 9 This is a schematic diagram of the structure of the electronic device proposed in the embodiments of this disclosure; Figure 10 This is a schematic diagram of the structure of a chip for implementing the above-described data access method, according to an exemplary embodiment. Detailed Implementation

[0032] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0033] In applications with extremely high system reliability requirements, such as servers, data centers, and automotive electronics, the integrity of memory data is paramount. Dynamic Random Access Memory (DRAM), due to its high density and volatility, may experience single-bit or multi-bit errors during operation due to factors such as particle impacts, electromagnetic interference, and process variations. To ensure data reliability, Error Correcting Code (ECC) technology is typically employed.

[0034] DRAM ECC technology achieves end-to-end error protection by generating redundant parity bits during data writing and performing verification and error correction during data reading. This includes protection of the transmission link between the controller and memory, as well as protection of the memory array itself. A typical SECDED (single error correction, double error detection) code can automatically correct single-bit errors, detect double-bit errors and errors in the parity bit itself, and partially detect three-bit and higher errors. To reduce additional requirements on DRAM chips and simplify design, Inline ECC technology was developed. This technology does not require dedicated ECC storage space in the DRAM chips; instead, it treats ECC verification data as regular data / normal data for transmission and storage. The basic process is as follows: during writing, the DRAM controller generates ECC data based on the normal data and writes both to the DRAM; during reading, the controller simultaneously retrieves the normal data and the corresponding ECC data for verification, achieving automatic correction of single-bit errors and alarm and recording of double-bit errors.

[0035] like Figure 1 The diagram shows a schematic of the ECC technology solution, taking the access of memory data by a System on Chip (SOC) as an example, including the following steps.

[0036] 1. Normal command and data caching: For access services from the upstream high-speed bus, the memory controller caches all read and write commands and write data.

[0037] 2. ECC Command and Data Generation: Based on the Normal read and write command information, the memory controller generates ECC read and write command information; based on the Normal write data, the memory controller generates the corresponding ECC data according to the ECC algorithm.

[0038] 3. Normal command sending: The memory controller first sends the Normal write command to the DRAM, and then transmits the Normal write data to the DRAM to complete the write data storage process; the memory controller first sends the Normal read command to the DRAM, then obtains the Normal read data from the DRAM, and returns the read data to the upstream high-speed bus.

[0039] 4. ECC command transmission: When the memory controller writes Normal write data to DRAM, it also requires ECC data to be transmitted to DRAM for storage; when the memory controller obtains Normal read data from DRAM, it also requires ECC data to be read out, complete the read data verification process, and return the verified read data to the upstream high-speed bus.

[0040] Figure 2 This diagram illustrates the ECC command address and ECC data processing logic. The processing logic is briefly described below.

[0041] 5. ECC command address generation: Based on the address information of the Normal read / write command, the memory controller generates the ECC command address information. In related technical solutions, after the read / write command is processed by address logic, the Normal data and the corresponding ECC data are stored in the same ROW. The storage areas of Normal data and ECC data are scattered and mixed together. After the introduction of ECC, the total number of ROWs accessed by DRAM increases.

[0042] 6. Each ROW reserves a portion of its address space to store ECC data. In the relevant technical solutions, the total space of each ROW is 2KByte, with a fixed high 256Byte reserved for storing ECC data.

[0043] 7. ECC Encoding and Decoding: When writing data according to Normal, the memory controller generates ECC data according to the ECC algorithm to complete the ECC encoding process; when reading data from Normal, ECC data is also required to be retrieved from DRAM, and the Normal data is verified according to the ECC algorithm to complete the ECC decoding process.

[0044] 8. In the relevant technical solution, Normal commands and ECC commands are centrally sent to DRAM, and eight Normal write commands and one ECC command are continuously scheduled to complete the storage process of Normal write data and ECC data. During read data calibration, after the memory controller schedules one ECC command, the acquired ECC data can be used for read data calibration operations of eight Normal read commands.

[0045] 9. A commonly used ECC algorithm is SECDED (single error correction, double error detection), which adds a global parity check bit to Hamming code, covering single-bit error correction, parity bit error detection, and double-bit error detection for all data bits. Hamming code is a linear error-correcting code primarily used to detect and correct single-bit errors occurring during data transmission or storage. By adding redundant parity bits, Hamming code can locate and correct erroneous bits.

[0046] However, inline ECC implementations have significant performance drawbacks. Since each read / write operation on normal data is accompanied by a corresponding ECC command and data transfer, this introduces additional command overhead and bandwidth consumption. Related technical solutions typically store normal data and its ECC data in the same storage row (ROW), but the storage layout often scatters and mixes their address spaces, resulting in accessing more ROWs when accessing the same batch of data, increasing the overhead of operations such as row activation. Meanwhile, while ECC command scheduling strategies (such as sending multiple normal commands followed by an ECC command) can partially optimize performance, they still cannot prevent a significant decrease in effective bandwidth. Furthermore, the storage space occupied by ECC data (such as a fixed 256 bytes reserved per ROW) is often based on a conservative design, failing to dynamically adapt according to the maximum transmission unit of the upstream bus or the optimal ratio of the ECC algorithm, leading to further waste of storage space and transmission bandwidth.

[0047] like Figure 3 The diagram illustrates an application scenario for the data access method disclosed herein. The System-on-a-Chip (SoC) includes a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), an Image Signal Processor (ISP), a Direct Memory Access Controller (DMA), a memory controller, and DRAM chips. The processor and controller can access data via a high-speed system bus. In critical applications such as servers, data centers, and automotive, in addition to high requirements for system data reliability, system access demands extremely high effective bandwidth for Double Data Rate (DDR) memory and also requires a certain degree of design flexibility.

[0048] Therefore, to address the aforementioned technical problems, this disclosure proposes a data access method. After address processing logic operations, the ECC address space reserved for each ROW is flexibly configurable, accommodating different requirements of upstream high-speed bus protocols and increasing design flexibility. Furthermore, after command processing logic operations, the bandwidth ratio of ECC commands to Normal commands can be further reduced, decreasing the proportion of ECC bandwidth and further increasing the effective bandwidth of DDR.

[0049] The data access method provided in this application will be described in detail below with reference to the accompanying drawings.

[0050] Figure 4 This is a flowchart illustrating a data access method proposed in an embodiment of this disclosure, as shown below. Figure 4 As shown, the method includes the following steps.

[0051] Step 401: Determine the first storage region of the storage cell in the dynamic random access memory (DRAM).

[0052] In some embodiments, the first storage area is used to store error detection and correction (ECC) data.

[0053] In some embodiments, the storage unit may be a ROW (row of storage) in DRAM.

[0054] In some embodiments, the DRAM has multiple storage cells, each of which stores write data for a write access request and corresponding ECC data. The ECC data is used for error detection and correction after the write data is retrieved.

[0055] In some embodiments, ECC data provides end-to-end protection for data access, including link-layer error protection during transmission and memory array error protection; it can prevent single-bit errors occurring between the controller and memory, or anywhere in memory, detect double-bit errors and parity bit errors, and partially detect three-bit and higher errors.

[0056] In some embodiments, determining the first storage area of ​​a storage cell in DRAM can be done by reserving a first storage area in each storage cell for storing ECC data, based on the maximum capacity of the upstream bus.

[0057] For example, for access requests from the upstream high-speed bus, the memory controller caches all read / write commands and write data. After address processing and command processing logic operations, the memory controller reserves an ECC address area and generates ECC command information and ECC data.

[0058] In some embodiments, determining a first storage region of a memory cell in DRAM includes: determining the maximum value of a bus command corresponding to an access request; determining a first space based on the maximum value of the bus command; determining a region of the first space in the memory cell as the first storage region, and determining a region outside the first space in the memory cell as a second storage region, wherein the second storage region is used to store write data.

[0059] In some embodiments, the maximum value of the bus command corresponding to the access request may be determined based on the maximum command transmission size of the upstream bus (such as 128B, 256B, or 512B).

[0060] In some embodiments, determining the first space based on the maximum bus command value can be based on the maximum command transmission size, combined with DRAM row alignment requirements, to calculate the minimum required space for the ECC data area (first storage area).

[0061] In some embodiments, a region of the first space within the memory cell is defined as the first storage region, and the region outside the first space within the memory cell is defined as the second storage region. This can be achieved by dividing the total space (e.g., 2KB) of each DRAM physical row (ROW) into two parts: a user data area with a fixed starting address (the second storage region) and an immediately following ECC data area. This mapping is written into the configuration register or mapping table of the memory controller.

[0062] In some embodiments, the size of the first storage area for storing ECC data is not fixed, but configured according to the capabilities of the actual system bus, thus avoiding waste of storage space.

[0063] In the above embodiments, the size of the ECC storage area is dynamically determined based on the maximum command value of the upstream bus, so that the storage space configuration is precisely matched with the system interface characteristics, avoiding the waste of space caused by fixed reservation and improving the utilization rate of DRAM storage space.

[0064] Step 402: In response to the write command information corresponding to the access request, determine the first ECC data corresponding to the write command information.

[0065] In some embodiments, the first ECC data is used to verify the write data corresponding to the write command information.

[0066] In some embodiments, when the access request is a write access request, the write access request includes write command information, the write command information includes write data, and the first ECC data determined based on the write command information corresponding to the access request can be used to verify the write data in the write command information.

[0067] In some embodiments, in response to write command information corresponding to an access request, determining the first ECC data corresponding to the write command information includes: determining a user data write command and an ECC write command based on the write request in the write command information; determining the first ECC data based on the write data corresponding to the write request, wherein the ECC write command and the first ECC data are associated.

[0068] In some embodiments, based on the write request in the write command information, ECC write command information corresponding to the write command information can be generated, which includes generating a user data write command based on the write request, as well as an ECC write command.

[0069] Specifically, after receiving a write access request from the upstream bus, the memory controller first parses the request. The write command information includes: target logical address, data length, data buffer pointer, etc. Based on a preset ECC protection granularity (e.g., generating a set of ECC codes for every 256 bits of user data), the memory controller internally splits the original single write request into two logically related sub-operations: a user data write command and an ECC write command. The user data write command is used to write user data to the user data area of ​​the DRAM. The ECC write command is used to write the calculated checksum data (ECC data) to the ECC data area of ​​the DRAM.

[0070] Specifically, the user data area is the second storage area, and the ECC data area is the first storage area.

[0071] In some embodiments, based on the write data corresponding to the write request, and according to the ECC calculation method, corresponding first ECC data is generated. This can be achieved by reading the user data to be written, calculating according to the selected ECC algorithm (such as SECDED), and generating the corresponding check bits, i.e., "first ECC data". The first ECC data strictly corresponds to the specific user data block in terms of content.

[0072] In some embodiments, the calculation of ECC data generated based on write requests may adopt any calculation method in the related technologies or any calculation method in the future related fields, and this disclosure does not limit it.

[0073] For example, based on the Normal read / write command information, the memory controller generates ECC read / write command information; based on the Normal write data, according to the ECC algorithm, the memory controller generates the corresponding ECC data.

[0074] In some embodiments, after generating the first ECC data, the memory controller establishes and maintains an association between the "ECC write command," the "first ECC data," and the original "user data write command." This association is typically achieved through an internal identifier (ID), a pointer to the same source address, or a shared metadata tag, ensuring that the two can be correctly paired and processed during subsequent scheduling, transfer, and storage.

[0075] In the above embodiments, by generating user data commands and ECC commands associated with the same write request, and generating ECC check bits based on the actual write data, the synchronization and accuracy of data integrity protection are ensured, and the command management logic is simplified.

[0076] Step 403: Store the write data corresponding to the write command information and the first ECC data in the same first storage unit.

[0077] In some embodiments, the first ECC data is stored in a first storage area within a first storage unit.

[0078] In some embodiments, the write data corresponding to the write command information and the first ECC data are stored in different areas of the first storage unit, that is, the associated original data and verification data are stored in the same storage unit, avoiding the need to read user data and ECC data from different storage units separately during the reading process.

[0079] In some embodiments, when an access request is received, the memory controller parses the logical address and command type in the request. The logical address is then translated into a physical address using an address mapping engine; that is, user data is always mapped to the user data area (second storage area); its corresponding ECC data is mapped to a specific location within the ECC data area (first storage area) of the same storage unit by calculating an index.

[0080] Specifically, for write operations, user data and ECC data are generated simultaneously and stored in the corresponding areas; for read operations, both are read in parallel from the same storage unit for verification.

[0081] For example, the memory controller stores both Normal write data and ECC data in DRAM. When waiting to retrieve Normal read data from DRAM, it also requests ECC data to be retrieved from DRAM. According to the ECC algorithm, the memory controller verifies the Normal data and returns the verified read data to the high-speed bus.

[0082] In the above embodiments, by forcing user data and its ECC data to be stored in the same DRAM storage unit, the additional storage unit activation operation caused by ECC data access is eliminated, which fundamentally reduces row switching latency and power consumption and improves storage access efficiency.

[0083] Figure 5 This is a flowchart illustrating another data access method proposed in an embodiment of this disclosure, based on... Figure 4 The illustrated embodiments, such as 5 pairs Figure 4 Step 403 in the text will be further explained, such as... Figure 5 As shown, the steps include the following.

[0084] Step 501: Based on the logical address corresponding to the write request in the write command information, determine the first storage unit corresponding to the write request.

[0085] In some embodiments, based on the logical address corresponding to the write request in the write command information, a first storage unit can be determined in at least one storage unit in the DRAM. The first storage unit is used to store the write data corresponding to the write request and the ECC data associated with the write data.

[0086] In some embodiments, determining the first storage unit based on a logical address can involve storing the write data of multiple write command messages with the same logical address in the same storage unit. In other words, user data from the same logical address will be stored in the same storage unit, and ECC data associated with the user data will also be stored in the same storage unit.

[0087] In the above embodiments, by performing specific mapping processing on logical addresses, it is ensured that write data and ECC data can be stored in the same physical ROW.

[0088] Step 502: Determine the preset configuration corresponding to the write command information.

[0089] In some embodiments, a preset configuration indicates the scheduling ratio of write data to first ECC data.

[0090] In some embodiments, the preset configuration may be a pre-configured scheduling ratio used to determine the ratio of write data to ECC data.

[0091] In some embodiments, the scheduling ratio can be determined based on the minimum value calculated using the ECC method.

[0092] For example, in order to minimize performance waste and maximize effective bandwidth, the ratio of ECC data to Normal data is implemented according to the minimum value of the ECC algorithm. For example, the SECDED algorithm supports 256 bits of Normal data and 10 bits of ECC data, so the bandwidth ratio of ECC commands is reduced to 1 / 16.

[0093] In some embodiments, the scheduling ratio can be set according to the actual scenario or needs, for example, it can be set to 10:1, or 12:1, etc., and this disclosure does not limit it.

[0094] In some embodiments, the scheduling ratio indicated by the preset configuration is greater than 8:1.

[0095] In the above embodiments, by setting a user data to ECC data scheduling ratio greater than 8:1, the storage space and transmission bandwidth occupied by ECC data are significantly reduced, thereby minimizing ECC overhead and maximizing effective bandwidth.

[0096] Step 503: Based on the scheduling ratio, the write data is stored in the second storage area of ​​the first storage unit, and the first ECC data is stored in the first storage area of ​​the first storage unit.

[0097] In some embodiments, based on the scheduling ratio, storing write data in the second storage area and storing the first ECC data in the first storage area can be done according to an 8:1 scheduling ratio, that is, storing 8 write data entries in the second storage area and storing 1 ECC data entry in the first storage area. In other words, the stored ECC data entry is associated with 8 write data entries and can be used to verify these 8 write data entries when they are retrieved.

[0098] In some embodiments, the ratio of the size of the first storage area used to store ECC data to the size of the second storage area in the first storage unit is independent of the scheduling ratio of write data and ECC data, which can satisfy the requirements of the bus interface protocol and achieve the maximum effective bandwidth and minimize the proportion of ECC bandwidth.

[0099] In the above embodiments, user data and ECC data are arranged in an orderly manner within the physical storage unit according to the logical address mapping and configurable scheduling ratio, establishing a definite storage structure for subsequent efficient access and realizing optimized organization of storage space.

[0100] Figure 6 This is a flowchart illustrating another data access method proposed in an embodiment of this disclosure, based on... Figures 4-5 The illustrated embodiments, such as 6, will be further described as follows: Figure 6 As shown, the steps include the following.

[0101] Step 601: In response to the read command information corresponding to the access request, determine the second storage unit corresponding to the read command information.

[0102] In some embodiments, when the access request is a read access request, the read request in the read command information is determined based on the read command information. The memory controller finds and locates the physical DRAM storage row (ROW) where the user data to be read is located, i.e., the second storage unit, through the address mapping engine according to the logical address of the read request.

[0103] Step 602: Based on the read command information, read the user data corresponding to the read command information and the second ECC data corresponding to the user data from the second storage unit.

[0104] In some embodiments, based on read command information, user data stored in the second storage unit can be retrieved, and second ECC data associated with the user data can be retrieved. This allows user data and ECC data for verifying user data to be retrieved by accessing only one storage unit, avoiding the need to access multiple storage units.

[0105] Specifically, the memory controller receives a read request from the upstream bus. This request includes at least: Logical start address: the starting position of the data to be read in the system address space; Data length (or burst length): the number of bytes to be read consecutively. The key fields for addressing are extracted from the logical address of the read command. The address mapping unit inside the controller uses the exact same mapping rules as for write operations to convert the logical ROW index into a physical ROW address. Once the physical ROW address is determined, that physical ROW is identified as the second memory location for this read operation.

[0106] Furthermore, the memory controller checks whether the second storage cell is activated (i.e., whether the data is already in the row buffer). If it is not activated, an activation command must first be sent to the DRAM to activate the second storage cell.

[0107] In some embodiments, reading user data corresponding to the read command information and second ECC data corresponding to the user data from the second storage unit based on read command information includes: determining user data read command and ECC read command based on read requests in the read command information; reading second ECC data corresponding to the ECC read command from the first storage area in the second storage unit based on a preset configuration, and sequentially reading user data corresponding to at least one user data read command from the second storage area in the second storage unit.

[0108] In some embodiments, determining the user data read command and the ECC read command based on the read request in the read command information can be achieved by the memory controller internally splitting the read request into two related sub-commands: a user data read command, responsible for reading the original user data from the second storage area (user data area) of the second storage unit; and an ECC read command, responsible for reading the corresponding verification data (i.e., "second ECC data") from the first storage area (ECC data area) of the same second storage unit.

[0109] Specifically, because user data and its ECC data are pre-stored in different fixed areas within the same storage unit, the memory controller knows that to complete a full read operation with verification, it must retrieve data from both areas separately.

[0110] In some embodiments, based on a preset configuration, reading the second ECC data corresponding to an ECC read command from the first storage area in the second storage unit, and sequentially reading the user data corresponding to at least one user data read command from the second storage area in the second storage unit, can be based on a scheduling ratio indicated by the preset configuration, and reading user data and ECC data from different areas of the same storage unit respectively.

[0111] In some embodiments, the default configuration defines the protection granularity ratio between ECC data and user data blocks (e.g., 1 copy of ECC data protects 8 copies of user data). Therefore, a copy of the second ECC data obtained by a single ECC read command can be used to verify the user data returned by subsequent consecutive user data read commands.

[0112] Specifically, the memory controller first calculates the exact storage address of the second ECC data in the second storage unit, sends an ECC read command to the DRAM, and reads the second ECC data from the calculated address. Simultaneously or shortly thereafter, the memory controller calculates the address of the user data within the second storage unit. Based on the data volume of the read request corresponding to a preset scheduling ratio, the memory controller generates one or more user data read commands, sequentially reading the required user data blocks from the corresponding locations in the second storage area.

[0113] For example, the "ECC read command" and the "at least one user data read command" are internally associated and bound. They share the same ID and point to the same physical ROW. The memory controller knows that the ECC data just read is used to verify the next batch of user data to be read.

[0114] In the above embodiments, by separating the scheduling of user data read commands and ECC read commands, and reading them in an orderly manner from different areas of the storage unit based on preset configuration, the command execution pipeline is optimized, and the parallel utilization of the command bus and data bus is improved.

[0115] Step 603: Based on the second ECC data, verify and correct the user data to determine the target user data.

[0116] In some embodiments, at least one user data read from the second storage area of ​​the second storage unit is verified and corrected by the second ECC data to determine at least one target user data.

[0117] In some embodiments, based on the second ECC data, user data is verified and corrected to determine target user data, including: determining at least one user data corresponding to the second ECC data, wherein the second ECC data and at least one user data meet a preset scheduling ratio; and based on the second ECC data, each user data in the at least one user data is verified and corrected to determine target user data.

[0118] In some embodiments, determining at least one user data corresponding to the second ECC data may be achieved by pairing the second ECC data read from the first storage area with one or more user data read from the second storage area, i.e., the pairing ratio is the write ratio in the process of writing user data into the storage unit.

[0119] Specifically, when writing data, there are 8 write data entries corresponding to 1 ECC data entry; when retrieving data, there are 8 user data entries corresponding to 1 ECC data entry.

[0120] For example, the memory controller first correctly pairs the second ECC data it reads with at least one user data record retrieved from its internal buffer. The pairing is based on a preset scheduling ratio (e.g., 1 copy of ECC data protects 8 copies of user data). Based on this ratio, the controller knows which consecutive user data records the current ECC data record corresponds to.

[0121] In some embodiments, based on the second ECC data, each user data in at least one set of user data is verified and corrected to determine the target user data. This can be achieved after pairing, where the ECC verification engine starts working and performs the following operations sequentially on each user data: Verification: The user data and the second ECC data are input into a verification algorithm (such as SECDED) to calculate syndromes; Judgment and Execution: If the syndrome is 0, there are no errors, and the user data passes directly; if the syndrome indicates a single-bit error, automatic error correction is performed, flipping the error bit to obtain correct data; if the syndrome indicates a double-bit or uncorrectable error, an alarm is triggered, the error address is recorded, and the data is marked as unreliable. Finally, the verified and potentially corrected data is determined as the target user data.

[0122] In the above embodiments, multiple user data blocks are batch-verified using a single ECC verification data block, which fully leverages the verification capability of the ECC algorithm, reduces the frequency of ECC data reading, and further improves data verification efficiency.

[0123] In the above embodiments, user data and its ECC verification data are obtained from the same storage unit during reading, realizing a complete data reading and verification process in a single row activation, which greatly reduces read operation latency and improves data reading reliability.

[0124] In summary, the data access method proposed in this disclosure systematically solves the performance bottleneck problem introduced by Inline ECC technology through a co-cell data-ECC bound storage architecture, combined with configurable region partitioning and an optimized command scheduling mechanism. At the storage level, dynamically configurable ECC regions reduce space waste; at the access level, co-cell layout eliminates additional row activation overhead; and at the transmission level, optimized scheduling reduces the proportion of ECC bandwidth. These three factors work synergistically to significantly improve the effective bandwidth and access efficiency of DRAM while ensuring data integrity and error correction capabilities, making it particularly suitable for high-end computing scenarios with stringent performance and reliability requirements.

[0125] The following is a specific implementation of the data access method provided in this disclosure.

[0126] Figure 7A This is a schematic diagram of an Inline ECC bandwidth scheme, which includes the following processes.

[0127] 1. For access requests from the upstream high-speed bus, the memory controller caches all read / write commands and write data. After address processing and command processing logic operations, the memory controller reserves an ECC address area and generates ECC command information and ECC data. This is determined based on the maximum command size; for example, 128 bytes for mobile phone chips and 256 bytes for automotive chips.

[0128] 2. Based on the Normal read / write command information, the memory controller generates ECC read / write command information; based on the Normal write data, according to the ECC algorithm, the memory controller generates corresponding ECC data; the memory controller stores both the Normal write data and the ECC data in DRAM. When waiting to retrieve Normal read data from DRAM, it also requires retrieving ECC data from DRAM. According to the ECC algorithm, the memory controller verifies the Normal data and returns the verified read data to the high-speed bus.

[0129] 3. For example Figure 7BThe diagram shows the address processing logic. The address processing logic is as follows: The memory controller processes the read and write command addresses of the system access. Each ROW reserves a portion of the address space (Extra area). The size of this address space is required to be associated with the maximum command SIZE of the upstream high-speed bus. For example, if the maximum command SIZE of the upstream high-speed bus is 256 bytes, the Extra area size of each ROW must be greater than or equal to 256 bytes.

[0130] 4. After the introduction of ECC, the storage areas of Normal data and ECC data are scattered and mixed together, and the total number of ROWs accessed by DRAM increases. For example, if the number of valid ROWs accessed by the upstream high-speed bus is N, after address processing, the total number of accessible DRAM ROWs becomes K, where K is greater than N.

[0131] 5. The Extra area of ​​each ROW is used to store the ECC data corresponding to the Normal data of that ROW. The size of the ECC area must be less than or equal to that of the Extra area. Normal read and write data and the corresponding ECC data are located in the same ROW of DRAM, which can realize the continuous scheduling of Normal read and write commands and ECC commands.

[0132] 6. In order to minimize performance waste and maximize effective bandwidth, the ratio of ECC data to Normal data is implemented according to the minimum value of the ECC algorithm. For example, the SECDED algorithm supports 256 bits of Normal data and 10 bits of ECC data, so the bandwidth ratio of ECC commands is reduced to 1 / 16.

[0133] 7. After address logic processing, the ratio of the address range of Normal data to Extra data in each ROW is independent of the ratio of Normal data to ECC data. This implementation satisfies the bus interface protocol requirements, such as the maximum command SIZE requirement, while also maximizing the effective bandwidth and minimizing the ECC bandwidth ratio.

[0134] In summary, the above-mentioned scheme has the following beneficial effects.

[0135] 1. After the read and write commands are processed by the address logic, the Normal data and the corresponding ECC data are stored in the same ROW. The bandwidth loss due to the introduction of ECC is close to the theoretical value. The data bits and parity bits supporting the ECC algorithm are 256:10, and the ECC bandwidth accounts for only 1 / 17. The effective bandwidth of DDR can be improved by 8%.

[0136] 2. Each ROW reserves a portion of the address space (Extra area). This implementation method is compatible with upstream high-speed bus sending read and write commands of different sizes, and the design is relatively flexible.

[0137] Figure 8 This is a schematic diagram of the structure of a memory controller 800 according to an embodiment of this disclosure. Figure 8 As shown, the memory controller includes: an address processing module 810, a command processing module 820, and a scheduling module 830.

[0138] Address processing module 810 is used to determine the first storage area of ​​the storage cell in dynamic random access memory (DRAM), the first storage area being used to store error detection and correction (ECC) data.

[0139] The command processing module 820 is used to respond to the write command information corresponding to the access request, determine the first ECC data corresponding to the write command information, and the first ECC data is used to verify the write data corresponding to the write command information.

[0140] The scheduling module 830 is used to store the write data corresponding to the write command information and the first ECC data in the same first storage unit, and the first ECC data is stored in the first storage area in the first storage unit.

[0141] In some embodiments, the address processing module is configured to: determine the maximum value of the bus command corresponding to the access request; determine a first space based on the maximum value of the bus command; determine a region of the first space in the storage unit as a first storage region, and determine a region outside the first space in the storage unit as a second storage region, wherein the second storage region is used to store write data.

[0142] In some embodiments, the command processing module is configured to: determine a user data write command and an ECC write command based on the write request in the write command information; determine first ECC data based on the write data corresponding to the write request, wherein the ECC write command and the first ECC data are associated.

[0143] In some embodiments, the scheduling module is configured to: determine the first storage unit corresponding to the write request based on the logical address corresponding to the write request in the write command information; determine the preset configuration corresponding to the write command information, wherein the preset configuration indicates the scheduling ratio of write data and first ECC data; and, based on the scheduling ratio, store the write data in the second storage area of ​​the first storage unit and store the first ECC data in the first storage area of ​​the first storage unit.

[0144] In some embodiments, the scheduling ratio indicated by the preset configuration is greater than 8:1.

[0145] In some embodiments, the memory controller further includes a verification module, an address processing module for determining a second storage unit corresponding to the read command information in response to the read command information corresponding to the access request, a scheduling module for reading user data corresponding to the read command information and second ECC data corresponding to the user data from the second storage unit based on the read command information, and a verification module for verifying and correcting user data based on the second ECC data to determine the target user data.

[0146] In some embodiments, the scheduling module is used to determine user data read commands and ECC read commands based on read requests in read command information; based on a preset configuration, it reads second ECC data corresponding to the ECC read command from the first storage area in the second storage unit, and sequentially reads user data corresponding to at least one user data read command from the second storage area in the second storage unit.

[0147] In some embodiments, the verification module is used to determine at least one user data corresponding to the second ECC data, wherein the second ECC data and the at least one user data conform to the scheduling ratio of the preset configuration; based on the second ECC data, each user data in the at least one user data is verified and corrected to determine the target user data.

[0148] In the above embodiments, the memory controller enables intelligent address mapping, efficient command scheduling, and parallel data processing. The controller adapts to different system requirements through built-in configurable registers, achieves collaborative processing of user data and ECC data through optimized pipeline design, and hides ECC check latency through prefetching and caching mechanisms. This hardware implementation makes ECC protection virtually transparent to upper-layer applications, providing robust data integrity while minimizing performance overhead, achieving a balance between reliability and high-performance access.

[0149] In some embodiments, this disclosure proposes a system-on-a-chip that integrates a memory controller. The memory controller is used to access data from external DRAM based on access requests, including data writing and data reading. The memory controller is used to perform actions such as... Figure 4-6 The embodiment shown. Alternatively, the memory controller structure is as follows: Figure 8 As shown.

[0150] In some embodiments, the system-on-a-chip further includes: a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), an image signal processing unit (ISP), a direct memory access unit (DMA), etc.

[0151] Figure 9 This is a schematic diagram of the structure of an electronic device 900 for implementing the above-described data access method, according to an exemplary embodiment.

[0152] Reference Figure 9 The electronic device 900 may include one or more of the following components: a processing component 902, a memory 904, a power supply component 906, a multimedia component 908, an audio component 910, an input / output (I / O) interface 912, a sensor component 914, and a communication component 916.

[0153] Processing component 902 typically controls the overall operation of electronic device 900, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 902 may include one or more processors 920 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 902 may include one or more modules to facilitate interaction between processing component 902 and other components. For example, processing component 902 may include a multimedia module to facilitate interaction between multimedia component 908 and processing component 902.

[0154] Memory 904 is configured to store various types of data to support the operation of electronic device 900. Examples of this data include instructions for any application or method operating on electronic device 900, contact data, phonebook data, messages, pictures, videos, etc. Memory 904 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0155] Power supply component 906 provides power to various components of electronic device 900. Power supply component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 900.

[0156] Multimedia component 908 includes a screen that provides an output interface between electronic device 900 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 908 includes a front-facing camera and / or a rear-facing camera. When electronic device 900 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0157] Audio component 910 is configured to output and / or input audio signals. For example, audio component 910 includes a microphone (MIC) configured to receive external audio signals when electronic device 900 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 904 or transmitted via communication component 916. In some embodiments, audio component 910 also includes a speaker for outputting audio signals.

[0158] I / O interface 912 provides an interface between processing component 902 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0159] Sensor assembly 914 includes one or more sensors for providing state assessments of various aspects of electronic device 900. For example, sensor assembly 914 may detect the on / off state of electronic device 900, the relative positioning of components such as the display and keypad of electronic device 900, changes in position of electronic device 900 or a component of electronic device 900, the presence or absence of user contact with electronic device 900, orientation or acceleration / deceleration of electronic device 900, and temperature changes of electronic device 900. Sensor assembly 914 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 914 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 914 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0160] Communication component 916 is configured to facilitate wired or wireless communication between electronic device 900 and other devices. Electronic device 900 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 916 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 916 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0161] In an exemplary embodiment, the electronic device 900 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0162] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions, which can be executed by a processor 920 of an electronic device 900 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0163] Embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the data access methods described in the above embodiments of this disclosure.

[0164] Embodiments of this disclosure also provide a computer program product, including a computer program that is executed by a processor using the data access method described in the above embodiments of this disclosure.

[0165] Figure 10 This is a schematic diagram illustrating the structure of a chip 1000 for implementing the above-described data access method according to an exemplary embodiment. (Refer to...) Figure 10 The chip 1000 includes at least one communication interface 1001 and a processor 1002. The communication interface 1001 is used to receive signals input to the chip 1000 or signals output from the chip 1000. The processor 1002 communicates with the communication interface 1001 and implements the data access method described in the above embodiments of this disclosure through logic circuits or executed code instructions.

[0166] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses, systems, and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0167] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0168] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of preferred embodiments of this disclosure includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this disclosure pertain.

[0169] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0170] It should be understood that various parts of the embodiments of this disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0171] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0172] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into a single processing module, or each unit can exist physically separately, or two or more units can be integrated into a single module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The aforementioned storage medium can be a read-only memory, a hard disk, or an optical disk, etc.

[0173] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A data access method, characterized in that, The method includes: A first storage region is determined in the memory cell of the dynamic random access memory (DRAM), and the first storage region is used to store error detection and correction (ECC) data. In response to the write command information corresponding to the access request, the first ECC data corresponding to the write command information is determined, and the first ECC data is used to verify the write data corresponding to the write command information; The write data corresponding to the write command information is stored in the same first storage unit as the first ECC data, and the first ECC data is stored in the first storage area of ​​the first storage unit.

2. The method according to claim 1, characterized in that, Determining the first storage region of a storage cell in a dynamic random access memory (DRAM) includes: Determine the maximum value of the bus command corresponding to the access request; The first space is determined based on the maximum value of the bus command; The area of ​​the first space in the storage unit is defined as the first storage area, and the area outside the first space in the storage unit is defined as the second storage area, which is used to store the write data.

3. The method according to claim 2, characterized in that, The step of responding to the write command information corresponding to the access request and determining the first ECC data corresponding to the write command information includes: Based on the write request in the write command information, determine the user data write command and the ECC write command; Based on the write data corresponding to the write request, the first ECC data is determined, and the ECC write command is associated with the first ECC data.

4. The method according to claim 3, characterized in that, The step of storing the write data corresponding to the write command information and the first ECC data in the same first storage unit includes: Based on the logical address corresponding to the write request in the write command information, the first storage unit corresponding to the write request is determined; Determine the preset configuration corresponding to the write command information, wherein the preset configuration indicates the scheduling ratio of the write data to the first ECC data; Based on the scheduling ratio, the write data is stored in the second storage area of ​​the first storage unit, and the first ECC data is stored in the first storage area of ​​the first storage unit.

5. The method according to claim 4, characterized in that, The scheduling ratio indicated by the preset configuration is greater than 8:

1.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: In response to the read command information corresponding to the access request, determine the second storage unit corresponding to the read command information; Based on the read command information, read the user data corresponding to the read command information and the second ECC data corresponding to the user data from the second storage unit; Based on the second ECC data, the user data is verified and corrected to determine the target user data.

7. The method according to claim 6, characterized in that, The step of reading user data corresponding to the read command information and second ECC data corresponding to the user data from the second storage unit based on the read command information includes: Based on the read request in the read command information, determine the user data read command and the ECC read command; Based on the preset configuration, the second ECC data corresponding to the ECC read command is read from the first storage area in the second storage unit, and user data corresponding to at least one user data read command is read sequentially from the second storage area in the second storage unit.

8. The method according to claim 7, characterized in that, The step of verifying and correcting the user data based on the second ECC data to determine the target user data includes: Determine at least one user data corresponding to the second ECC data, wherein the second ECC data and the at least one user data conform to the preset scheduling ratio; Based on the second ECC data, each user data in the at least one user data is verified and corrected to determine the target user data.

9. A memory controller, characterized in that, include: Address processing module, command processing module, scheduling module The address processing module is used to determine the first storage area of ​​the storage cell in the dynamic random access memory (DRAM), and the first storage area is used to store error detection and correction (ECC) data. The command processing module is used to respond to the write command information corresponding to the access request, determine the first ECC data corresponding to the write command information, and the first ECC data is used to verify the write data corresponding to the write command information. The scheduling module is used to store the write data corresponding to the write command information and the first ECC data in the same first storage unit, and the first ECC data is stored in the first storage area in the first storage unit.

10. The memory controller according to claim 9, characterized in that, The address processing module is used for: Determine the maximum value of the bus command corresponding to the access request; The first space is determined based on the maximum value of the bus command; The area of ​​the first space in the storage unit is defined as the first storage area, and the area outside the first space in the storage unit is defined as the second storage area, which is used to store the write data.

11. The memory controller according to claim 10, characterized in that, The command processing module is used for: Based on the write request in the write command information, determine the user data write command and the ECC write command; Based on the write data corresponding to the write request, the first ECC data is determined, and the ECC write command is associated with the first ECC data.

12. The memory controller according to claim 11, characterized in that, The scheduling module is used for: Based on the logical address corresponding to the write request in the write command information, the first storage unit corresponding to the write request is determined; Determine the preset configuration corresponding to the write command information, wherein the preset configuration indicates the scheduling ratio of the write data to the first ECC data; Based on the scheduling ratio, the write data is stored in the second storage area of ​​the first storage unit, and the first ECC data is stored in the first storage area of ​​the first storage unit.

13. The memory controller according to claim 11, characterized in that, The scheduling ratio indicated by the preset configuration is greater than 8:

1.

14. The memory controller according to any one of claims 9 to 13, characterized in that, The memory controller also includes a verification module. The address processing module is used to determine the second storage unit corresponding to the read command information in response to the access request; The scheduling module is used to read the user data corresponding to the read command information and the second ECC data corresponding to the user data from the second storage unit based on the read command information; The verification module is used to verify and correct the user data based on the second ECC data to determine the target user data.

15. A system-on-a-chip, characterized in that, The system integrates the memory controller as described in any one of claims 9 to 14. The memory controller is used to access data in the dynamic random access memory (DRAM) based on access requests, and the data access includes data writing and data reading.

16. An electronic device, characterized in that, include: A processor and a memory for storing a computer program capable of running on the processor, wherein the processor, when running the computer program, performs the method of any one of claims 1 to 8.

17. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 8.

18. A program product, characterized in that, Includes computer instructions for causing a computer to perform the method of any one of claims 1 to 8.

19. A chip, characterized in that, It includes at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method as described in any one of claims 1 to 8 through logic circuits or executing code instructions.

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