A method and system for determining the validity of match-3 game grids

Abstract

This invention relates to the field of game data processing technology, specifically to a method and system for determining the validity of grids in a match-3 game. The method includes the following steps: parsing the acquired game layout configuration data to determine geometric boundary features; traversing each scan line using a scan line algorithm to extract continuous valid intervals; constructing a compact index list containing only valid units based on the valid intervals; and generating interactive objects based on this index list. This invention introduces a discrete topology mapping mechanism to directly locate valid interactive areas, eliminating redundant calculations for invalid empty areas in the traditional full matrix traversal mode. This significantly reduces the time complexity and memory space consumption of logic initialization, solves the technical problem of low efficiency in constructing irregularly shaped layouts, ensures rapid construction and accurate response of game logic in complex terrain scenes, and effectively improves the frame rate stability and user interaction smoothness.

Description

Technical Field

[0001] This invention relates to the field of game data processing technology, and in particular to a method and system for determining the validity of match-3 game tiles. Background Technology

[0002] The field of game data processing technology involves the underlying calculation and control of matrix logic mapping, discrete object attribute management, and real-time event triggering mechanisms in interactive digital entertainment systems. In particular, the traditional method for determining the validity of grids in match-3 games involves the system using a full matrix traversal during the initialization phase. This method employs a double-loop structure to scan all two-dimensional coordinate points within a defined rectangular area, reading preset configuration markers to determine whether each coordinate point belongs to an interactive region. This determines whether to instantiate a game object at that location or simply mark it as a blank placeholder.

[0003] Currently, the traditional method for determining the validity of grids in match-3 games mainly adopts a full matrix traversal mode. This mode scans all coordinate points on the screen one by one through a double loop to confirm their state attributes. When faced with irregularly shaped screens containing a large number of hollow areas or irregular boundaries, this processing mode forces the processing chip to perform meaningless logical judgments and memory addressing on a massive number of invalid and empty coordinates. This results in a large amount of redundant calculation occupying the system's computing resources, increasing the risk of latency and stuttering during the data initialization phase, and significantly exacerbating the hardware heat generation and energy consumption burden on mobile devices during frequent switching in complex levels. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a method and system for determining the validity of match-3 game tiles.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a method for determining the validity of match-3 game tiles, comprising the following steps: S1: Obtain the original layout configuration data of the match-3 game level through the game engine interface, perform binarization threshold parsing on the terrain identifier bits in the original layout configuration data, map the grid where elimination blocks can be placed and the hollow obstacle grid to logic high level and logic low level respectively, and construct a binarized topology mask mapping map. S2: Call the scan line parsing algorithm to perform a line-by-line scan on the binarized topological mask mapping map, detect the edge transition points where the logic level flips in multiple scan lines, calculate the starting column coordinates and ending column coordinates of continuous valid line segments, and extract the valid run interval data; S3: Linearly reorganize the effective run interval data according to the row number order, establish a direct mapping index from two-dimensional logical coordinates to one-dimensional physical memory address, calculate the projection overlap relationship of multiple interval segments in the vertical direction to determine the neighborhood connection attribute, and construct a compact sparse index list. S4: Sequentially parse the interval parameters stored in the compact sparse index list, extract game element entities from the object pool and bind rendering components only within the valid coordinate range defined by the interval segment, skip the logical calculation of invalid areas, and generate the match-3 game logic layout.

[0006] As a further aspect of the present invention, step S1 specifically comprises: S11: Call the underlying data reading interface to load the configuration structure of the match-3 game level, parse the two-dimensional array including terrain metadata, traverse the attribute fields of each cell in the two-dimensional array, and obtain the corresponding terrain identifier value; S12: A preset binary judgment threshold is used to distinguish between playable and non-playable areas. The obtained terrain identifier value is compared with the binary judgment threshold. If the terrain identifier value meets the passage conditions, it is marked as a logic high level; otherwise, it is marked as a logic low level. S13: Based on the row and column arrangement order of the two-dimensional array, write the logic high level or logic low level corresponding to multiple cells into the pre-allocated bitmap memory block bit by bit to generate the binarized topology mask mapping map.

[0007] As a further aspect of the present invention, step S2 specifically comprises: S21: Initialize the scan line pointer, set the scan direction to traverse line by line from top to bottom, allocate a temporary buffer queue for each line to store the jump point position information, and reset the scan status register of the current line to a logic low level. S22: Read the level signal in the binary topology mask mapping map bit by bit along the horizontal direction, perform an XOR operation between the level value of the current bit and the level value of the previous bit, and determine the edge transition point when the operation result is true, and record the column index value of the transition point. S23: The scan line is segmented according to the recorded jump point column index value. The continuous area composed of logic high level is identified as the continuous valid line segment. The starting column coordinates corresponding to the left boundary and the ending column coordinates corresponding to the right boundary of multiple line segments are extracted respectively to generate the valid run interval data.

[0008] As a further aspect of the present invention, step S3 specifically comprises: S31: Based on the total grid width parameter of the match-3 game level, the two-dimensional row and column coordinates included in the effective run interval data are converted into continuous one-dimensional memory offsets using a linearization formula, and the correspondence between logical location and physical storage unit is established. S32: Traverse the effective run interval data between two adjacent rows, compare the column coordinate range of the current row interval segment and the next row interval segment, determine whether there is a vertical projection intersection, determine the block falling path connectivity, and generate the neighborhood connection attribute. S33: Encapsulate the starting column coordinates, the ending column coordinates, the one-dimensional memory offset, and the neighborhood connection attribute into a structure node, and push all nodes into a dynamic array in row number order to construct the compact sparse index list.

[0009] As a further aspect of the present invention, step S4 specifically comprises: S41: Create an iterator for traversing the compact sparse index list, sequentially read the starting column coordinates and the ending column coordinates stored in each structure node, and calculate the number of entities to be generated in the current interval. S42: Based on the calculated number of entities, repeatedly execute the object request operation, pop a batch of inactive game element entities from the pre-initialized object pool, and set the activation status flag of the entities to true; S43: Using the one-dimensional memory offset and row and column index in the structure node, calculate the position of each activated game element entity in the world coordinate system, attach the corresponding texture rendering component and physical collision component, and generate the match-3 game logic layout.

[0010] As a further aspect of the present invention, the numerical comparison process in S12 includes: Obtain preset mask bit field configuration parameters, wherein the mask bit field configuration parameters define the bit features corresponding to the differentiated terrain types; Perform a bitwise AND operation on the obtained terrain identifier bit values, extract key feature bits, and determine whether the operation result is equal to the preset passable feature code; When the calculation result indicates that the current grid attribute is a normal plot, a conveyor belt plot, or a boost item plot, the passage condition is confirmed to be met and a logic high-level signal is output. When the calculation result indicates that the current grid property is a hollowed-out plot, that is, a fixed obstacle plot that cannot be eliminated or a locked plot, it is confirmed that the passage conditions are not met and a logic low-level signal is output.

[0011] As a further aspect of the present invention, the XOR logic operation process in S22 includes: Load the binary level value of the current scan bit into the first register, load the binary level value of the previous bit into the second register, and call the processor's hardware XOR instruction to perform the operation on the values ​​of the two registers. If the XOR result is 1 and the value of the first register is 1, the current position is determined to be a rising edge transition point, and it is marked as the starting point of the new round of continuous valid line segments. If the XOR result is 1 and the value of the first register is 0, the current position is determined to be a falling edge transition point, and it is marked as the end point of the current continuous valid line segment; If the XOR result is 0, keep the current line segment state unchanged and continue to read the level signal of the next bit for subsequent detection.

[0012] As a further aspect of the present invention, the calculation process of the projection overlap relationship in S32 includes: Obtain the horizontal span parameters of the current row interval and the horizontal span parameters of the next row interval to be detected. Combined with the gravity fall rule, calculate the overlap coefficient using the following formula: ; in, This represents the overlap coefficient. and These represent the starting column coordinates and the ending column coordinates of the consecutive valid line segments in the current row, respectively. and The starting column coordinates and the ending column coordinates respectively represent the starting column coordinates and the ending column coordinates of the adjacent line segment in the next row; The overlap coefficient is compared with a preset connectivity threshold. If it is greater than the threshold, the neighborhood connection attribute is marked as "vertically reachable", allowing the elimination of block fall across rows.

[0013] As a further aspect of the present invention, the object request operation in S42 includes: Check if the idle queue pointer in the object pool points to an empty address to determine if there is a reusable game element entity. If the idle queue is not empty, remove an entity handle directly from the head of the queue, reset the entity's lifecycle counter and transformation matrix, and mark it as pending rendering. If the idle queue is empty, a dynamic expansion mechanism is triggered. The current memory block is requested based on the memory pressure coefficient of the current frame, a specified number of new entities are instantiated and added to the management list, and then the reference handle of the newly created entities is returned. After extracting entities, immediately update the statistics counters in the object pool to monitor whether the total number of active entities exceeds the warning threshold.

[0014] A system for determining the validity of match-3 game tiles, the system being used to implement the aforementioned method for determining the validity of match-3 game tiles, the system comprising: The binarized topology mapping construction module is used to obtain the original layout configuration data of the match-3 game level through the game engine interface, perform binarized threshold parsing on the terrain identifier bits in the original layout configuration data, map the grid where elimination blocks can be placed and the hollow obstacle grid to logic high level and logic low level respectively, and construct a binarized topology mask mapping map. The scan line run extraction module is used to call the scan line parsing algorithm to perform a line-by-line scan of the binarized topological mask mapping map, detect edge transition points where logic levels flip in multiple scan lines, calculate the start and end column coordinates of continuous valid line segments, and extract valid run interval data. The sparse index reorganization module is used to linearly reorganize the effective run interval data according to the row number order, establish a direct mapping index from two-dimensional logical coordinates to one-dimensional physical memory addresses, calculate the projection overlap relationship of multiple interval segments in the vertical direction to determine the neighborhood connection attribute, and construct a compact sparse index list. The logic layout generation module is used to sequentially parse the interval parameters stored in the compact sparse index list, extract game element entities from the object pool and bind rendering components only within the valid coordinate range defined by the interval segment, skip the logical calculation of invalid areas, and generate the match-3 game logic layout.

[0015] Compared with the prior art, the advantages and positive effects of the present invention are as follows: In this invention, by introducing a discrete topology mapping mechanism, the geometric boundaries of the layout configuration data are directly parsed and the valid intervals are extracted. This technique uses a scanline algorithm to quickly identify continuous valid segments of each row of data, thereby constructing a compact index list containing only legal interactive units. This eliminates the need to traverse invalid empty areas, significantly reducing the time complexity and space occupation at the logic level. It ensures the rapid construction and accurate response of game logic under irregular layouts, effectively improving the frame rate stability and interaction smoothness in complex terrain scenes. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the validity determination of match-3 game grids in this invention. Figure 2 This is a flowchart illustrating the construction process of the binarized topological mask mapping graph of the present invention. Figure 3 This is a flowchart of the effective run interval data extraction process of the present invention; Figure 4 This is a flowchart illustrating the construction process of the compact sparse index list of the present invention. Figure 5 This is a flowchart illustrating the logic layout generation process for the match-3 game of this invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the software-based technical solution is described in detail below with reference to system architecture diagrams and embodiments. It should be understood that the specific embodiments described herein are only for explaining the technical solutions of this invention and do not constitute a limitation on the scope of protection.

[0018] In the description of this invention, the system architecture relationships or data processing flows indicated by terms such as "layer," "module," "interface," "data flow," "client," and "server" are all defined based on the architecture diagram or flowchart corresponding to the embodiments. This way of describing is only used to clearly illustrate the logical relationships between the elements in the technical solution, and not to limit the physical deployment form. The term "multiple" includes two or more technical units, including but not limited to multiple data nodes, processing threads, service instances, or functional components and other scalable elements. The specific number is determined according to the actual business scenario and needs to be specifically specified.

[0019] Please see Figure 1 and Figure 2 This invention provides a technical solution: a method for determining the validity of match-3 game tiles, comprising the following steps: S1: Obtain the original layout configuration data of the match-3 game level through the game engine interface, perform binarization threshold parsing on the terrain identifier bits in the original layout configuration data, map the grid where matchable blocks can be placed and the hollow obstacle grid to logic high level and logic low level respectively, and construct a binarized topology mask mapping map. The specific steps of S1 are as follows: S11: Call the underlying data reading interface to load the configuration structure of the match-3 game level, parse the two-dimensional array including terrain metadata, traverse the attribute fields of each cell in the two-dimensional array, and obtain the corresponding terrain identifier value; S12: A preset binary judgment threshold is used to distinguish between playable and non-playable areas. The obtained terrain identifier value is compared with the binary judgment threshold. If the terrain identifier value meets the passage conditions, it is marked as a logic high level; otherwise, it is marked as a logic low level. The numerical comparison process in S12 includes: Obtain the preset mask bit field configuration parameters. The mask bit field configuration parameters define the bit features corresponding to the differentiated terrain types. Perform a bitwise AND operation on the acquired terrain identifier values, extract key feature bits, and determine whether the operation result is equal to the preset passable feature code; When the calculation result indicates that the current grid attribute is a normal plot, a conveyor belt plot, or a boost item plot, the passage condition is confirmed to be met and a logic high-level signal is output. When the calculation result shows that the current grid attribute is a hollowed-out plot, that is, a fixed obstacle plot that cannot be eliminated or a locked plot, it is confirmed that the passage conditions are not met and a logic low level signal is output. S13: Based on the row and column arrangement order of the two-dimensional array, write the logic high level or logic low level corresponding to multiple cells into the pre-allocated bitmap memory block bit by bit to generate a binary topology mask mapping map.

[0020] This embodiment is built on a cloud-based collaborative high-concurrency game logic processing architecture. It utilizes a server cluster configured with Intel Xeon multi-core CPUs to read the match-3 game level configuration file stored in a distributed file system via a low-level file I / O interface. This configuration file is stored in a serialized and compressed Protocol Buffers binary format, with the core data segment containing a 12x12 two-dimensional grid array. The server first deserializes the binary stream data into a level configuration structure in memory. This structure contains the level ID, maximum move limit, drop weight table, and core terrain metadata matrix. The program traverses each row and column of this matrix using double loop pointers, accessing the grid object corresponding to each grid cell and extracting the 32-bit unsigned integer attribute field containing the terrain identifier. This attribute field uses bit-field technology to compress and store multi-dimensional information including terrain type, freeze level, and overlay status. For example, when processing the grid cell in row 5, column 3, the 32-bit integer value corresponding to that memory address is directly read, and the resulting raw hexadecimal value is... This value serves as the basis for subsequent binarization determination.

[0021] The aforementioned bit field refers to a data structure in programming languages ​​such as C or C++ that allows the length of member variables to be defined in units of bits within a structure. This is intended to save memory space and facilitate low-level bit operations.

[0022] For the extracted 32-bit terrain identifier values, strict bitwise operation filtering is performed according to the predefined game logic bitmask specification. Mask bit field configuration parameters are defined. for This is used to mask out the high 24 bits of interfering information about items or status, retaining only the low 8 bits to represent terrain texture. The acquired... and Perform a bitwise AND operation to obtain the result. Subsequently, the logic for determining the passage threshold is set, and the set of permissible feature codes is defined. The system defines: Represents ordinary grassland. Represents a conveyor belt. Represents a gain plot, while The values ​​above represent various obstacles. The calculation results... Compare with the preset passable set. Because If a block exists in this set, the system determines that the grid meets the passage conditions, meaning that the elimination block is allowed to reside or pass through it. At this time, the logic level signal is set to 1 (logic high). Conversely, if the calculation result is... If the area is not within the passable set (representing a hollow or locked area), the passability condition is not met, and a logic level signal of 0 (logic low) is output. To verify the accuracy of this judgment logic, automated testing was performed on a test set containing 10,000 grid samples during the development phase. Table 1 lists the parsing and binarization judgment results of some terrain identifier bit values. As shown in Table 1, bit operations accurately eliminated interference from irrelevant state bits, ensuring the uniqueness and accuracy of terrain attribute judgment. Experiments show that the misjudgment rate of this logic is 0% when processing complex composite terrain.

[0023] After completing the single-point determination, leveraging the CPU's L1 cache characteristics, the generated logic level signals are sequentially written into a pre-allocated bitmap memory block according to the linear arrangement of the two-dimensional array in memory. The size of this memory block is strictly aligned with the CPU's cache lines to maximize write efficiency. In practice, a... Using a variable of type as a sliding window, after processing 64 grids, the accumulated 64 bits are written to memory all at once, avoiding frequent single-byte memory accesses. For a 12x12 level, its corresponding binary topology mask map is compressed and stored in more than two locations. With a longer data segment length, the memory bandwidth usage during high-frequency access is reduced to 1 / 32 of that in the uncompressed state, greatly improving the data throughput of subsequent scanning operations.

[0024] Table 1. Experimental Data on Numerical Analysis and Binarization Determination of Terrain Marker Locations Please see Figure 1 and Figure 3 S2: Call the scan line parsing algorithm to perform a line-by-line scan of the binary topology mask mapping map, detect the edge transition points where the logic level flips in multiple scan lines, calculate the starting column coordinates and ending column coordinates of continuous valid line segments, and extract the valid run interval data; The specific steps of S2 are as follows: S21: Initialize the scan line pointer, set the scan direction to traverse line by line from top to bottom, allocate a temporary buffer queue for each line to store the jump point position information, and reset the scan status register of the current line to a logic low level. S22: Read the level signal in the binary topology mask mapping bit by bit along the horizontal direction, perform an XOR operation between the level value of the current bit and the level value of the previous bit, and determine the edge transition point when the operation result is true, and record the column index value where the transition point is located; The XOR logic operation process in S22 includes: Load the binary level value of the current scan bit into the first register, load the binary level value of the previous bit into the second register, and call the processor's hardware XOR instruction to perform the operation on the values ​​of the two registers. If the XOR result is 1 and the value of the first register is 1, the current position is determined to be a rising edge transition point, and it is marked as the starting point of a new round of continuous valid line segments; If the XOR result is 1 and the value of the first register is 0, the current position is determined to be a falling edge transition point, and it is marked as the end point of the current continuous valid line segment; If the XOR result is 0, keep the current line segment state unchanged and continue to read the level signal of the next bit for subsequent detection; S23: Based on the recorded jump point column index value, the scan line is segmented, and the continuous area composed of logic high level is identified as a continuous valid line segment. The starting column coordinates corresponding to the left boundary and the ending column coordinates corresponding to the right boundary of multiple line segments are extracted respectively to generate valid run interval data.

[0025] Please see Figure 1 and Figure 4 S3: Linearly reorganize the effective run interval data according to the row number order, establish a direct mapping index from two-dimensional logical coordinates to one-dimensional physical memory addresses, calculate the projection overlap relationship of multiple interval segments in the vertical direction to determine the neighborhood connection attribute, and construct a compact sparse index list.

[0026] During the initialization phase, a high-speed temporary storage area is allocated in the server memory to instantiate the context environment required by the scan-line algorithm. A pointer to the starting address of the binary topology mask map is defined, and the scanning direction is set to top-down, i.e., starting from row 0 of the level matrix and progressing row by row to row 11. An integer array of capacity 12 is allocated to each row as a temporary buffer queue to temporarily store the indexes of detected transition points. At the same time, a Boolean register is set to record the current level state, initially reset to logic low level 0. This means that the scan of each row starts from an unplayable region by default, ensuring that the first valid grid will necessarily trigger a state flip.

[0027] The aforementioned high-speed temporary storage area refers to a high-speed static random access memory (SRAM) located inside or adjacent to the processor. Its access speed is close to that of a register, and it is often used to store frequently accessed temporary data to reduce the access latency to main memory.

[0028] The actual row scanning process then begins, utilizing the processor's SIMD instruction set or optimizing the loop through bitwise operations to read the binary data of the current row bit by bit along the horizontal direction. Currently, the 5th row of data is being processed, and the corresponding bitmap data segment is a binary sequence. Within each clock cycle, the currently scanned bit... Load into the first register R1, and set the previous bit Load into the second register R2 (R2 defaults to 0 for the first character of each row). Call the hardware XOR instruction. Perform logical operations. The core characteristic of the XOR operation lies in detecting signal toggling: the result is 1 only when the values ​​of R1 and R2 are different. (Based on a sequence...) For example, when the scan pointer moves to index 2 (starting from 0), ,and If the XOR result is 1, it is determined that an edge transition point has been detected. At this time, the column index value 2 is immediately pushed into the temporary cache queue.

[0029] The aforementioned SIMD instruction set refers to Single Instruction Multiple Data (SIMD) technology, which allows the processor to perform the same operation on multiple data points simultaneously within a single instruction cycle, significantly improving the efficiency of parallel computing.

[0030] For each transition point marked as 1 by the XOR operation, the transition direction needs to be further determined by combining the value of the first register R1. Continuing the example above, at index 2, the XOR result is 1 and R1 (the current bit) is 1. The system determines that this is a rising edge transition point from an unplayable area to a playable area, and marks it as the starting point of a new round of continuous valid line segments. When scanning reaches index 5, , The XOR result is 1, but R1 (the current bit) is 0 at this time. The system determines that this is a falling edge transition point from a playable to an unplayable region, and marks the previous bit, index 4, as the end point of the current continuous valid line segment. If the XOR result is 0, it indicates that the logic level remains continuous, keeping the current line segment state machine unchanged, and directly advancing to the next bit. Through this logic, the sequence... It was precisely analyzed into two sets of transition events: from start point 2 to end point 4, and from start point 7 to end point 8.

[0031] Based on the paired transition point indexes recorded in the temporary cache queue, the current scan line is logically segmented. Each pair of rising edge indices and the index preceding the falling edge is mapped to a closed interval of continuous valid line segments. For example, the above detection results generate two valid run-length intervals: interval A is... Interval B is These data structures not only contain geometric coordinates but also reserve attribute fields for subsequent physics calculations. This step transforms the original discrete point map into a highly compressed vectorized interval description. For a typical match-3 level map with a sparsity of 30%, this processing reduces the amount of data for subsequent logical operations by approximately 70%, significantly reducing the load on the server CPU when performing large-scale connectivity calculations.

[0032] Please see Figure 1 and Figure 4 S3: Based on the total grid width parameter of the match-3 game level, use the linearization formula to convert the two-dimensional row and column coordinates included in the effective run interval data into continuous one-dimensional memory offsets, and establish the correspondence between logical location and physical storage unit; S32: Traverse the valid run interval data between two adjacent rows, compare the column coordinate range of the current row interval segment with the next row interval segment, determine whether there is a vertical projection intersection, determine the connectivity of the block's falling path, and generate the neighborhood connection attribute. The calculation process for the projection overlap relationship in S32 includes: Obtain the horizontal span parameters of the current row interval and the horizontal span parameters of the next row interval to be detected. Combined with the gravity fall rule, calculate the overlap coefficient using the following formula: ; in, Represents the overlap coefficient. and These represent the starting and ending column coordinates of the current row's continuous valid line segments, respectively. and These represent the starting and ending column coordinates of the adjacent line segment in the next row, respectively. The overlap coefficient is compared with a preset connectivity threshold. If it is greater than the threshold, the neighborhood connection attribute is marked as "vertically reachable", allowing the elimination of block fall across rows. S33: Encapsulate the starting column coordinates, ending column coordinates, one-dimensional memory offset, and neighborhood connection attributes into structure nodes, and push all nodes into a dynamic array in row number order to build a compact sparse index list.

[0033] After completing the row-level scan, linearization address transformation is performed on all extracted valid run-length interval data based on the global grid width parameter of 10 for the match-3 game level. This is achieved using the linear mapping formula. This maps two-dimensional coordinates to one-dimensional memory offsets. For example, for an interval... Its corresponding initial one-dimensional offset is The termination offset is 54. This step establishes a direct index relationship between logical space coordinates and physical memory unit addresses, so that when accessing the properties of a specific grid later, it can be directly addressed through array subscripts without the need for time-consuming two-dimensional array pointer jumps.

[0034] Next, the system iterates through the valid run intervals between adjacent rows to determine the vertical reachability of the elimination block under gravity. The system then sequentially retrieves one interval from the current row. to and the interval of the next row to The column coordinate ranges of the two intervals are compared. To quantify the degree of overlap between the two intervals in the vertical direction, an overlap coefficient is introduced. The computational logic.

[0035] Obtain the horizontal span parameters of the current row interval and the horizontal span parameters of the next row interval to be detected. Combined with the gravity fall rule, calculate the overlap coefficient using the following formula: ; in, Represents the overlap coefficient; Represents the starting column coordinates of the current row of consecutive valid line segments; Represents the coordinates of the last column of a continuous valid line segment in the current row; Represents the starting column coordinates of the adjacent line segment in the next row; This represents the coordinates of the last column of the adjacent line segment in the next row.

[0036] Assume the range of the current row interval is 2 to 6 (i.e. Its span is 5 grids; the range of the next row interval is 4 to 8 (i.e., The interval spans 5 grids. First, calculate the horizontal intersection length of the two intervals. Then, take the minimum value of their termination coordinates. Take the maximum value of the two starting coordinates. The intersection length is Next, calculate the normalized denominator. Calculate the square root of the product of the lengths of the two intervals: Finally, the overlap coefficient is obtained by dividing the intersection length by the normalized denominator. .

[0037] The connectivity threshold for the system was set to 0.3. Since the calculated value of 0.6 is greater than 0.3, the system determined that the two intervals had significant projective overlap in the vertical direction, and the generated neighborhood connectivity attribute was marked as "vertically reachable." This means that the elimination block located in the current row interval can fall directly to the next row interval due to gravity, or in the path search algorithm, the two are considered connected nodes. Table 2 lists the overlap coefficient calculation results and connectivity determination for different interval positional relationships. As shown in Table 2, this formula effectively filters out edge contact or slight overlap (such as in experimental group 3), ensuring that only areas with sufficient physical support area are considered valid falling paths, preventing physical logic errors.

[0038] Table 2 Experimental Data Table for Calculation of Vertical Projection Overlap Coefficient and Connectivity Determination Finally, the calculated start column coordinates, end column coordinates, calculated one-dimensional memory offsets, and determined neighborhood connectivity attributes are encapsulated into a compact structure node. These nodes are then pushed into a dynamic array in ascending row number order. This dynamic array constitutes a "compact sparse index list." Compared to traditional full matrix storage, this list only stores data references to valid regions, greatly reducing memory fragmentation and providing a continuous memory access pattern for subsequent rendering and logical traversal, significantly improving CPU cache hit rate.

[0039] Please see Figure 1 and Figure 5 S4: Sequentially parse the interval parameters stored in the compact sparse index list, extract game element entities from the object pool and bind rendering components only within the valid coordinate range of the interval segment, skip the logical calculation of invalid areas, and generate the match-3 game logic layout; The specific steps for S4 are as follows: S41: Create an iterator for traversing the compact sparse index list, read the starting column coordinates and ending column coordinates stored in each structure node in turn, and calculate the number of entities to be generated in the current interval. S42: Based on the calculated number of entities, repeatedly execute the object request operation, pop a batch of inactive game element entities from the pre-initialized object pool, and set the activation status flag of the entities to true; The object request operation in S42 includes: Check if the idle queue pointer in the object pool points to an empty address to determine if there are any reusable game element entities; If the idle queue is not empty, remove an entity handle directly from the head of the queue, reset the entity's lifecycle counter and transformation matrix, and mark it as pending rendering. If the idle queue is empty, a dynamic expansion mechanism is triggered. The current memory block is requested based on the memory pressure coefficient of the current frame, a specified number of new entities are instantiated and added to the management list, and then the reference handle of the newly created entities is returned. After extracting entities, immediately update the statistics counter of the object pool to monitor whether the total number of active entities exceeds the warning threshold; S43: Utilize the one-dimensional memory offset and row and column indices in the structure node to calculate the position of each activated game element entity in the world coordinate system, attach the corresponding texture rendering component and physical collision component, and generate the match-3 game logic layout.

[0040] In the final stage of logical layout generation, a dedicated iterator pointer is created to sequentially traverse the compact sparse index list stored in memory. This iterator points equally to each structure node in the list, reading the start and end column coordinates encapsulated within each node. For each node, a subtraction operation is performed... This process precisely calculates the number of game element entities that need to be generated within the current continuous interval. For example, if the interval read is 2 to 4, it calculates that 3 entities need to be generated. This step skips all invalid cutouts or obstacle areas and only calculates for valid coordinates, ensuring that computing resources are not wasted on blank areas.

[0041] Based on the calculated number of entities required, a batch request is initiated to the pre-initialized object pool system. In the server-side memory management module, the object pool maintains an idle queue consisting of inactive entities. First, it checks if the head pointer of the idle queue points to a null address or if the queue counter is zero. If there are available entities in the queue (e.g., the current idle queue length is 50, and the request quantity is 3), three entity handles are popped directly from the head of the queue, their lifecycle states are switched from inactive to active, and their transformation matrices are reset to the identity matrix, ready for reuse. If the idle queue is empty or insufficient, a dynamic expansion mechanism is triggered. At this time, the current device's memory pressure coefficient is read. If the coefficient is below 0.8, a new memory block capable of accommodating the new request quantity is requested, the corresponding number of new game element entities are instantiated, they are registered to the global entity management list, and a reference to the newly created entities is returned. After retrieving the entities, the active entity counter of the object pool is atomically incremented immediately and compared with the warning threshold of 500. If the threshold is exceeded, the system will mark a performance warning log.

[0042] The aforementioned object pool refers to a software design pattern that avoids frequent object creation and destruction operations by pre-allocating and maintaining a set of reusable object instances, thereby significantly reducing the risk of memory fragmentation and reducing the overhead of garbage collection (GC).

[0043] Finally, using the one-dimensional memory offset stored in the structure node combined with the row and column indices, the precise position of each active entity in the world coordinate system is calculated. Assuming the physical size of the mesh cell is 100 pixels, the calculation formula is: ; The calculated coordinate vectors are assigned to the entity's transformation component. Then, based on the entity's type ID, the corresponding texture material is loaded and attached to the rendering component, while the physics collision component is initialized according to its collision volume parameters. At this point, a complete, visual, and physically interactive match-3 game logic layout is built in memory, ready to receive rendering instructions or logic updates for the next frame. Experimental data shows that this generation strategy based on sparse indexing and object pooling reduces the CPU time for layout initialization by approximately 45% compared to the full mesh traversal instantiation method, significantly shortening level loading time.

[0044] A system for determining the validity of match-3 game tiles, the system being used to execute the aforementioned method for determining the validity of match-3 game tiles, the system comprising: The binarized topology mapping construction module is used to obtain the original layout configuration data of the match-3 game level through the game engine interface, perform binarized threshold parsing on the terrain identifier bits in the original layout configuration data, map the grid where the matchable blocks can be placed and the hollow obstacle grid to logic high level and logic low level respectively, and construct a binarized topology mask mapping map. The scan line run extraction module is used to call the scan line parsing algorithm to perform a line-by-line scan of the binarized topological mask mapping map, detect the edge transition points where the logic level flips in multiple scan lines, calculate the start column coordinates and end column coordinates of continuous valid line segments, and extract the valid run interval data. The sparse index reorganization module is used to linearly reorganize the effective run interval data according to the row number order, establish a direct mapping index from two-dimensional logical coordinates to one-dimensional physical memory addresses, calculate the projection overlap relationship of multiple interval segments in the vertical direction to determine the neighborhood connection attribute, and construct a compact sparse index list. The logic layout generation module is used to sequentially parse the interval parameters stored in the compact sparse index list, extract game element entities from the object pool and bind rendering components only within the valid coordinate range of the interval segment, skip the logical calculation of invalid areas, and generate the match-3 game logic layout.

[0045] The above embodiments illustrate preferred embodiments of the present invention. Any equivalent adjustments to the technical solution based on software engineering methods are within the scope of protection, including but not limited to: implementing algorithm logic using different programming languages, refactoring functional modules into services, adjusting data interaction protocols, and optimizing resource scheduling strategies. Any implementation scheme derived from reasonable modifications to the data processing flow, service call chain, or system architecture layer without departing from the core technology of the present invention should be considered within the protection scope defined by the technical solution of the present invention.

Claims

1. A method for determining the validity of grids in a match-3 game, characterized in that, Includes the following steps: S1: Obtain the original layout configuration data of the match-3 game level through the game engine interface, perform binarization threshold parsing on the terrain identifier bits in the original layout configuration data, map the grid where elimination blocks can be placed and the hollow obstacle grid to logic high level and logic low level respectively, and construct a binarized topology mask mapping map. S2: Call the scan line parsing algorithm to perform a line-by-line scan on the binarized topological mask mapping map, detect the edge transition points where the logic level flips in multiple scan lines, calculate the starting column coordinates and ending column coordinates of continuous valid line segments, and extract the valid run interval data; S3: Linearly reorganize the effective run interval data according to the row number order, establish a direct mapping index from two-dimensional logical coordinates to one-dimensional physical memory address, calculate the projection overlap relationship of multiple interval segments in the vertical direction to determine the neighborhood connection attribute, and construct a compact sparse index list. S4: Sequentially parse the interval parameters stored in the compact sparse index list, extract game element entities from the object pool and bind rendering components only within the valid coordinate range defined by the interval segment, skip the logical calculation of invalid areas, and generate the match-3 game logic layout.

2. The method of claim 1, wherein, The specific steps of S1 are as follows: S11: Call the underlying data reading interface to load the configuration structure of the match-3 game level, parse the two-dimensional array including terrain metadata, traverse the attribute fields of each cell in the two-dimensional array, and obtain the corresponding terrain identifier value; S12: A preset binary judgment threshold is used to distinguish between playable and non-playable areas. The obtained terrain identifier value is compared with the binary judgment threshold. If the terrain identifier value meets the passage conditions, it is marked as a logic high level; otherwise, it is marked as a logic low level. S13: Based on the row and column arrangement order of the two-dimensional array, write the logic high level or logic low level corresponding to multiple cells into the pre-allocated bitmap memory block bit by bit to generate the binarized topology mask mapping map.

3. The method for determining the validity of match-3 game grids according to claim 1, characterized in that, The specific steps of S2 are as follows: S21: Initialize the scan line pointer, set the scan direction to traverse line by line from top to bottom, allocate a temporary buffer queue for each line to store the jump point position information, and reset the scan status register of the current line to a logic low level. S22: Read the level signal in the binary topology mask mapping map bit by bit along the horizontal direction, perform an XOR operation between the level value of the current bit and the level value of the previous bit, and determine the edge transition point when the operation result is true, and record the column index value of the transition point. S23: The scan line is segmented according to the recorded jump point column index value. The continuous area composed of logic high level is identified as the continuous valid line segment. The starting column coordinates corresponding to the left boundary and the ending column coordinates corresponding to the right boundary of multiple line segments are extracted respectively to generate the valid run interval data.

4. The method for determining the validity of match-3 game grids according to claim 1, characterized in that, The specific steps in S3 are as follows: S31: Based on the total grid width parameter of the match-3 game level, the two-dimensional row and column coordinates included in the effective run interval data are converted into continuous one-dimensional memory offsets using a linearization formula, and the correspondence between logical location and physical storage unit is established. S32: Traverse the effective run interval data between two adjacent rows, compare the column coordinate range of the current row interval segment and the next row interval segment, determine whether there is a vertical projection intersection, determine the block falling path connectivity, and generate the neighborhood connection attribute. S33: Encapsulate the starting column coordinates, the ending column coordinates, the one-dimensional memory offset, and the neighborhood connection attribute into a structure node, and push all nodes into a dynamic array in row number order to construct the compact sparse index list.

5. The method for determining the validity of match-3 game grids according to claim 1, characterized in that, The specific steps of S4 are as follows: S41: Create an iterator for traversing the compact sparse index list, sequentially read the starting column coordinates and the ending column coordinates stored in each structure node, and calculate the number of entities to be generated in the current interval. S42: Based on the calculated number of entities, repeatedly execute the object request operation, pop a batch of inactive game element entities from the pre-initialized object pool, and set the activation status flag of the entities to true; S43: Using the one-dimensional memory offset and row and column index in the structure node, calculate the position of each activated game element entity in the world coordinate system, attach the corresponding texture rendering component and physical collision component, and generate the match-3 game logic layout.

6. The method for determining the validity of match-3 game grids according to claim 2, characterized in that, The numerical comparison process in S12 includes: Obtain preset mask bit field configuration parameters, wherein the mask bit field configuration parameters define the bit features corresponding to the differentiated terrain types; Perform a bitwise AND operation on the obtained terrain identifier bit values, extract key feature bits, and determine whether the operation result is equal to the preset passable feature code; When the calculation result indicates that the current grid attribute is a normal plot, a conveyor belt plot, or a boost item plot, the passage condition is confirmed to be met and a logic high-level signal is output. When the calculation result indicates that the current grid property is a hollowed-out plot, that is, a fixed obstacle plot that cannot be eliminated or a locked plot, it is confirmed that the passage conditions are not met and a logic low-level signal is output.

7. The method for determining the validity of match-3 game grids according to claim 3, characterized in that, The XOR logic operation process in S22 includes: Load the binary level value of the current scan bit into the first register, load the binary level value of the previous bit into the second register, and call the processor's hardware XOR instruction to perform the operation on the values ​​of the two registers. If the XOR result is 1 and the value of the first register is 1, the current position is determined to be a rising edge transition point, and it is marked as the starting point of the new round of continuous valid line segments. If the XOR result is 1 and the value of the first register is 0, the current position is determined to be a falling edge transition point, and it is marked as the end point of the current continuous valid line segment; If the XOR result is 0, keep the current line segment state unchanged and continue to read the level signal of the next bit for subsequent detection.

8. The method for determining the validity of match-3 game grids according to claim 4, characterized in that, The calculation process for the projection overlap relationship in S32 includes: Obtain the horizontal span parameters of the current row interval and the horizontal span parameters of the next row interval to be detected. Combined with the gravity fall rule, calculate the overlap coefficient using the following formula: ； in, This represents the overlap coefficient. and These represent the starting column coordinates and the ending column coordinates of the consecutive valid line segments in the current row, respectively. and The starting column coordinates and the ending column coordinates respectively represent the starting column coordinates and the ending column coordinates of the adjacent line segment in the next row; The overlap coefficient is compared with a preset connectivity threshold. If it is greater than the threshold, the neighborhood connection attribute is marked as "vertically reachable", allowing the elimination of block fall across rows.

9. The method for determining the validity of match-3 game grids according to claim 5, characterized in that, The object request operation in S42 includes: Check if the idle queue pointer in the object pool points to an empty address to determine if there is a reusable game element entity. If the idle queue is not empty, remove an entity handle directly from the head of the queue, reset the entity's lifecycle counter and transformation matrix, and mark it as pending rendering. If the idle queue is empty, a dynamic expansion mechanism is triggered. The current memory block is requested according to the memory pressure coefficient of the current frame, a specified number of new entities are instantiated and added to the management list, and then the reference handle of the newly created entities is returned. After extracting entities, immediately update the statistics counters in the object pool to monitor whether the total number of active entities exceeds the warning threshold.

10. A system for determining the validity of match-3 game grids, characterized in that, The system is used to implement the method for determining the validity of match-3 game grids as described in any one of claims 1-9, and the system comprises: The binarized topology mapping construction module is used to obtain the original layout configuration data of the match-3 game level through the game engine interface, perform binarized threshold parsing on the terrain identifier bits in the original layout configuration data, map the grid where elimination blocks can be placed and the hollow obstacle grid to logic high level and logic low level respectively, and construct a binarized topology mask mapping map. The scan line run extraction module is used to call the scan line parsing algorithm to perform a line-by-line scan of the binarized topological mask mapping map, detect edge transition points where logic levels flip in multiple scan lines, calculate the start and end column coordinates of continuous valid line segments, and extract valid run interval data. The sparse index reorganization module is used to linearly reorganize the effective run interval data according to the row number order, establish a direct mapping index from two-dimensional logical coordinates to one-dimensional physical memory addresses, calculate the projection overlap relationship of multiple interval segments in the vertical direction to determine the neighborhood connection attribute, and construct a compact sparse index list. The logic layout generation module is used to sequentially parse the interval parameters stored in the compact sparse index list, extract game element entities from the object pool and bind rendering components only within the valid coordinate range defined by the interval segment, skip the logical calculation of invalid areas, and generate the match-3 game logic layout.

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