Memory system and controller thereof

Abstract

The present disclosure relates to a memory system and a controller of a memory system. The memory system according to an embodiment of the present disclosure includes a memory device including a plurality of first type planes and a plurality of second type planes, wherein each of the plurality of first type planes and each of the plurality of second type planes includes a plurality of main blocks and an additional block, and a controller configured to control the first additional block to perform an operation command, wherein the plurality of first type planes includes the first additional block allocated with a block address, and the plurality of second type planes includes the second additional block not allocated with the block address.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0001505, filed with the Korean Intellectual Property Office on January 6, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to an electronic device, including but not limited to a memory system and a controller for the memory system. Background Technology

[0003] A typical memory device includes multiple planes, each of which includes multiple memory blocks for storing data.

[0004] Multiple storage blocks include a main block that stores user data and an extra block that stores system information.

[0005] To increase memory capacity, the number of planes in the memory device is increased, as are the number of main blocks and the number of extra blocks. Summary of the Invention

[0006] A memory system according to an embodiment of the present disclosure may include: a memory device including a plurality of first-type planes and a plurality of second-type planes, wherein each of the plurality of first-type planes and each of the plurality of second-type planes includes a plurality of main blocks and additional blocks; and a controller configured to control a first additional block to execute operation commands, wherein the plurality of first-type planes include a first additional block with allocated block addresses, and the plurality of second-type planes include a second additional block without allocated block addresses.

[0007] A controller for a memory system according to an embodiment of the present disclosure may include: a block address decoder configured to decode a received block address to generate a block selection signal; and a block activator configured to determine, based on the block selection signal, whether to activate a first additional block in a first type of plane of the memory device, wherein the memory device includes a first type of plane and a second type of plane, each of the first type of plane and the second type of plane including a plurality of main blocks and additional blocks, the first type of plane including a first additional block with assigned block addresses, and the second type of plane including a second additional block without assigned block addresses. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure; Figure 2This is a diagram illustrating a memory device according to an embodiment of the present disclosure; Figure 3 This is a diagram illustrating a memory cell array according to an embodiment of the present disclosure; Figure 4A This is a diagram illustrating an additional block of a memory cell array having a four-plane structure according to an embodiment of the present disclosure; Figure 4B This is a diagram illustrating an additional block of a memory cell array having a six-plane structure according to an embodiment of the present disclosure; Figure 4C This is a diagram illustrating an additional block of a memory cell array having a six-plane structure according to an embodiment of the present disclosure; Figure 4D This is a diagram illustrating an additional block of a memory cell array having a six-plane structure according to an embodiment of the present disclosure; Figure 5A This is a table showing the addresses of storage blocks according to embodiments of this disclosure; Figure 5B This is a table showing the addresses of storage blocks according to embodiments of this disclosure; Figure 6A This is a diagram illustrating the block address decoder when it receives the master block allocation block address according to an embodiment of the present disclosure; Figure 6B This is a timing diagram illustrating the signals of a block address decoder according to an embodiment of the present disclosure; Figure 7A This is a diagram illustrating a block address decoder that receives a major block allocation block address according to an embodiment of the present disclosure; Figure 7B This is a timing diagram illustrating the signals of a block address decoder according to an embodiment of the present disclosure; Figure 8 This is a diagram illustrating a memory card system including a memory device according to an embodiment of the present disclosure; Figure 9 This is a diagram illustrating a solid-state drive (SSD) system including a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0009] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided merely as examples for illustrating the concepts disclosed in this application. Examples or embodiments based on these concepts may be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0010] Terms such as "first" and "second" are used to distinguish multiple components, but do not imply the size, order, priority, number, or importance of the components. For example, in one example, the first component may be referred to as the second component, while in another example, the second component may be referred to as the first component.

[0011] Embodiments of this disclosure include a memory system and a controller for the memory system, which can improve the storage efficiency of a memory device.

[0012] Figure 1 This is a diagram illustrating a memory system 1000 according to an embodiment of the present disclosure.

[0013] Reference Figure 1 The memory system 1000 includes a memory device 100 and a controller 200. The memory system 1000 communicates with the host 300.

[0014] The controller 200 communicates with the host 300 and accesses the memory device 100 in response to requests from the host 300. For example, the controller 200 controls programming, reading, and erasing operations of the memory device 100.

[0015] For example, controller 200 includes an interface between memory device 100 and host 300. Controller 200 drives the firmware of memory device 100. For example, controller 200 receives host commands and logical addresses from host 300 and controls memory device 100 to perform corresponding operations.

[0016] The controller 200 provides commands and physical addresses to the memory device 100. Commands sent to the memory device 100 are called "memory commands." Physical addresses are derived from logical addresses. Based on the memory commands and physical addresses, the memory device 100 performs programming, reading, and erasing operations. For example, the memory device 100 programs data into a region corresponding to a physical address derived from a received logical address, reads data from a region corresponding to a physical address derived from a received logical address, or erases data from a region corresponding to a physical address derived from a received logical address.

[0017] Figure 2 It is shown as an example Figure 1 A diagram of the memory device 100 shown. Figure 3 It is shown as an example Figure 2 The diagram shows a memory cell array.

[0018] Reference Figure 2 and Figure 3 The memory device 100 includes a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0019] The memory cell array 110 includes multiple planes, each of which includes multiple memory blocks. Each memory block includes multiple memory cells, and each of the multiple memory cells is connected to a row line RL and a bit line BL.

[0020] The peripheral circuitry 120 is configured, under the control of the control logic 130, to perform programming, reading, and erasing operations on selected regions of the memory cell array 110. For example, under the control of the control logic 130, the peripheral circuitry 120 applies various operating voltages to the row lines RL and BL, or selectively discharges the row lines RL and BL.

[0021] The peripheral circuit 120 includes a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0022] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row lines RL include at least one source select line, multiple word lines, and at least one drain select line. In this embodiment, the word lines include normal word lines and dummy word lines.

[0023] Row decoder 121 is configured to decode the row address RADD received from control logic 130. Row decoder 121 selects at least one memory block based on the decoded address. Row decoder 121 transmits the operating voltage Vop generated by voltage generator 122 to the row line RL of the selected memory block based on the decoded address.

[0024] For example, during a programming operation, the line decoder 121 applies a programming voltage to the selected word line and a programming pass voltage to the unselected word line, the programming pass voltage being lower than the programming voltage. During a programming verification operation, the line decoder 121 applies a verification voltage to the selected word line and a verification pass voltage to the unselected word line, the verification pass voltage being higher than the verification voltage. During a reading operation, the line decoder 121 applies a read voltage to the selected word line and a read pass voltage to the unselected word line, the read pass voltage being higher than the read voltage.

[0025] Erasing operations on memory device 100 are performed on a block-by-block basis. During the erase operation, line decoder 121 selects a memory block based on the decoded address. During the erase operation, line decoder 121 applies 0V or ground voltage to the word line connected to the selected memory block, or floats the word line.

[0026] Voltage generator 122 operates in response to control of control logic 130. Voltage generator 122 uses the external power supply voltage supplied to memory device 100 to generate multiple voltages. For example, in response to the operation signal OPSIG generated by control logic 130, voltage generator 122 generates various operating voltages Vop for programming, reading, and erasing operations. For example, in response to control of control logic 130, voltage generator 122 generates programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc.

[0027] Page buffer group 123 includes first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn are connected to the memory cell array 110 via corresponding bit lines BL. The first to nth page buffers PB1 to PBn operate in response to control logic 130. For example, page buffers PB1 to PBn operate in response to the page buffer control signal PBSIGNALS. For example, during a read operation or a verification operation, page buffers PB1 to PBn temporarily store data received using the corresponding bit line BL, or sense the voltage or current of the corresponding bit line BL.

[0028] During programming operations, when a programming voltage is applied to the selected word line, page buffers PB1 to PBn transmit the data DATA received via input / output circuit 125 to the selected memory cell through bit line BL. The memory cell of the selected page, based on the transmitted data DATA, is programmed. During programming verification operations, page buffers PB1 to PBn sense the voltage or current received from the selected memory cell through the corresponding bit line BL to read the page data.

[0029] During the read operation, under the control of the column decoder 124, page buffers PB1 to PBn read data DATA from the memory cell of the selected page through bit line BL and output the read data DATA to the input / output circuit 125.

[0030] During the erase operation, page buffers PB1 to PBn either float the corresponding bit line BL or apply an erase voltage to the corresponding bit line BL.

[0031] Column decoder 124 transfers data between input / output circuitry 125 and page buffer group 123 in response to column address CADD. For example, column decoder 124 exchanges data with page buffers PB1 to PBn via data lines DL, or with input / output circuitry 125 via column lines CL.

[0032] The input / output circuit 125 sends the command CMD and address ADDR received from the memory controller to the control logic 130, or it can exchange data DATA with the column decoder 124.

[0033] During a read or verification operation, the sensing circuit 126 generates a reference current in response to the allow bit signal VRYBIT, and compares the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current to output a pass signal PASS or a failure signal FAIL.

[0034] Control logic 130, in response to command CMD and address ADDR, outputs operation signal OPSIG, row address RADD, page buffer control signal PBSIGNALS, and enable bit signal VRYBIT to control peripheral circuitry 120. For example, control logic 130, in response to a block read command and address ADDR, controls the read operation on the selected memory block. Control logic 130, in response to a block erase command and address ADDR, controls the erase operation on the selected blocks included in the selected memory block. Control logic 130, in response to pass signal PASS or failure signal FAIL, determines whether the verification operation passes or fails.

[0035] Control logic 130 includes an address table storing address information used to select word lines and bit lines based on addresses. The address table includes not only the address information of the main blocks for each plane, but also the address information of additional blocks within the additional blocks that have been assigned block addresses. Although user access to the original additional blocks is restricted, when a block address is assigned to an additional block for a certain plane, the block address of that additional block for that plane is provided in the address table.

[0036] Reference Figure 3 The memory cell array 110 includes a first plane PL1 to an nth plane PLn. Each of the planes PL1 to PLn includes a main block, a replacement block, an extended block, an additional block, and an extra block.

[0037] The number of each of the main blocks, replacement blocks, extension blocks, supplementary blocks, and extra blocks included in the memory cell array 110 increases with the increase of memory capacity. The number of planes included in the memory cell array 110 can also increase with the increase of memory capacity.

[0038] The main block stores user data. Replacement blocks are used to replace main blocks that are identified as bad, defective, or unusable. Extension blocks expand the capacity of the main blocks. Supplementary blocks store information and data related to various currently executed memory operations in the event of a sudden power failure.

[0039] Additional blocks can be used as at least one of Content Addressable Memory (CAM) blocks and One-Time Programmable Memory (OTP) blocks. Among the additional blocks, those not used as CAM blocks can be unused blocks. CAM blocks are storage blocks that store information used during the operation of the memory device 100. The information used during the operation of the memory device 100 can be at least one of information used during the operation of the memory device, such as programming start voltage, programming pulse application time, and read level voltage. OTP blocks are storage blocks that store protected data information such as restricted access information, security information, encrypted information, and fixed data.

[0040] Return to reference Figure 1 The controller 200 includes a receiver 211, a block address decoder 212, and a block activator 213.

[0041] Receiver 211 receives commands and addresses input from host 300.

[0042] For example, the command is an operation command, including one of the following: a programming command, a read command, and an erase command. The memory block address refers to the address of the main block on which the operation command is executed.

[0043] The block address decoder 212 decodes the received block address to generate a block selection signal for selecting a storage block.

[0044] Block activator 213 determines whether the decoded block address corresponds to the mainblock allocation block based on the block selection signal, and activates the additional block based on the determination result. Block activator 213 can be configured as a logic circuit. For example, block activator 213 uses logic gates to perform logical operations on the decoded and output block selection signal, and determines whether to activate the block based on the value calculated or determined by the logical operation.

[0045] For example, when the decoded block address corresponds to an additional block in the first plane PL1 or the second plane PL2, and that additional block is a main block allocation block that has been allocated a main block address, the additional block activation unit 133 activates the additional block. When the decoded block address is not included in the main block addresses of the third plane PL3 to the sixth plane PL6, the additional block activation unit 133 does not generate an enable signal.

[0046] Figure 4A This is a diagram illustrating an additional block of a memory cell array having a four-plane structure according to an embodiment of the present disclosure.

[0047] Reference Figure 4A The memory cell array 110 includes planes PL1 to PL4, which comprise first extra blocks Extra1 to fourth extra blocks Extra4. The first extra block Extra1 of the first plane PL1 is used as the first CAM block CAM1, and the second extra block Extra2 of the second plane PL2 is used as the second CAM block CAM2. The third extra block Extra3 of the third plane PL3 is used as the first OTP block OTP1, and the fourth extra block Extra4 of the fourth plane PL4 is used as the second OTP block OTP2.

[0048] The memory cell array 110 with a four-plane structure includes four extra blocks Extra1 to Extra4, which are used as two CAM blocks CAM1 and CAM2 and two OTP blocks OTP1 and OTP2. The memory cell array 110 with a four-plane structure does not include unused extra blocks.

[0049] Figure 4B This is a diagram illustrating an additional block of a memory cell array having a six-plane structure according to an embodiment.

[0050] Reference Figure 4B The planes PL1 to PL6 of the memory cell array 110 include extra blocks Extra1 to Extra6.

[0051] The first extra block Extra1 of the first plane PL1 is used as the first CAM block CAM1, and the second extra block Extra2 of the second plane PL2 is used as the second CAM block CAM2. The third extra block Extra3 of the third plane PL3 is used as the first OTP block OTP1, and the fourth extra block Extra4 of the fourth plane PL4 is used as the second OTP block OTP2.

[0052] The fifth extra block Extra5 in the fifth plane PL5 and the sixth extra block Extra6 in the sixth plane PL6 are not used. Figure 4A Compared to memory cell arrays with a four-plane structure, Figure 4B The memory cell array with a six-plane structure has more planes. The fifth extra block (Extra5) and the sixth extra block (Extra6) of the fifth plane (PL5) are neither used as CAM blocks nor as OTP blocks, but exist in an unused state. As the number of planes increases, the number of extra blocks in the memory device also increases. Despite the increase in the number of extra blocks, the amount of data stored in the CAM blocks and OTP blocks may not increase. Figure 4B In a memory cell array with a six-plane structure, the fifth extra block (Extra5) and the sixth extra block (Extra6) are neither used as CAM blocks nor as OTP blocks, but exist as unused extra blocks. When unused extra blocks exist in a memory cell array with a planar structure, the storage efficiency of the memory device decreases, and storage space is wasted.

[0053] Figure 4C This is a diagram illustrating an additional block of a memory cell array having a six-plane structure according to an embodiment.

[0054] Reference Figure 4C The planes PL1 to PL6 of the memory cell array 110 include extra blocks Extra1 to Extra6.

[0055] The first extra block Extra1 of the first plane PL1 is used as the first CAM block CAM1, and the second extra block Extra2 of the second plane PL2 is used as the second CAM block CAM2. The third extra block Extra3 of the third plane PL3 is used as the first OTP block OTP1, and the fourth extra block Extra4 of the fourth plane PL4 is used as the second OTP block OTP2.

[0056] The fifth extra block Extra5 in plane PL5 and the sixth extra block Extra6 in plane PL6 are not unused. Extra5 in plane PL5 is used as the first main block allocation block MainA1, and Extra6 in plane PL6 is used as the second main block allocation block MainA2. Planes PL5 and PL6, where the main block allocation blocks reside, are referred to as planes of type 1, while planes PL1 to PL4, where no main block allocation blocks exist, are referred to as planes of type 2. As the number of planes increases, the number of extra blocks also increases. When a main block address is assigned to an extra block that is neither used as a CAM block nor as an OTP block, that extra block is used as storage space for user data. In this example, the settings for type 1 planes and type 2 planes can be specified by the user, or can be pre-specified by the manufacturer, for example, before being provided to the user.

[0057] Figure 4DThis is a diagram illustrating an additional block of a memory cell array having a six-plane structure according to an embodiment.

[0058] and Figure 4C The memory cell arrays in them are different. Figure 4D The memory cell array will allocate additional blocks, which will be used as major block allocation blocks, to the index ratio. Figure 4C The index is faster for the plane.

[0059] Reference Figure 4D The planes PL1 to PL6 of the memory cell array 110 include extra blocks Extra1 to Extra6.

[0060] The first extra block Extra1 of the first plane PL1 is used as the first main block allocation block MainA1, and the second extra block Extra2 of the second plane PL2 is used as the second main block allocation block MainA2.

[0061] The first plane PL1 and the second plane PL2 where a master block allocation block exists are called the first type of planes, while the third plane PL3 to the sixth plane PL6 where a master block allocation block does not exist are called the second type of planes.

[0062] Planes PL1 through PL6 can be indexed sequentially. For example, planes PL1 and PL2 of the first type can be indexed faster than planes PL3 through PL6 of the second type. When planes PL1 and PL2 of the first type have faster indexing than planes PL3 through PL6 of the second type, the storage space for user data in the memory system that stores information provided to the user can be represented as a contiguous data region.

[0063] The third extra block Extra3 of the third plane PL3 is used as the first CAM block CAM1, and the fourth extra block Extra4 of the fourth plane PL4 is used as the second CAM block CAM2. The fifth extra block Extra5 of the fifth plane PL5 is used as the first OTP block OTP1, and the sixth extra block Extra6 of the sixth plane PL6 is used as the second OTP block OTP2.

[0064] Figure 5A It is shown, for example, according to Figure 4B A table of storage block addresses for each plane.

[0065] Reference Figure 5A The storage block address of each of the multiple planes PL1 to PL6 includes the addresses of multiple main blocks, multiple extended blocks, multiple supplementary blocks, and additional blocks.

[0066] The address of the first plane PL1 is described as a representative of the addresses of multiple planes PL1 to PL6. The addresses of each of planes PL2 to PL6 are allocated in a similar manner to those of the first plane PL1.

[0067] The first plane PL1 includes multiple main blocks, multiple replacement blocks, multiple extended blocks, multiple supplementary blocks, and additional blocks. The addresses of storage blocks can be assigned only to user-accessible storage blocks. Therefore, users may not be able to access replacement blocks and additional blocks within the storage blocks, and storage block addresses may not be assigned to replacement blocks and / or additional blocks. Therefore, in this embodiment, the storage block addresses of the first plane PL1 can be sequentially assigned to the multiple main blocks, multiple extended blocks, and multiple supplementary blocks, which are user-accessible storage blocks.

[0068] In this example, the memory device has a six-plane architecture, where the number of primary blocks, secondary blocks, and supplementary blocks in the first plane PL1 are x, y, and z, respectively. The addresses of the first primary block, second primary block, third primary block, fourth primary block, ..., x-th primary block are 0, 1, 2, 3, ..., x-1, respectively. The addresses of the first secondary block, second secondary block, ..., y-th secondary block are x, x+1, ..., x+y-1, respectively. The addresses of the first supplementary block, second supplementary block, ..., z-th supplementary block are x+y, x+y+1, ..., x+y+z-1, respectively.

[0069] In this embodiment, the first plane PL1 has 273 main blocks, 7 extended blocks, and 26 supplementary blocks. In this example, the address of the first main block is 0, the address of the 273rd main block is 272, the address of the first extended block is 273, the address of the 7th extended block is 279, the address of the first supplementary block is 280, and the address of the 26th supplementary block is 305.

[0070] Figure 5B It is shown, for example, according to Figure 4D A table of storage block addresses.

[0071] Reference Figure 5B The storage block addresses of planes PL1 and PL2 include the addresses of multiple main blocks, multiple extended blocks, multiple supplementary blocks, and additional blocks.

[0072] The storage block addresses of planes PL3 to PL6 include the addresses of multiple main blocks, multiple extended blocks, multiple supplementary blocks, and additional blocks. In this embodiment, the user may not be able to access replacement blocks and used additional blocks within the storage blocks.

[0073] According to Figure 5B In one embodiment, storage block addresses are assigned to user-accessible storage blocks and additional blocks that are not accessible to the user.

[0074] The additional blocks in planes PL1 to PL4 are used as CAM blocks and OTP blocks; however, using the additional blocks in planes PL3 to PL6 as CAM blocks and OTP blocks can advantageously provide contiguous storage block information capable of storing user data.

[0075] Each of planes PL1 through PL6 includes an additional block. In the example of a conventional four-plane structure, the additional blocks of planes PL1 and PL2 are used as CAM blocks, and the additional blocks of planes PL3 and PL4 are used as OTP blocks. Figure 5B In this case, since the block addresses are assigned to the additional blocks of PL1 and PL2 respectively, these additional blocks are shown in the table displaying the storage block addresses.

[0076] To increase the capacity of a memory device, no additional use of the extra blocks is involved when the number of extra blocks increases due to the increase in the number of planes, but the data capacity used for CAM blocks and OTP blocks does not increase significantly. Therefore, in a memory device with a six- or more-plane structure, there may be unused extra blocks in planes PL5 and PL6.

[0077] In this embodiment, the addresses of the storage blocks of planes PL1 to PL6 that are accessible to the user can be sequentially assigned to multiple main blocks, multiple extended blocks, and multiple supplementary blocks.

[0078] For example, in a memory device with a six-plane architecture, the number of main blocks, the number of extended blocks, and the number of supplementary blocks in planes PL1 and PL2 are x, y, and z, respectively. The addresses of the first main block, second main block, third main block, fourth main block, ..., x-th main block are 0, 1, 2, 3, ..., x-1, respectively. The addresses of the first extended block, second extended block, ..., y-th extended block are x, x+1, x+2, ..., x+y-1, respectively. The addresses of the first supplementary block, second supplementary block, ..., z-th supplementary block are x+y, x+y+1, ..., x+y+z-1, respectively. The address of the supplementary block is the last block address among those allocated to the individual blocks. Therefore, the address of the supplementary block is x+y+z.

[0079] For example, each of planes PL1 and PL2 has 273 main blocks, 7 extended blocks, 26 supplementary blocks, and 1 extra block. The address of the 273rd main block is 272, the address of the 7th extended block is 279, the address of the 26th supplementary block is 305, and the address of the extra block is 306.

[0080] In an embodiment of a memory device with a six-plane structure, the number of primary blocks, the number of extended blocks, and the number of supplementary blocks in each of planes PL3 to PL6 are x, y, and z, respectively. The addresses of the first primary block, the second primary block, the third primary block, the fourth primary block, ..., the xth primary block are 0, 1, 2, 3, ..., x-1, respectively. The addresses of the first extended block, the second extended block, ..., the yth extended block are x, x+1, x+2, ..., x+y-1, respectively. The addresses of the first supplementary block, the second supplementary block, ..., the zth supplementary block are x+y, x+y+1, ..., x+y+z-1, respectively.

[0081] For example, in one embodiment, each of planes PL1 and PL2 has 273 main blocks, 7 extended blocks, 26 supplementary blocks, and 1 additional block. The address of the 273rd main block is 272, the address of the 7th extended block is 279, and the address of the 26th supplementary block is 305.

[0082] To prevent additional blocks with predetermined roles from becoming unused as the number of planes increases, block addresses are assigned to one or more unused additional blocks on one plane. For example, according to this disclosure, the address of an additional block on one or more planes is specified by adding 1 to the last address in the block address of the main block. Therefore, it is possible to simplify the process of assigning additional blocks to one or more planes while minimizing software changes. Figure 1 The physical logic circuit configuration added to the block address decoder 212.

[0083] Figure 6A This is a diagram illustrating the block address decoder when it receives the major block allocation block address of the plane, in which extra blocks are used as major block allocation blocks; Figure 6B It is shown, for example, according to Figure 6A Timing diagram of the signals of the block address decoder.

[0084] Reference Figure 6A and Figure 6B The block address decoder 212 receives plane and block addresses.

[0085] exist Figure 6A In the middle, the block address decoder 212 receives the PLANE1 / 2_SEL signal and the 9-bit block address <8:0> signal. The PLANE1 / 2_SEL signal indicates the identification information of the plane, and the 9-bit block address <8:0> signal indicates the block address 306.

[0086] Although the plane information P1 / P2 included in the signal information is grouped for convenience, the actual signal name refers to one of planes P1 or P2.

[0087] For example, plane information P1 / P2 is configured for either plane PL1 or PL2, which are first-type planes where extra blocks exist as accessible primary block allocation blocks. Therefore, EXTBLC_ENABLE_P1 / P2 is P1 Extra Block Enable when referring to the first extra block enable of the first plane PL1, or P2 Extra Block Enable when referring to the second extra block enable of the second plane PL2.

[0088] Since the last major block address in the major block address set is 305, the block address of the first extra block is 306, which is obtained by adding 1 to the last block address. In this example, the block address 306 of the first extra block is represented by the binary number 100110010. When 100110010 is divided into 3-bit groups, the first group is 4 (2'b100), the second group is 6 (2'b110), and the third group is 2 (2'n010), which is XC. <4> XB <6> and XA <2> The logic circuit is based on each signal XC. <4> XB <6> and XA <2> Generate the first extra block and enable P1 Extra block Enable.

[0089] When the block address consists of 9 bits, the input value obtained by dividing the block address into 3-bit groups is fed into an AND gate, and an enable signal is generated. Other numbers of bits can also be used. When from... Figure 1 When the address received by host 300 is identified as the first additional block of a first type of plane such as PL1 and PL2, block address decoder 212 generates an enable signal for the first additional block.

[0090] This disclosure customizes only a specific plane among multiple planes by allocating block addresses to additional blocks, while keeping the remaining planes unchanged. In an embodiment, the received signal XC is... <0> XB <0> and XA <0> To XC <4> XB <6> and XA <1> The logic circuit that outputs the enable signal is added to receive the signal XC corresponding to block address 306. <4> XB <6> and XA <2> And the logic circuit that outputs the enable signal. In Figure 6B When an erase setup command 60h is received for block address 306 in plane 1 or plane 2, EXBLC_ENABLE_P1 or EXBLC_ENABLE_P2 can be enabled because the block address is also assigned to the corresponding address 306 in plane 1 or plane 2. Figure 6AThe logic gates in the signal are activated. Therefore, according to this disclosure, by using the received signal XC... <4> XB <6> and XA <2> The logic circuit that outputs the enable signal can use an additional block as the main block with minimal or no software modifications.

[0091] Figure 2 The control logic 130 performs one of the following operations on the additional block corresponding to the selected address: programming, reading, or erasing.

[0092] Figure 7A This is a diagram illustrating the block address decoder when it receives the corresponding plane's main block allocation address in an example where the additional block is not used as the main block allocation block. Figure 7B It is shown, for example, according to Figure 7A Timing diagram of the block address decoder signal.

[0093] Although the plane information P3 / P4 / P5 / P6 included in the signal information is grouped for convenience, the actual signal name refers to one of planes P3, P4, P5, or P6.

[0094] For example, PLANE3 / 4 / 5 / 6_SEL refers to one of PLANE3_SEL, PLANE4_SEL, PLANE5_SEL, and PLANE6_SEL. The signals PLANE3_SEL, PLANE4_SEL, PLANE5_SEL, and PLANE6_SEL respectively refer to the signals that select the third plane PL3, the fourth plane PL4, the fifth plane PL5, and the sixth plane PL6. Each of PLANE3, PLANE4, PLANE5, and PLANE6 is a plane of type II and refers to planes from the third plane PL3 to the sixth plane PL6.

[0095] For example, EXTBLC_ENABLE_P3 / P4 / P5 / P6 or P3 / P4 / P5 / P6 Extra Block Enable refers to one of EXTBLC_ENABLE_P3, EXTBLC_ENABLE_P4, EXTBLC_ENABLE_P5, or EXTBLC_ENABLE_P6. The aforementioned signal is one of the extra block enable signals for the third plane PL3, the fourth plane PL4, the fifth plane PL5, and the sixth plane PL6.

[0096] Reference Figure 7A and Figure 7BThe block address decoder 212 receives one of the input signals PLANE3_SEL, PLANE4_SEL, PLANE5_SEL or PLANE6_SEL indicating the identification information of the plane, and receives the 9-bit block address <8:0>100110010 signal indicating the block address 306.

[0097] The last block address in the block address range is 305, and the received address 306 exceeds the range of 0 to 305. In this embodiment, the user is restricted from accessing additional blocks. Therefore, when the decoded address is XC, which is one of the planes PL3 to PL6 as a second type of plane... <4> XB <6> XA <2> At that time, the block address decoder does not select any block. This is because there is no block with XC. <4> XB <6> and XA <2> The corresponding logic circuit, therefore, as Figure 7B As shown, no enable signal is generated in the block address decoder 212, and the ready / busy R / B signal is activated for a short time tBERS and then deactivated. Figure 7B When an erase setting command 60h is received for block address 306 in plane 3, plane 4, plane 5 or plane 6, since the block address has not been assigned to the corresponding address 306 in plane 3, plane 4, plane 5 and plane 6, when a status read operation 70h is requested for the block, the block is treated as a bad block, defective block or unusable block.

[0098] Figure 8 This is a diagram illustrating a memory card system including a memory device according to an embodiment of the present disclosure.

[0099] Reference Figure 8 The memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0100] Controller 3100 is connected to memory device 3200. Controller 3100 is configured to access memory device 3200. For example, controller 3100 is configured to control programming, reading, and erasing operations on memory device 3200, or to control background operations. Controller 3100 is configured to provide an interface between memory device 3200 and a host. Controller 3100 is configured to run firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit.

[0101] Controller 3100 communicates with external devices via connector 3300. Controller 3100 communicates with external devices—such as a host—according to a specific communication protocol. For example, controller 3100 is configured to communicate with external devices via at least one of various communication standards or interfaces, such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, or High Speed ​​Non-Volatile Memory (NVMe). For example, connector 3300 can be configured to communicate with at least one of these various communication standards or interfaces.

[0102] The memory device 3200 includes memory cells and can be similar to... Figure 1 The memory device 100 is configured to include, for example, a combination of Figure 3 , Figures 4A to 4D , Figure 5A and Figure 5B The additional block described.

[0103] The controller 3100 and the memory device 3200 are integrated into a semiconductor device within the memory card. For example, the controller 3100 and the memory device 3200 may be integrated into a semiconductor device within a memory card such as: PCMCIA memory card, compact flash (CF) card, smart media card (SM, SMC), memory stick, multimedia card (MMC, RS-MMC, MMCmicro), secure digital (SD) card (SD, mini SD, micro SD, SDHC), or universal flash (UFS) device.

[0104] Figure 9 This is a diagram illustrating a solid-state drive (SSD) system 4000 including a memory device according to an embodiment of the present disclosure.

[0105] Reference Figure 9 The SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals SIG with the host 4100 through a signal connector 4001 and receives power PWR through a power connector 4002. The SSD 4200 includes a controller 4210, multiple memory devices 4221 to 422n, an auxiliary power supply 4230, and buffer memory 4240.

[0106] The controller 4210 can control multiple memory devices 4221 to 422n in response to signals received from the host 4100. For example, the signal can be based on the interface between the host 4100 and the SSD 4200. For example, the signal can be defined by at least one interface such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Accessory (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe interface.

[0107] The plurality of memory devices 4221 to 422n include units capable of storing data. Each of the plurality of memory devices 4221 to 422n may be similar to Figure 1 The memory device 100 shown is configured to include, for example, a combination of Figure 3 , Figures 4A to 4D , Figure 5A and Figure 5B The additional block described.

[0108] Auxiliary power supply 4230 is connected to host 4100 via power connector 4002. Auxiliary power supply 4230 receives power from host 4100 and can charge it. When the power supply from host 4100 is unstable or unstable, auxiliary power supply 4230 provides power voltage to SSD 4200. For example, auxiliary power supply 4230 may be located inside or outside SSD 4200. For example, auxiliary power supply 4230 may be located within the motherboard and can provide auxiliary power to SSD 4200.

[0109] Buffer memory 4240 operates as a buffer memory for SSD 4200. For example, buffer memory 4240 temporarily stores data received from host 4100 or from multiple memory devices 4221 to 422n, or temporarily stores metadata such as mapping tables for memory devices 4221 to 422n. Buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, or LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, or PRAM.

[0110] According to embodiments of this disclosure, by allocating a main block address to an unused extra block in the memory device and using that extra block as a main block, storage space waste can be prevented and the storage efficiency of the memory system can be improved.

[0111] The relevant concepts have been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions can be made without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered illustrative rather than restrictive. Therefore, the scope of this disclosure is not limited to the description provided. All changes within the meaning and equivalents of the claims are included within the scope of this disclosure.

Claims

1. A memory system, comprising: A memory device includes a plurality of first-type planes and a plurality of second-type planes, each of the plurality of first-type planes and each of the plurality of second-type planes including a plurality of main blocks and additional blocks; as well as A controller controls a first additional block to execute operation commands, the first additional block being included in the plurality of first-type planes and being assigned block addresses; The plurality of first-type planes include the first additional block that has been assigned the block address, and the plurality of second-type planes include the second additional block that has not been assigned the block address.

2. The memory system according to claim 1, wherein, The last block address assigned to the plurality of first-type planes is assigned to the first additional block.

3. The memory system according to claim 1, wherein, The second additional block included in the plurality of second-type planes is one of a single-programmable memory block, i.e., an OTP block, and a content-addressable memory block, i.e., a CAM block.

4. The memory system according to claim 1, wherein, The plurality of first-type planes and the plurality of second-type planes are indexed sequentially; and The indexing of the plurality of first-type planes is faster than the indexing of the plurality of second-type planes.

5. The memory system according to claim 1, wherein, When the address received from the host is a block address of the plurality of first-type planes and is assigned to the first additional block, the controller generates an enable signal to activate the first additional block.

6. The memory system according to claim 5, wherein, The controller includes a first logic circuit that generates the enable signal for the first additional block.

7. The memory system according to claim 3, wherein, When the block address received from the host is a block address of the plurality of second-type planes and the second additional block is addressed, the controller does not select a primary block.

8. The memory system according to claim 1, wherein, The controller includes a block address decoder, which decodes the received block address to generate a block selection signal.

9. The memory system according to claim 1, wherein, The operation commands include programming commands, reading commands, and erasing commands for the first additional block.

10. The memory system according to claim 1, wherein, The block address consists of 9 bits, and the 9 bits are divided into 3-bit groups as input signals to the logic circuit.

11. A controller for a memory system, the controller comprising: The block address decoder decodes the received block address to generate a block selection signal; as well as A block activator determines, based on the block selection signal, whether to activate a first additional block in a first type of plane of the memory device; The memory device includes a first type of plane and a second type of plane, each of the first type of plane and the second type of plane including a plurality of main blocks and additional blocks, the first type of plane including a first additional block with allocated block addresses, and the second type of plane including a second additional block without allocated block addresses.

12. The controller for the memory system according to claim 11, wherein, The last block address assigned to the first type of plane is assigned to the first additional block.

13. The controller for the memory system according to claim 11, wherein, The second additional block included in the second type of plane is one of a once-programmable memory block, i.e., an OTP block, and a content-addressable memory block, i.e., a CAM block.

14. The controller for the memory system according to claim 11, wherein, The first type of plane and the second type of plane are indexed sequentially; and The indexing of the first type of plane is faster than the indexing of the second type of plane.

15. The controller for the memory system according to claim 11, wherein, When an address received from the host is associated with a plane of the first type and the block address is assigned to the first additional block, an enable signal is generated to activate the first additional block.

16. The controller for the memory system according to claim 15, wherein, The block activator includes a first logic circuit that generates the enable signal for the first additional block.

17. The controller for the memory system according to claim 13, wherein, When the block address received from the host is a block address of the second type of plane and the second additional block is addressed, the primary block is not selected.

18. The controller for the memory system of claim 11, further comprising a block address decoder, the block address decoder decoding the received block address to generate a block selection signal.

19. The controller for the memory system according to claim 11, wherein, The operation commands include programming commands, reading commands, and erasing commands for the first additional block.

20. The controller for the memory system according to claim 11, wherein, The block address consists of 9 bits, and the 9 bits are divided into 3-bit groups as input signals to the logic circuit.

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