Integrated development environment system for systemverilog hardware design language

Abstract

The application discloses a kind of incremental semantic analysis integrated development environment systems for SystemVerilog hardware design language, comprising: workspace discovery component, for automatically identifying project list and constructing project boundary;Virtual file system component, for maintaining source path and file identification mapping and tracking file status;Incremental semantic database component, for performing local failure and incremental recalculation after source code changes;Semantic capability component, for providing completion, jump, reference, renaming, semantic highlighting, formatting and other capabilities;Protocol scheduling component, for unified scheduling and returning results to requests, notifications, background tasks.The application can perform real-time semantic processing on Verilog / SystemVerilog code in a continuous editing scenario, reduce the delay caused by full recalculation, and improve hardware design and development efficiency.

Description

Technical Field

[0001] This invention relates to an integrated development environment system for incremental semantic analysis of the SystemVerilog hardware design language, belonging to the field of hardware design automation software and programming language analysis technology. Background Technology

[0002] Hardware design refers to the design and implementation of the logical structure and implementation path of an electronic system or chip based on functional requirements. Its core components include, but are not limited to, processor modules and bus interconnect modules. With the evolution of process nodes and the increase in system complexity, modern hardware design has shifted from single-module development to a comprehensive R&D model that integrates multi-module collaboration, cross-team collaboration, and cross-engineering reuse. Under this model, the size of the design code continues to increase, and the number of files, hierarchical instance relationships, parameter configuration relationships, and cross-file symbol reference relationships increase significantly, placing higher demands on the maintainability and verifiability of hardware description language engineering.

[0003] In the specific R&D process, design engineers typically first use Verilog or SystemVerilog to describe the hardware behavior and structure, and then gradually achieve design convergence through simulation, synthesis, timing analysis, formal verification, and other methods. The "code editing phase" in this process is the input foundation for subsequent verification and implementation phases, and its quality directly affects the efficiency of subsequent processes. If the code analysis system cannot quickly return accurate semantic results after local changes, it will directly lengthen the R&D feedback loop, reduce R&D efficiency, and increase the risk of human error.

[0004] Among the current technical solutions, common approaches include full updates, lexical-level completion, and syntax tree analysis. 1) The full-update analysis approach involves a complete scan of the project each time analysis is triggered, reading a large number of source code files and re-executing parsing, relationship establishment, and result output. Its advantages include an intuitive workflow, unified implementation, and easily manageable result consistency. Its disadvantages include coarse-grained calculations, making it difficult to effectively distinguish between "changed code areas" and "unchanged code areas." When the project is large and editing frequency is high, this approach repeatedly processes a large amount of unchanged content, leading to a significant increase in response time. Especially in scenarios where developers continuously input code, full updates consume substantial computing resources, causing delays or even interruptions in interactive capabilities such as code completion, navigation, and renaming.

[0005] 2) Lexical-level lightweight analysis refers to generating suggestions through keyword dictionaries, string prefix matching, or simple rule matching, focusing on solving basic input suggestion problems. This approach can be helpful in small-scale script scenarios, but it has significant limitations in SystemVerilog engineering scenarios: First, it lacks understanding of semantic relationships such as module instances, port connections, parameter passing, and scope masking; second, it struggles to handle cross-file definitions and references; and third, it easily generates candidate results that do not conform to syntactic or semantic constraints when faced with complex contexts. Because this type of solution mainly stays at the lexical level, it cannot meet the needs of engineering-level semantic interaction.

[0006] 3) Syntax tree analysis refers to constructing a syntax tree based on the source code and performing checks and navigation at the syntactic structure level, providing stronger structure awareness than lexical methods. Typical outputs include syntax error locations, structured nodes, and local scope information. This approach has certain advantages in syntax correctness checking, but most implementations still focus on syntactic layer information, lacking a complete construction of semantic intermediate representations, symbol definition relationships, scope resolution relationships, and reference propagation relationships. Furthermore, hardware projects typically include a main project and multiple dependent libraries. If the variation characteristics of different source roots are not distinguished, stable results on the library side will frequently become invalid, further amplifying analysis costs. Existing solutions lack a unified link between protocol scheduling and incremental semantic computation, making it difficult to balance response latency and result consistency.

[0007] SystemVerilog is one of the most commonly used hardware description and verification languages ​​in current chip design and verification workflows, and it has been widely applied in engineering practices such as processors, bus interconnects, memory controllers, and SoC integration. Hardware code written in SystemVerilog typically undergoes syntax checking and partial simulation during the editing phase before proceeding to synthesis, formal verification, and back-end implementation, relying on various EDA tools to complete timing convergence and tape-out manufacturing. However, large-scale projects involve complex cross-file symbol relationships, deep instance hierarchies, and strong coupling between parameters and ports. Traditional editing aids based on full recalculation, lexical rules, or syntax trees struggle to provide low-latency and consistent semantic feedback in scenarios with continuous modifications. Furthermore, after locating completion errors, jump failures, and missing references, developers often need to manually trace semantic relationships across files, resulting in high debugging costs. Currently, there is still a lack of an integrated tool solution that can directly provide incremental semantic analysis for SystemVerilog projects at the editing end, and uniformly support completion, navigation, reference renaming, semantic highlighting, and formatting collaborative processing. Summary of the Invention

[0008] Objective: To address the problems and shortcomings of existing technologies, this invention provides an integrated development environment (IDE) system for incremental semantic analysis using the SystemVerilog hardware design language. Through workspace discovery, file status management, and collaboration with an incremental semantic database, it enables rapid analysis and stable feedback under localized modifications.

[0009] Technical solution: An integrated development environment system for incremental semantic analysis of the SystemVerilog hardware design language, comprising the following components: 1) The workspace discovery component is used to find the project configuration list, construct the workspace boundary based on the project configuration list, determine the workspace file set and library file set, and read the project-related configurations; 2) Virtual file system component, used to maintain the mapping from file path to file identifier, record the creation, modification and deletion status of files, calculate changes and store the changes in the queue of changes to be committed; 3) Incremental semantic database component, used to receive file changes and commit transactions, and perform incremental updates on parse trees, semantic intermediate representations and scope queries; 4) Semantic capability components, which provide features such as code completion, definition navigation, declaration navigation, reference lookup, renaming, semantic highlighting, signature assistance, formatting, and code actions; 5) Protocol scheduling component, used to route messages of different protocols to the corresponding processing channels, drive change submission and workspace refresh after event processing, and respond to requests.

[0010] The following sections will introduce the content and specific technologies of each component: 1) Workspace Discovery Component. This component first recursively searches the project configuration manifest within the project based on the project path provided by the client. If no project configuration manifest is found, the component generates a blank workspace configuration manifest containing pre-defined default settings. Then, based on the workspace configuration manifest, the component constructs the workspace boundaries, determining and searching for the corresponding workspace file sets and library file sets according to the configuration. The library file set is assumed not to be modified during development, thus its update priority is reduced to the lowest, improving the update rate of other files. Finally, the component reads other relevant configurations from the workspace configuration manifest and sets the project accordingly.

[0011] 2) Virtual File System Component. This component is responsible for converting external file system changes into a computable internal change sequence. The virtual file system component's data structure includes: a path index table, a file state table, and a queue of changes to be committed. During file updates, the component first normalizes the path and maps it to a file identifier. If the file identifier already exists, it is reused; otherwise, a new file identifier is generated for mapping. Then, the component records the file's state: if the old state exists and the new content is the same, the update is discarded; if the old state is deleted and the new content is readable, a file creation event is generated; if the old state exists and the new content is different, a file modification event is generated; if the old state exists but reading fails, a file deletion event is generated. Next, the component calculates the changes, folding and merging consecutive changes with the same identifier to retain the final valid state, thereby effectively reducing the number of changes and minimizing memory usage and latency. Finally, the component stores the calculated changes in the queue of changes to be committed for use by subsequent components.

[0012] 3) Incremental Semantic Database Component. This component employs a transactional incremental update mechanism. At runtime, it first receives file change records from the virtual file system, organizes and categorizes them, and then uses these records to update the text input and file set input in the database. When this component is queried by the semantic capability component, its incremental update function is triggered. Based on the graph of computational dependencies, the component searches from top to bottom for unchanged nodes and performs corresponding incremental updates on the parse tree, semantic intermediate representation, and scope query based on the affected query region. When an unchanged computational node is found, the search stops, the previously computed cache is returned, and new computational cache results are generated based on the dependencies.

[0013] 4) Semantic Capability Component. This component utilizes semantic information provided by the incremental semantic database component to complete semantic interaction functions. These functions include code completion, definition navigation, declaration navigation, reference lookup, renaming, semantic highlighting, signature assistance, formatting, and code actions. The completion process constructs a completion context based on the trigger character and context qualifiers; then it identifies syntax regions within the completion context, such as module instantiation and port declaration; next, it routes the completion request to semantic completion branches such as module instantiation completion and named port completion; if no valid replacement region is identified during this process, it directly returns an empty completion result to avoid generating invalid edits; The definition jump will be parsed on the mapping relationship between the syntax node and the semantic definition, the semantic object corresponding to the syntax node will be obtained, the definition position corresponding to the identifier will be calculated and output, and the jump information will be generated based on the definition position; Declaration jumps are resolved by parsing the mapping relationship between syntax nodes and semantic definitions, obtaining the declaration object corresponding to the syntax node, and then calculating the declaration position corresponding to the identifier. When the declaration position is unavailable, it will actively fall back to the definition position and recalculate. When neither the definition nor the declaration can be resolved, it will directly return an empty navigation result to ensure that the navigation behavior is consistent with the semantic state. The reference lookup first locates the corresponding semantic definition and then finds all semantic references used by that semantic definition. Subsequently, the system summarizes and organizes these reference results to generate a jump list, making it convenient for users to navigate and track between different reference locations efficiently. Renaming modifies the identifier name at a given location and simultaneously modifies the semantic definition and semantic reference corresponding to that location based on semantic association information, enabling rapid code refactoring. Semantic highlighting distinguishes different types of identifiers more precisely based on semantic information, including type and context information. By highlighting special identifiers in the code through special coloring, it improves code readability and helps users understand the code structure and semantic roles more intuitively. Signature assistance can analyze the current input context in real time when modifying module instantiation or function calls, and prompt module interface information or function parameter information, reducing the cost of consulting documentation or manually comparing interface definitions, and improving coding efficiency and accuracy; The formatting process calls an external SystemVerilog formatting tool to obtain the formatted text, performs a difference comparison between the original text and the formatted text, generates an editing patch, and minimizes irrelevant changes to ensure code style consistency; then it applies the editing patch to the corresponding file. The code actions will generate automatic editing operations based on the code context and analyze the semantic objects edited by the user, performing operations such as generating, modifying or deleting code, reducing repetitive user operations and improving development efficiency.

[0014] 5) Protocol Scheduling Component. This component receives information from clients or the file system and routes it to the corresponding processing channel. The processing channel uses a thread pool to handle different requests using multiple threads. After processing an event, this component collects changes generated during event processing, drives change commit, and refreshes the workspace to update project information, ensuring consistency. Finally, the component combines this information to respond to the processed event, sends the response to the client, and then enters the next processing loop.

[0015] Beneficial effects: Compared with existing technical solutions, the present invention has the following advantages: 1) This invention adopts an incremental transaction update mechanism, which avoids full recalculation in local editing scenarios and significantly reduces the overhead of repeated calculations.

[0016] 2) This invention maintains result consistency in concurrent interaction scenarios by analyzing snapshots to execute semantic requests.

[0017] 3) This invention designs completion and navigation strategies for high-frequency semantic scenarios in SystemVerilog, improving the effectiveness of suggestions and the accuracy of positioning.

[0018] 4) This invention supports automatic discovery and dynamic refreshing of the workspace, and can continuously provide available capabilities after changes in the engineering structure. Attached Figure Description

[0019] Figure 1 This is a flowchart of the system implementation in an embodiment of the present invention. Detailed Implementation

[0020] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading the present invention, any modifications of the present invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.

[0021] like Figure 1 As shown, when analyzing a specific SystemVerilog hardware design project, the incremental semantic analysis integrated development environment system for the SystemVerilog hardware design language includes: 1) Workspace Discovery Component. This component first recursively searches the project configuration manifest within the project based on the project path provided by the client. If no project configuration manifest is found, the component generates a blank workspace configuration manifest containing pre-defined default settings. Then, based on the workspace configuration manifest, the component constructs the workspace boundaries, determining and searching for the corresponding workspace file sets and library file sets according to the configuration. The library file set is assumed not to be modified during development, thus its update priority is reduced to the lowest, improving the update rate of other files. Finally, the component reads other relevant configurations from the workspace configuration manifest and sets the project accordingly.

[0022] When recursively searching the project configuration manifest, a candidate root set is first generated based on the project path location. Then, a configuration manifest search is performed on each candidate root. The configuration manifest search prioritizes a direct search strategy within the current directory. If no match is found, a backtracking search of the parent directory is performed. If the backtracking still fails, a probe of the first-level subdirectories is then performed to avoid amplified directory traversal during the startup phase due to deep recursion. For each found configuration manifest, the system parses the project file list and converts the parsing results into a unified workspace object, thus constructing the workspace boundary. Then, the component searches for the corresponding workspace file set and library file set based on the workspace boundary, setting different priorities. Finally, the component reads other relevant configurations from the workspace configuration manifest, including macro-related configurations and top-level project information, to configure the project.

[0023] 2) Virtual File System Component. This component is responsible for converting external file system changes into a computable internal change sequence. The virtual file system component's data structure includes: a path index table, a file state table, and a queue of changes to be committed. During file updates, the component first normalizes the path and maps it to a file identifier. If the file identifier already exists, it is reused; otherwise, a new file identifier is generated for mapping. Then, the component records the file's state: if the old state exists and the new content is the same, the update is discarded; if the old state is deleted and the new content is readable, a file creation event is generated; if the old state exists and the new content is different, a file modification event is generated; if the old state exists but reading fails, a file deletion event is generated. Next, the component calculates the changes, folding and merging consecutive changes with the same identifier to retain the final valid state, thereby effectively reducing the number of changes and minimizing memory usage and latency. Finally, the component stores the calculated changes in the queue of changes to be committed for use by subsequent components.

[0024] In the data structures maintained by this component, the path index table maps absolute file paths to stable file identifiers, the file status table records file existence status, file text content, and a list of line terminators, and the pending change queue records and buffers creation, modification, and deletion changes in the current event cycle. Through these data structures, the virtual file system component can transform unstable external file event streams into predictable, mergeable, and incrementally processable internal change streams.

[0025] 3) Incremental Semantic Database Component. This component employs a transactional incremental update mechanism. At runtime, it first receives file change records from the virtual file system, organizes and categorizes them, and then uses these records to update the text input and file set input in the database. When this component is queried by the semantic capability component, its incremental update function is triggered. Based on the graph of computational dependencies, the component searches from top to bottom for unchanged nodes and performs corresponding incremental updates on the parse tree, semantic intermediate representation, and scope query based on the affected query region. When an unchanged computational node is found, the search stops, the previously computed cache is returned, and new computational cache results are generated based on the dependencies.

[0026] To ensure concurrency consistency, all semantic capability requests are based on database snapshot reads, which remain read-only and stable throughout the lifecycle of a single request. When the incremental semantic database component retrieves file change records from the virtual file system, it first requires semantic queries still executing on older database snapshots to exit as soon as possible, preventing long-running queries from occupying the old state and blocking the new state from taking effect. The component then applies the file change records to the database input layer in one go, and the database automatically propagates the changes to the derived query layer. The derived query layer calculates the dependency graph and searches for unchanged nodes from top to bottom according to the hierarchical structure. For affected query regions, it performs corresponding update operations and maintains cached information.

[0027] 4) Semantic Capability Component. This component utilizes semantic information provided by the incremental semantic database component to complete semantic interaction functions. This component is uniformly built on the incremental semantic database snapshot, avoiding inconsistencies in results caused by changes in the underlying state during request execution. The semantic interaction functions include completion, definition jump, declaration jump, reference lookup, renaming, semantic highlighting, signature help, formatting, and code actions.

[0028] The completion process constructs a completion context based on the trigger character and context qualifiers. This context includes lexical regions, syntactic regions, trigger characters, replacement ranges, and prefixes. Then, it identifies syntactic regions within the completion context, such as module instantiation and port declarations. Next, it routes the completion request to semantic completion branches, such as module instantiation completion and named port completion. Specifically, the system returns port candidates in named port scenarios, instantiation parameter candidates in module instantiation scenarios, visible members in member access scenarios, and trigger items in sensitive list scenarios. If no valid replacement region is identified during this process, an empty completion result is returned directly to avoid generating invalid edits. The definition jump is parsed on the mapping relationship between the syntax node and the semantic definition, the semantic object corresponding to the syntax node is obtained, the definition position corresponding to the identifier is calculated and output, and the jump information is generated according to the definition position; after receiving the cursor position, this component first converts the outer row and column coordinates into the inner offset, and then locates the syntax node at the offset to complete the parsing of the mapping relationship. Declaration jumps are resolved by parsing the mapping relationship between syntax nodes and semantic definitions, obtaining the declaration object corresponding to the syntax node, and then calculating the declaration position corresponding to the identifier. When the declaration position is unavailable, it will actively fall back to the definition position and recalculate. When neither the definition nor the declaration can be resolved, it will directly return an empty navigation result to ensure that the navigation behavior is consistent with the semantic state. The reference lookup first locates the corresponding semantic definition and then finds all semantic references used by that semantic definition. Subsequently, the system summarizes and organizes these reference results to generate a jump list, which includes a set of deduplicated file ranges, making it convenient for users to navigate and track between different reference locations efficiently. Renaming modifies the identifier name at a given location and simultaneously modifies the semantic definition and semantic reference corresponding to that location based on semantic association information, enabling rapid code refactoring. To ensure reliability, renaming performs a new name validity check before execution to prevent duplicate names from breaking program semantics. Semantic highlighting distinguishes different types of identifiers more precisely based on semantic information, including type and context information. By highlighting special identifiers in the code, it improves code readability and helps users understand the code structure and semantic roles more intuitively. When highlighting, the component first collects semantic intervals within the request range and establishes a nested interval structure. Then, it performs flattening and segmentation during output to obtain highlighting information for non-overlapping marker sequences, which is convenient for client-side rendering. The signature help function can analyze the current input context in real time when modifying module instantiation or function calls, and prompt module interface information or function parameter information, reducing the cost of consulting documentation or manually comparing interface definitions, and improving coding efficiency and accuracy. During execution, the component will reverse locate the calling or instantiating node, identify the current active parameter position, and then combine it with the target definition to output signature text, parameter list and active parameter index for client rendering of signature help information. The formatting process calls an external SystemVerilog formatting tool to obtain the formatted text, compares the original text and the formatted text to identify the added, deleted, or modified positions, and generates an editing patch. The editing patch must ensure that code content, text positions, and the original editing area that are unrelated to the formatting adjustment will not undergo any additional changes, thereby minimizing irrelevant modifications to ensure the standardization of code style; and then the editing patch is applied to the corresponding file. The code actions analyze the semantic objects edited by the user based on the code context, including the current cursor position, the selected text range, and syntactic structure information. Then, it generates automatic editing operations, such as automatically completing missing parameters, automatically completing port connections, inserting templated code snippets, adjusting existing declarations, or removing redundant code, to generate, modify, or delete code, reducing repetitive user operations and improving development efficiency.

[0029] 5) Protocol Scheduling Component. This component receives information from clients or the file system and routes it to the corresponding processing channel. The processing channel uses a thread pool to handle different requests using multiple threads. After processing an event, this component collects changes generated during event processing, drives change commit, and refreshes the workspace to update project information, ensuring consistency. Finally, the component combines this information to respond to the processed event, sends the response to the client, and then enters the next processing loop. This component is responsible for uniformly receiving and processing request messages, notification messages, response messages, background task results, and file system events. The component adopts an event-driven model, distributing tasks to thread pools in different processing channels according to event type to execute corresponding processing logic. After each round of event processing, the component collects change information generated during event processing, drives change commit, and initiates a workspace refresh and dynamic registration process to ensure consistency between the client's capability view and the server's internal state.

[0030] According to the method and software system of the present invention, users can obtain stable, real-time semantic feedback while continuously editing SystemVerilog code, reducing redundant computation overhead without sacrificing analysis accuracy. Furthermore, the system supports maintaining a high reusability of analysis in scenarios with multiple workspaces and dependent libraries, making it suitable for engineering practices such as chip design, verification, and collaborative development.

[0031] It is obvious to those skilled in the art that the steps of the methods described in the embodiments of the present invention can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using device-executable program code, which can then be stored in a storage device for execution by a computing device. Furthermore, in some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the embodiments of the present invention are not limited to any particular hardware and software combination.

Claims

1. An integrated development environment system for incremental semantic analysis of the SystemVerilog hardware design language, characterized in that, Includes the following components: 1) The workspace discovery component is used to find the project configuration list, construct the workspace boundary based on the project configuration list, determine the workspace file set and library file set, and read the project-related configurations; 2) Virtual file system component, used to maintain the mapping from file path to file identifier, record the creation, modification and deletion status of files, calculate changes and store the changes in the queue of changes to be committed; 3) Incremental semantic database component, used to receive file changes and commit transactions, and perform incremental updates on parse trees, semantic intermediate representations and scope queries; 4) Semantic capability components, which provide features such as code completion, definition navigation, declaration navigation, reference lookup, renaming, semantic highlighting, signature assistance, formatting, and code actions; 5) Protocol scheduling component, used to route messages of different protocols to the corresponding processing channels, drive change submission and workspace refresh after event processing, and respond to requests.

2. The incremental semantic analysis integrated development environment system for SystemVerilog hardware design language according to claim 1, characterized in that, The workspace discovery component first recursively searches for the project configuration list in the project based on the project path provided by the client; if the project configuration list is not found, the component will generate a blank workspace configuration list. Then, based on the workspace configuration manifest, the component constructs the workspace boundaries, determines and locates the corresponding workspace file set and library file set according to the configuration; finally, the component reads other relevant configurations in the workspace configuration manifest and sets up the project.

3. The incremental semantic analysis integrated development environment system for SystemVerilog hardware design language according to claim 1, characterized in that, The virtual file system component is responsible for converting external file system changes into a computable internal change sequence. The virtual file system component's data structure includes a path index table, a file state table, and a queue of changes to be committed. During file updates, the component first normalizes the path and maps it to a file identifier. Then, the component records the file's state: if the old state exists and the new content is the same, the update is discarded; if the old state is deleted and the new content is readable, a file creation event is generated; if the old state exists and the new content is different, a file modification event is generated; if the old state exists but reading fails, a file deletion event is generated. Finally, the component calculates the changes, folds and merges consecutive changes with the same identifier to retain the final valid state, and stores the calculated changes in the queue of changes to be committed.

4. The integrated development environment system for incremental semantic analysis of SystemVerilog hardware design language according to claim 1, characterized in that, The incremental semantic database component employs a transactional incremental update mechanism. This component first receives file change records from the virtual file system, organizes and categorizes them, and then uses these records to update the text input and file set input in the database. When this component is queried by the semantic capability component, its incremental update function is triggered, performing corresponding incremental update operations on the parse tree, semantic intermediate representation, and scope query based on the affected query region.

5. The incremental semantic analysis integrated development environment system for SystemVerilog hardware design language according to claim 1, characterized in that, The semantic capability component can utilize the semantic information provided by the incremental semantic database component to complete semantic interaction functions. These semantic interaction functions include: code completion, definition navigation, declaration navigation, reference lookup, renaming, semantic highlighting, signature assistance, formatting, and code actions. The completion process constructs a completion context based on the trigger character and context qualifiers, identifies syntax regions within the completion context, and routes the completion request to completion processing branches such as named port completion. Return an empty completion result if no valid replacement area is identified, to avoid generating invalid edits; Definition jumps are parsed based on the mapping relationship between syntax nodes and semantic definitions, outputting the definition location corresponding to the identifier and generating jump information; Declaration jumps are resolved based on the mapping relationship between syntax nodes and semantic definitions; when the declaration position is unavailable, it will actively fall back to the definition position; when neither the definition nor the declaration can be resolved, an empty navigation result will be returned to ensure that the navigation behavior is consistent with the semantic state. Reference lookup first locates the corresponding semantic definition, then finds all semantic references used by that semantic definition, and generates a jump list; Renaming modifies the identifier name at a given location and simultaneously modifies the semantic definition and semantic reference at that location, enabling rapid code refactoring. Semantic highlighting processes use semantic information, including type information and context information, to color the code in a special way and highlight special identifiers in the code. Signature assistance can provide module interface information or function parameter information when modifying module instantiation or function calls; The formatting process calls an external SystemVerilog formatting tool to obtain the formatted text, performs a difference comparison between the original text and the formatted text, generates an editing patch, and applies the editing patch to the corresponding file. The code actions will generate automatic editing operations based on the code context, performing operations such as generating, modifying or deleting code.

6. The incremental semantic analysis integrated development environment system for SystemVerilog hardware design language according to claim 1, characterized in that, The protocol scheduling component can receive information from clients or the file system and route it to the corresponding processing channel. After processing an event, the component can collect changes generated during event processing, drive the changes to be committed, and refresh the workspace to update project information. Finally, the component will combine this information to respond to the event processed this time, and then enter the next processing loop.

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