Integrated development environment system oriented to SystemVerilog hardware design language

By using an incremental semantic analysis integrated development environment system, the problem of semantic feedback delay in SystemVerilog hardware design language in large-scale engineering is solved, realizing fast and stable semantic analysis and interactive functions, which are suitable for chip design and verification processes.

CN122346306APending Publication Date: 2026-07-07NANJING UNIV
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Patent Information

Application Number
CN202610449373.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-04-07
Publication Date
2026-07-07

AI Technical Summary

Technical Problem

Existing code analysis systems for the SystemVerilog hardware design language cannot provide low-latency and consistent semantic feedback in large-scale engineering projects. In particular, the overhead of repeated computation is large in scenarios with local modifications, making it difficult to meet the needs of incremental semantic analysis.

Method used

An incremental semantic analysis integrated development environment system is adopted, including workspace discovery, virtual file system, incremental semantic database and protocol scheduling component. Through incremental transaction update mechanism, it provides fast analysis and stable feedback under local modification, and supports functions such as completion, navigation, renaming, semantic highlighting.

Benefits of technology

It significantly reduces redundant computation overhead, maintains result consistency, and improves the effectiveness of suggestions and positioning accuracy in semantic scenarios, making it suitable for chip design and verification processes.

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Abstract

The invention discloses a SystemVerilog hardware design language-oriented incremental semantic analysis integrated development environment system, which comprises a work area discovery component, a work area analysis component, a work area analysis component, a work area analysis component and a work area analysis component, and is characterized in that the work area discovery component is used for automatically identifying an engineering list and constructing an engineering boundary; the virtual file system component is used for maintaining mapping of a source code path and a file identifier and tracking a file state; the incremental semantic database component is used for executing local failure and incremental recalculation after the source code changes; the semantic capability component is used for providing capabilities of complementing, skipping, quoting, renaming, semantic highlighting, formatting and the like; and the protocol scheduling component is used for uniformly scheduling requests, notices and background tasks and returning results. According to the method, the Verilog / SystemVerilog code can be subjected to real-time semantic processing in a continuous editing scene, so that the delay caused by total recalculation is reduced, and the hardware design and development efficiency is improved.
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