Target channel selection output method and system for frequency division multiplexing superconducting detector

Abstract

The application discloses a target channel selection output method and system for frequency division multiplexing superconducting detectors, and belongs to the technical field of digital signal processing and superconducting detector readout electronics. The method aims at the problems of high resolution channelization resource occupation, high full spectrum output bandwidth pressure, and obvious spectrum leakage and crosstalk under high multiplexing ratio. On the basis of high resolution channelization processing, the mapping relationship between target frequency points and channels and the target channel selection output mechanism are introduced. After the wideband digital input signal is processed by the polyphase filter bank channelization, only the complex data corresponding to the target frequency points containing effective signals are selected and output, and are further separated into I / Q data stream output. The scheme combines high resolution channelization processing with the mapping driven selection output mechanism, reduces resource occupation and data transmission bandwidth while ensuring frequency resolution, and improves real-time performance and signal fidelity in the readout scene of high multiplexing ratio detectors.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing and superconducting detector readout electronics, and more particularly to a target channel selection output method and system for frequency division multiplexing superconducting detectors. Background Technology

[0002] Superconducting detectors possess high sensitivity, high energy resolution, and high array integration potential, making them widely applicable in millimeter-wave, submillimeter-wave, terahertz, infrared, and astronomical observation fields. As the scale of superconducting detector arrays continues to expand, frequency division multiplexing readout has become one of the mainstream technologies due to its ability to support a large number of detector elements simultaneously under limited readout links.

[0003] In large-scale frequency division multiplexing (FDM) superconducting detector readout systems, high-resolution channelization of the broadband digital input signal is typically required to achieve fine resolution of weak target signals. High-resolution channelization improves frequency resolution and provides a foundation for detector resonance peak localization and effective signal extraction.

[0004] However, in existing technologies, high-resolution channelization processing is typically accompanied by a significant increase in resource consumption, especially in the implementation of polyphase filter banks and large-point-count Fast Fourier Transforms. This can easily lead to excessive on-chip memory usage and increase the difficulty of timing convergence. Meanwhile, directly outputting all frequency domain sub-channel data will generate a large amount of invalid frequency data, increasing the burden on subsequent processing. These issues affect the real-time performance, scalability, and engineering efficiency of the readout system.

[0005] Furthermore, under high multiplexing ratio conditions, traditional channelization structures are prone to spectral leakage and channel crosstalk, which affects the extraction accuracy of weak and effective signals. Summary of the Invention

[0006] To address the problems existing in the prior art, the present invention aims to provide a target channel selection output method for frequency division multiplexing (FDM) superconducting detectors. This method can output only the I / Q data stream corresponding to the target frequency point while ensuring high frequency resolution, and also takes into account resource consumption, timing implementation, and crosstalk suppression capabilities. Another objective of the present invention is to provide a target channel selection output system for FDM superconducting detectors that implements the above method.

[0007] To achieve the above objectives, the present invention provides a target channel selection output method for frequency division multiplexing superconducting detectors, comprising the following steps: S1. Acquire the wideband digital input signal to be processed; S2. Perform high-resolution channelization processing on the broadband digital input signal to obtain complex data corresponding to multiple channels; S3. Establish a mapping relationship between target frequency points and channels based on preset target frequency point information, and write the mapping relationship into the storage unit; S4. Generate a selection control signal based on the mapping relationship, select the complex data corresponding to the target channel from the complex data corresponding to multiple channels, and thus output only the target frequency data containing the effective signal; S5. Separate the complex data corresponding to the target channel into in-phase component I and quadrature component Q, and after converting the in-phase component I and quadrature component Q into integer data of a predetermined bit width, output the corresponding I / Q data stream.

[0008] Furthermore, the high-resolution channelization processing is implemented using a polyphase filter bank channelization structure, which includes polyphase decomposition processing of finite impulse response filters and fast Fourier transform processing, to achieve high-frequency resolution signal decomposition.

[0009] Furthermore, the high-resolution channelization processing is implemented by combining a parallel processing structure with a resource folding structure.

[0010] Furthermore, the storage unit is a block random access memory, and the mapping relationship includes channel number information or channel position index information corresponding to the target frequency point.

[0011] Furthermore, the selection control signal is a selection pulse signal generated according to the mapping relationship, and the selection output of the complex data corresponding to the target channel is completed through a multiplexer.

[0012] Furthermore, when complex data corresponding to multiple channels are output in a multi-channel parallel manner, a selection control signal is generated based on the correspondence between the target channel position index and the number of parallel output channels; and the parallel output branch corresponding to the target channel is determined based on the result obtained by taking the remainder of the target channel position index with respect to the number of parallel output channels.

[0013] Furthermore, the in-phase component I and the quadrature component Q are converted into integer data of a predetermined bit width before being output, including: converting the in-phase component I and the quadrature component Q into 32-bit integer data respectively before outputting.

[0014] Furthermore, the target frequency in the preset target frequency information is the resonant frequency of the superconducting detector.

[0015] Furthermore, acquiring broadband digital input signals includes: acquiring I and Q digital signals, which serve as the digital baseband signals in the readout link of the frequency division multiplexing superconducting detector; performing parallel branching on the I and Q digital signals to form corresponding multi-channel I parallel data and multi-channel Q parallel data; and then merging the I and Q data of the corresponding branches into complex data for high-resolution channelization processing.

[0016] A target channel selection output system for frequency division multiplexing superconducting detectors includes: Input signal front end, used to provide wideband digital input signals; The target channel selection output device is used to perform the target channel selection output method for frequency division multiplexing superconducting detectors as described above. The subsequent processing unit is used to receive the I / Q data stream output by the target channel selection output device and perform subsequent analysis, display, storage or control operations.

[0017] Beneficial effects: This application addresses detector readout scenarios requiring high resolution, high multiplexing ratios, and limited resources and bandwidth. By combining high-resolution channelization processing, target frequency point mapping-driven selective output, and unified output of integer I / Q data, it achieves targeted extraction and output of effective target frequency point data. Compared with existing technologies, this application offers at least the following advantages: First, this application improves the frequency resolution of broadband input signals through high-resolution channelization processing, providing a basis for accurate target frequency positioning; Second, this application establishes a mapping relationship between target frequency points and channels, extracts only the complex data of target frequency points containing valid signals, thereby reducing invalid frequency point output, reducing interface call pressure, and improving subsequent data processing efficiency. Third, this application reduces storage resource consumption and improves timing convergence capability through parallel processing, resource folding and quantization optimization, thereby improving the engineering feasibility of implementation for programmable logic devices such as FPGA and RFSoC. Fourth, by adopting a multiphase filter bank channelization structure, this application can effectively suppress spectral leakage and channel crosstalk, and increase the signal fidelity in high-multiplexing ratio frequency division multiplexing superconducting detector readout scenarios; Fifth, this application separates the complex data of the target frequency point into in-phase component I and quadrature component Q, and converts them into integer data for output, which is beneficial to unifying the output data format and facilitating subsequent interface processing, data caching and readout link calls; Sixth, the proposed solution can complete module-level or system-level functional verification through a simulation environment, which is beneficial for pre-verifying the correctness of parameter configuration, channel selection logic and I / Q data stream output before hardware implementation. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating the overall process of the method of the present invention. Figure 2 A schematic diagram of the parallel PFB channelization and target channel selection process; Figure 3 A schematic diagram of the target frequency mapping and channel selection module; Figure 4 Output a flowchart for the I / Q data flow; Figure 5 A comparison of the spectral responses of PFB channelization and traditional FFT channelization; Figure 6 Example diagram of logic selection for target channel; Figure 7 This is a schematic diagram of a parallel PFB channelization architecture that employs resource folding and bit width control. Detailed Implementation

[0019] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0022] The following combination Figures 1-7 Specific embodiments of the present invention will be described in detail below. It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the present invention.

[0023] This application aims to address the following technical problems existing in current frequency division multiplexing superconducting detector readout systems: In high-multiplexing detector readout scenarios, to obtain sufficient frequency resolution, it is usually necessary to perform high-resolution channelization processing on the broadband digital input signal. However, this processing is often accompanied by high on-chip resource consumption and significant timing implementation pressure. At the same time, if all frequency domain sub-channel data after channelization are directly output, a large amount of invalid frequency point data will be generated, resulting in a significant increase in data transmission bandwidth and subsequent processing burden. In addition, under high multiplexing ratio conditions, traditional channelization methods are also prone to causing spectrum leakage and channel crosstalk, thereby affecting the extraction accuracy of weak effective signals.

[0024] Therefore, there is an urgent need for a technical solution that can perform directional extraction and output of effective target frequencies, so as to ensure high frequency resolution while taking into account resource consumption, bandwidth pressure, timing implementation, and spectral performance under high reuse ratio conditions, thereby improving the engineering feasibility and signal readout quality of frequency division multiplexing superconducting detector readout systems.

[0025] like Figure 1 As shown, the present invention provides a target channel selection output method for frequency division multiplexing superconducting detectors, comprising the following steps.

[0026] Step S1: Input the signal to be processed The input signal is a broadband digital signal to be processed. In one specific embodiment of this application, the input signal is two digital signals, I and Q. The I and Q digital signals can be the digital baseband signals in the readout link of the frequency division multiplexing superconducting detector, or they can be test input signals generated by a simulation platform or test platform. The input signal contains frequency components corresponding to multiple superconducting detectors, or effective information related to the resonant frequencies of multiple detectors.

[0027] Step S2: High-resolution channelization processing High-resolution channelization processing is performed on the broadband digital input signal to obtain complex data corresponding to multiple channels.

[0028] like Figure 2 As shown, the input I and Q signals are split into parallel channels to form corresponding multiple I-channel parallel data and multiple Q-channel parallel data. Then, the I and Q data of the corresponding branches are merged into complex data, and parallel PFB channelization processing is performed on the complex data to obtain complex output data corresponding to multiple channels. Figure 2 The processing flow shown is mainly used to implement the channelization processing chain from the input signal to the target channel selection.

[0029] PFB channelization is implemented using a polyphase filter bank structure. This structure includes polyphase finite impulse response filtering and fast Fourier transform processing, used to decompose the broadband input signal into multiple channels of complex data with high frequency resolution. Compared to direct FFT channelization, PFB channelization is beneficial for improving spectral leakage and channel crosstalk issues in high multiplexing scenarios. Figure 5 As shown, PFB channelization has better sidelobe suppression effect in spectral response compared with traditional FFT channelization, which is beneficial to improving the spectral leakage and channel crosstalk problems in high reuse ratio scenarios.

[0030] In this embodiment, PFB channelization processing can be implemented by a parameterized configurable digital signal processing module. Specifically, a PFB channelization processing link can be constructed based on the FIR and FFT modules in the CASPER toolchain. Combined with the actual needs of the frequency division multiplexing superconducting detector readout scenario, parameters such as the number of parallel paths, the number of FFT points, the number of FIR taps, the input data bit width, the internal calculation bit width, the coefficient bit width, the quantization method, and the output bit width can be configured and modified to meet the frequency resolution requirements while also considering resource consumption, processing throughput, and timing requirements. It should be noted that the improvement focus of this application is not on the underlying operational principles of the FIR or FFT modules themselves, but rather on the collaborative design of the parallel organization method, resource reuse method, bit width control method, and subsequent target channel selection output mechanism of the PFB processing link for the target channel selection output scenario. In this embodiment, an 8-way parallel method can be used; in other embodiments, 4-way or other parallel paths can also be used. Figure 7 As shown, in this embodiment, the parallel PFB channelization architecture includes an I / Q complex merging unit, a shared multiphase FIR processing unit, a first bit width control unit Q1, a shared FFT processing unit, a second bit width control unit Q2, a channel output buffer / alignment unit, and corresponding time-division multiplexing control unit, address and buffer control unit, and coefficient storage / delay buffer / intermediate result buffer BRAM. Specifically, the I / Q complex merging unit merges the I-channel and Q-channel data of the corresponding branch into complex data; the shared multiphase FIR processing unit performs multiphase filtering on the complex data; the first bit width control unit Q1 performs convergence control on the data bit width after the multiphase FIR output; the shared FFT processing unit performs fast Fourier transform processing on the multiphase FIR output; the second bit width control unit Q2 further controls the data bit width during the FFT processing stage and / or at the FFT output; and the channel output buffer / alignment unit performs buffering and timing alignment on the channelized complex output results.

[0031] In this embodiment, parallel PFB processing is further implemented by combining a parallel processing structure and a resource folding structure. Specifically, the resource folding structure means that, while meeting the requirements of input sampling rate and system throughput, instead of configuring a separate complete FIR processing unit and FFT processing unit for each parallel branch, multiple logical processing branches share some physical computing resources through time-division multiplexing. Specifically, in the multiphase FIR processing stage, data from multiple logical branches can be sent to the shared multiphase FIR processing unit according to a predetermined timing. The time-division multiplexing control unit controls the entry timing of data from different branches, and the address and cache control unit cooperates to complete coefficient reading, delayed data retrieval, and intermediate result caching. In the FFT processing stage, multiple logical branches can share some FFT computing resources, and data processing for different branches or different processing stages is completed through scheduling control and cache control.

[0032] To achieve the above resource folding, such as Figure 7 As shown, the channelized processing chain includes a time-division multiplexing control unit and an address and cache control unit. The time-division multiplexing control unit determines the logic branch that enters the shared multiphase FIR processing unit or the shared FFT processing unit during the current clock cycle; the address and cache control unit generates read and write addresses for coefficient storage, delay buffering, and intermediate result buffering, and cooperates in completing data retrieval, caching, and write-back. Through this method, the consumption of BRAM, DSP, and logic resources can be reduced while ensuring the target throughput.

[0033] In one specific implementation, when the system uses P-way parallel input and the number of shared physical computing unit groups is U, the folding factor M can be expressed as:

[0034] in, This indicates rounding up. By mapping multiple logic branches to a smaller number of physical processing units for execution, hardware resource consumption can be reduced while meeting throughput and timing constraints. In other words, some computing resources that originally required P groups of parallel configuration can be reduced to U groups of shared computing resources, and the processing of the corresponding P groups of logic data can be completed in M ​​consecutive clock cycles, thereby reducing resource consumption while meeting real-time requirements. Here, the folding factor M can be configured based on the system clock frequency, input sampling rate, number of FFT points, and timing margin.

[0035] During the channelization process, a bit-width control node is further set for quantization optimization. For example... Figure 7As shown, in this embodiment, quantization optimization is set at the output of the multiphase FIR filter and / or the FFT processing stage to perform bit width control on the intermediate data and / or output data. Specifically, since multiply-accumulate operations are involved in the multiphase FIR filtering process, the bit width of the filtered output data will increase compared to the input bit width. Therefore, a first bit width control unit Q1 can be set at the FIR output to quantize the FIR output data and reduce it to a predetermined bit width before sending it to the shared FFT processing unit. Since butterfly operations, twitch factor multiplication, and addition / subtraction operations are involved in the FFT processing, the data bit width will continue to increase. Therefore, a second bit width control unit Q2 can be set at the FFT processing stage and / or the FFT output to further control the bit width of the intermediate data or output data.

[0036] In one specific implementation, bit width control can be achieved by setting parameters such as the input data bit width, internal calculation bit width, coefficient bit width, quantization method, and output bit width of the parameterization module. Preferably, the bit width control method includes truncation quantization, rounding quantization, saturation output, or a combination thereof. In one implementation, a truncation strategy that retains the most significant bits and discards the least significant bits can be adopted; in another implementation, a strategy of rounding followed by truncation can be adopted to reduce the impact of quantization error on the target frequency detection accuracy. To prevent the intermediate data bit width from growing indefinitely while also considering dynamic range requirements, a preset number of guard bits can be retained during the bit width control process, thereby suppressing the accumulation of quantization noise while reducing the hardware resource consumption caused by subsequent buffers, multipliers, and bus bit width.

[0037] Furthermore, when the Fast Fourier Transform (FFT) processing is implemented using a parameterized configurable module, the bit width-related parameters within the module can be set to ensure that the data converges to a predetermined bit width at intermediate nodes and / or outputs during the FFT processing stage, or to increase to a preset upper limit when bit width growth is allowed. This suppresses unlimited bit width growth and reduces hardware resource consumption. The location of the bit width control node, the number of bits reserved for bit width, and the quantization method can be configured according to the target frequency resolution, system signal-to-noise ratio requirements, device resource budget, and timing constraints.

[0038] Under specific implementation conditions, by introducing time-division multiplexing scheduling of shared computing units in the PFB processing link, reducing redundant intermediate cache configuration, and implementing convergence control on the intermediate data bit width at the multi-phase FIR output and FFT processing stage, the intermediate data cache depth and storage bit width can be reduced, thereby decreasing BRAM resource usage from approximately 84% before optimization to approximately 61% after optimization. This result demonstrates that the combination of parallel processing, resource folding, and hierarchical bit width control can effectively reduce on-chip storage resource usage and alleviate resource consumption and timing implementation pressures in engineering implementations.

[0039] Step S3: Establish the mapping relationship between the target frequency and the channel, and write it into the storage unit. Establish a mapping relationship between the target frequency and the channel based on the preset target frequency information, and write the mapping relationship into the storage unit.

[0040] In this application, the target frequency is preferably the resonant frequency of the superconducting detector. In other embodiments, the target frequency may also be other frequencies containing effective detection signals. The mapping relationship is used to characterize the correspondence between the target frequency and the corresponding channel in the channelization result, thereby providing a basis for subsequent target channel selection.

[0041] In one specific implementation, the mapping relationship between the target frequency and the channel number can be calculated based on the channelization parameters. Let the total bandwidth of the PFB processing be B, and the number of FFT points be N, then the frequency resolution of a single channel can be expressed as:

[0042] For the target frequency Its corresponding target channel number It can be determined as follows:

[0043] in, The channelization start frequency or reference frequency, This indicates rounding down. Through the above calculations, the target frequency information can be converted into corresponding channel number information or channel position index information and written into the storage unit.

[0044] In one specific implementation, when the target frequency point is close to the boundary of the adjacent channel, the channel with better amplitude-frequency response can be selected as the target channel based on the distance between the target frequency point and the center frequency of the adjacent channel, so as to improve the stability and accuracy of the target frequency point selection output.

[0045] The storage unit is preferably a block random access memory (BRAM). The mapping relationship includes the channel number information or channel position index information corresponding to the target frequency point, which is pre-stored in the BRAM for subsequent reading and retrieval by the selection control logic. In one specific embodiment, the channel number information or channel position index information can be calculated offline based on the channelization parameters and target frequency point information and then written into the BRAM; in another specific embodiment, it can also be calculated online by the control logic based on the input target frequency point information and channelization parameters and then written into the BRAM.

[0046] Furthermore, the mapping relationship can be organized and stored according to the target frequency point order or the channel number order, so that the subsequent control logic can read the mapping relationship according to a predetermined timing and generate the corresponding selection control signal. In one specific embodiment, in addition to storing the target channel number, the BRAM can also store auxiliary index information related to the target channel output, which is used to subsequently generate the control signal corresponding to the parallel output branch where the target channel is located and its output time.

[0047] like Figure 3 As shown, after the mapping relationship is established, the relevant channel number information or channel position index information is written into the BRAM for subsequent control logic to read.

[0048] Step S4: Generate a selection control signal based on the mapping relationship and perform target channel selection. A selection control signal is generated based on the mapping relationship, and the complex data corresponding to the target channel is selected from the complex data corresponding to multiple channels.

[0049] like Figure 3 As shown, the control logic reads the mapping relationship between the target frequency and the channel from the BRAM and generates a corresponding selection control signal based on the mapping relationship. The selection control signal is preferably a selection pulse signal. The selection control signal drives a multiplexer or equivalent selection circuit to select the complex data corresponding to the target channel from the multiple channel complex data outputs. This step avoids directly outputting all channel data, retaining only the valid channel data corresponding to the target frequency, thereby reducing data transmission bandwidth pressure and subsequent processing burden, and improving the real-time performance and engineering implementation efficiency of the readout link.

[0050] In one specific implementation, when the channelization result is output in P-way parallel mode, the parallel output branch number corresponding to the target channel is... It can be represented as:

[0051] Timing index of the target channel in the parallel output sequence It can be represented as:

[0052] in, Let P be the target channel number, P be the number of parallel output channels, and mod represent the modulo operation. Through the above calculations, the parallel output branch containing the target channel and its time position in the output sequence can be determined, thereby generating the corresponding selection control signal.

[0053] In a specific implementation, when the number of parallel output channels is 8, the parallel output branch corresponding to the target channel can be determined by taking the result of the target channel position index modulo 8; when the number of parallel output channels is 4, the parallel output branch corresponding to the target channel can be determined by taking the result of the target channel position index modulo 4.

[0054] Furthermore, the selection control logic can be based on the target channel number. Parallel output branch number and time-series index It generates selection pulses corresponding to the output timing and drives the multiplexer to select the complex data of the target channel at the corresponding time, realizing the sequential arrangement from multiple parallel outputs to single target channel outputs.

[0055] In one specific implementation, the selection control signal may include a branch gating signal and a timing trigger signal. The branch gating signal is used to determine the parallel output branch selected at the current moment, and the timing trigger signal is used to determine the moment when the target channel data is retrieved from the parallel output sequence. By coordinating the branch gating signal and the timing trigger signal, the complex data corresponding to the target channel can be accurately selected from multiple parallel output channels.

[0056] Furthermore, when multiple target frequencies exist, the control logic can sequentially read the channel number information corresponding to the multiple target frequencies in a preset order, and generate multiple sets of selection control signals according to the corresponding timing sequence to achieve sequential selection and output of multiple target channel data. In one embodiment, the preset order can be the target frequency order, the channel number order, or the priority output order set by the system.

[0057] like Figure 6 As shown, after the input signal is processed by the selection control signal, the selected data is output only at the time corresponding to the target channel, thereby achieving effective extraction of the target channel data and verifying the correctness of the target channel selection logic. Through the above selection control mechanism, this application can output only the effective channel data corresponding to the target frequency point while maintaining the high-resolution channelization result, reducing the output of invalid frequency points and reducing the burden of subsequent transmission and processing. Figure 6 In the graph, the horizontal axis represents the discrete channel number after FFT channelization. The vertical axis of the first and third graphs represents the amplitude of the digitized signal; the vertical axis of the second graph represents the channel selection control signal, with 1 indicating selection and 0 indicating non-selection. The third graph shows the output result after channel selection.

[0058] Step S5: Separate the complex data of the target channel into I / Q data and output the I / Q data stream. The complex data corresponding to the target channel is separated into in-phase component I and quadrature component Q, and the I and Q components are converted into integer data before the corresponding I / Q data stream is output.

[0059] like Figure 4 As shown, the complex data corresponding to the target channel contains real and imaginary parts. By separating the complex data, the in-phase component I and the quadrature component Q can be obtained. The I and Q components can be further used to calculate the amplitude and phase information of the signal corresponding to the target frequency point, and can serve as the basis data for subsequent readout processing.

[0060] To facilitate a unified interface format and data retrieval method, the I and Q components are converted into integer data of a predetermined width before output. In one specific implementation, the I and Q components can each be converted into 32-bit integer data before output. By separating and converting the complex data corresponding to the target channel into integer I / Q data streams, a unified data output format can be formed, facilitating subsequent interface processing, data caching, and calls from subsequent modules in the readout link.

[0061] In this embodiment, the output is in the form of two I / Q data streams corresponding to the target frequency. The I / Q data streams can be further used as inputs for subsequent amplitude calculation, phase calculation, vector accumulation, event discrimination, or other readout processing modules, or they can be connected to data transmission, display, or storage units according to subsequent system requirements.

[0062] The present invention also provides a target channel selection output device for frequency division multiplexing superconducting detectors, the device comprising: The input signal acquisition module is used to acquire wideband digital input signals; The channelization processing module is used to perform high-resolution channelization processing on the broadband digital input signal to obtain complex data corresponding to multiple channels. The high-resolution channelization processing adopts a polyphase filter bank (PFB) channelization structure and performs quantization optimization during the channelization process to reduce resource consumption. The mapping storage module is used to establish and store the mapping relationship between target frequency points and channels; The channel selection module is used to generate a selection control signal based on the mapping relationship, and select the complex data corresponding to the target channel from the complex data corresponding to multiple channels; The I / Q output module is used to separate the complex data corresponding to the target channel into in-phase component I and quadrature component Q, and then convert the in-phase component I and quadrature component Q into integer data before outputting the corresponding I / Q data stream.

[0063] Each of the above modules is used to implement the corresponding steps in the aforementioned method.

[0064] The present invention also provides a target channel selection output system for frequency division multiplexing superconducting detectors. The system includes an input signal front end, the aforementioned target channel selection output device, and a subsequent processing unit. The input signal front end is used to provide an input signal, and the subsequent processing unit is used to receive I / Q data streams and perform subsequent analysis, display, storage, or control operations.

[0065] Furthermore, the method of this invention can also be functionally verified in a simulation environment. By constructing an input module, a parallel PFB channelization processing module, a mapped storage module, a channel selection module, and an I / Q output module corresponding to the above method, the target channel selection logic and the I / Q data stream output logic can be verified. Under a set of parameter configurations and implementation conditions, such as a 64K-level high-resolution channelization configuration and a 1000:1 high multiplexing ratio readout condition, the solution of this application can reduce on-chip storage resource occupation, reduce data transmission bandwidth pressure, and improve spectrum performance while ensuring effective extraction of the target frequency point; in a specific implementation, BRAM occupation can be reduced by about 20%, transmission bandwidth can be reduced by more than 90%, and sidelobe suppression can be better than 60 dB. The above results are exemplary verification results and do not constitute a limitation on the scope of protection of this application.

[0066] Compared to repeated iterations and verifications on the hardware platform, this application can complete module-level and system-level functional verification before hardware implementation, and pre-evaluate the parameter configuration, target channel selection logic, I / Q data stream output correctness, as well as the engineering implementation effects related to resource consumption, bandwidth pressure and spectrum suppression, thereby reducing the number of hardware iterations, shortening the development cycle and improving development efficiency.

[0067] This application combines high-resolution channelization processing, the mapping relationship between target frequency points and channels, and the target channel selection output mechanism to achieve directional extraction of effective target frequency point data and output the corresponding integer I / Q data stream. This allows for the simultaneous consideration of engineering constraints between frequency resolution, resource consumption, data bandwidth, and spectral performance in high multiplexing ratio detector readout scenarios.

[0068] Any process or method described in the flowcharts of this invention or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, which can be implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device. The computer-readable medium can be any medium containing a program for storage, communication, propagation, or transmission for use by an execution system, apparatus, or device, including read-only memory, magnetic disks, or optical disks.

[0069] In the description of this specification, references to terms such as "embodiment," "example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, those skilled in the art can combine or combine the different embodiments or examples described in this specification and the features therein without causing contradiction.

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

Claims

1. A target channel selection output method for frequency division multiplexing superconducting detectors, characterized in that, Includes the following steps: S1. Acquire the wideband digital input signal to be processed; S2. Perform high-resolution channelization processing on the broadband digital input signal to obtain complex data corresponding to multiple channels; S3. Establish a mapping relationship between target frequency points and channels based on preset target frequency point information, and write the mapping relationship into the storage unit; S4. Generate a selection control signal based on the mapping relationship, select the complex data corresponding to the target channel from the complex data corresponding to multiple channels, and thus output only the target frequency data containing the effective signal; S5. Separate the complex data corresponding to the target channel into in-phase component I and quadrature component Q, and after converting the in-phase component I and quadrature component Q into integer data of a predetermined bit width, output the corresponding I / Q data stream.

2. The method according to claim 1, characterized in that, The high-resolution channelization processing is implemented using a polyphase filter bank channelization structure, which includes polyphase decomposition processing of finite impulse response filters and fast Fourier transform processing, to achieve high-frequency resolution signal decomposition.

3. The method according to claim 1, characterized in that, The high-resolution channelization process is implemented by combining a parallel processing structure with a resource folding structure.

4. The method according to claim 1, characterized in that, The storage unit is a block random access memory, and the mapping relationship includes the channel number information or channel position index information corresponding to the target frequency point.

5. The method according to claim 1, characterized in that, The selection control signal is a selection pulse signal generated according to the mapping relationship, and it completes the selection output of the complex data corresponding to the target channel through a multiplexer.

6. The method according to claim 5, characterized in that, When complex data corresponding to multiple channels are output in a multi-channel parallel manner, a selection control signal is generated based on the correspondence between the target channel position index and the number of parallel output channels. The parallel output branch corresponding to the target channel is determined by taking the remainder of the number of parallel output paths based on the target channel location index.

7. The method according to claim 1, characterized in that, The process of converting the in-phase component I and the quadrature component Q into integer data of a predetermined bit width and then outputting them includes: converting the in-phase component I and the quadrature component Q into 32-bit integer data and then outputting them.

8. The method according to claim 1, characterized in that, The target frequency in the preset target frequency information is the resonant frequency of the superconducting detector.

9. The method according to claim 1, characterized in that, Acquiring broadband digital input signals includes: acquiring I and Q digital signals, which serve as the digital baseband signals in the readout link of the frequency division multiplexing superconducting detector; performing parallel branching on the I and Q digital signals to form corresponding multi-channel I parallel data and multi-channel Q parallel data; and then merging the I and Q data of the corresponding branches into complex data for high-resolution channelization processing.

10. A target channel selection output system for frequency division multiplexing superconducting detectors, used to execute the target channel selection output method for frequency division multiplexing superconducting detectors as described in any one of claims 1-9, characterized in that, include: Input signal front end, used to provide wideband digital input signals; A target channel selection output device is used to execute a target channel selection output method for frequency division multiplexing superconducting detectors. The subsequent processing unit is used to receive the I / Q data stream output by the target channel selection output device and perform subsequent analysis, display, storage or control operations.

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