A Multiphase Digital Quadrature Mixing Method and System
By initializing and simplifying the acquisition module using an FPGA module, the resource consumption and error problems of the multiphase digital quadrature mixing scheme are solved, achieving low-power and high-efficiency signal processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 成都玖锦科技有限公司
- Filing Date
- 2025-04-10
- Publication Date
- 2026-05-26
AI Technical Summary
Existing multiphase digital quadrature mixing schemes suffer from high resource consumption, high power consumption, and large errors, especially in high-frequency and wide-bandwidth intermediate frequency signal processing.
The acquisition module is initialized and configured using an FPGA module to determine whether the ratio of the frequency of the digital local oscillator signal to the sampling frequency is a preset ratio. If the condition is met, the preset multiphase digital quadrature mixing logic is performed through the FPGA module, including hold, set to zero and invert operations, to obtain the sub-I signal and sub-Q signal.
It reduces resource consumption and power consumption, eliminates quantization errors, and improves processing efficiency, especially showing significant advantages in high-frequency and high-bandwidth signal processing.
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Figure CN119966355B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of modern digital signal processing technology, and provides a multiphase digital quadrature mixer and system. Background Technology
[0002] With the development of modern superheterodyne receivers, the intermediate frequency (IF) signal frequency is increasing, and the bandwidth is also increasing. Under these circumstances, polyphase digital quadrature mixing of the IF signal has become a common solution in the industry. Figure 1 As shown, this is an existing multiphase digital quadrature mixing scheme. Furthermore, based on this… Figure 1 It can be seen that the existing multiphase digital quadrature mixing scheme has the following defects: (1) Since each sub-I and Q signal requires a DDS core and two multipliers, the entire digital quadrature mixing process requires n DDS cores and 2n multipliers (n is the number of sub-IF signals). Therefore, if the intermediate frequency signal of a receiver is very high and the bandwidth is very large, it will inevitably need to divide into many sub-IF signals. At this time, the resource consumption is very large, which leads to excessive power consumption. (2) Since the DDS core is ultimately a digital circuit, it has quantization error and cannot accurately generate the sub-local oscillator signal with a specified frequency and initial phase. Therefore, strictly speaking, the sub-I and Q signals obtained by multiplying the sub-local oscillator signal generated by the DDS core by the sub-IF signal have errors, and these errors can only be reduced, not completely eliminated.
[0003] Therefore, how to reduce the resource consumption, power consumption and error of multiphase digital quadrature mixing schemes has become an urgent problem to be solved. Summary of the Invention
[0004] This application provides a multiphase digital quadrature mixing method and system to solve the problems of high resource consumption, power consumption and error in existing multiphase digital quadrature mixing schemes.
[0005] On the one hand, a multiphase digital quadrature mixing method is provided, which is applied to a multiphase digital quadrature mixing system including a data acquisition module and an FPGA module, comprising:
[0006] For any given channel, the acquisition module is initialized and configured via the FPGA module;
[0007] Determine whether the acquisition module is working properly, and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio; wherein the preset ratio is three-quarters or one-quarter;
[0008] If it is determined that the acquisition module is working normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, then the FPGA module performs preset multi-phase digital quadrature mixing logic processing on the sub-IF signal corresponding to any channel to obtain the sub-I signal and sub-Q signal corresponding to the sub-IF signal; wherein, the preset multi-phase digital quadrature mixing logic processing only includes hold, set to 0 and invert.
[0009] Optionally, the step of initializing and configuring the acquisition module through the FPGA module includes:
[0010] The clock chip and ADC chip of the acquisition module are initialized and configured through the acquisition module control logic of the FPGA module.
[0011] Optionally, the step of initializing and configuring the clock chip and ADC chip of the acquisition module through the acquisition module control logic of the FPGA module includes:
[0012] The clock chip generates a sampling clock through a control protocol in the control logic of the acquisition module; wherein, the control protocol is determined according to the ADC chip used.
[0013] The sampling frequency of the ADC chip is initialized according to the control protocol, the sampling clock, and the center frequency of the sub-IF signal of any channel.
[0014] Optionally, if it is determined that the acquisition module is working normally and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, then the step of performing preset multiphase digital quadrature mixing logic processing on the sub-IF signal corresponding to any channel through the FPGA module to obtain the sub-I signal and sub-Q signal corresponding to the sub-IF signal includes:
[0015] If it is determined that the acquisition module is working normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, then the digital quadrature mixing logic of the FPGA module is used to process the sub-IF signal corresponding to any channel according to the preset multi-phase digital quadrature mixing logic to obtain the sub-I signal and sub-Q signal corresponding to the sub-IF signal.
[0016] Optionally, after determining whether the acquisition module is working properly and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, the method further includes:
[0017] If it is determined that the acquisition module is not working properly, or the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is not a preset ratio, the acquisition module is reconfigured through the FPGA module.
[0018] Optionally, after performing preset multiphase digital quadrature mixing logic processing on the sub-IF signal corresponding to any one channel through the FPGA module to obtain the sub-I signal and sub-Q signal corresponding to the sub-IF signal, the method further includes:
[0019] If the working channel changes, the acquisition module is reconfigured through the FPGA module.
[0020] Optionally, the sub-I signal is represented by the following formula (1):
[0021] (1)
[0022] The sub-Q signal is represented by the following formula (2):
[0023] (2)
[0024] in, This is the sub-I signal corresponding to the k-th channel; Let f be the sub-I signal corresponding to the k-th channel; f be the center frequency of the intermediate frequency signal; fc be the frequency of the digital local oscillator signal of the k-th channel; and t be the time. This is the initial phase corresponding to the k-th sub-signal.
[0025] On the one hand, a multiphase digital quadrature mixing system is provided, the system including an acquisition module and an FPGA module; wherein, the acquisition module is used to acquire intermediate frequency signals; and the FPGA module is used to control the acquisition module and the multiphase digital quadrature mixing processing.
[0026] Optionally, the acquisition module includes a clock chip and an ADC chip; wherein the clock chip is used to provide a stable sampling clock; and the ADC chip is used to acquire and convert the intermediate frequency signal according to the sampling clock.
[0027] Optionally, the FPGA module includes acquisition module control logic and digital quadrature mixing logic; wherein, the acquisition module control logic is used to control each chip in the acquisition module through a control protocol, so that the acquisition module works normally and ensures that the center frequency of the output intermediate frequency signal data is fixed at three-quarters or one-quarter of the sampling rate of the ADC chip; the digital quadrature mixing logic is used to perform preset multi-phase digital quadrature mixing logic processing on the sub-intermediate frequency signals corresponding to each channel to obtain the sub-I signal and sub-Q signal corresponding to each sub-intermediate frequency signal.
[0028] Compared with the prior art, the beneficial effects of this application are as follows:
[0029] In this application, for any channel, firstly, the acquisition module can be initialized and configured using the FPGA module; then, it can be determined whether the acquisition module is working properly, and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio; wherein, the preset ratio is three-quarters or one-quarter; finally, if it is determined that the acquisition module is working properly, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, then the FPGA module can perform preset multiphase digital quadrature mixing logic processing on the sub-IF signal corresponding to any channel to obtain the sub-I signal and sub-Q signal corresponding to the sub-IF signal; wherein, the preset multiphase digital quadrature mixing logic processing only includes the three simplest operations: hold, set to zero, and invert.
[0030] Therefore, in this application, since the properties of special points of trigonometric functions are fully utilized in principle, and the multiplication operation is simplified to the three simplest operations of preset hold, set to 0 and invert, the sub-I signal and sub-Q signal corresponding to the sub-IF signal are obtained by eliminating the need for a DDS core. Therefore, compared with the prior art, this application has technical advantages such as low resource consumption, low power consumption and low delay, and there is no quantization error. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0032] Figure 1 A schematic diagram of an existing multiphase digital quadrature mixing scheme provided in an embodiment of this application;
[0033] Figure 2 An electronic device provided in an embodiment of this application;
[0034] Figure 3 A schematic diagram of a multiphase digital quadrature mixer system provided in an embodiment of this application;
[0035] Figure 4 A schematic diagram of a multiphase digital quadrature mixing method provided in an embodiment of this application;
[0036] Figure 5 This is a schematic diagram of a multiphase digital quadrature mixing scheme provided in an embodiment of this application.
[0037] The diagram is labeled as follows: 20-Multiphase digital quadrature mixer, 201-Processor, 202-Memory, 203-I / O interface, 204-Database. Detailed Implementation
[0038] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.
[0039] Definitions:
[0040] Intermediate frequency (IF) signal, in modern digital superheterodyne receivers, is the signal obtained after the radio frequency (RF) signal undergoes multiple frequency conversion stages at the RF front end.
[0041] With the development of modern superheterodyne receivers, the intermediate frequency (IF) signal frequency is increasing, and the bandwidth is also increasing. Under these circumstances, polyphase digital quadrature mixing of the IF signal has become a common solution in the industry. Figure 1 The diagram illustrates an existing multiphase digital quadrature mixing scheme. First, the digitized intermediate frequency (IF) signal is divided into multiple sub-IF signals with fixed but different initial phases. Then, multiple direct digital synthesizer (DDS) cores within a Field Programmable Gate Array (FPGA) generate multiple sub-local oscillator (LoLO) signals with fixed but different initial phases. Each LoLO signal corresponds one-to-one with the initial phase of the sub-IF signal, and each LoLO signal includes a cosine LoLO signal and a sine LoLO signal. Finally, the cosine LoLO signal corresponding to each initial phase is multiplied by the LoLO signal to obtain the sub-I signal, and the sine LoLO signal corresponding to each initial phase is multiplied by the LoLO signal to obtain the sub-Q signal, thus achieving multiphase digital quadrature mixing.
[0042] Depend on Figure 1It can be seen that the existing multiphase digital quadrature mixing scheme has the following defects: (1) Since each sub-I and Q signal requires a DDS core and two multipliers, the entire digital quadrature mixing process requires n DDS cores and 2n multipliers (n is the number of sub-IF signals). Therefore, if the intermediate frequency signal of a receiver is very high and the bandwidth is very large, it will inevitably need to be divided into many sub-IF signals, which will consume a lot of resources and thus increase power consumption. (2) Since the DDS core is ultimately a digital circuit, it has quantization error and cannot accurately generate the sub-local oscillator signal with a specified frequency and initial phase. Therefore, the sub-I and Q signals obtained by multiplying the sub-local oscillator signal generated by the DDS core by the sub-IF signal are strictly speaking error. Although the quantization error can be reduced by increasing the quantization bit width of the frequency control word and phase control word of the DDS core, this can only reduce the error and cannot completely eliminate it. Moreover, as the quantization bit width increases, the resources consumed by the DDS core will also increase, further aggravating the first defect.
[0043] Based on this, this application provides a multiphase digital quadrature mixing method. In this method, for any channel, firstly, the acquisition module can be initialized and configured using an FPGA module; then, it can be determined whether the acquisition module is working properly and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio; wherein, the preset ratio is three-quarters or one-quarter; finally, if it is determined that the acquisition module is working properly and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, then the FPGA module can perform preset multiphase digital quadrature mixing logic processing on the sub-IF signal corresponding to any channel to obtain the sub-I signal and sub-Q signal corresponding to the sub-IF signal; wherein, the preset multiphase digital quadrature mixing logic processing only includes the three simplest operations: hold, set to zero, and invert. Therefore, in this application, since the properties of special points of trigonometric functions are fully utilized in principle, and the multiplication operation is simplified to the three simplest operations of preset hold, set to 0 and invert, the sub-I signal and sub-Q signal corresponding to the sub-IF signal are obtained by eliminating the need for a DDS core. Therefore, compared with the prior art, this application has technical advantages such as low resource consumption, low power consumption and low delay, and there is no quantization error.
[0044] After introducing the design concept of the embodiments of this application, the following is a brief introduction to the application scenarios to which the technical solutions of the embodiments of this application can be applied. It should be noted that the application scenarios described below are only for illustrating the embodiments of this application and are not intended to limit the scope. In specific implementation, the technical solutions provided by the embodiments of this application can be flexibly applied according to actual needs.
[0045] like Figure 2As shown, this is an electronic device provided in an embodiment of the present application. Specifically, the electronic device can be a multiphase digital quadrature mixer 20.
[0046] The multiphase digital quadrature mixer 20 can be used to perform multiphase digital quadrature mixing on various sub-IF signals. For example, it can be a personal computer (PC), server, or laptop. The multiphase digital quadrature mixer 20 may include one or more processors 201, memory 202, I / O interfaces 203, and database 204. Specifically, the processor 201 can be a central processing unit (CPU) or a digital processing unit, etc. The memory 202 can be volatile memory, such as random-access memory (RAM); the memory 202 can also be non-volatile memory, such as read-only memory, flash memory, hard disk drive (HDD), or solid-state drive (SSD); or the memory 202 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. The memory 202 can be a combination of the above-mentioned memories. The memory 202 can store some program instructions of the multiphase digital quadrature mixing method provided in the embodiments of this application. When these program instructions are executed by the processor 201, they can be used to implement the steps of the multiphase digital quadrature mixing method provided in the embodiments of this application, so as to solve the problems of high resource consumption, power consumption and error in existing multiphase digital quadrature mixing schemes. The database 204 can be used to store data such as the frequency, sampling frequency, center frequency and preset ratio of the digital local oscillator signal involved in the scheme provided in the embodiments of this application.
[0047] In this embodiment, the multiphase digital quadrature mixer 20 can acquire the intermediate frequency signal through the I / O interface 203. Then, the processor 201 of the multiphase digital quadrature mixer 20 will reduce the resource consumption, power consumption, and error of the multiphase digital quadrature mixing scheme according to the program instructions of the multiphase digital quadrature mixing method provided in this embodiment of the application stored in the memory 202. In addition, the frequency, sampling frequency, center frequency, and preset ratio of the digital local oscillator signal can be stored in the database 204.
[0048] Of course, the methods provided in the embodiments of this application are not limited to... Figure 2 The application scenarios shown can also be used in other possible scenarios, and this application embodiment does not impose any limitations. Figure 2The functions that the various devices in the application scenarios shown can achieve will be described in subsequent method embodiments, and will not be elaborated on here. Below, the methods of the embodiments of this application will be described in conjunction with the accompanying drawings.
[0049] like Figure 3 The diagram shown is a schematic of a multiphase digital quadrature mixing system provided in an embodiment of this application. Specifically, the multiphase digital quadrature mixing system includes an acquisition module and an FPGA module. The acquisition module can be used to acquire intermediate frequency signals, and the FPGA module can be used to control the acquisition module and the multiphase digital quadrature mixing process.
[0050] In one possible implementation, the acquisition module includes a clock chip and an ADC chip; wherein the clock chip can be used to provide a stable sampling clock; and the ADC chip can be used to acquire and convert the intermediate frequency signal according to the sampling clock.
[0051] In one possible implementation, the FPGA module includes acquisition module control logic and digital quadrature mixing logic. The acquisition module control logic can be used to control each chip in the acquisition module through a control protocol, so that the acquisition module works normally and ensures that the center frequency of the output intermediate frequency signal data is fixed at three-quarters or one-quarter of the sampling rate of the ADC chip. The digital quadrature mixing logic can be used to perform preset multi-phase digital quadrature mixing logic processing on the sub-intermediate frequency signals corresponding to each channel to obtain the sub-I signal and sub-Q signal corresponding to each sub-intermediate frequency signal.
[0052] like Figure 4 The diagram shown is a schematic representation of a multiphase digital quadrature mixing method provided in an embodiment of this application. This method is applied to, for example... Figure 3 The multiphase digital quadrature mixer system shown can be used to achieve this. Figure 2 The multiphase digital quadrature mixer 20 is used to perform this operation. The specific process of this method is described below.
[0053] Step 401: For any channel, initialize and configure the acquisition module through the FPGA module.
[0054] In the embodiments of this application, such as Figure 3As shown, the acquisition module includes a clock chip and an analog-to-digital converter (ADC) chip. The clock chip can provide a stable sampling clock for the ADC chip. The FPGA module includes acquisition module control logic and digital quadrature mixing logic. Therefore, in this embodiment, when the acquisition module is initialized and configured through the Field Programmable Gate Array (FPGA) module, the clock chip and ADC chip of the acquisition module can be initialized and configured through the acquisition module control logic of the FPGA module.
[0055] Furthermore, to ensure the accuracy of the initialization configuration, in this embodiment, when initializing the clock chip and ADC chip of the acquisition module through the acquisition module control logic of the FPGA module, the clock chip can be controlled to generate a sampling clock through the control protocol in the acquisition module control logic. The control protocol used is determined according to the ADC chip, and can generally be a Serial Peripheral Interface (SPI) protocol or an Inter-Integrated Circuit (IIC) protocol, etc. Then, the sampling frequency of the ADC chip can be initialized according to the control protocol, the sampling clock, and the center frequency of the sub-IF signal of any channel. For example, receiver A's intermediate frequency (IF) signal is divided into three channels. The center frequency of the first channel is 5.625 GHz, the center frequency of the second channel is 2.25 GHz, and the center frequency of the third channel is 0.75 GHz. According to the control protocol, sampling clock, and the center frequency of the sub-IF signal of each channel, "center frequency / sampling frequency = 3 / 4 or 1 / 4" can be achieved. Therefore, the sampling frequency of the ADC chip in the first channel can be 7.5 GHz, and the sampling frequency in the second and third channels can be 3 GHz.
[0056] Step 402: Determine whether the acquisition module is working properly, and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is the preset ratio.
[0057] In the embodiments of this application, the preset ratio is three-quarters or one-quarter.
[0058] Step 403: If it is determined that the acquisition module is working normally and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, then the FPGA module performs preset multiphase digital quadrature mixing logic processing on the sub-IF signal corresponding to any channel to obtain the sub-I signal and sub-Q signal corresponding to the sub-IF signal.
[0059] In this embodiment, the preset multiphase digital quadrature mixer logic processing only includes the three simplest operations: hold, set to zero, and invert. Specifically, as shown... Figure 3 As shown, if the acquisition module is confirmed to be working normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, then the digital quadrature mixing logic of the FPGA module can be used to process the sub-IF signals corresponding to any channel according to their preset numbers using preset multi-phase digital quadrature mixing logic to obtain the sub-I and sub-Q signals corresponding to the sub-IF signals. Specifically, for the sub-I signals, the hold, set to zero, invert, and set to zero operations are performed sequentially according to the channel numbers until all sub-I signals are obtained; for the sub-Q signals, the set to zero, hold, set to zero, and invert operations are performed sequentially according to the channel numbers until all sub-Q signals are obtained. For example, the hold operation is performed on the sub-IF signal of the first channel to obtain the first sub-I signal, the set to zero operation is performed on the sub-IF signal of the second channel to obtain the second sub-I signal, the invert operation is performed on the sub-IF signal of the third channel to obtain the third sub-I signal, the set to zero operation is performed on the sub-IF signal of the fourth channel to obtain the fourth sub-I signal, the hold operation is performed on the sub-IF signal of the fifth channel to obtain the fifth sub-I signal, and so on. Figure 5 The diagram shown is a schematic of a multiphase digital quadrature mixing scheme provided in an embodiment of this application.
[0060] In one possible implementation, after determining whether the acquisition module is working properly and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, if it is determined that the acquisition module is not working properly, or the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is not a preset ratio, the acquisition module can be reconfigured through the FPGA module.
[0061] In one possible implementation, after the FPGA module performs preset multiphase digital quadrature mixing logic processing on the sub-IF signal corresponding to any channel to obtain the sub-I and sub-Q signals, if the channel through which the sub-IF signal operates changes, the FPGA module reconfigures the acquisition module. That is, when the operating channel changes, the FPGA module's acquisition module control logic can reconfigure the registers inside the clock chip, ADC chip, etc., through a control protocol. During this period, other components pause operation until the acquisition module resumes normal operation and the frequency of the digital local oscillator signal of the current channel is fixed at three-quarters or one-quarter of the sampling rate of the ADC chip. Specific implementation examples:
[0063] Assuming the sampling rate of the ADC chip is fs, the center frequency of the intermediate frequency signal is f, the frequency of the digital local oscillator signal is fc, and the time is t, the intermediate frequency signal is divided into n sub-intermediate frequency signals after digitization. According to the existing polyphase digital quadrature mixing scheme, the kth sub-I signal can be represented by the following formula (1):
[0064] (1)
[0065] The kth sub-Q signal is represented by the following formula (2):
[0066] (2)
[0067] in, This is the initial phase corresponding to the k-th sub-signal.
[0068] make:
[0069] (3)
[0070] as well as,
[0071] (4)
[0072] in, For the sub-I signal corresponding to the k-th channel of the digitally controlled oscillator (NCO), Let be the sub-Q signal corresponding to the NCO in the kth channel.
[0073] Initialize the configuration (make sure fc and fs satisfy the following relationship):
[0074] (5)
[0075] or,
[0076] (6)
[0077] Therefore, according to formulas (3)-(6), we can obtain:
[0078] (7)
[0079] (8)
[0080] Furthermore, according to formulas (1), (3), and (7), the sub-I signal corresponding to any sub-IF signal in this application can be obtained:
[0081] (9)
[0082] Similarly, according to formulas (1), (4) and (8), the sub-Q signal corresponding to any sub-IF signal in this application can be obtained:
[0083] (10)
[0084] In summary, compared with the prior art, this application has the following advantages:
[0085] (1) Low power consumption: The more sub-IF signals are generated, the more obvious the advantage of low power consumption becomes.
[0086] Specifically, on the one hand, since the logic implementation of multiphase digital quadrature mixer does not require DDS core and multiplier at all, the static power consumption caused by DDS core and multiplier is eliminated.
[0087] On the other hand, since the sampling frequency of the ADC chip is configurable in different channels, and the number of sub-IF signals generated when the FPGA implements multi-phase digital quadrature mixing is constant, the lower the center frequency of the IF signal, the lower the clock frequency for computation and processing within the FPGA, reducing the dynamic power consumption of the FPGA during digital signal processing. For example, if a receiver's IF signal is divided into three channels, with the center frequency of the first channel being 5.625 GHz, the center frequency of the second channel being 2.25 GHz, and the center frequency of the third channel being 0.75 GHz, and the sampling frequency of the ADC chip is fixed at 7.5 GHz, and the number of sub-IF signals is fixed at 32, then based on the existing multi-phase digital quadrature mixing scheme, the clock frequency for computation and processing within the FPGA is 234.375 MHz regardless of which channel the receiver operates in. However, if the multi-phase digital quadrature mixing scheme of this application is adopted, the sampling frequency in the second and third channels will only reach 3 GHz, thus requiring only 93.75 MHz for computation and processing within the FPGA when the receiver operates in the second and third channels.
[0088] (2) There is no quantization error and almost no processing delay.
[0089] Specifically, on the one hand, as mentioned above, the multiphase digital quadrature mixing scheme of this application does not require the use of a DDS core to generate a digital local oscillator signal, and naturally there will be no quantization error, that is, the quantization error is fundamentally eliminated.
[0090] On the other hand, since the multiphase digital quadrature mixing scheme of this application only involves three operations: hold, reset, and invert for each sub-IF signal, and the logic implementation of these three operations in the FPGA is very simple (the hold operation only requires directly assigning the sub-IF signal to the corresponding sub-I or sub-Q signal; the reset operation only requires directly assigning the corresponding sub-I or sub-Q signal to the constant 0; the invert operation only requires assigning the inverse code of the sub-IF signal to the corresponding sub-I or sub-Q signal), this application greatly improves the processing efficiency compared to the calculation delay of dozens of clock cycles of the DDS core.
[0091] It is evident that the multiphase digital quadrature mixing scheme of this application is very practical and has certain value for multiphase digital quadrature mixing processing of large bandwidth intermediate frequency signals.
[0092] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.
[0093] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. A multiphase digital quadrature mixing method, characterized in that, The method is applied to a multiphase digital quadrature mixer system that includes a data acquisition module and an FPGA module, and includes: For any channel, the acquisition module is initialized and configured through the FPGA module; wherein, the initialization configuration is to make the ratio of the center frequency of the sub-IF signal of any channel to the sampling frequency three-quarters or one-quarter. Determine whether the acquisition module is working properly, and whether the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio; wherein the preset ratio is three-quarters or one-quarter; If it is determined that the acquisition module is working normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, then the FPGA module performs preset multi-phase digital quadrature mixing logic processing on the sub-IF signal corresponding to any channel to obtain the sub-I signal and sub-Q signal corresponding to the sub-IF signal; wherein, the preset multi-phase digital quadrature mixing logic processing only includes hold, set to 0 and invert; the sub-I signal is represented by the following formula (1): （1） The sub-Q signal is represented by the following formula (2): （2） in, This is the sub-I signal corresponding to the k-th channel; Let f be the sub-I signal corresponding to the k-th channel; f be the center frequency of the intermediate frequency signal; fc be the frequency of the digital local oscillator signal of the k-th channel; and t be the time. The initial phase corresponding to the k-th sub-signal; If it is determined that the acquisition module is not working properly, or the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is not a preset ratio, or the working channel is changed, the acquisition module is reconfigured through the FPGA module; during the reconfiguration, other devices are suspended.
2. The method as described in claim 1, characterized in that, The step of initializing and configuring the acquisition module through the FPGA module includes: The clock chip and ADC chip of the acquisition module are initialized and configured through the acquisition module control logic of the FPGA module.
3. The method as described in claim 2, characterized in that, The step of initializing and configuring the clock chip and ADC chip of the acquisition module through the acquisition module control logic of the FPGA module includes: The clock chip generates a sampling clock through a control protocol in the control logic of the acquisition module; wherein, the control protocol is determined according to the ADC chip used. The sampling frequency of the ADC chip is initialized according to the control protocol, the sampling clock, and the center frequency of the sub-IF signal of any one channel.
4. The method as described in claim 1, characterized in that, If it is determined that the acquisition module is working normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, then the step of performing preset multiphase digital quadrature mixing logic processing on the sub-IF signal corresponding to any channel through the FPGA module to obtain the sub-I signal and sub-Q signal corresponding to the sub-IF signal includes: If it is determined that the acquisition module is working normally, and the ratio of the frequency of the digital local oscillator signal of any channel to the sampling frequency is a preset ratio, then the digital quadrature mixing logic of the FPGA module is used to process the sub-IF signal corresponding to any channel according to the preset multi-phase digital quadrature mixing logic to obtain the sub-I signal and sub-Q signal corresponding to the sub-IF signal.
5. A multiphase digital quadrature mixing system, characterized in that, The system includes a data acquisition module and an FPGA module. The data acquisition module acquires intermediate frequency (IF) signals. The FPGA module controls the data acquisition module and performs multiphase digital quadrature mixing. The FPGA module also initializes the data acquisition module, ensuring that the ratio of the center frequency to the sampling frequency of any channel's sub-IF signal is three-quarters or one-quarter. The FPGA module also reconfigures the data acquisition module if it is determined that the data acquisition module is not functioning correctly, or if the ratio of the frequency to the sampling frequency of any channel's digital local oscillator signal is not a preset ratio, or if the operating channel has changed. During reconfiguration, other components are suspended. The preset ratio is three-quarters or one-quarter. The acquisition module includes a clock chip and an ADC chip; wherein, the clock chip is used to provide a stable sampling clock; and the ADC chip is used to acquire and convert the intermediate frequency signal according to the sampling clock. The FPGA module includes acquisition module control logic and digital quadrature mixing logic; wherein, the acquisition module control logic is used to control each chip in the acquisition module through a control protocol, so that the acquisition module works normally and ensures that the center frequency of the output intermediate frequency signal data is fixed at three-quarters or one-quarter of the sampling rate of the ADC chip; the digital quadrature mixing logic is used to perform preset multi-phase digital quadrature mixing logic processing on the sub-intermediate frequency signals corresponding to each channel to obtain the sub-I signal and sub-Q signal corresponding to each sub-intermediate frequency signal; the sub-I signal is represented by the following formula (1): （1） The sub-Q signal is represented by the following formula (2): （2） in, This is the sub-I signal corresponding to the k-th channel; Let f be the sub-I signal corresponding to the k-th channel; f be the center frequency of the intermediate frequency signal; fc be the frequency of the digital local oscillator signal of the k-th channel; and t be the time. This is the initial phase corresponding to the k-th sub-signal.