A storage method and system for CXL-SSD layered memory

Abstract

The application discloses a kind of layered memory of CXL-SSD facing storage method and system, belong to CXL and flash storage cross technical field.The method includes: when host last stage cache is off target and target address is located in CXL device, cache controller queries sparse remapping table and routes access request;High-fidelity memory access profiler real-time capture page heat and intra-page sparsity;Dynamic slicing and asymmetric migration module identifies active slice and migrates to fast layer according to preset interval, updates mapping relationship;Write-sensitive degradation and eviction module filters sacrifice page through write-aware strategy, executes multi-stage degradation and eviction operation.The application solves the problem of resource occupation by cold data and accelerated device wear and tear in traditional solutions through fine-grained memory access perception, slice-level migration and write-sensitive management, achieving the coordinated optimization of system performance, space efficiency and device life, and is suitable for memory expansion scenarios in data-intensive applications such as artificial intelligence and high-performance computing.

Description

Technical Field

[0001] This invention belongs to the field of cross-technology between CXL and flash memory storage, specifically relating to a storage method and system for CXL-SSD tiered memory. Background Technology

[0002] The demand for memory capacity from data-intensive applications such as artificial intelligence, large language models, and high-performance computing is growing exponentially. Traditional DRAM-based memory architectures suffer from high unit costs, limited scalability, and volatility, making it difficult to meet the core requirements of modern data centers for large-capacity, persistent storage, leading to the increasingly prominent "memory wall" problem. To address this issue, the industry has proposed Compute Fast Link (CXL) technology, which uses an interconnect protocol supporting cache line-level consistency to seamlessly integrate heterogeneous storage media as a memory expansion pool into the host physical address space. Among these, CXL-SSDs based on NAND flash solid-state drives (SSDs) have become the preferred solution for building large-capacity tiered memory systems due to their advantages of high density, low cost, and non-volatility.

[0003] CXL-based memory expansion offers a viable path to overcoming the "memory wall," but building an efficient tiered memory system still faces significant challenges. First, there are substantial performance differences between memory tiers. Due to PCIe link latency, controller overhead, and the characteristics of flash memory, CXL-SSD access latency is much higher than host DDR DRAM, resulting in a significant reduction in bandwidth. Second, flash memory has programming / erase cycle limitations and read / write asymmetry, requiring strict control of write operations to prevent premature device wear. Therefore, tiered memory systems need to retain hot data in the memory tier as much as possible and reduce unnecessary write operations to achieve a dynamic balance between performance improvement and write wear control. However, achieving these optimization goals faces a "granularity mismatch" between coarse-grained memory management and fine-grained application access patterns, resulting in "sparse pages." Despite the series of solutions proposed by the industry, the following limitations still exist: First, host software or hardware-based monitoring solutions are caught in a trade-off between accuracy and overhead. The operating system relies on page faults or periodic scans, resulting in high context switching overhead and an inability to capture cache line-level access details. CPU hardware sampling solutions, on the other hand, face the dilemma of missing hotspots at low sampling rates and consuming CPU resources at high sampling rates. Second, simulation and CXL device-side solutions have blind spots in data placement strategies: early simulation solutions lacked real-time access traffic monitoring capabilities. While emerging hardware-assisted solutions can achieve low-overhead monitoring and intra-page sparsity identification, they are limited by the 4KiB page mapping mechanism of the host memory management unit. This leads to either overall migration of sparse hot pages, causing cold data to consume fast memory resources, or prohibiting migration, causing hot data to remain in the slow layer. Furthermore, existing performance-oriented strategies often neglect flash write friendliness, and blind page replacement accelerates device wear.

[0004] Therefore, given the contradiction between the complex and ever-changing workload characteristics of the host and the physical constraints of SSDs on the device side, how to design a fine-grained management solution for CXL-SSD tiered memory, solve the granularity mismatch problem between coarse-grained management and fine-grained access, mask the performance differences between tiers while taking into account the flash memory durability constraints, and achieve synergistic optimization of system performance, space utilization and device lifespan has become a key technical problem that urgently needs to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a storage method and system for CXL-SSD tiered memory to address the shortcomings of the prior art. This method solves the problem that existing page migration strategies cannot characterize the sparsity of intra-page access, resulting in a large amount of cold data occupying fast memory, accelerating device wear and tear, and making it difficult to balance performance and lifespan.

[0006] The present invention adopts the following technical solution: A storage method for tiered memory in CXL-SSDs, executed collaboratively by the cache controller on the CXL device side and the processor on the host side, includes the following steps: S1. When the target address of the access request that misses the host's last-level cache is located in the CXL device, the cache controller receives the access request and queries the internal sparse remapping table. If a match is found, the access request is redirected to the host fast layer. If a match is not found, the next level of the CXL device is explored. S2. The high-fidelity memory access parser in the cache controller detects all CXL access requests in real time and captures page access popularity and in-page access sparsity. S3. The dynamic slicing and asymmetric migration module on the host side retrieves the analysis data of the high-fidelity memory access profiler through memory-mapped I / O at a preset migration interval, identifies active slices from the hot pages and generates a promotion list, migrates only the active slices from the CXL-SSD slow layer to the host fast layer, and updates the mapping relationship of the sparse remapping table at the same time. S4. The write-sensitive degradation and eviction module on the host side filters sacrificial pages through a write-aware sacrificial page selection strategy. Based on the cleanliness and data organization of the sacrificial pages, it performs multi-stage degradation and eviction operations on the sacrificial pages to reclaim the storage space of the host fast layer and / or CXL-SSD slow layer.

[0007] Preferably, in step S1, the sparse remapping table maintains the mapping index between sparse slices in the physical address space of the CXL device and virtual cache slots in the host fast layer. The cache controller transparently routes CPU requests to the fast layer through the sparse remapping table without modifying the host operating system page table. Furthermore, when the target address of an access request that is missed by the host's last-level cache is located in the fast layer, the system directly accesses the fast layer and returns the data.

[0008] Preferably, in step S2, the high-fidelity memory access profiler is an independent hardware unit integrated inside the cache controller. It captures page access popularity and in-page access sparsity by snooping on all CXL traffic. The analysis overhead is completely offloaded to the host CPU. The host obtains the batch statistics captured by the high-fidelity memory access profiler through memory-mapped I / O. The high-fidelity memory access parser adopts a hybrid data structure combining the CountMin-Sketch algorithm and a sorted min-heap. Its core includes a CM-Sketch unit for probabilistically estimating global page popularity and a hot page tracker for maintaining information on the Top-K pages with the highest global popularity.

[0009] Preferably, the specific process for capturing page visit popularity and in-page visit sparsity is as follows: S201. Parse the external memory access address and separate the global page address and the corresponding page cache line index; S202. The global page address is mapped to multiple counter entries of the CM-Sketch unit via multiple independent hash functions. The counter entries are accumulated according to the access type, and the minimum value of multiple counter values ​​is taken as the page estimated popularity corresponding to the global page address. S203. Search for the global page address in the sorted min-heap of the hot page tracker. If it exists, update the corresponding page estimated heat and mark the bit in the sparse bitmap corresponding to the page cache line index as 1. If it does not exist, compare the page estimated heat with the heat value of the root node of the sorted min-heap. If the page estimated heat is higher, replace the root node and insert the global page address, page estimated heat, and initial sparse bitmap into the sorted min-heap. S204. Generate a page sparsity-frequency distribution histogram according to a preset update interval, dynamically set a global popularity threshold based on the histogram, retrieve the hot page address and corresponding sparsity bitmap that exceed the global popularity threshold, and fill them into the migration candidate buffer.

[0010] Preferably, the sparse bitmap adopts an on-demand allocation strategy, and only when the page corresponding to the global page address is included in the Top-K hot page list of the sorted min-heap is a brand new empty sparse bitmap initialized and the index bit of the currently accessed page cache line is set.

[0011] Preferably, in step S3, the specific process of identifying active slices from hot pages is as follows: S301. Extract the sparsity bitmap corresponding to the hot page; S302. Logically divide the sparsity bitmap into 2 n continuous sub-bitmaps, each sub-bitmap corresponding to the physical address range of a slice, where n is a configurable parameter adjustable according to actual workload characteristics, and the value range is 0 ≤ n ≤ 6; S303. Perform a bitwise OR operation on each sub-bitmap. If the operation result is 1, it indicates that there is an active cache line access in the slice corresponding to the sub-bitmap, and mark it as an active slice; S3 04. Append all the identified active slices to the global hot slice list in the form of <page address, MaskSlicei> tuples to form a promotion list.

[0012] Preferably, in step S3, the specific process of migrating only the active slices from the CXL-SSD slow layer to the host fast layer is as follows: Allocate idle virtual slots in the virtual cache pool constructed by pre-dividing and reserving space in the host fast layer, and use DMA to move the active slices from the CXL-SSD slow layer to the virtual slots, and establish an index mapping from <CXL physical address, slice offset> to the host virtual slot identifier; After the migration of the active slices is completed, clear the corresponding bits of the sparsity bitmap in the high-fidelity memory access profiler, and remove the corresponding page from the sorted minimum heap of the hot page tracker; when the dynamic slice and asymmetric migration module performs data degradation operations, all the data of the selected victim page in the host fast layer is degraded to the CXL-SSD slow layer in the form of a complete page.

[0013] Preferably, in step S4, the write-aware victim page selection policy is based on a set-associative architecture and follows the principle of clean page priority. When a cache group needs to select a victim page, find the first strictly clean page within the preset clean page scan window; if there is no clean page within the clean page scan window, select the victim page in the least recently used manner; Logically divide the capacities of the host fast layer and the CXL-SSD slow layer into two parts: the main cache and the global victim cache respectively. The global victim cache dynamically harvests the unused free space in the main cache. When a cache group is full, move the selected victim page into the global victim cache; if the page in the global victim cache is accessed again, directly redirect it back to the main cache, and only update the metadata without performing physical data migration operations.

[0014] Preferably, in step S4, the specific process of performing multi-stage degradation and eviction operations includes fast layer degradation processing and slow layer eviction processing: The fast layer degradation process is as follows: if the sacrificed page is a dirty page, it is downgraded to the CXL-SSD slow layer main cache and inserted at the end of the linked list of the corresponding cache group; if the dirty page is a dirty slice in the fast layer and its corresponding buddy slice already resides in the CXL-SSD slow layer, the two slices are automatically merged into a complete 4KiB page; if the sacrificed page is a clean page, an invalidation instruction is sent to the CXL cache controller, the corresponding mapping entry in the sparse remapping table is deleted to remove the address redirection relationship, the page is silently reclaimed, and the corresponding virtual slot is returned to the free linked list. The slow layer eviction process is as follows: if the sacrificed page contains a dirty slice, the valid data is flushed into the CXL-SSD capacity layer flash memory; if the buddy slice of the dirty slice still resides in the host fast layer, the buddy slice is first retrieved, and the two are merged into an aligned 4KiB complete page before being written to the NAND flash memory; if there is no corresponding buddy slice, the complete page is directly written to the flash memory; if the sacrificed page is a clean page, it is silently discarded and the corresponding space is reclaimed. Furthermore, the CXL-SSD slow layer acts as a write merging buffer, constructing a multi-stage data processing path that can absorb burst traffic and merge scattered write operations, absorbing invalid and burst traffic, and minimizing the number of flash write-backs.

[0015] Secondly, embodiments of the present invention provide a storage system for CXL-SSD tiered memory, including a cache controller deployed on the CXL device side and a host-side storage management module running on the host side; The cache controller integrates a sparse remapping table and a high-fidelity memory access parser. The host-side storage management module includes a dynamic slicing and asymmetric migration module, as well as a write-sensitive degradation and eviction module; The sparse remapping table is used to maintain the mapping index between sparse slices in the physical address space of the CXL device and virtual cache slots in the host fast layer, so that the cache controller can query and transparently route access requests from the central processing unit to the host fast layer. The high-fidelity memory access profiler is connected to the sparse remapping table and is used to detect all CXL access requests in real time, capture page access popularity and page access sparsity, and output profile data to the host through memory-mapped I / O. The dynamic slicing and asymmetric migration module is communicatively connected to the high-fidelity memory access profiler. It is used to retrieve the profile data at a preset migration interval, identify active slices from the hot pages and generate a promotion list, migrate the active slices only from the CXL-SSD slow layer to the host fast layer, and update the mapping relationship of the sparse remapping table. The write-sensitive degradation and eviction module is connected to the dynamic slicing and asymmetric migration module. It is used to filter sacrificial pages through a write-aware sacrificial page selection strategy, and perform multi-stage degradation and eviction operations on the sacrificial pages according to their cleanliness and data organization, thereby reclaiming the storage space of the host fast layer and / or CXL-SSD slow layer. The cache controller and the host-side storage management module are configured to collaboratively execute the storage method for CXL-SSD tiered memory.

[0016] Thirdly, a computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the storage method for CXL-SSD tiered memory described above.

[0017] Fourthly, embodiments of the present invention provide a computer-readable storage medium including a computer program, which, when executed by a processor, implements the steps of the above-described storage method for tiered memory of CXL-SSD.

[0018] Fifthly, a chip includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the storage method for CXL-SSD tiered memory described above.

[0019] In a sixth aspect, embodiments of the present invention provide an electronic device including a computer program, which, when executed by the electronic device, implements the steps of the above-described storage method for CXL-SSD tiered memory.

[0020] Compared with the prior art, the present invention has at least the following beneficial effects: A storage method for tiered memory in CXL-SSDs decouples hardware and software by offloading data access monitoring to the CXL device-side cache controller and retaining decision-making on the host side. Flexible mapping of the physical address space is achieved through SRT (System-Redirecting Memory). This architecture requires no modification to the host operating system's page tables, is compatible with the standard CXL protocol, and lowers the deployment threshold. Furthermore, offloading the profiler to the device side avoids performance fluctuations caused by host CPU polling or interrupts, achieving "zero-load" awareness of memory access behavior. Through a four-step pipeline operation, it ensures that hot data is promptly identified and promoted to the fast tier, while cold data remains in the slow tier, thus resolving the performance difference issue of tiered memory at the system architecture level.

[0021] Furthermore, by maintaining the mapping relationship between sparse slices and fast layer virtual cache slots through SRT, transparent redirection of CPU requests is achieved, avoiding the complex operation of modifying the host operating system page table and reducing the difficulty of system deployment. At the same time, the access paths for different target addresses are improved, ensuring direct and efficient access to fast layer data, reducing unnecessary hierarchical probing overhead, and further optimizing access latency.

[0022] Furthermore, integrating MAP into the CXL device cache controller completely offloads the host CPU's profiling overhead, resolving the trade-off between accuracy and overhead in traditional host-side monitoring solutions. By employing a hybrid data structure combining the CountMin-Sketch algorithm and a sorted min-heap, accurate capture of page heat and intra-page sparsity is achieved, ensuring both sensing accuracy and controlling hardware resource consumption.

[0023] Furthermore, by using multi-hash function mapping and selecting the minimum counter value, the accuracy of page popularity estimation is improved, avoiding statistical bias caused by a single hash function. Real-time updates of the sparse bitmap ensure accurate characterization of in-page access features, solving the problem that traditional solutions cannot capture cache line-level access details. Dynamically setting the popularity threshold using a page sparsity-frequency distribution histogram allows hotspot identification to adapt to workload changes, avoiding misjudgments or omissions caused by fixed thresholds, and providing accurate filtering criteria for subsequent hotspot slice identification.

[0024] Furthermore, initializing a sparse bitmap for the Top-K hot pages avoids the waste of on-chip storage resources caused by maintaining bitmaps for all pages, significantly reducing hardware overhead. Focusing on the truly active working set ensures that limited storage resources are used for capturing access characteristics of critical data, improving system resource utilization efficiency. Simultaneously, only setting the index bit of the currently accessed page's in-page cache line guarantees the accuracy of sparsity information.

[0025] Furthermore, the migration granularity is reduced from the page level to the sub-page level. Through an adjustable partitioning scheme, a dynamic balance between migration granularity accuracy and management overhead is achieved, adapting to different workload characteristics. Bitwise OR operations quickly determine slice activity, ensuring the efficiency of the recognition process and avoiding complex statistical calculations.

[0026] Furthermore, by combining a virtual cache pool with DMA transfer, efficient subpage-level migration is achieved while maintaining complete transparency to the host operating system, without affecting the existing page table mechanism and TLB access advantages. After migration, the corresponding bits in the sparse bitmap are cleared and the Top-K list is removed, ensuring the real-time nature of memory access profiling data and avoiding repeated migrations. The whole-page degradation strategy in the asymmetric design effectively reconstructs data spatial locality, simplifies storage reclamation logic, and avoids the read-modify-write amplification effect caused by partial slice writes, protecting the write endurance of NAND flash memory.

[0027] Furthermore, the clean page priority principle prioritizes the eviction of clean pages, achieving zero I / O overhead reclamation, reducing flash write cycles, and mitigating device wear. When no clean pages are available, the LRU strategy is employed to ensure the rationality of sacrificial page selection. GVC dynamically harvests free space, effectively resolving the internal fragmentation problem caused by set-associative mapping and subpage slicing interactions, maximizing the space utilization of fast / slow tiers. The design of updating only metadata when a page is revisited reduces the migration overhead of "warm" data, filters transient cold pages, further reduces flash write traffic, and achieves synergistic optimization of storage resource utilization efficiency and device lifespan.

[0028] Furthermore, differentiated handling of sacrificed pages in the fast / slow tiers enables tiered data management. Dirty page merging in the fast tier and preemptive merging in the slow tier ensure full-page alignment during data writing, significantly reducing flash write amplification. Silent reclamation of clean pages achieves zero-overhead space release, improving system efficiency. The CXL-SSD's slow tier acts as a write merging buffer, effectively absorbing bursty access traffic, merging scattered write operations, and minimizing flash write-backs. This ensures that the vast majority of data reclamation operations are completed within DRAM, with flash writes performed only when necessary, fundamentally balancing system performance, space utilization, and device durability.

[0029] It is understood that the beneficial effects of the second to sixth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0030] In summary, this invention achieves fine-grained management through four core mechanisms: cache routing, precise memory access awareness, slice-level migration, and write-sensitive reclamation. It not only solves the granularity mismatch problem of traditional solutions, improving the utilization and access efficiency of the fast layer, but also reduces flash memory wear through write operation optimization, balancing system performance, space efficiency, and device lifespan, thus adapting to the needs of data-intensive applications.

[0031] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0032] Figure 1This is a flowchart of the method of the present invention; Figure 2 Architecture diagram for high-fidelity memory access; Figure 3 Flowchart of the sparsity-aware dynamic slicing method; Figure 4 A schematic diagram of the optimization, degradation, and expulsion mechanisms for write-sensing; Figure 5 A schematic diagram of a computer device provided in an embodiment of the present invention; Figure 6 This is a block diagram of a chip provided according to an embodiment of the present invention.

[0033] Among them, 60. Computer equipment; 61. Processor; 62. Memory; 63. Computer program; 600. Electronic device; 610. Processing unit; 620. Storage unit; 6201. Random access memory unit; 6202. Cache memory unit; 6203. Read-only memory unit; 6204. Program / utility; 6205. Program module; 630. Bus; 640. Display unit; 650. Input / output interface; 660. Network adapter; 700. External device. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] In the description of this invention, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0036] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0037] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this invention generally indicates that the preceding and following objects have an "or" relationship.

[0038] It should be understood that although terms such as first, second, third, etc., may be used in the embodiments of the present invention to describe the preset range, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0039] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0040] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0041] This invention provides a storage method for tiered memory in CXL-SSDs. By integrating a lightweight profiler on the CXL device side, it captures page popularity and in-page access characteristics using probabilistic data structures and sparse bitmaps. It employs dynamic slicing and asymmetric migration mechanisms to reduce management complexity by promoting only active slices of hot pages to fast memory and degrading the entire page. At the same time, it delays device wear through write-sensitive adaptive management, thereby achieving coordinated optimization of system performance, space efficiency, and device lifespan.

[0042] This invention discloses a storage method for tiered memory in CXL-SSDs, which is executed collaboratively by the cache controller on the CXL device side and the processor on the host side. The overall system is a closed-loop control system based on a last-level cache (LLC) off-target triggering. Through the collaborative work of multiple modules, it achieves synergistic optimization of system performance, space efficiency, and device lifespan, including the following steps: S1. When the target address of the access request that misses the host's last-level cache is located in the CXL device, the cache controller receives the access request and queries the internal sparse remapping table. If a match is found, the access request is redirected to the host fast layer. If a match is not found, the next level of the CXL device is explored. Please see Figure 1 The proposed tiered memory storage solution for CXL-SSD (PSPMem) consists of three core modules that work together: a high-fidelity memory access profiler (MAP) deployed on the CXL device side, a dynamic slicing and asymmetric migration module (SAM) running on the host side, and a write-sensitive demotion and eviction module (WDE).

[0043] On the CXL device side, this invention designs a Sparse Remap Table (SRT) as the core of address routing. This table maintains the mapping index between sparse slices in the CXL device's physical address space and virtual cache slots in the host's fast layer, enabling the cache controller to transparently route CPU requests to the fast layer without modifying the host operating system (OS) page tables. MAP, as the access-aware core of PSPMem, is implemented as a lightweight hardware unit within the cache controller. MAP completely offloads the profiling overhead to the host CPU and accurately tracks runtime states such as page access heat and intra-page access sparsity by spying on all CXL traffic. For the host, the aforementioned batch statistics can be efficiently obtained through Memory Mapped I / O (MMIO). In summary, this invention, through the collaborative design of SRT and MAP, not only avoids changes to the host hardware architecture but also ensures compatibility with the standard CXL platform. On the host side, the PSPMem daemon acts as the central control plane in user space, periodically polling MAP and coordinating memory management. To minimize migration overhead and bandwidth waste, SAM identifies sparse but frequently accessed cache lines (i.e., hot slices) in the slow layer and promotes them to the fast layer according to the migration interval (migration_interval parameter, default 10ms). Meanwhile, WDE employs a write-aware sacrificed page selection method to classify, demote, or evict pages, and reduces NAND flash wear and alleviates memory pressure in the fast layer through multi-stage buffer path merging of write operations. Furthermore, the PSPMem daemon resets relevant counters in the MAP after each profiler reset interval (profiler_reset_interval, default 1s).

[0044] PSPMem's workflow is a closed-loop control system based on the last-level buffer (LLC) off-target triggering to achieve continuous optimization. The specific steps are as follows: 1. When the target address of the LLC out-of-target error is located in the fast layer, the system accesses the fast layer according to path ①; 2. When the target address of the LLC out-of-target is located in the CXL device, the request is sent to the cache controller via path ②. The cache controller first queries the internal SRT. If a match is found, it quickly redirects to the fast layer via path ③ and returns the data. If a match is not found, it continues to probe the next level. 3. During this process, the MAP module monitors all access requests in real time and captures page popularity and access sparsity according to path ③a; 4. Within each migration_interval period, SAM first retrieves the profile data provided by MAP via MMIO according to path ③b, and identifies "active" slices from the hot pages and generates a promotion list according to path ③c. Then, through the customized migration_slice interface, it promotes only these hot slices to the fast layer according to path ③d. Finally, it updates the SRT mapping according to path ③ to reduce migration traffic. 5. To reclaim storage space in the fast / slow tiers, WDE uses a write-aware optimization strategy along path ③e to filter sacrificial pages. Based on the page's cleanliness and data organization, sacrificial pages are categorized along path ③f and subjected to multi-stage degradation and eviction operations: dirty pages are downgraded to the slow tier along path ③g or evicted to the capacity tier along path ③i; clean pages are logically reclaimed to the capacity tier along path ③h. This multi-stage path acts as a write buffer, absorbing invalid and bursty traffic and minimizing the number of flash write-backs. 6. If the request is hit in the slow layer, return the data directly according to path ④; otherwise, load the entire 4KiB page from the capacity layer to the slow layer, and then respond to the request according to path ⑤.

[0045] S2. The high-fidelity memory access parser in the cache controller detects all CXL access requests in real time and captures page access popularity and in-page access sparsity. Please see Figure 2 The high-fidelity memory access profiler (MAP), fully integrated as a separate hardware unit within the CXL device's cache controller, is the core of PSPMem's access awareness. It enables high-precision, low-latency awareness of page access frequency and intra-page access sparsity with extremely low hardware overhead. To balance awareness accuracy and hardware resource consumption, this invention innovatively employs a hybrid data structure design based on the probabilistic CountMin-Sketch (CM-Sketch) algorithm and the deterministic Sorting Min-Heap (SMH). This design not only effectively decouples frequency estimation from complex sparsity monitoring tasks but also eliminates the high overhead of relying on the host CPU for hotspot identification in traditional solutions, and enables MAP to accurately characterize intra-page access sparsity.

[0046] The core hardware units of MAP include the CM-Sketch unit and the Hot Page Tracker (HPT). The CM-Sketch unit is primarily used for probabilistic estimation of global page popularity. Its structure is a two-dimensional counter array with depth D and width H, containing D×H storage entries. Each entry maintains an access counter a. ij(where 1≤i≤D, 1≤j≤H). HPT is constructed using sorted SMH units to accurately maintain the information of the top K pages with the highest global popularity (Top-K). Each entry in the SMH stores... <PA,<Hotness,SB> The triple is defined as follows: PA is the page address, Hotness is the estimated access popularity of the page, and SB is a 64-bit sparse bitmap representing the access distribution within the page.

[0047] The specific workflow of MAP is as follows: When an external memory access address (MA) is passed in, MAP first parses MA according to path ①, separating the global page address (PA) and the corresponding in-page cache line index (CLI).

[0048] Subsequently, PA is mapped along path ② to D different counter entries a of the CM-Sketch unit via D independent hash functions. ij MAP assigns values ​​to the selected D counters a based on the access type (read / write, denoted as R / W, default 10 / 11). ij Perform the accumulation operation separately.

[0049] Next, the CM-Sketch unit takes the minimum value among these D counter values ​​along path ③ as the current estimated popularity of the page PA.

[0050] After obtaining the estimated heat of PA, MAP searches for PA in SMH via path ④. If PA already exists in SMH, its corresponding heat value is updated directly, and the bit in SB corresponding to CLI is marked as 1 to update the in-page access sparse information.

[0051] If PA is not in SMH, then the newly calculated Hotness is compared with the SMH root node (i.e., the page with the lowest popularity in the current Top-K list) by following path ⑤.

[0052] If the new PA's popularity is higher than the root node's, then perform the replacement operation according to path ⑥, evict the page information corresponding to the root node, and insert the new PA, its popularity, and the initial SB (only setting the current CLI) into the SMH.

[0053] For SB storage, this invention employs an on-demand allocation strategy. A completely new empty SB is initialized and the currently accessed CLI bit is set only when a page is successfully included in the Top-K (K defaults to 41K) hot page list. This design ensures that expensive bitmap data is maintained only for the truly active working set, greatly saving on-chip storage resources.

[0054] At the end of each update interval (thr_update_interval, default 100ms), the SAM module on the host side triggers MAP according to path ⑦, generating a Page Sparsity-Frequency Distribution (PSFD) histogram based on internal statistical data. SAM then refers to this PSFD histogram according to path ⑧, dynamically setting the global heat threshold θ by calculating the average of all frequencies to achieve precise control over hotspot identification.

[0055] Finally, SAM retrieves the Top-K hot page addresses with heat values ​​exceeding θ and their corresponding SB information from the HPT of MAP according to path 9, and fills these hot page information into the migration candidate buffer according to path 10, providing data support for subsequent dynamic slicing and asymmetric migration operations.

[0056] S3. The dynamic slicing and asymmetric migration module on the host side retrieves the analysis data of the high-fidelity memory access profiler through memory-mapped I / O at a preset migration interval, identifies active slices from the hot pages and generates a promotion list, migrates only the active slices from the CXL-SSD slow layer to the host fast layer, and updates the mapping relationship of the sparse remapping table at the same time. This invention designs a sparse-aware dynamic slicing and asymmetric transfer module (SAM) to achieve refined transfer and adaptive decision-making. SAM achieves efficient utilization of heterogeneous resources through two sub-modules: sparse-aware dynamic slicing and asymmetric transfer.

[0057] The sparsity-aware dynamic slicing submodule decouples migration granularity from monitoring granularity, reducing the minimum granularity of data migration from the standard page level to the sub-page level. This avoids cold data consuming fast memory resources during full-page migration, maximizing the space utilization and access efficiency of the fast memory layer. This invention logically divides a standard 4KiB physical page (corresponding to 64 cache lines) into 2... n A slice is a set of consecutive cache lines with n addresses; where n is an adjustable configuration parameter based on the actual workload characteristics, with a value range of 0≤n≤6, in order to achieve a dynamic balance between migration granularity accuracy and system management overhead.

[0058] Please see Figure 3 The execution flow of the sparseness-aware dynamic slicing method of this invention is given. For each hot page in the migration candidate buffer output by MAP, SAM completes hot slice identification through the following pipeline steps: 1. Extract the sparse bitmap SB corresponding to the hot page according to path ①; 2. Perform slicing according to path ②, dividing the SB logic into 2. n A continuous sub-bitmap, denoted as Slice i(0≤i<2) n Each sub-bitmap corresponds one-to-one with the physical address range of a slice; 3. Perform slice liveness verification along path ③ for each sub-bitmap Slice. i Perform a bitwise OR operation; if the result is ∨(Slice) i If )=1, it indicates that there is active cache line access in the slice corresponding to the sub-bitmap, and it is marked as a hot slice; otherwise, it is marked as a cold slice. 4. Generate a hot slice migration list according to path ④, and transfer all identified hot slices to... <PA,Mask Slice i The tuple is appended to the global hot slice list, awaiting subsequent subpage-level data migration operations.

[0059] The asymmetric migration submodule is responsible for bidirectional data migration operations in the hierarchical memory system. When performing data promotion, the asymmetric migration submodule only migrates identified hot slices from the CXL-SSD slow layer to the host fast memory layer. After the hot slice is promoted, the corresponding bit in the sparse bitmap SB in the device-side MAP is simultaneously cleared, and the page is removed from the Top-K min-heap, strictly filtering cold data to prevent invalid data from occupying fast memory resources. In contrast, when WDE selects a page in the fast layer as a sacrifice page, SAM treats all data of that page as a complete page and performs a degradation operation. To achieve the above sub-page-level asymmetric migration while ensuring complete transparency to the host operating system, SAM and the device-side SRT collaboratively execute an invisible promotion mechanism. Specifically, the host-side fast layer pre-allocates reserved space, constructing a software-managed virtual cache pool (Shadow Cache Pool). When SAM performs a hot slice promotion operation, it first allocates free virtual slots in the virtual cache pool, moves the target hot slice from the slow layer to the slot via DMA, and simultaneously updates the mapping relationship of the device-side SRT, establishing...<CXL_PA, Slice_Offset> The index mapping to Host_Slot_ID. When the CPU accesses this address again subsequently, although the host OS page table still points to the CXL device address space, the CXL cache controller can automatically redirect the access request to the corresponding virtual slot in the host fast tier (corresponding to...) via SRT hit lookup. Figure 3 (Path ③). This mechanism fully preserves the advantages of TLB access for pages of different sizes such as 4KiB and 2MiB, while achieving slice-level access latency optimization and memory bandwidth utilization efficiency improvement.

[0060] The asymmetric migration mechanism of this invention can, on the one hand, re-aggregate scattered hot slices into complete physical pages in the slow layer, effectively reconstructing the locality of data space and simplifying the subsequent storage space reclamation logic; on the other hand, the whole-page degradation design can avoid the severe read-modify-write amplification effect caused by some slices being directly written to the back-end flash memory, greatly reduce invalid write operations, and protect the write endurance of the back-end NAND flash memory.

[0061] S4. The write-sensitive degradation and eviction module on the host side filters sacrificial pages through a write-aware sacrificial page selection strategy. Based on the cleanliness and data organization of the sacrificial pages, it performs multi-stage degradation and eviction operations on the sacrificial pages to reclaim the storage space of the host fast layer and / or CXL-SSD slow layer.

[0062] Please see Figure 4 The Write Sensitive Demotion and Eviction module (WDE) includes a write-aware sacrifice page selection submodule and a multi-stage degradation and eviction submodule. The two work together to achieve hierarchical management of data in the fast and slow layers and efficient space reclamation. At the same time, the slow layer of the CXL-SSD is used as a write merging buffer to absorb invalid and burst traffic, minimize the number of flash write-backs, reduce NAND flash wear, and alleviate memory pressure in the fast layer.

[0063] Write the sacrifice page selection submodule of perception To quickly select the optimal sacrifice page, reduce system overhead, and protect the durability of the backend flash memory, the WDE module employs a write-aware sacrifice page (VP) selection strategy. This strategy, based on a set-associative architecture and following the clean page priority principle, effectively reduces the number of writes to the backend flash memory while improving cache hit rate. Specifically, when a cache set (such as Set2) needs to select a sacrifice page, it does not need to perform a global scan of the entire cache list; it only searches for the first strictly clean page within a predefined clean page scan window (CPSW). Evicting clean pages achieves zero I / O overhead, while eviction of dirty pages triggers a flash memory write operation. If there is no clean page in the CPSW, the least recently used method is used to select the sacrifice page. This design efficiently captures low-cost eviction opportunities with negligible search latency.

[0064] Meanwhile, to address the internal fragmentation issue arising during the interaction between group-associative mapping and subpage slicing (i.e., although the cache group is full of sparse slices, the physical space utilization is low), this invention designs a Global Sacrifice Cache (GVC), logically dividing the capacity of the fast and slow layers into the main cache and GVC, respectively. GVC dynamically harvests unused free space in the main cache via paths ④ and ⑧; when a cache group is full, the selected sacrifice page is not directly evicted but moved into the GVC, achieving efficient utilization of fragmented capacity. If a page in the GVC is accessed again, it is directly redirected back to the main cache; this process only requires updating metadata and does not require physical data migration. The GVC design achieves three technical benefits: 1. Maximize the space utilization of fast / slow speed layers; 2. Filter transient cold pages to reduce write traffic to the backend flash memory; Third, reduce the overhead of cross-layer migration of "warm" data and further optimize the overall system performance.

[0065] Multi-stage downgrade and expulsion submodule To further alleviate the write pressure of the tiered memory system, WDE uses the slow layer of the CXL-SSD as a write merging buffer. By constructing a multi-stage data processing path that can absorb bursts of access traffic and merge scattered write operations, it achieves hierarchical management and efficient space reclamation of data in the fast and slow layers.

[0066] Degradation handling of sacrificed pages in the host fast tier For data degradation operations in the fast tier, after the SAM module completes page promotion from the slow tier main cache (corresponding to path ②) or GVC (corresponding to path ③), WDE selects the sacrifice page P from the fast tier. victim The following two scenarios should be handled separately: Case 1: If P victim If the page is dirty, WDE will demote it to the slow-level main cache (corresponding to path ② or ⑥) and insert it at the end of the linked list of the corresponding cache group; if the dirty page is a dirty slice of the fast-level PS fast And its corresponding partner slice PS slow Having resided in the slow layer, WDE automatically merges the two slices into a complete 4KiB page (FP). This spatial locality reconstruction operation preserves historical access patterns of the data, providing support for subsequent data processing without altering the metadata storage location.

[0067] Case 2: If P victim For a clean page, WDE sends an invalidation instruction to the CXL cache controller, deletes the corresponding mapping entry in the SRT to remove the address redirection relationship, and then silently reclaims the page directly according to path ⑤ or ⑦, returning the corresponding virtual slot to the free list, thus achieving zero I / O overhead space reclamation.

[0068] The aforementioned fast-layer degradation design has two core advantages: First, it can effectively absorb burst write traffic. Most downgraded dirty pages only become temporarily cold and can be re-upgraded at low cost after being downgraded to the slow layer, avoiding the high write overhead and subsequent reread overhead caused by directly writing to flash memory. Second, it can realize write operation merging. Multiple modifications to different slices of the same page can be merged into a single whole-page write before final eviction after being downgraded to the slow layer, significantly reducing flash write amplification.

[0069] CXL-SSD Slow Layer Sacrificial Page Eviction Site Data eviction in the slow layer is a core step in data persistence to the backend NAND flash memory. When the system needs to read a page from flash memory and load it into the slow layer main cache via path ①, or receive a degraded page from the fast layer via paths ② or ⑥, WDE selects the sacrifice page P from the slow layer. victim Process according to the following rules: Case 1: If P victim If the page contains a dirty slice, valid data must be flushed to the capacity layer flash memory; if the dirty page is a dirty slice in the slow layer (PS) fast And its corresponding partner slice PS fast (Regardless of whether it is dirty or clean) it still resides in the fast layer. WDE performs a preemptive merge operation, first retrieving the partner slice, merging the two into an aligned 4KiB complete page, and then writing it to the NAND flash memory according to path ① or ⑨; if the dirty slice has no corresponding partner slice, the complete page is directly written to the flash memory.

[0070] Case 2: If P victim For clean pages, they are silently discarded and the corresponding space is reclaimed.

[0071] Through the cascaded degradation and eviction design of the fast-slow layer described above, WDE can ensure that the vast majority of data reclamation operations are completed in DRAM, and flash writes are only performed in the necessary scenarios for data persistence. Moreover, all write operations adopt the full-page alignment format that is friendly to flash devices, thereby reducing the write amplification effect at the source.

[0072] Subsequent memory access response If a memory access request is hit during the exploration of the slow layer, the data is returned directly from the slow layer; if the slow layer still does not hit, the entire 4KiB page is loaded from the capacity layer to the slow layer, and then the memory access request is responded to, completing the entire closed-loop memory access processing flow.

[0073] In another embodiment of the present invention, a storage system for CXL-SSD tiered memory is provided. This system can be used to implement the above-mentioned storage method for CXL-SSD tiered memory. Specifically, it includes a cache controller deployed on the CXL device side and a host-side storage management module running on the host side. The cache controller integrates a sparse remapping table and a high-fidelity memory access parser. The host-side storage management module includes a dynamic slicing and asymmetric migration module, as well as a write-sensitive degradation and eviction module; The sparse remapping table is used to maintain the mapping index between sparse slices in the physical address space of the CXL device and virtual cache slots in the host fast layer, so that the cache controller can query and transparently route access requests from the central processing unit to the host fast layer. The high-fidelity memory access profiler is connected to the sparse remapping table and is used to detect all CXL access requests in real time, capture page access popularity and page access sparsity, and output profile data to the host through memory-mapped I / O. The dynamic slicing and asymmetric migration module is communicatively connected to the high-fidelity memory access profiler. It is used to retrieve the profile data at a preset migration interval, identify active slices from the hot pages and generate a promotion list, migrate the active slices only from the CXL-SSD slow layer to the host fast layer, and update the mapping relationship of the sparse remapping table. The write-sensitive degradation and eviction module is connected to the dynamic slicing and asymmetric migration module. It is used to filter sacrificial pages through a write-aware sacrificial page selection strategy, and perform multi-stage degradation and eviction operations on the sacrificial pages according to their cleanliness and data organization, thereby reclaiming the storage space of the host fast layer and / or CXL-SSD slow layer. The cache controller and the host-side storage management module are configured to collaboratively execute the storage method for CXL-SSD tiered memory.

[0074] This invention provides a terminal device comprising a processor and a memory. The memory stores a computer program, which includes program instructions. The processor executes the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, graphics processing units (GPUs), tensor processing units (TPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions to achieve a corresponding method flow or corresponding function. The processor described in this embodiment can be used for operations of storage methods for CXL-SSD tiered memory, including: When an access request that misses its target address in the host's last-level cache is located in the CXL device, the cache controller receives the access request and queries its internal sparse remapping table. If a match is found, the access request is redirected to the host fast layer; otherwise, the next level of the CXL device is probed. The high-fidelity memory profiler within the cache controller monitors all CXL access requests in real time, capturing page access popularity and intra-page access sparsity. The host-side dynamic slicing and asymmetric migration module retrieves the profile data from the high-fidelity memory profiler via memory-mapped I / O at preset migration intervals, identifies active slices from hot pages and generates a promotion list, and migrates only the active slices from the CXL-SSD slow layer to the host fast layer, while updating the mapping relationship in the sparse remapping table. The host-side write-sensitive degradation and eviction module filters sacrificed pages using a write-aware sacrificed page selection strategy. Based on the cleanliness and data organization of the sacrificed pages, it performs multi-stage degradation and eviction operations to reclaim storage space in the host fast layer and / or the CXL-SSD slow layer.

[0075] Please see Figure 5The terminal device is a computer device. In this embodiment, the computer device 60 includes a processor 61, a memory 62, and a computer program 63 stored in the memory 62 and executable on the processor 61. When executed by the processor 61, the computer program 63 implements the storage method for CXL-SSD tiered memory in this embodiment. To avoid repetition, these details are not elaborated here. Alternatively, when executed by the processor 61, the computer program 63 implements the functions of each model / unit in the CXL-SSD tiered memory storage system of this embodiment. To avoid repetition, these details are not elaborated here.

[0076] Computer device 60 can be a desktop computer, laptop, handheld computer, cloud server, or other computing device. Computer device 60 may include, but is not limited to, a processor 61 and a memory 62. Those skilled in the art will understand that... Figure 5 This is merely an example of computer device 60 and does not constitute a limitation on computer device 60. It may include more or fewer components than shown, or combine certain components, or different components. For example, computer device may also include input / output devices, network access devices, buses, etc.

[0077] The processor 61 may be a Central Processing Unit (CPU), or other general-purpose processors, graphics processing units (GPUs), tensor processing units (TPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0078] The memory 62 can be an internal storage unit of the computer device 60, such as a hard disk or memory of the computer device 60. The memory 62 can also be an external storage device of the computer device 60, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc. equipped on the computer device 60.

[0079] Furthermore, the memory 62 may include both internal storage units of the computer device 60 and external storage devices. The memory 62 is used to store computer programs and other programs and data required by the computer device. The memory 62 can also be used to temporarily store data that has been output or will be output.

[0080] Please see Figure 6 The terminal device is an electronic device 600, which is manifested in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: at least one processing unit 610, at least one storage unit 620, a bus 630 connecting different platform components (including storage unit 620 and processing unit 610), a display unit 640, etc.

[0081] The storage unit stores program code, which can be executed by the processing unit 610 to perform the steps described in the method section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 610 can perform actions such as... Figure 1 The steps are shown in the figure.

[0082] Storage unit 620 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 6201 and / or cache memory 6202, and may further include a read-only memory (ROM) 6203.

[0083] Storage unit 620 may also include a program / utility 6204 having a set (at least one) program module 6205, such program module 6205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0084] Bus 630 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the multiple bus structures.

[0085] Electronic device 600 can also communicate with one or more external devices 700 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 600, and / or with any device that enables electronic device 600 to communicate with one or more other computing devices (e.g., router, modem). This communication can be performed via input / output interface 650. Furthermore, electronic device 600 can also communicate with one or more networks (e.g., local area network, wide area network, and / or public network, such as the Internet) via network adapter 660. Network adapter 660 can communicate with other modules of electronic device 600 via bus 630. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage platforms.

[0086] Example 4 This invention also provides a storage medium, specifically a computer-readable storage medium, which is a memory device in a terminal device for storing programs and data. It is understood that the computer-readable storage medium here can include both built-in storage media in the terminal device and extended storage media supported by the terminal device; it can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. The computer-readable storage medium provides storage space that stores the terminal's operating system. Furthermore, the storage space also stores one or more instructions suitable for loading and execution by a processor, which can be one or more computer programs (including program code). More specific examples of the computer-readable storage medium include: an electrical connection with one or more wires, a portable disk, a hard disk, random access memory, read-only memory, erasable programmable read-only memory, optical fiber, portable compact disk read-only memory, optical storage device, magnetic storage device, or any suitable combination thereof.

[0087] Computer-readable storage media also include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium can also be any readable medium other than a readable storage medium that can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium can be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, radio frequency, etc., or any suitable combination thereof.

[0088] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0089] One or more instructions stored in a computer-readable storage medium can be loaded and executed by a processor to implement the corresponding steps of the storage method for CXL-SSD tiered memory in the above embodiments; one or more instructions in the computer-readable storage medium are loaded and executed by the processor in the following steps: When an access request that misses its target address in the host's last-level cache is located in the CXL device, the cache controller receives the access request and queries its internal sparse remapping table. If a match is found, the access request is redirected to the host fast layer; otherwise, the next level of the CXL device is probed. The high-fidelity memory profiler within the cache controller monitors all CXL access requests in real time, capturing page access popularity and intra-page access sparsity. The host-side dynamic slicing and asymmetric migration module retrieves the profile data from the high-fidelity memory profiler via memory-mapped I / O at preset migration intervals, identifies active slices from hot pages and generates a promotion list, and migrates only the active slices from the CXL-SSD slow layer to the host fast layer, while updating the mapping relationship in the sparse remapping table. The host-side write-sensitive degradation and eviction module filters sacrificed pages using a write-aware sacrificed page selection strategy. Based on the cleanliness and data organization of the sacrificed pages, it performs multi-stage degradation and eviction operations to reclaim storage space in the host fast layer and / or the CXL-SSD slow layer.

[0090] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0091] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0092] To verify the technical advantages of this invention, a layered memory test platform based on the CXL 2.0 protocol was built. The platform was configured with host DDR5 DRAM (fast layer) and CXL-SSD (including a DRAM cache slow layer and a NAND Flash capacity layer). Three typical data-intensive workloads—artificial intelligence training, database querying, and high-performance computing—were selected for comparative testing with traditional full-page migration solutions and device-side seamless migration solutions. Experimental results show that the proposed solution significantly outperforms traditional solutions in terms of fast layer space utilization, thanks to the refined strategy of migrating only active slices. Average memory access latency is significantly reduced, attributed to the fast routing of the sparse remapping table and the close proximity storage of active slices. Flash write amplification and device wear are significantly reduced, demonstrating the advantages of write-sensitive management and full-page merged writes. Host CPU overhead is only about 1 / 6 of the traditional solution, due to the CXL device-side offloading of memory access profiling and routing overhead. The throughput of all three workloads is significantly improved, verifying the efficient adaptability of this invention in different application scenarios and fully demonstrating the advanced nature and practicality of the technical solution.

[0093] This invention addresses the shortcomings of existing technologies in CXL-SSD tiered memory systems, achieving three core beneficial effects: High-precision, low-overhead fine-grained memory access awareness The CXL device-side lightweight hardware memory profiler, designed with a combination of probabilistic data structures and sparse bitmaps, accurately tracks cache line-level access patterns in real time with extremely low host CPU overhead, providing reliable support for data migration decisions.

[0094] Fine-grained data transfer with sparsity awareness By decoupling monitoring and migration granularity through dynamic slicing and asymmetric migration mechanisms, only active slices within hot pages are migrated, eliminating bandwidth and storage resource waste associated with the migration of cold data and significantly improving the efficiency of fast memory layer space utilization.

[0095] Co-optimization of system performance and equipment lifespan Through a full-path write-sensitive adaptive management mechanism, the system dynamically optimizes data placement strategies to adapt to various workloads, effectively filters invalid writes, reduces flash write amplification and device wear, and balances system performance and device durability.

[0096] In summary, this invention provides a storage method and system for tiered memory in CXL-SSDs. Addressing the three core challenges of tiered memory systems—performance differences across tiers, flash write endurance limitations, and granularity mismatch—this invention achieves breakthrough optimization through multi-module collaborative design. Regarding performance improvements, the high-fidelity memory profiler accurately captures cache row-level access characteristics, while dynamic slicing and asymmetric migration mechanisms migrate only active slices, preventing cold data from occupying fast memory and increasing the utilization rate of the fast tier by over 40%. The sparse remapping table enables transparent redirection of access requests, and combined with the advantages of TLB access, memory access latency is reduced by 30%–50%, significantly improving the operational efficiency of data-intensive applications. In terms of device lifespan protection, the write-sensitive degradation and eviction module effectively filters invalid writes through a clean page priority strategy, global victim caching, and full-page merge write mechanism, reducing the flash write amplification factor to below 1.2 and slowing down device wear rate by over 60%, significantly extending the lifespan of the CXL-SSD. In terms of compatibility and scalability, all designs require no modification to the host hardware architecture and operating system page tables, ensuring full compatibility with the standard CXL platform. The adjustable migration granularity, threshold parameters, and other designs adapt to different workload characteristics and have broad application scenario adaptability. This invention successfully resolves the contradiction between coarse-grained management and fine-grained access, achieving synergistic optimization of system performance, space efficiency, and device lifespan, and providing an efficient and feasible solution for breaking through the "memory wall".

[0097] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0098] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0099] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0100] In the embodiments provided by this invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0101] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0102] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0103] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random-access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0104] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0105] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0106] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0107] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A storage method for tiered memory in CXL-SSD, characterized in that, The process is executed collaboratively by the cache controller on the CXL device side and the processor on the host side, including the following steps: S1. When the target address of the access request that misses the host's last-level cache is located in the CXL device, the cache controller receives the access request and queries the internal sparse remapping table. If a match is found, the access request is redirected to the host fast layer. If a match is not found, the next level of the CXL device is explored. S2. The high-fidelity memory access parser in the cache controller detects all CXL access requests in real time and captures page access popularity and in-page access sparsity. S3. The dynamic slicing and asymmetric migration module on the host side retrieves the analysis data of the high-fidelity memory access profiler through memory-mapped I / O at a preset migration interval, identifies active slices from the hot pages and generates a promotion list, migrates only the active slices from the CXL-SSD slow layer to the host fast layer, and updates the mapping relationship of the sparse remapping table at the same time. S4. The write-sensitive degradation and eviction module on the host side filters sacrificial pages through a write-aware sacrificial page selection strategy. Based on the cleanliness and data organization of the sacrificial pages, it performs multi-stage degradation and eviction operations on the sacrificial pages to reclaim the storage space of the host fast layer and / or CXL-SSD slow layer.

2. The storage method for CXL-SSD tiered memory according to claim 1, characterized in that, In step S1, the sparse remapping table maintains the mapping index between sparse slices in the physical address space of the CXL device and virtual cache slots in the host fast layer. The cache controller transparently routes CPU requests to the fast layer through the sparse remapping table without modifying the host operating system page table. When the target address of an access request that is out of bounds from the host last-level cache is located in the fast layer, the system directly accesses the fast layer and returns the data.

3. The storage method for CXL-SSD tiered memory according to claim 1, characterized in that, In step S2, the high-fidelity memory access profiler is an independent hardware unit integrated inside the cache controller. It captures page access popularity and in-page access sparsity by snooping on all CXL traffic. The analysis overhead is completely offloaded to the host CPU. The host obtains the batch statistics captured by the high-fidelity memory access profiler through memory-mapped I / O. The high-fidelity memory access parser adopts a hybrid data structure combining the CountMin-Sketch algorithm and a sorted min-heap. Its core includes a CM-Sketch unit for probabilistically estimating global page popularity and a hot page tracker for maintaining information on the Top-K pages with the highest global popularity.

4. The storage method for CXL-SSD tiered memory according to claim 3, characterized in that, The specific process of capturing page visit popularity and in-page visit sparsity is as follows: S201. Parse the external memory access address and separate the global page address and the corresponding page cache line index; S202. The global page address is mapped to multiple counter entries of the CM-Sketch unit via multiple independent hash functions. The counter entries are accumulated according to the access type, and the minimum value of multiple counter values ​​is taken as the page estimated popularity corresponding to the global page address. S203. Search for the global page address in the sorted min-heap of the hot page tracker. If it exists, update the corresponding page estimated heat and mark the bit corresponding to the page cache line index in the sparse bitmap as 1. If it does not exist, compare the estimated page heat with the heat value of the root node of the sorting min-heap. If the estimated page heat is higher, replace the root node and insert the global page address, the estimated page heat, and the initial sparse bitmap into the sorting min-heap; S204. Generate a page sparsity-frequency distribution histogram at a preset update interval, dynamically set a global heat threshold based on the histogram, retrieve the hot page addresses whose heat values exceed the global heat threshold and the corresponding sparse bitmaps, and fill them into the migration candidate buffer.

5. The storage method for CXL-SSD tiered memory according to claim 4, characterized in that, The sparse bitmap adopts a demand-allocation strategy. Only when the page corresponding to the global page address is included in the Top-K hot page list of the sorting min-heap, initialize a new empty sparse bitmap and set the index bit of the in-page cache line being accessed.

6. The storage method for CXL-SSD tiered memory according to claim 1, characterized in that, In step S3, the specific process of identifying active slices from hot pages is as follows: S301. Extract the sparse bitmap corresponding to the hot page; S302, Logically divide the sparse bitmap into 2 n Each sub-bitmap corresponds to a slice of physical address range, where n is an adjustable configuration parameter based on the actual workload characteristics, with a value range of 0≤n≤6. S303. Perform a bitwise OR operation on each sub-bitmap. If the operation result is 1, it indicates that there is an active cache line access in the slice corresponding to the sub-bitmap, and mark it as an active slice; S304. Append all the identified active slices to the global hot slice list in the form of <page address, MaskSlicei> tuples to form a promotion list.

7. The storage method for tiered memory for CXL-SSD according to claim 1, characterized in that, In step S3, the specific process of migrating only the active slices from the CXL-SSD slow layer to the host fast layer is as follows: Allocate an idle virtual slot in the virtual cache pool constructed by pre-dividing and reserving space in the host fast layer, use DMA to move the active slice from the CXL-SSD slow layer to the virtual slot, and establish an index mapping from <CXL physical address, slice offset> to the host virtual slot identifier; After the migration of the active slice is completed, clear the corresponding bits of the corresponding sparse bitmap in the high-fidelity memory access profiler, and remove the corresponding page from the sorting min-heap of the hot page tracker; when the dynamic slice and asymmetric migration module perform data degradation operations, downgrade all the data of the selected victim page in the host fast layer to the CXL-SSD slow layer in the form of a complete page.

8. The storage method for CXL-SSD tiered memory according to claim 1, characterized in that, In step S4, the write-aware victim page selection policy is based on a set-associative architecture and follows the principle of clean page priority. When a cache group needs to select a victim page, find the first strictly clean page within the preset clean page scan window; if there is no clean page within the clean page scan window, select the victim page in the least recently used manner; Logically divide the capacities of the host fast layer and the CXL-SSD slow layer into two parts: the main cache and the global victim cache. The global victim cache dynamically harvests the unused free space in the main cache. When a cache group is full, move the selected victim page into the global victim cache; If the page in the global victim cache is accessed again, directly redirect it back to the main cache, and only update the metadata without performing physical data migration operations.

9. The storage method for CXL-SSD tiered memory according to claim 1, characterized in that, In step S4, the specific process of performing multi-stage degradation and eviction operations includes fast layer degradation processing and slow layer eviction processing: The fast layer degradation process is as follows: if the sacrificed page is a dirty page, it is downgraded to the CXL-SSD slow layer main cache and inserted at the end of the linked list of the corresponding cache group; if the dirty page is a dirty slice in the fast layer and its corresponding buddy slice already resides in the CXL-SSD slow layer, the two slices are automatically merged into a complete 4KiB page; if the sacrificed page is a clean page, an invalidation instruction is sent to the CXL cache controller, the corresponding mapping entry in the sparse remapping table is deleted to remove the address redirection relationship, the page is silently reclaimed, and the corresponding virtual slot is returned to the free linked list. The slow layer eviction process is as follows: if the sacrificed page contains a dirty slice, the valid data is flushed into the CXL-SSD capacity layer flash memory; if the buddy slice of the dirty slice still resides in the host fast layer, the buddy slice is first retrieved, and the two are merged into an aligned 4KiB complete page before being written to the NAND flash memory; if there is no corresponding buddy slice, the complete page is directly written to the flash memory. If the sacrificed page is a clean page, it will be silently discarded and the corresponding space will be reclaimed. Furthermore, the CXL-SSD slow layer acts as a write merging buffer, constructing a multi-stage data processing path that can absorb burst traffic and merge scattered write operations, absorbing invalid and burst traffic, and minimizing the number of flash write-backs.

10. A storage system for CXL-SSD tiered memory, characterized in that, This includes a cache controller deployed on the CXL device side and a host-side storage management module running on the host side; The cache controller integrates a sparse remapping table and a high-fidelity memory access parser. The host-side storage management module includes a dynamic slicing and asymmetric migration module, as well as a write-sensitive degradation and eviction module; The sparse remapping table is used to maintain the mapping index between sparse slices in the physical address space of the CXL device and virtual cache slots in the host fast layer, so that the cache controller can query and transparently route access requests from the central processing unit to the host fast layer. The high-fidelity memory access profiler is connected to the sparse remapping table and is used to detect all CXL access requests in real time, capture page access popularity and page access sparsity, and output profile data to the host through memory-mapped I / O. The dynamic slicing and asymmetric migration module is communicatively connected to the high-fidelity memory access profiler. It is used to retrieve the profile data at a preset migration interval, identify active slices from the hot pages and generate a promotion list, migrate the active slices only from the CXL-SSD slow layer to the host fast layer, and update the mapping relationship of the sparse remapping table. The write-sensitive degradation and eviction module is connected to the dynamic slicing and asymmetric migration module. It is used to filter sacrificial pages through a write-aware sacrificial page selection strategy, and perform multi-stage degradation and eviction operations on the sacrificial pages according to their cleanliness and data organization, thereby reclaiming the storage space of the host fast layer and / or CXL-SSD slow layer. The cache controller and the host-side storage management module are configured to collaboratively execute the storage method for CXL-SSD tiered memory as described in any one of claims 1 to 9.

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