A method and apparatus for evaluating chip test efficiency
By recording and saving timestamp events during chip testing, the problem of inaccurate chip testing efficiency assessment is solved, efficient test time management and the identification of inefficient stages are achieved, and the chip testing process is optimized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI SUIYUAN TECH CO LTD
- Filing Date
- 2026-04-14
- Publication Date
- 2026-07-17
AI Technical Summary
In existing chip testing technologies, the evaluation of test cases relies on the experience of engineers, lacks unified standards, and is not accurate enough, making it difficult to reduce testing time and accurately locate inefficient stages while ensuring coverage.
By adding timestamps to generate various events during chip testing and storing these events in the event storage unit, the hardware timing unit records the start and end events of chip and core functional modules testing, calculates chip and core efficiency, and achieves accurate evaluation of testing efficiency and location of inefficient stages.
It enables accurate assessment of chip testing efficiency, reduces testing time while ensuring coverage, and accurately identifies inefficient stages by analyzing event types, thereby optimizing the testing process.
Smart Images
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